WO2019227909A1

WO2019227909A1 - Gate driver unit monolithic, gate driver monolithic and display apparatus

Info

Publication number: WO2019227909A1
Application number: PCT/CN2018/122466
Authority: WO
Inventors: 戴超; 黄洪涛; 陈旭; 王志军
Original assignee: 南京中电熊猫平板显示科技有限公司; 南京中电熊猫液晶显示科技有限公司; 南京华东电子信息科技股份有限公司
Priority date: 2018-05-30
Filing date: 2018-12-20
Publication date: 2019-12-05
Also published as: CN108847192A; CN108847192B

Abstract

A gate driver unit monolithic, a gate driver monolithic and a display apparatus. The gate driver unit monolithic is suitable for multi-stage connection to form the gate driver monolithic, and comprises a memory compensation module (05), wherein the memory compensation module (05) comprises a compensation sub-module (05A), a memory sub-module (05B) and a secondary memory sub-module (05C); at an early touch control detection stage, the memory compensation module (05) copies voltage information of a pull-up control node (netAn) and transfers same to a first memory compensation node (netCn) and a second memory compensation node (netDn); at a touch control detection stage, the voltage of the pull-up control node (netAn) is pulled down to a second stage voltage; and at the later touch control detection stage, the voltage of the pull-up control node (netAn) is pulled up to a first stage voltage. At a touch control detection stage, pull-up control nodes (netAn) at all stages are maintained at a low potential, thereby eliminating cross display stripes caused by the difference between characteristic drifts of thin-film transistors (M10) in a pull-up module (02).

Description

Gate driving unit circuit, gate driving circuit and display device

Technical field

The invention relates to the field of liquid crystal display, in particular to a gate driving unit circuit, a gate driving circuit and a display device for an in-cell touch display screen.

Background technique

In recent years, gate driver circuits (GDM, Monolithic, GDM) in liquid crystal displays have been gradually integrated in the liquid crystal panel technically using the existing thin film transistor process. This can reduce manufacturing costs and reduce design. Left and right border sizes. In small-sized display applications, in order to meet the needs of different customer applications, the gate drive circuit design generally needs to be capable of supporting forward scan and reverse scan switching. In addition, the integration of touch functions into the display has become a technology trend, which can not only save costs, but also reduce the overall thickness of the display, but at the same time put forward higher technical requirements for panel design.

FIG. 1 is a circuit diagram of a gate drive unit circuit of an embedded touch display screen. The gate drive unit circuit includes a forward and reverse scan control module 01, a pull-up module 02, a touch assist module 03, and a maintenance. The auxiliary module 04 and the first capacitor C1. The scanning direction of the gate driving unit circuit is controlled by a pair of mutually opposite constant voltage signals, a forward scanning control signal U2D and a reverse scanning control signal D2U. When U2D takes a high level and D2U takes a low level, Top-down forward scanning, otherwise reverse scanning, that is, the function of switching different scanning directions is achieved by controlling the states of the two thin film transistors M1 and M9.

Figure 2 is a schematic diagram of the driving method of an in-cell touch display. The original frame is divided into multiple blocks, and then the signal (Touch) is input between the blocks to display the pause. Touch detection. In this way, for the gate driving circuit, in order to meet the touch detection, the circuit needs to suspend the output of the gate scan signal Gn during the touch detection phase, and then it can be started normally after the touch is completed, and the gate scan is continued to be output sequentially. Signal Gn.

As shown in FIG. 3, the normal waveform of the gate driving circuit (that is, the level where no touch pause occurs) and the special level where the touch pause occurs. The driving waveform of the pull-up control node netAn is significantly different. After a long time operation, Will cause the thin film transistor M10 in these two different levels of gate drive unit circuits to generate different threshold voltage drifts, and then generate different gate scan signal outputs, which will eventually result in the formation of pit stop stripes at the touch pause position, that is, Black streaks appear on the same horizontal line as the touch pause position.

In addition, when the display is in a forward scanning state for a long period of time, U2D maintains a high potential, and the previous-stage gate scan signal is at a low potential for a long period of time. M1 will withstand a long period of negative bias stress, which will cause the threshold voltage of the component to be negative. Drift will eventually cause the M1 component to turn on incorrectly and the circuit function to fail. Similarly, the same problem exists when the scan is reversed for a long time. This instability is also related to the device itself, and obvious functional failure will occur in oxide thin film transistor applications. This negative drift can also cause the circuit to malfunction when switching the scan direction.

On the other hand, by adding additional forward scan control signal U2D, reverse scan control signal D2U, and the single-sided gate drive circuit to use the two start signals GSP1 and GSP3 to achieve the forward and reverse scan function, the reliability of the circuit is reduced, It also increases the complexity of the circuit.

Summary of the Invention

In order to solve the above technical problems, the present invention provides a gate driving unit circuit, a gate driving circuit, and a display device, which can avoid the pit stop horizontal stripes of the touch pause position caused by the threshold voltage drift of the thin film transistor and improve the reliability of the circuit Sex.

According to a first aspect of the present invention, a gate driving unit circuit is provided, which is suitable for multi-level connection to form a gate driving circuit, including a forward and reverse scan control module, a pull-up module, a touch assist module, a maintenance assist module, and Memory compensation module; forward and reverse scan control module, pull-up module, maintenance assistance module and memory compensation module are connected to the pull-up control node of this level; pull-up module and touch-assistance module are connected to the gate scan signal line of this level;

The memory compensation module includes a compensation sub-module, a memory sub-module, and a secondary memory sub-module; the memory sub-module and the secondary memory sub-module are connected to the first memory compensation node, and the compensation sub-module and the secondary memory sub-module are connected to The second memory compensation node, the compensation sub-module and the memory sub-module are connected to a pull-up control node of this level, the compensation sub-module inputs a touch start signal, and the secondary memory sub-module inputs a touch control signal;

The compensation sub-module is used to reduce the voltage of the pull-up control node of this stage from the voltage of the first stage to the voltage of the second stage during the touch detection stage, and pull up the voltage of the control node at this stage after the touch detection stage. The voltage is raised to the first stage voltage;

The memory sub-module is used to copy the voltage of the pull-up control node of this stage to the first memory compensation node before the touch detection stage, so that the voltage of the first memory compensation node is raised to the first memory voltage;

The secondary memory sub-module is used to raise the voltage of the second memory compensation node to the second memory voltage under the input of the touch control signal in the pre-touch detection stage.

According to a preferred embodiment of the present invention, the memory compensation module further includes a pull-down sub-module and a node control sub-module; the pull-down sub-module and the node control sub-module are connected to the first memory compensation node, and the node control sub-module and the maintenance auxiliary module are connected to the present Level maintenance control node;

The pull-down sub-module is used to pull down the voltage of the first memory compensation node to a low level and maintain it after the touch detection;

The node control sub-module is configured to pull the voltage of the control node at this stage to a low level when the first memory compensation node is at a high level of the first memory voltage.

According to a preferred embodiment of the present invention, the compensation sub-module includes a first thin film transistor, a control end of the first thin film transistor is connected to a second memory compensation node, a first path terminal of the first thin film transistor inputs a touch start signal, and a second path terminal Connected to this level pull-up control node;

The memory sub-module includes a fourth thin film transistor, the control end of the fourth thin film transistor and the first path end are short-circuited and connected to the pull-up control node of this level, and the second path end is connected to the first memory compensation node;

The secondary memory sub-module includes a fifteenth thin film transistor, the control end of the fifteenth thin film transistor is connected to the current level control node, the first path end inputs the touch control signal, and the second path end is connected to the second memory compensation node;

The pull-down sub-module includes an eighteenth thin film transistor, a control terminal of the eighteenth thin film transistor inputs a second clock signal, a first path end is connected to a first memory compensation node, and a second path end inputs a constant voltage low level;

The node control sub-module includes a sixteenth thin film transistor, a control end of the sixteenth thin film transistor is connected to a first memory compensation node, a first path end is connected to a current-level maintenance control node, and a second path end inputs a constant voltage low level.

According to a preferred embodiment of the present invention, the forward and reverse scanning control module includes a seventh thin film transistor, a ninth thin film transistor, and a fifteenth thin film transistor;

The control terminal of the seventh thin film transistor and the first path terminal are short-circuited and a first control signal is input, and the second path terminal is connected to the pull-up control node of this stage;

The control terminal of the ninth thin film transistor and the first path terminal are short-circuited and a second control signal is input, and the second path terminal is connected to the pull-up control node of this stage;

The control terminal of the fifteenth thin film transistor inputs a second clock signal, the first path terminal is connected to the pull-up control node of this stage, and the second path terminal inputs a constant voltage low level.

According to a preferred embodiment of the present invention, when the gate drive unit circuit is a first-stage gate drive unit circuit, the first control signal is a first start signal; otherwise, the first control signal is a previous-stage gate scan signal;

When the gate driving unit circuit is a tail-stage gate driving unit circuit, the second control signal is a first start signal; otherwise, the second control signal is a subsequent-stage gate scan signal.

According to a preferred embodiment of the present invention, the touch assist module includes a fourteenth thin film transistor, a control terminal of the fourteenth thin film transistor inputs a touch control signal, a first path end is connected to a gate scanning signal line of this stage, and a second path end Input constant voltage low level.

According to a preferred embodiment of the present invention, the maintenance auxiliary module includes a maintenance submodule and an empty submodule, and the maintenance submodule and the empty submodule and the memory compensation module are connected to the current level maintenance control node;

The maintenance sub-module is used to charge and discharge the maintenance control node of this stage, and maintain the pull-up control node and gate scan signal line of this stage;

The clearing sub-module is used to clear the charge of the pull-up control node of this stage and the maintenance control node of this stage at the end of the frame and when it is turned on and off.

According to a preferred embodiment of the present invention, the maintenance sub-module includes a fifth thin film transistor, a sixth thin film transistor, an eighth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, and a seventeenth thin film transistor. ;

The control terminal of the fifth thin film transistor and the first path terminal are short-circuited and input a constant high voltage level, and the second path terminal is connected to the current stage maintenance control node;

The control terminal of the sixth thin film transistor is connected to the pull-up control node, the first path terminal is connected to the current stage maintenance control node, and the second path terminal inputs a constant voltage low level;

The control terminal of the eighth thin film transistor is connected to the maintenance control node, the first path terminal is connected to the pull-up control node of this stage, and the constant voltage low level is input to the second path terminal;

The control terminal of the eleventh thin film transistor inputs the gate scanning signal of the previous stage, the first path terminal is connected to the current stage maintenance control node, and the second path terminal inputs the constant voltage low level;

The control terminal of the twelfth thin film transistor inputs the gate scanning signal of the subsequent stage, the first path terminal is connected to the current stage maintenance control node, and the second path terminal inputs the constant voltage low level;

The control terminal of the thirteenth thin film transistor is connected to the maintenance control node, the first path terminal is connected to the gate scanning signal line of this stage, and the constant voltage low level is input to the second path terminal;

The control terminal of the seventeenth thin film transistor is connected to the memory compensation node, the first path terminal is connected to the current stage maintenance control node, and the second path terminal is input with a constant low voltage level.

According to a preferred embodiment of the present invention, the emptying sub-module includes a second thin film transistor and a third thin film transistor;

The control terminal of the second thin film transistor inputs a clear reset signal, the first path terminal is connected to the pull-up control node of this stage, and the second path terminal inputs a constant voltage low level;

The control terminal of the third thin film transistor inputs a clear reset signal, the first path terminal is connected to the current stage maintenance control node, and the second path terminal inputs a constant voltage low level.

According to a second aspect of the present invention, a gate driving circuit is provided, which includes an N-level gate driving unit circuit as in any of the foregoing embodiments, wherein N is a positive integer greater than 4.

According to a third aspect of the present invention, a display device is provided, including the gate driving circuit according to the foregoing embodiment.

Compared with the prior art, the present invention can bring at least one of the following beneficial effects:

1. The pull-up control nodes of all stages in the touch detection stage are maintained at a low potential to eliminate the pit stop horizontal stripes caused by different characteristics of thin-film transistor in the pull-up module;

2. The capacitor is not included in the memory compensation module, which is helpful to reduce the layout area;

3. The two thin-film transistors receiving the first control signal and the second control signal in the forward and reverse scanning control module use a short-circuit connection of the gate and source to avoid circuit failure caused by threshold voltage drift;

4. Use the existing signal to realize the forward and reverse scanning function and the single-sided gate drive circuit only needs a start signal, which is conducive to narrowing the frame of the display panel.

BRIEF DESCRIPTION OF THE DRAWINGS

Hereinafter, the preferred embodiments will be described in a clear and easy-to-understand manner with reference to the accompanying drawings to further explain the present invention.

FIG. 1 is a schematic circuit diagram of a gate driving unit circuit of an in-cell touch display screen; FIG.

FIG. 2 is a schematic diagram of a driving manner of the gate driving unit circuit shown in FIG. 1; FIG.

3 is a schematic diagram of driving waveforms of a pull-up control node of a normal stage and a special stage where a touch pause occurs in the gate driving unit circuit shown in FIG. 1;

4 is a schematic circuit diagram of a gate driving unit circuit according to the present invention;

5 is a schematic circuit diagram of a memory compensation module in a gate driving unit circuit according to the present invention;

6 is a schematic diagram of a left and right interleaved driving architecture of a gate driving unit circuit;

7 is a circuit diagram of a gate driving unit circuit according to the first embodiment of the present invention;

8 is a schematic diagram of driving waveforms of a touch control signal and a touch high level in a gate driving unit circuit according to the first embodiment of the present invention;

9 is a circuit diagram of a gate driving unit circuit according to a second embodiment of the present invention;

10 is a schematic diagram of driving waveforms of a second start signal and a touch control signal in the circuit shown in FIG. 9;

11 is a schematic diagram of driving waveforms of the circuit shown in FIG. 9 during forward scanning;

FIG. 12 is a schematic diagram of driving waveforms of the circuit shown in FIG. 9 during reverse scanning.

BRIEF DESCRIPTION OF THE DRAWINGS

01, positive and negative scanning control module, 02, pull-up module, 03, touch assist module, 04, maintenance assist module, 04A, maintenance sub-module, 04B, empty sub-module, 05, memory compensation module, 05A, compensation sub-module , 05B, memory sub-module, 05C, secondary memory sub-module, 05D, pull-down sub-module, 05E, node control sub-module,

M1, first thin film transistor, M2, second thin film transistor, M3, third thin film transistor, M4, fourth thin film transistor, M5, fifth thin film transistor, M6, sixth thin film transistor, M1A, seventh thin film transistor, M8 Eighth thin film transistor, M1B, ninth thin film transistor, M10, tenth thin film transistor, M6A, eleventh thin film transistor, M6B, twelfth thin film transistor, M6C, sixteenth thin film transistor, M9A, seventeenth thin film Transistor, M9B, eighteenth thin film transistor, C1, first capacitor;

Gn, gate scan signal of n-th gate drive unit circuit, netAn, pull-up control node of n-th gate drive unit circuit, netBn, sustain control node of n-th gate drive unit circuit, netCn, First memory compensation node of n-level gate drive unit circuit, netDn, second memory compensation node of n-th gate drive unit circuit, VGH1, constant voltage high level, VGH2, touch high level, VSS, constant Low level, CKm, first clock signal, CKm + 4, second clock signal, Gn-2, gate scan signal of gate driving unit circuit of stage n-2, Gn + 2, stage n + 2 Gate scan signal of the gate drive unit circuit, CLR1, clear reset signal, GSP1, first start signal, GSP2, second start signal, TC1, touch control signal.

Detailed ways

In order to more clearly explain the embodiments of the present invention or the technical solutions in the prior art, specific implementations of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings in the following description are just some embodiments of the present invention. For those of ordinary skill in the art, other creative drawings can be obtained based on these drawings without any creative work, and Other implementations.

In order to make the drawings concise, each figure only schematically shows the parts related to the present invention, and they do not represent its actual structure as a product. Here, when the first element is described as “electrically connected” to the second element, the first element may be directly connected to the second element or indirectly connected to the second element via one or more additional elements. Further, for the sake of clarity, certain elements that are not necessary for a full understanding of the present invention have been omitted concisely.

FIG. 4 is a schematic circuit diagram of a gate driving unit circuit of the present invention, and FIG. 5 is a schematic circuit diagram of a memory compensation module in the gate driving unit circuit of the present invention.

As shown in FIG. 4, the gate driving unit circuit of the present invention is suitable for multi-level connection to form a gate driving circuit. The gate driving unit circuit includes a forward and reverse scan control module 01, a pull-up module 02, and a touch assistant. Module 03, maintenance assistance module 04, and memory compensation module 05. The forward and reverse scanning control module 01, pull-up module 02, maintenance assistance module 04, and memory compensation module 05 are connected to the pull-up control node netAn; the forward and reverse scanning control module 01, touch assistance module 03, and maintenance assistance module 04 are all input to constant Low level VSS; the pull-up module 02 and the touch assist module 03 are connected to the gate scanning signal line of this level, and the gate scanning signal line outputs a gate scanning signal Gn.

As shown in FIG. 5, the memory compensation module 05 includes a compensation sub-module 05A, a memory sub-module 05B, and a secondary memory sub-module 05C. The memory sub-module 05B and the secondary memory sub-module 05C are connected to the first memory compensation node netCn to compensate. The sub-module 05A and the secondary memory sub-module 05C are connected to the second memory compensation node netDn. The compensation sub-module 05A and the memory sub-module 05B are connected to the pull-up control node netAn of the current level of the gate drive unit circuit, and the compensation sub-module 05A. A touch start signal is input, and the secondary memory sub-module 05C inputs a touch control signal TC1.

In the embodiment of the present invention, one frame time is divided into a pre-touch detection stage, a touch detection stage, and a post-touch detection stage.

The compensation sub-module 05A is used to pull down the voltage of the control node netAn at this stage from the first stage voltage to the second stage voltage at the touch detection stage, and pull up the voltage of the control node netAn at the post-touch detection stage. Pull up to the first stage voltage.

The memory sub-module 05B is used to copy the voltage of the pull-up control node netAn at this stage to the first memory compensation node netCn before the touch detection, so that the voltage of the first memory compensation node is raised to the first memory voltage.

The secondary memory sub-module 05C is used to raise the voltage of the second memory compensation node netDn to the second memory voltage under the input of the touch control signal TC1 in the pre-touch detection stage.

The gate driving unit circuit of the present invention copies the voltage information of the memory pull-up control node netAn to the memory compensation module 05 through the memory compensation module 05 before the touch detection stage, and pulls down the pull-up control node netAn during the touch detection stage. For voltage, the voltage information stored in the memory compensation module 05 is copied to the pull-up control node netAn by inputting a touch start signal at the post-touch detection stage, and voltage or time compensation is performed at the same time. The gate driving unit circuit supports bidirectional scanning, and can be applied to an in-cell touch display screen, reducing the gate scanning signal lines of the touch pause level gate drive unit circuit and the non-touch pause level gate drive unit circuit. The difference in output reduces or even eliminates the horizontal lines of the pit stop, and the capacitor is not included in the memory compensation module 05, which is helpful to reduce the area occupied by the layout.

In an optional implementation manner, the memory compensation module 05 may further include a pull-down sub-module 05D and a node control sub-module 05E. The pull-down sub-module 05D and the node control sub-module 05E are connected to the first memory compensation node netCn, and the node control sub-module 05D and the maintenance auxiliary module 04 are connected to the current-level maintenance control node netBn.

The pull-down sub-module 05D is used to pull down the voltage of the first memory compensation node netCn to a low level and maintain it in the post-touch detection stage.

The node control sub-module 05E is used to pull the voltage of the current control node netBn to a low level when the first memory compensation node netCn is at a high first memory voltage, so as not to affect the gate scan of the current stage. Output of the signal Gn.

In an alternative embodiment, the gate driving unit circuit of the present invention may further include a first capacitor C1, which is connected between the pull-up control node netAn of this stage and the gate scan signal line of the stage, and is responsible for During the output of the gate scan signal Gn of this stage, the voltage of the pull-up control node netAn of this stage is raised.

The N-level gate driving unit circuit can realize the gate driving circuit of the embodiment of the present invention by cascading. According to a preferred embodiment of the present invention, N may be a positive integer greater than 4.

The gate drive unit circuit of the present invention has various specific embodiments. The circuit structure of each stage of the gate drive unit circuit is the same, and the difference is only that the signals input by some thin film transistors are different. The following will be based on the nth stage gate drive unit circuit. Description, 1 ≦ n ≦ N, and n is a positive integer.

It should be noted that the circuit diagrams involved in the following embodiments are all left-side gate drive unit circuits or right-side gate drive unit circuits under an interlace drive architecture (as shown in FIG. 6), but the present invention The application of the gate driving unit circuit is not limited to this method, and it can be applied to any mode of driving architecture, including non-left and right interleaved bilateral driving architecture, unilateral driving architecture, etc. In the left-right interleaved driving architecture, the number of clock signals in a single-sided gate drive circuit is M, and the total number of clock signals on both sides is 2M, and the single-sided clock signal is expressed as CKm (m = 1, 3, ..., 2M-1 or m = 2, 4, ..., 2M).

The pre-stage gate drive unit circuit of the n-th stage gate drive unit circuit referred to in the following embodiments refers to the (na) stage gate drive unit circuit, where 1≤na <n, the so-called nth stage The subsequent gate driving unit circuit of the gate driving unit circuit refers to the (n + a) th stage gate driving unit circuit, where n <n + a ≦ N. Preferably, in the left-right interleaved driving architecture, the previous-stage gate driving unit circuit of the n-th stage gate driving unit circuit may be an n-2-stage gate driving unit circuit, The stage gate driving unit circuit may be an n + 2 stage gate driving unit circuit.

In the left and right interleaved driving architecture, the first-stage gate driving unit circuit referred to in the following embodiments refers to the first-stage gate driving unit circuit (the first-stage gate driving unit circuit) of the left-side gate driving circuit and The first-stage gate drive unit circuit (the second-stage gate drive unit circuit) of the right-side gate drive circuit; the last-stage gate drive unit circuit referred to in the following embodiments refers to: The gate driving unit circuit (the N-1th stage gate driving unit circuit) and the tail gate driving unit circuit (the Nth stage gate driving unit circuit) of the right gate driving circuit.

In the following embodiments, four clock signals CK1, CK3, CK5, and CK7 are selected. The waveforms of CK1, CK3, CK5, and CK7 are shown in Figures 7 and 8. When the waveforms of CK1, CK3, CK5, and CK7 are sequentially generated, This clock signal input mode is called clock signal positive sequence input, and the gate drive unit circuit is in the forward scanning state. When the CK1, CK3, CK5, CK7 waveforms are generated in reverse order, this clock signal input mode is called clock signal. Reverse sequence input, the gate drive unit circuit is in the reverse scanning state. It should be noted that, on the basis of the present invention, the use of other numbers and waveforms of clock signals and other clock signal input modes to improve the conventional functions should fall into the protection scope of the present invention.

In the following embodiments, the thin film transistor includes a control terminal, a first via terminal, and a second via terminal. The control terminal is a gate, the first via terminal is a source, and the second via terminal is a drain. In the method, the first via end may also be a drain, and the second via end may be a source. When the control terminal is high, the source and drain are connected through the semiconductor layer, and the thin film transistor is in an on state at this time.

The gate driving unit circuit of the present invention is described in detail in the following specific embodiments.

Embodiment one:

FIG. 7 is a circuit diagram of a gate driving unit circuit according to the first embodiment of the present invention. As shown in FIG. 7, the gate driving unit circuit of this embodiment includes a forward and reverse scanning control module 01, a pull-up module 02, a touch assist module 03, a maintenance assist module 04, and a memory compensation module 05. The forward and reverse scanning control module 01, pull-up module 02, maintenance assistance module 04, and memory compensation module 05 are connected to the pull-up control node netAn at this level; the forward and reverse scanning control module 01, touch assistance module 03, and maintenance assistance module 04 are all Input the constant voltage low level VSS; the pull-up module 02 and the touch assist module 03 are connected to the gate scanning signal line of this stage, and the gate scanning signal line outputs the gate scanning signal Gn.

The memory compensation module 05 includes a compensation sub-module 05A, a memory sub-module 05B, a secondary memory sub-module 05C, a pull-down sub-module 05D, and a node control sub-module 05E.

Specifically, the compensation sub-module 05A includes a first thin film transistor M1, a control end of the first thin film transistor M1 is connected to a second memory compensation node netDn, and two path ends of the first thin film transistor M1 are respectively connected to pull-up control nodes netAn and Input the touch start signal, where the touch start signal is the touch high level VGH2, VGH2 is a constant voltage high level, which is mainly responsible for pulling down the pull-up control node netAn during the touch, and pulling it up after the touch is completed netAn and compensate. The first thin film transistor M1 pulls down the pull-up control node netAn from the first phase voltage to the second phase voltage during the touch detection phase, and pulls up and voltage compensates the pull-up control node netAn during the touch detection phase. To restore the first stage voltage.

The memory sub-module 05B includes a fourth thin film transistor M4. The control terminal of the fourth thin film transistor M4 and the first path terminal are short-circuited and connected to the pull-up control node netAn at this level. The second path terminal of the fourth thin film transistor M4 is connected to the first memory. Compensation node netCn; the fourth thin film transistor M4 copies the voltage information of the current level pull-up control node netAn to the first memory compensation node netCn before the touch detection stage, so that the voltage of the first memory compensation node netCn rises to the first A memory voltage.

The secondary memory sub-module 05C includes a fifteenth thin film transistor M15. The control terminal of the fifteenth thin film transistor M15 is connected to the first memory compensation node netCn, and the two path ends of the fifteenth thin film transistor M15 are respectively connected to the second memory compensation node netDn. And input the touch control signal TC1; in the pre-touch detection stage, the fifteenth thin film transistor raises the voltage of the second memory compensation node netDn to the second memory under the input of the high-level touch control signal TC1. Voltage, the high-level second memory voltage can control the compensation sub-module 05A to open.

The pull-down sub-module 05D includes an eighteenth thin film transistor M9B, a control terminal of the eighteenth thin film transistor M9B inputs a second clock signal CKm + 4, and two path ends of the eighteenth thin film crystal M9B are respectively connected to the first memory compensation nodes netCn and Input constant voltage low VSS. The eighteenth thin film transistor M9B is used to pull down the voltage of the first memory compensation node netCn to a low level and maintain it after the touch detection.

The node control sub-module 05E includes a sixteenth thin film transistor M6C. The control terminal of the sixteenth thin film transistor M6C is connected to the first memory compensation node netCn, and the two path ends of the sixteenth thin film transistor M6C are respectively connected to the maintenance control nodes netBn and The input constant voltage low level VSS; the sixteenth thin film transistor M6C is used to assist in pulling the voltage of the control node netBn maintained at this stage to a low level to ensure that the output of the gate scan signal is not affected.

As shown in FIG. 7, the maintenance auxiliary module 04 includes a maintenance sub-module 04A and an empty sub-module 04B. The maintenance sub-module 04A and the empty sub-module 04B are connected to the current-level maintenance control node netBn.

Maintenance sub-module 04A is connected to the pull-up control node netAn of this stage, and inputs constant-voltage low-level VSS and constant-voltage high-level VGH1. Maintenance sub-module 04A is used to charge and discharge the maintenance control node netBn of this stage, and The control node netAn and the gate scan signal line Gn are pulled for maintenance.

Clear sub-module 04B, pull-up module 02, and touch assist module 03 are connected to the gate scan signal line Gn of this stage. Clear sub-module 04B is used to pull up the control node netAn, this stage at the end of the frame and switch on and off. The control node netBn is maintained for charge emptying.

The maintenance sub-module 04A includes a fifth thin film transistor M5, a sixth thin film transistor M6, an eighth thin film transistor M8, an eleventh thin film transistor M6A, a twelfth thin film transistor M6B, and a thirteenth thin film transistor M13.

The control terminal of the fifth thin film transistor M5 and the first path terminal of the fifth thin film transistor M5 are short-circuited, and a constant voltage high level VGH1 is input, and the second path terminal of the fifth thin film transistor M5 is connected to the current stage maintenance control node netBn; The five thin-film transistors M5 use the constant voltage high-level VGH1 to charge the maintenance control node netBn at this stage.

The control terminal of the sixth thin film transistor M6 is connected to the pull-up control node netAn of this stage, and the two path ends of the sixth thin film transistor M6 are respectively connected to the control node netB of the current stage and the input constant voltage low level VSS; In this stage, the control node netBn is pulled down to ensure that the output of the gate scan signal Gn is not affected.

The control terminal of the eleventh thin film transistor M6A inputs the first control signal, and the two path ends of the eleventh thin film transistor M6A are respectively connected to the current stage control node netBn and the input constant voltage low level VSS; the eleventh thin film transistor M6A is used for During the forward scan, the auxiliary control node netBn is pulled down to ensure that the output of the gate scan signal Gn is not affected.

The control terminal of the twelfth thin film transistor M6B inputs the second control signal, and the two path ends of the twelfth thin film transistor M6B are respectively connected to the maintenance control node netBn and the input constant voltage low level VSS; the twelfth thin film transistor M6B is used for During the reverse scanning, the auxiliary control node netBn is pulled down to ensure that the output of the gate scanning signal Gn is not affected.

In an alternative embodiment, when the n-th gate drive unit circuit is a first-stage gate drive unit circuit, the first control signal is a first start signal GSP1; otherwise, the first control signal is a previous-stage gate scan signal. Preferably, it is a gate scan signal Gn-2 of the n-2th-level gate driving unit circuit.

When the n-th stage gate drive unit circuit is a tail-stage gate drive unit circuit, the second control signal is a first start signal GSP1; otherwise, the second control signal is a subsequent-stage gate scan signal; preferably, it is an n-th stage. A gate scan signal Gn + 2 of the +2 stage gate driving unit circuit.

The control terminal of the eighth thin film transistor M8 is connected to the maintenance control node netBn at this stage, and the two path terminals of the eighth thin film transistor M8 are respectively connected to the pull-up control node netAn at this stage and the input constant voltage low level VSS; Maintain the pull-up control node netAn at this level.

The control terminal of the thirteenth thin film transistor M13 is connected to the maintenance control node netBn at this stage, and the two path ends of the thirteenth thin film transistor M13 are respectively connected to the gate scanning signal line of this stage and the input constant voltage low level VSS; the thirteenth thin film The transistor M13 is used for maintaining the gate-scanning signal line of this stage.

The clearing sub-module 04B includes a second thin film transistor M2 and a third thin film transistor M3.

The control terminal of the second thin film transistor M2 inputs the clear reset signal CLR1, and the two path terminals of the second thin film transistor M2 are respectively connected to the pull-up control node netAn of this stage and the input constant voltage low level VSS; the second thin film transistor M2 is used for At the end of each frame and when the machine is turned on and off, the charge of the pull-up control node netAn at this stage is cleared.

The control terminal of the third thin film transistor M3 inputs the clear reset signal CLR1, and the two path terminals of the third thin film transistor M3 are respectively connected to the maintenance control node netBn and the input constant voltage low level VSS; The control node netBn is maintained for charge emptying.

In the embodiment of the present invention, the maintenance auxiliary module 04 may be configured according to different design requirements, and may include various functions such as maintaining or pulling down and clearing the net pull-up control node netAn and the gate scan signal Gn of the current stage.

As shown in FIG. 7, specifically, the forward and reverse scanning control module 01 includes a seventh thin film transistor M1A, a ninth thin film transistor M1B, and a fifteenth thin film transistor M9A.

The control terminal of the seventh thin film transistor M1A and the first path terminal of the seventh thin film transistor M1A are short-circuited and a first control signal is input, the second path terminal of the seventh thin film transistor M1A is connected to the pull-up control node netAn, and the fourth thin film transistor M4A Pre-charge the netAn pull-up control node netAn during the forward scan.

The control terminal of the ninth thin film transistor M1B and the first path terminal of the ninth thin film transistor M1B are short-circuited and a second control signal is input, the second path terminal of the ninth thin film transistor M1B is connected to the pull-up control node netAn, and the ninth thin film transistor M1B Pre-charge the netAn pull-up control node netAn during the reverse scan.

The seventh thin film transistor M1A and the ninth thin film transistor M1B adopt a diode connection method to avoid circuit failure caused by negative drift of the threshold voltage.

The control terminal of the fifteenth thin film transistor M9A inputs the second clock signal CKm + 4, and the two path terminals of the fifteenth thin film transistor M9A are respectively connected to the pull-up control node netAn of this stage and the input constant voltage low level VSS. The fifteenth thin film transistor M9A clears the pull-up control node netAn and controls the forward and reverse scan switching. The second clock signal CKm + 4 is input in the positive sequence when the forward scan is performed, and the second clock is input when the reverse scan is performed. Signal CKm + 4 is input in reverse order.

In the embodiment of the present invention, the seventh thin film transistor M1A and the ninth thin film transistor M1B, which are the main precharging elements in the forward and reverse scanning control module 01, adopt a diode connection to avoid the negative drift of the thin film transistor from affecting the circuit function. At the same time, the second clock signal CKm + 4 is used to implement the functions of forward scan and reverse scan control.

As shown in FIG. 7, specifically, the pull-up module 02 includes a tenth thin film transistor M10. The control terminal of the tenth thin film transistor M10 is connected to the pull-up control node netAn of this stage, and the two path ends of the tenth thin film transistor M10 are respectively connected to the first clock signal CKm and the gate scanning signal line of the stage. The tenth thin film transistor M10 performs pull-up output and pull-down to clear the gate scan signal line of this stage.

As shown in FIG. 7, specifically, the touch assist module 03 includes a fourteenth thin film transistor M14.

The control terminal of the fourteenth thin film transistor M14 inputs the touch control signal TC1, and the two path terminals of the fourteenth thin film transistor M14 are respectively connected to the gate scan signal line of this stage and the constant voltage low level VSS input. The fourteenth thin film transistor M14 maintains the gate scan signal line of the current level through the touch control signal TC1 during the touch detection phase.

The control terminal of the fourteenth thin film transistor M14 inputs the touch control signal TC1, and the two path terminals of the fourteenth thin film transistor M14 are respectively connected to the pull-up control node netAn at this stage and the input constant voltage low level VSS. The fourteenth thin film transistor M14 maintains the potential of the pull-up control node netAn at this stage through the touch control signal TC1 during the touch detection phase, and clears the charge of the pull-up control node netAn at this stage at the end of each frame and when the machine is turned on and off .

In an alternative implementation manner, the gate driving unit circuit according to the embodiment of the present invention may further include a first capacitor C1 connected between the pull-up control node netAn at this stage and the gate scan signal line at the current stage. Is responsible for raising the voltage of the pull-up control node netAn of this stage during the output of the gate scan signal Gn of this stage.

8 is a schematic diagram of driving waveforms of a touch control signal TC1 and a touch high VGH2 in a gate driving unit circuit according to the first embodiment of the present invention. As shown in FIG. 8, the touch high-level VGH2 divides a frame time into a pre-touch detection phase, a touch detection phase, and a post-touch detection phase. The touch high-level VGH2 is in the touch detection phase. Low level, high level before and after touch detection; touch control signal TC1 rises from low level to high level before touch detection, during touch detection The later stage is reduced from high to low. As shown in FIG. 8, the time when the touch high level VGH2 is at the low level is slightly shorter than the time when the touch control signal TC1 is at the high level and the level is high. The time period during which the touch control signals TC1 are all at a high level.

The working principle of the memory compensation module 05 in this embodiment is described below. The main action process is as follows:

Step①: When the first thin film transistor M1A in the forward and reverse scan control module 01 receives the high-level previous-stage gate scan signal, the voltage of the pull-up control node netAn rises to the first stage voltage, and the fourth thin film transistor M4 is turned on at the same time. , Copying the voltage information of the pull-up control node netAn to the first memory compensation node netCn, so that the first memory compensation node netCn is raised to the first memory voltage, and the first copy is completed;

Step②: The touch control signal TC1 rises from a low level to a high level. The first memory compensation node netCn of the high level controls the fifteenth thin film transistor M15 to turn on. By controlling the voltage of the touch control signal TC1 and the maintaining time of this step Raise the second memory compensation node netDn to the second memory voltage to complete the second copy. The second memory voltage at a high level can control the first thin film transistor M1 to turn on;

Step③: The touch control signal VGH2 is lowered from a high level to a low level, the potential of the pull-up control node netAn is pulled down through the first thin film transistor M1, and the charge of the pull-up control node netAn is cleared; since the fourth thin film transistor is The transistor (Diode) is connected, the first memory compensation node netCn is still maintained at a high level, and the touch control signal TC1 is at a high level, so that the second memory compensation node netDn is maintained at a high level; the driving circuit enters the touch detection During the testing phase, the pull-up control nodes netAn of all stages are maintained at a low level, and the bias stress of the tenth thin film transistor M10 in different stages is the same, which can eliminate the pit stop horizontal stripes caused by the different characteristics of the tenth thin film transistor M10;

Step④: After the touch detection is completed, the touch high-level VGH2 is pulled low, and then cooperate with the second memory compensation node netDn to control the first thin film transistor M1 to turn on, and the touch high-level VGH2 input is pulled up. The control node netAn raises the voltage of the pull-up control node netAn, and the voltage of the touch-up pause-level pull-up control node netAn is pulled up again. At the same time, it can be performed by adjusting the touch high-level VGH2 voltage and the time of this step Compensation, so that the voltage of the pull-up control node netAn rises back to the first stage voltage;

Step ⑤: The touch control signal TC1 is reduced from a high level to a low level, the voltage of the second memory compensation node netDn is pulled down, and the first thin film transistor M1 is turned off, which effectively prevents the first thin film transistor M1 from controlling the pull-up during normal output. Influence of node netAn;

Step ⑥: The eighteenth thin film transistor M9B is turned on, and the charge of the first memory compensation node netCn is cleared, and at the same time, it is responsible for the subsequent maintenance of the first memory compensation node netCn.

Embodiment two:

FIG. 9 is a circuit diagram of a gate driving unit circuit according to a second embodiment of the present invention. As shown in FIG. 9, the second embodiment is improved on the basis of the first embodiment. The specific improvement lies in that the touch high-level VGH2 input by the first thin film transistor M1 of the compensation sub-module 05A is changed to the second start signal GSP2. .

In the embodiment of the present invention, the touch control signal TC1 rises from a low level to a high level before the touch detection stage, and decreases from a high level to a low level after the touch detection stage; the second start signal GSP2 The driving waveform of the touch control signal TC1 is shown in FIG. 10. The second start signal GSP2 is high only during the start time Td before the touch control signal TC1 decreases from high to low, and the remaining time is Low.

The second start signal GSP2 is specifically responsible for the start after the touch is paused. Compared to the high touch VGH2 in the first embodiment, the second start signal GSP2 and the touch control signal TC1 are both at low power during the non-touch detection phase. Flat, the first memory compensation node netCn and the second memory compensation node netDn are at a low potential for a long period of time. The bias stresses on the first thin film transistor M1, the fourth thin film transistor M4, and the fifteenth thin film transistor M14 in the memory compensation module 05 Weak, the drift of the threshold voltage is small, which is conducive to improving the stability of the circuit.

FIG. 11 is a schematic diagram of driving waveforms of the circuit shown in FIG. 9 during forward scanning. The figure shows the waveform when the circuit is driven with 4 clock signals (the number of clock signals can be adjusted in practical applications):

GSP1 is the first start signal and is responsible for starting during forward scanning and reverse scanning;

CK1, CK3, CK5, and CK7 are clock signals, which are output in positive sequence during forward scanning;

CLR1 is a clear reset signal, which is mainly responsible for clearing the charge of the internal nodes of the circuit at the end of each frame and when it is turned on and off;

TC1 is a touch control signal, which assists in maintaining the potential of the gate scan signal line, the pull-up control node netAn, and the control node netBn during the touch detection phase;

VGH1 is a constant voltage high level and is mainly responsible for maintaining the input of submodule 04A;

GSP2 is the second startup signal, which is mainly responsible for pulling down the pull-up control node netAn during the touch detection phase, and pulling up the voltage of the pull-up control node netAn and performing compensation after the touch is completed;

VSS is a constant voltage low level VSS, which is mainly responsible for providing the low potential of the gate scan signal Gn;

Other waveforms such as netA1, netA2, netAlast-1, and netAlast are the output waveforms of the internal nodes of the circuit, and G1, G2, and Glast are the waveforms of the gate scan signals output by the gate drive unit circuits at each level.

FIG. 12 is a schematic diagram of driving waveforms of the circuit shown in FIG. 9 during reverse scanning. The figure shows the waveform when the circuit driver uses 4 clock signals (the number of clock signals can be adjusted in practical applications):

CK1, CK3, CK5, and CK7 are clock signals, which are output in reverse order when scanning in reverse;

The touch control signal at TC1 assists in maintaining the potential of the gate scan signal line, the pull-up control node netAn, and the control node netBn at the touch detection stage;

As shown in FIG. 11 and FIG. 12, the gate driving unit circuit of the embodiment of the present invention uses the existing signals to implement the forward and reverse scanning function, and does not require additional control signals for forward and reverse scanning, and only needs one start signal GSP1 on one side. It is beneficial to narrow the border of the display panel.

An embodiment of the present invention further provides a gate driving circuit, which includes an N-level gate driving unit circuit as shown in any of the foregoing embodiments. Wherein, N is a positive integer greater than 4.

An embodiment of the present invention further provides a display device including the above-mentioned gate driving circuit. The gate driving circuit may be a left-right interleaved driving method, a non-left-right interleaved bilateral driving method, or a unilateral driving method.

It should be noted that the above embodiments can be freely combined as required. The above is only a preferred embodiment of the present invention. It should be noted that, for those of ordinary skill in the art, without departing from the principle of the present invention, a number of improvements and retouches can be made. These improvements and retouches also It should be regarded as the protection scope of the present invention.

Claims

A gate drive unit circuit is suitable for multi-level connection to form a gate drive circuit, and is characterized by comprising a forward and reverse scan control module, a pull-up module, a touch assist module, a maintenance assist module, and a memory compensation module; The anti-sweep control module, pull-up module, maintenance assistance module and memory compensation module are connected to the pull-up control node of this level; the pull-up module and touch-assistance module are connected to the gate-scan signal line of this level;

The memory compensation module includes a compensation sub-module, a memory sub-module, and a secondary memory sub-module; the memory sub-module and the secondary memory sub-module are connected to the first memory compensation node, and the compensation sub-module and the secondary memory sub-module are connected to The second memory compensation node, the compensation sub-module and the memory sub-module are connected to a pull-up control node of this level, the compensation sub-module inputs a touch start signal, and the secondary memory sub-module inputs a touch control signal;

The compensation sub-module is used to pull down the voltage of the pull-up control node of this stage from the voltage of the first stage to the voltage of the second stage in the touch detection stage, and pull up the control of this stage in the post-touch detection stage. The voltage of the node is pulled up to the first stage voltage;

The memory sub-module is used to copy the voltage of the pull-up control node at this level to the first memory compensation node before the touch detection stage, so that the voltage of the first memory compensation node is raised to the first memory voltage;

The secondary memory sub-module is configured to raise the voltage of the second memory compensation node to a second memory voltage under the input of the touch control signal in the pre-touch detection stage.
The gate driving unit circuit according to claim 1, wherein the memory compensation module further comprises a pull-down sub-module and a node control sub-module; the pull-down sub-module and the node control sub-module are connected to the first memory compensation Node, node control sub-module and maintenance auxiliary module are connected to the maintenance control node at this level;

The pull-down sub-module is used to pull down the voltage of the first memory compensation node to a low level and maintain it in the post-touch detection stage;

The node control sub-module is configured to pull the voltage of the control node of the current stage to a low level when the first memory compensation node is at a high level of the first memory voltage.
The gate driving unit circuit according to claim 2, wherein the compensation sub-module comprises a first thin film transistor, a control end of the first thin film transistor is connected to the second memory compensation node, and the first One channel terminal inputs the touch start signal, and the second channel terminal is connected to the pull-up control node of this level;

The memory sub-module includes a fourth thin film transistor, the control end of the fourth thin film transistor and the first path end are short-circuited and connected to the pull-up control node of this level, and the second path end is connected to the first memory compensation node;

The secondary memory sub-module includes a fifteenth thin film transistor, a control end of the fifteenth thin film transistor is connected to a current level control node, a first path end inputs a touch control signal, and a second path end is connected to a second memory compensation node;

The pull-down sub-module includes an eighteenth thin film transistor, a control terminal of the eighteenth thin film transistor inputs a second clock signal, a first path end is connected to a first memory compensation node, and a second path end inputs a constant voltage low level;

The node control sub-module includes a sixteenth thin film transistor, a control end of the sixteenth thin film transistor is connected to a first memory compensation node, a first path end is connected to a current-level maintenance control node, and a second path end inputs a constant voltage low level.
The gate driving unit circuit according to claim 1, wherein the forward and reverse scanning control module comprises a seventh thin film transistor, a ninth thin film transistor, and a fifteenth thin film transistor;

The control terminal of the seventh thin film transistor and the first path terminal are short-circuited and a first control signal is input, and the second path terminal is connected to the pull-up control node of this stage;

The control terminal of the ninth thin film transistor and the first path terminal are short-circuited and a second control signal is input, and the second path terminal is connected to the pull-up control node of this stage;

The control terminal of the fifteenth thin film transistor inputs a second clock signal, the first path terminal is connected to the pull-up control node of this stage, and the second path terminal inputs a constant voltage low level.
The gate drive unit circuit according to claim 4, wherein:

When the gate drive unit circuit is a first-stage gate drive unit circuit, the first control signal is a first start signal; otherwise, the first control signal is a previous-stage gate scan signal;

When the gate driving unit circuit is a tail-stage gate driving unit circuit, the second control signal is a first start signal; otherwise, the second control signal is a subsequent-stage gate scan signal.
The gate driving unit circuit according to claim 1, wherein:

The touch assist module includes a fourteenth thin film transistor, a control terminal of the fourteenth thin film transistor inputs a touch control signal, a first path end is connected to a gate scanning signal line of this stage, and a second path end inputs a constant voltage low level .
The gate driving unit circuit according to claim 1, wherein:

The maintenance auxiliary module includes a maintenance sub-module and an empty sub-module, and the maintenance sub-module and the empty sub-module and the memory compensation module are connected to a current-level maintenance control node;

The maintenance sub-module is used for charging and discharging the maintenance control node of the current stage, and maintaining the pull-up control node and the gate scanning signal line of the current stage;

The emptying sub-module is used for emptying the charge of the pull-up control node of the current stage and the maintenance control node of the current stage when the frame ends and the machine is turned on and off.
The gate driving unit circuit according to claim 7, wherein:

The maintenance sub-module includes a fifth thin film transistor, a sixth thin film transistor, an eighth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, and a seventeenth thin film transistor;

The control terminal of the fifth thin film transistor and the first path terminal are short-circuited and input a constant high voltage level, and the second path terminal is connected to the current stage maintenance control node;

The control terminal of the sixth thin film transistor is connected to the pull-up control node, the first path terminal is connected to the current stage maintenance control node, and the second path terminal inputs a constant voltage low level;

The control terminal of the eighth thin film transistor is connected to the maintenance control node, the first path terminal is connected to the pull-up control node of this stage, and the constant voltage low level is input to the second path terminal;

The control terminal of the eleventh thin film transistor inputs the gate scanning signal of the previous stage, the first path terminal is connected to the current stage maintenance control node, and the second path terminal inputs the constant voltage low level;

The control terminal of the twelfth thin film transistor inputs the gate scanning signal of the subsequent stage, the first path terminal is connected to the current stage maintenance control node, and the second path terminal inputs the constant voltage low level;

The control terminal of the thirteenth thin film transistor is connected to the maintenance control node, the first path terminal is connected to the gate scanning signal line of this stage, and the constant voltage low level is input to the second path terminal;

The control terminal of the seventeenth thin film transistor is connected to the memory compensation node, the first path terminal is connected to the current stage maintenance control node, and the second path terminal is input with a constant low voltage level.
The gate driving unit circuit according to claim 7, wherein:

The emptying sub-module includes a second thin film transistor and a third thin film transistor;

The control terminal of the second thin film transistor inputs a clear reset signal, the first path terminal is connected to the pull-up control node of this stage, and the second path terminal inputs a constant voltage low level;

The control terminal of the third thin film transistor inputs a clear reset signal, the first path terminal is connected to the current stage maintenance control node, and the second path terminal inputs a constant voltage low level.
A gate driving circuit, comprising the N-level gate driving unit circuit according to any one of claims 1 to 9, wherein N is a positive integer greater than 4.
A display device, comprising the gate driving circuit according to claim 10.