CN109064964B - Shifting register unit, driving method, grid driving circuit and display device - Google Patents
Shifting register unit, driving method, grid driving circuit and display device Download PDFInfo
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- CN109064964B CN109064964B CN201811085216.7A CN201811085216A CN109064964B CN 109064964 B CN109064964 B CN 109064964B CN 201811085216 A CN201811085216 A CN 201811085216A CN 109064964 B CN109064964 B CN 109064964B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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Abstract
The invention provides a shift register unit, a driving method, a grid driving circuit and a display device. The shift register unit comprises N control voltage ends, N output circuits and N pull-up node control circuits, wherein the nth pull-up node control circuit is respectively connected with the nth control voltage end, the nth pull-up node and the input end and is used for controlling the communication between the nth pull-up node and the input end under the control of the nth control voltage end and the input end in the nth display time period; the nth output circuit is respectively connected with the nth pull-up node, the grid driving signal output end and the output signal end and is used for controlling the grid driving signal output end to be communicated with the output signal end under the control of the nth pull-up node; n is an integer greater than 1, and N is a positive integer less than or equal to N. The invention reduces the characteristic drift of the transistor caused by the long-term continuous operation or high-temperature reliability evaluation of the transistor.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register unit, a driving method, a grid driving circuit and a display device.
Background
In the display process of the display panel, the grid driving circuit is used for generating grid driving signals and scanning pixels of each row line by line. The Gate driver On Array (GOA) is a technology for integrating Gate driver circuits On an Array substrate, and each GOA unit is used as a shift register unit to sequentially transmit scanning signals to the next GOA unit, and turn On TFTs (thin film transistors) row by row to complete data signal input of pixel units. The current GOA circuit has its own drawbacks: the transistor may not operate within a controllable range due to characteristic drift of the transistor caused by long-term continuous operation or high-temperature reliability evaluation of the transistor, which may cause abnormal display of the display panel.
When the existing GOA unit works normally, the potential of a pull-up node can reach 50V-60V due to the bootstrap effect of a capacitor, the characteristics of a transistor are easy to drift when the grid of the transistor is connected with high voltage, and after the grid of the transistor is connected with the high voltage for a period of time, the transistor with the grid connected with the pull-up node cannot work in a controllable range, so that a display panel cannot normally display.
Disclosure of Invention
The invention mainly aims to provide a shift register unit, a driving method, a grid driving circuit and a display device, and solves the problems that in the prior art, when a transistor continuously works for a long time or is evaluated at high temperature, the characteristic of the transistor is drifted, the transistor cannot work in a controllable range, and a display panel cannot normally display.
In order to achieve the above object, the present invention provides a shift register unit comprising N control voltage terminals, N output circuits, and N pull-up node control circuits, wherein,
the nth pull-up node control circuit is respectively connected with the nth control voltage end, the nth pull-up node and the input end and is used for controlling the communication between the nth pull-up node and the input end under the control of the nth control voltage end and the input end in the nth display time period;
the nth output circuit is respectively connected with the nth pull-up node, the grid driving signal output end and the output signal end and is used for controlling the grid driving signal output end to be communicated with the output signal end under the control of the nth pull-up node;
n is an integer greater than 1, and N is a positive integer less than or equal to N.
In practice, the nth pull-up node control circuit includes a 2n-1 th control transistor and a 2 nth control transistor, wherein,
the control electrode of the 2n-1 control transistor is connected with the nth control voltage end, and the first electrode of the 2n-1 control transistor is connected with the input end;
a control electrode of the 2 n-th control transistor and a first electrode of the 2 n-th control transistor are both connected to a second electrode of the 2 n-1-th control transistor, and a second electrode of the 2 n-th control transistor is connected to the nth pull-up node.
In practice, the nth output circuit includes an nth output transistor and an nth storage capacitor, wherein,
a control electrode of the nth output transistor is connected with the nth pull-up node, a first electrode of the nth output transistor is connected with the output signal end, and a second electrode of the nth output transistor is connected with the gate drive signal output end;
the first end of the nth storage capacitor is connected with the nth pull-up node, and the second end of the nth storage capacitor is connected with the gate driving signal output end.
In implementation, the shift register unit further comprises a pull-up node reset circuit, a pull-down node control circuit and an output reset circuit;
the pull-up node reset circuit is respectively connected with a reset terminal, a pull-down node and N pull-up nodes and is used for controlling the potentials of the N pull-up nodes to be reset under the control of the reset terminal and/or the pull-down node;
the pull-down node control circuit is respectively connected with a pull-down control clock signal end, a pull-down node and the N pull-up nodes and is used for controlling the potential of the pull-down node under the control of the N pull-up nodes and the pull-down control clock signal end;
the output reset circuit is respectively connected with the pull-down node, the reset end, the grid driving signal output end and the reset voltage end, and is used for controlling the grid driving signal output end to be communicated with the reset voltage end under the control of the pull-down node and the reset end.
In implementation, the pull-up node reset circuit comprises N pull-up node reset sub-circuits;
the nth pull-up node reset sub-circuit includes a 2n-1 th pull-up reset transistor and a 2 nth pull-up reset transistor, wherein,
a control electrode of the 2n-1 pull-up reset transistor is connected with the reset end, a first electrode of the 2n-1 pull-up reset transistor is connected with the nth pull-up node, and a second electrode of the 2n-1 pull-up reset transistor is connected with the first voltage end;
the control electrode of the 2n pull-up reset transistor is connected with the pull-down node, the first electrode of the 2n pull-up reset transistor is connected with the n pull-up node, and the second electrode of the 2n pull-up reset transistor is connected with the first voltage end.
In implementation, the pull-down node control circuit comprises a pull-down control sub-circuit and N pull-down node control sub-circuits;
the pull-down control sub-circuit comprises a first pull-down control transistor and a second pull-down control transistor, and the nth pull-down node control sub-circuit comprises a 2n-1 pull-down node control transistor and a 2 nth pull-down node control transistor;
a control electrode of the first pull-down control transistor and a first electrode of the first pull-down control transistor are both connected with the pull-down control clock signal end, and a second electrode of the first pull-down control transistor is connected with a pull-down control node;
a control electrode of the second pull-down control transistor is connected with the pull-down control node, and a first electrode of the second pull-down control transistor is connected with the pull-down control clock signal end;
a control electrode of the 2n-1 pull-down node control transistor is connected with an nth pull-up node, a first electrode of the 2n-1 pull-down node control transistor is connected with the pull-down control node, and a second electrode of the 2n-1 pull-down node control transistor is connected with a first voltage end;
the control electrode of the 2 nth pull-down node control transistor is connected with the nth pull-up node, the first electrode of the 2 nth pull-down node control transistor is connected with the second electrode of the second pull-down control transistor, and the second electrode of the 2 nth pull-down node control transistor is connected with the first voltage end.
In practice, the output reset circuit includes a first output reset transistor and a second output reset transistor, wherein,
a control electrode of the first output reset transistor is connected with the pull-down node, a first electrode of the first output reset transistor is connected with the gate drive signal output end, and a second electrode of the first output reset transistor is connected with the first voltage end;
the control electrode of the second output reset transistor is connected with the reset end, the first electrode of the second output reset transistor is connected with the grid drive signal output end, and the second electrode of the first output reset transistor is connected with the first voltage end.
The invention also provides a driving method of the shift register unit, which is applied to the shift register unit, wherein the display period comprises a plurality of display stages, and the display stages comprise N display time periods which are sequentially set; the driving method of the shift register unit comprises the following steps:
in the nth display time period, the nth control voltage end outputs effective voltage, and the other control voltage ends except the nth control voltage end output ineffective voltage so as to control the communication between the nth pull-up node and the input end when the effective voltage is input into the input end;
n is an integer greater than 1, and N is a positive integer less than or equal to N.
The invention also provides a grid driving circuit which comprises a plurality of cascaded shift register units.
The invention also provides a display device which comprises the grid drive circuit.
Compared with the prior art, the shift register unit, the driving method, the grid driving circuit and the display device adopt at least two pull-up nodes, in the corresponding display time period, the corresponding pull-up node control circuit works to control the potential of the corresponding pull-up node to be effective voltage in the input stage and the output stage included in the display time period, thereby controlling the transistor with the grid electrode connected with the pull-up node to be conducted and simultaneously controlling the potentials of other pull-up nodes to be invalid voltage, so as to realize that at least two pull-up nodes alternately output effective voltage, the corresponding output circuits alternately work to ensure that the pull-up nodes are fully discharged, and the characteristic drift caused by the long-term continuous work or high-temperature reliability evaluation of a transistor of which the grid electrode is connected with the pull-up node and included in the shift register unit is reduced, and the service life and the stability of the transistor are increased.
Drawings
FIG. 1 is a block diagram of a shift register unit according to an embodiment of the present invention;
FIG. 2 is a block diagram of a shift register unit according to another embodiment of the present invention;
FIG. 3 is a block diagram of a shift register unit according to another embodiment of the present invention;
FIG. 4 is a circuit diagram of one embodiment of a shift register cell according to the present invention;
FIG. 5 is a timing diagram illustrating operation of the shift register unit according to the embodiment of the present invention in a first display period;
FIG. 6 is a timing diagram illustrating operation of the shift register unit according to the embodiment of the present invention in a second display period;
FIG. 7 is a timing diagram illustrating the operation of the shift register unit according to the present invention;
fig. 8 is a structural diagram of a gate driving circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
The shift register unit according to the embodiment of the present invention includes N control voltage terminals, N output circuits, and N pull-up node control circuits,
the nth pull-up node control circuit is respectively connected with the nth control voltage end, the nth pull-up node and the input end and is used for controlling the communication between the nth pull-up node and the input end under the control of the nth control voltage end and the input end in the nth display time period;
the nth output circuit is respectively connected with the nth pull-up node, the grid driving signal output end and the output signal end and is used for controlling the grid driving signal output end to be communicated with the output signal end under the control of the nth pull-up node;
n is an integer greater than 1, and N is a positive integer less than or equal to N.
In practical operation, the output signal terminal may be an output clock signal terminal, but not limited thereto, and in specific implementation, the output signal terminal may also be a dc voltage terminal.
The shift register unit adopts at least two pull-up nodes, and in a corresponding display time period, the corresponding pull-up node control circuit works to control the potential of the corresponding pull-up node to be effective voltage in an input stage and an output stage included in the display time period, so that a transistor with a grid connected with the pull-up node is controlled to be conducted, and the potentials of other pull-up nodes are controlled to be invalid voltages at the same time, so that the effective voltage is alternately output by at least one pull-up node, the corresponding output circuit works alternately, full discharge of the pull-up node is ensured, characteristic drift caused by long-term continuous work or high-temperature reliability evaluation of the transistor with the grid connected with the pull-up node included in the shift register unit is reduced, and the service life and the stability of the transistor are improved.
In specific implementation, the effective voltage is a voltage capable of turning on a transistor with a gate connected thereto, and the ineffective voltage is a voltage capable of turning off the transistor with the gate connected thereto. For example, when the transistor is an n-type transistor, the active voltage is a high voltage and the inactive voltage is a low voltage; when the transistor is a p-type transistor, the active voltage is a low voltage and the inactive voltage is a high voltage.
In the embodiment of the present invention, N is equal to 2 for example, and in actual operation, N may be other integers greater than 1.
Specifically, the shift register unit according to the embodiment of the present invention may further include a pull-up node reset circuit, a pull-down node control circuit, and an output reset circuit;
the pull-up node reset circuit is respectively connected with a reset terminal, a pull-down node and N pull-up nodes and is used for controlling the potentials of the N pull-up nodes to be reset under the control of the reset terminal and/or the pull-down node;
the pull-down node control circuit is respectively connected with a pull-down control clock signal end, a pull-down node and the N pull-up nodes and is used for controlling the potential of the pull-down node under the control of the N pull-up nodes and the pull-down control clock signal end;
the output reset circuit is respectively connected with the pull-down node, the reset end, the grid driving signal output end and the reset voltage end, and is used for controlling the grid driving signal output end to be communicated with the reset voltage end under the control of the pull-down node and the reset end.
In practical operation, the reset voltage terminal may be a low voltage terminal or a ground terminal, but not limited thereto.
In specific implementation, the pull-up node reset circuit resets the potentials of the N pull-up nodes in a reset stage and an output cut-off holding stage, the pull-down node control circuit controls the potentials of the pull-down nodes in an nth display time period under the control of an nth pull-up node and the pull-down control clock signal terminal, and the output reset circuit resets the gate driving signal output by the gate driving signal terminal.
As shown in fig. 1, the shift register unit according to the embodiment of the present invention includes a first control voltage terminal, a second control voltage terminal, a first pull-up node control circuit 101, a second pull-up node control circuit 102, a first output circuit 111, a second output circuit 112, a pull-up node reset circuit 12, a pull-down node control circuit 13, and an output reset circuit 14;
the first control voltage end is used for inputting a first control voltage VDDO, and the second control voltage end is used for inputting a second control voltage VDDE;
the first pull-up node control circuit 101 is respectively connected to the first control voltage terminal, the first pull-up node PU1 and the INPUT terminal INPUT, and is configured to control the connection between the first pull-up node PU1 and the INPUT terminal INPUT under the control of the first control voltage terminal and the INPUT terminal INPUT in a first display time period;
the second pull-up node control circuit 102 is respectively connected to the second control voltage terminal, a second pull-up node PU2 and an INPUT terminal INPUT, and is configured to control the connection between the second pull-up node PU2 and the INPUT terminal INPUT under the control of the second control voltage terminal and the INPUT terminal INPUT in a second display time period;
the first OUTPUT circuit 111 is respectively connected to the first pull-up node PU1, the gate driving signal OUTPUT terminal OUTPUT and the OUTPUT clock signal terminal, and is configured to control the gate driving signal OUTPUT terminal OUTPUT to access the OUTPUT clock signal CLKA under the control of the first pull-up node PU 1;
the second OUTPUT circuit 112 is respectively connected to the second pull-up node PU2, the gate driving signal OUTPUT terminal OUTPUT and the OUTPUT clock signal terminal, and is configured to control the gate driving signal OUTPUT terminal OUTPUT to access the OUTPUT clock signal CLKA under the control of the second pull-up node PU 2; the output clock signal CLKA is provided by the output clock signal terminal;
the pull-up node Reset circuit 12 is respectively connected to a Reset terminal Reset, a pull-down node PD, a first pull-up node PU1, a second pull-up node PU2, and a low voltage terminal, and is configured to control the communication between the first pull-up node PU1 and the low voltage terminal and the communication between the second pull-up node PU2 and the low voltage terminal under the control of the Reset terminal Reset and/or the pull-down node PD, so as to Reset the potential of the first pull-up node PU1 and the potential of the second pull-up node PU 2; the low voltage end is used for inputting low voltage VSS;
the pull-down node control circuit 13 is respectively connected to a pull-down control clock signal terminal, a pull-down node PD, the first pull-up node PU1, the second pull-up node PU2 and the low voltage terminal, and is configured to control a potential of the pull-down node PD under control of the first pull-up node PU1, the second pull-up node PU2 and the pull-down control clock signal terminal; the pull-down control clock signal terminal is used for providing a pull-down control clock signal CLKB;
the OUTPUT Reset circuit 14 is connected to the pull-down node PD, the Reset terminal Reset, the gate driving signal OUTPUT terminal OUTPUT and the low voltage terminal, and is configured to control the gate driving signal OUTPUT terminal OUTPUT and the low voltage terminal to communicate with each other under the control of the pull-down node PD and the Reset terminal Reset.
In the embodiment shown in fig. 1, the output signal terminal is taken as an output clock signal terminal for illustration.
When the embodiment of the shift register unit shown in fig. 1 of the present invention works, VDDO and VDDE are alternately effective voltages, and VDDO and VDDE (the polarity inversion period may be 2s (seconds) -3s) with opposite polarities are used to respectively control the corresponding pull-up node control circuits, so as to ensure that the first pull-up node control circuit 101 and the second pull-up node control circuit 122 alternately work, so that the first output circuit 111 and the second output circuit 112 alternately work, so that two pull-up nodes can alternately output effective voltages, when PU1 or PU2 does not output an effective voltage, the effective voltage can be discharged for many times, so as to ensure that the pull-up node is fully discharged, and because the first output circuit 111 and the second output circuit 112 alternately work, the working time of a transistor with a gate connected to the pull-up node can be reduced, so as to improve the condition of characteristic drift of the transistor, the lifetime and stability of the transistor are enhanced.
Specifically, the nth pull-up node control circuit may include a 2n-1 th control transistor and a 2 nth control transistor, wherein,
the control electrode of the 2n-1 control transistor is connected with the nth control voltage end, and the first electrode of the 2n-1 control transistor is connected with the input end;
a control electrode of the 2 n-th control transistor and a first electrode of the 2 n-th control transistor are both connected to a second electrode of the 2 n-1-th control transistor, and a second electrode of the 2 n-th control transistor is connected to the nth pull-up node.
In particular implementations, the nth output circuit may include an nth output transistor and an nth storage capacitor, wherein,
a control electrode of the nth output transistor is connected with the nth pull-up node, a first electrode of the nth output transistor is connected with the output signal end, and a second electrode of the nth output transistor is connected with the gate drive signal output end;
the first end of the nth storage capacitor is connected with the nth pull-up node, and the second end of the nth storage capacitor is connected with the gate driving signal output end.
As shown in fig. 2, on the basis of the embodiment of the shift register cell shown in fig. 1,
the first pull-up node control circuit 101 includes a first control transistor M15 and a second control transistor M1;
the gate of the first control transistor M15 is connected to the first control voltage terminal, and the drain of the first control transistor M15 is connected to the INPUT terminal INPUT;
the gate of the second control transistor M1 and the drain of the second control transistor M1 are both connected to the source of the first control transistor M15, and the source of the second control transistor M1 is connected to the first pull-up node PU 1;
the first control voltage end is used for inputting a first control voltage VDDO;
the second pull-up node control circuit 102 includes a third control transistor M16 and a fourth control transistor M14;
the gate of the third control transistor M16 is connected to the second control voltage terminal, and the drain of the third control transistor M16 is connected to the INPUT terminal INPUT;
the gate of the fourth control transistor M14 and the drain of the fourth control transistor M14 are both connected to the source of the third control transistor M16, and the source of the fourth control transistor M14 is connected to the second pull-up node PU 2;
the second control voltage terminal is used for inputting a second control voltage VDDO;
the first output circuit 111 includes a first output transistor M3 and a first storage capacitor C1; the second output circuit 112 includes a second output transistor M3' and a second storage capacitor C2, wherein,
the gate of the first OUTPUT transistor M3 is connected to the first pull-up node PU1, the drain of the first OUTPUT transistor M3 is connected to the OUTPUT clock signal CLKA, and the source of the first OUTPUT transistor M3 is connected to the gate driving signal OUTPUT terminal OUTPUT;
a first terminal of the first storage capacitor C1 is connected to the first pull-up node PU1, and a second terminal of the first storage capacitor C1 is connected to the gate driving signal OUTPUT terminal OUTPUT;
the gate of the second OUTPUT transistor M3 ' is connected to the second pull-up node PU2, the drain of the second OUTPUT transistor M3 ' is connected to the OUTPUT clock signal CLKA, and the source of the second OUTPUT transistor M3 ' is connected to the gate driving signal OUTPUT terminal OUTPUT;
a first terminal of the second storage capacitor C2 is connected to the second pull-up node PU2, and a second terminal of the second storage capacitor C2 is connected to the gate driving signal OUTPUT terminal OUTPUT.
In the embodiment shown in fig. 2, all transistors are n-type TFTs (thin film transistors), but not limited thereto.
When the specific embodiment of the shift register unit shown in fig. 2 of the present invention works, the display cycle includes a plurality of display phases, where the display phases include a first display time period and a second display time period that are sequentially set, and the duration of each display time period may be 2s-3s, but not limited thereto, and the duration of the display time period may be set according to an actual situation.
In operation of the embodiment of the shift register cell of the present invention shown in figure 2,
in the first display time period, VDDO is high voltage, VDDE is low voltage, M15 is opened, M16 is closed, the grid of M1 is communicated with the INPUT, the grid of M14 is floating, and in the INPUT stage in the first display time period, when the INPUT INPUTs high level, M1 is opened, so that the potential of PU1 becomes high level, and the potential of PU2 is maintained to be low level; in the output phase in the first display period, the potential of PU1 further rises due to bootstrap of C1; in the input stage in the first display period and the output stage in the first display period, the first output circuit 111 operates, and the second output circuit 112 does not operate; resetting the potential of PU1 and the potential of PU2 in a reset phase in the first display period and an output off hold phase in the first display period so that the potential of PU1 and the potential of PU2 are both at a low level;
in the second display time period, VDDO is low voltage, VDDE is high voltage, M15 is closed, M16 is opened, the grid of M14 is communicated with the INPUT, the grid of M1 is floating, in the INPUT stage in the second display time period, when the INPUT INPUTs high level, M14 is opened, so that the potential of PU2 becomes high level, and the potential of PU1 is maintained to be low level; in the output phase in the second display period, the potential of PU1 further rises due to bootstrap of C1; in the input stage in the second display period and the output stage in the second display period, the second output circuit 112 operates, and the first output circuit 111 does not operate; in the reset phase in the second display period and the output off hold phase in the second display period, the potential of PU1 and the potential of PU2 are reset so that the potential of PU1 and the potential of PU2 are both at a low level.
In a specific implementation, the pull-up node reset circuit may include N pull-up node reset sub-circuits, and the nth pull-up node is reset by the nth pull-up node reset sub-circuit;
the nth pull-up node reset sub-circuit includes a 2n-1 th pull-up reset transistor and a 2 nth pull-up reset transistor, wherein,
a control electrode of the 2n-1 pull-up reset transistor is connected with the reset end, a first electrode of the 2n-1 pull-up reset transistor is connected with the nth pull-up node, and a second electrode of the 2n-1 pull-up reset transistor is connected with the first voltage end;
the control electrode of the 2n pull-up reset transistor is connected with the pull-down node, the first electrode of the 2n pull-up reset transistor is connected with the n pull-up node, and the second electrode of the 2n pull-up reset transistor is connected with the first voltage end.
In practical operation, the first voltage terminal may be a low voltage terminal or a ground terminal, but is not limited thereto.
Specifically, the pull-down node control circuit may include a pull-down control sub-circuit and N pull-down node control sub-circuits;
the pull-down control sub-circuit comprises a first pull-down control transistor and a second pull-down control transistor, and the nth pull-down node control sub-circuit comprises a 2n-1 pull-down node control transistor and a 2 nth pull-down node control transistor;
a control electrode of the first pull-down control transistor and a first electrode of the first pull-down control transistor are both connected with the pull-down control clock signal end, and a second electrode of the first pull-down control transistor is connected with a pull-down control node;
a control electrode of the second pull-down control transistor is connected with the pull-down control node, and a first electrode of the second pull-down control transistor is connected with the pull-down control clock signal end;
a control electrode of the 2n-1 pull-down node control transistor is connected with an nth pull-up node, a first electrode of the 2n-1 pull-down node control transistor is connected with the pull-down control node, and a second electrode of the 2n-1 pull-down node control transistor is connected with a first voltage end;
the control electrode of the 2 nth pull-down node control transistor is connected with the nth pull-up node, the first electrode of the 2 nth pull-down node control transistor is connected with the second electrode of the second pull-down control transistor, and the second electrode of the 2 nth pull-down node control transistor is connected with the first voltage end.
As shown in fig. 3, the pull-down node control circuit 13 may include a pull-down node control sub-circuit 131, a first pull-down node control sub-circuit 132, and a second pull-down node control sub-circuit 133, wherein,
the pull-down node control sub-circuit 131 includes a first pull-down control transistor M9 and a second pull-down control transistor M5; the first pull-down node control sub-circuit 131 includes a first pull-down node control transistor M8 and a second pull-down node control transistor M6; the second pull-down node control sub-circuit 132 includes a third pull-down node control transistor M8 'and a fourth pull-down node control transistor M6';
the grid electrode of the first pull-down control transistor M9 and the drain electrode of the first pull-down control transistor M9 are both connected to a pull-down control clock signal CLKB, and the source electrode of the first pull-down control transistor M9 is connected with a pull-down control node PDCN;
the gate of the second pull-down control transistor M6 is connected to the pull-down control node PDCN, and the drain of the second pull-down control transistor M6 is connected to the pull-down control clock signal CLKB;
the gate of the first pull-down node control transistor M8 is connected to a first pull-up node PU1, the drain of the first pull-down node control transistor M8 is connected to the pull-down control node PDCN, and the source of the first pull-down node control transistor M8 is connected to a low voltage VSS;
the gate of the second pull-down node control transistor M6 is connected to the first pull-up node PU1, the drain of the second pull-down node control transistor M6 is connected to the source of the second pull-down node control transistor M5, and the source of the second pull-down node control transistor M6 is connected to a low voltage VSS;
the gate of the third pull-down node control transistor M8 ' is connected to the second pull-up node PU2, the drain of the third pull-down node control transistor M8 ' is connected to the pull-down control node PDCN, and the source of the third pull-down node control transistor M8 ' is connected to a low voltage VSS;
the gate of the fourth pull-down node control transistor M6 ' is connected to the second pull-up node PU2, the drain of the fourth pull-down node control transistor M6 ' is connected to the source of the second pull-down node control transistor M5, and the source of the fourth pull-down node control transistor M6 ' is connected to the low voltage VSS.
In the embodiment of the shift register unit shown in fig. 3, all the transistors are n-type TFTs, but not limited thereto.
In the embodiment of the shift register cell shown in fig. 3, the width-to-length ratio of M8 is set to be greater than that of M9, and the width-to-length ratio of M8' is set to be greater than that of M9.
When the embodiment of the shift register unit shown in fig. 3 of the present invention is in operation, when the potential of PU1 is at a high level, the potential of PU2 is at a low level, and CLKB is at a high level, M9, M6, and M8 are turned on, M5, M6 ', and M8' are turned off, and the potential of PDCN and the potential of PD are pulled low; when the potential of PU2 is at high level, the potential of PU1 is at low level, and CLKB is at high level, M9, M5, M6 and M8 are closed, M6 'and M8' are opened, and the potential of PDCN and the potential of PD are pulled down; when both the potential of PU1 and the potential of PU2 are low and CLKB is high, M8, M6, M8 ', and M6' are all off, and M9 and M5 are on to pull up the potential of PDCN and the potential of PD.
In particular implementations, the output reset circuit can include a first output reset transistor and a second output reset transistor, wherein,
a control electrode of the first output reset transistor is connected with the pull-down node, a first electrode of the first output reset transistor is connected with the gate drive signal output end, and a second electrode of the first output reset transistor is connected with the first voltage end;
the control electrode of the second output reset transistor is connected with the reset end, the first electrode of the second output reset transistor is connected with the grid drive signal output end, and the second electrode of the first output reset transistor is connected with the first voltage end.
The shift register unit according to the present invention is described below with reference to an embodiment.
As shown in fig. 4, an embodiment of the shift register unit according to the present invention includes a first control voltage terminal, a second control voltage terminal, a first pull-up node control circuit 101, a second pull-up node control circuit 102, a first output circuit 111, a second output circuit 112, a pull-up node reset circuit 12, a pull-down node control circuit 13, and an output reset circuit 14;
the first control voltage end is used for inputting a first control voltage VDDO, and the second control voltage end is used for inputting a second control voltage VDDE;
the first pull-up node control circuit 101 includes a first control transistor M15 and a second control transistor M1;
the gate of the first control transistor M15 is connected to the first control voltage terminal, and the drain of the first control transistor M15 is connected to the INPUT terminal INPUT;
the gate of the second control transistor M1 and the drain of the second control transistor M1 are both connected to the source of the first control transistor M15, and the source of the second control transistor M1 is connected to the first pull-up node PU 1;
the first control voltage end is used for inputting a first control voltage VDDO;
the second pull-up node control circuit 102 includes a third control transistor M16 and a fourth control transistor M14;
the gate of the third control transistor M16 is connected to the second control voltage terminal, and the drain of the third control transistor M16 is connected to the INPUT terminal INPUT;
the gate of the fourth control transistor M14 and the drain of the fourth control transistor M14 are both connected to the source of the third control transistor M16, and the source of the fourth control transistor M14 is connected to the second pull-up node PU 2;
the second control voltage terminal is used for inputting a second control voltage VDDO;
the first output circuit 111 includes a first output transistor M3 and a first storage capacitor C1; the second output circuit 112 includes a second output transistor M3' and a second storage capacitor C2, wherein,
the gate of the first OUTPUT transistor M3 is connected to the first pull-up node PU1, the drain of the first OUTPUT transistor M3 is connected to the OUTPUT clock signal CLKA, and the source of the first OUTPUT transistor M3 is connected to the gate driving signal OUTPUT terminal OUTPUT;
a first terminal of the first storage capacitor C1 is connected to the first pull-up node PU1, and a second terminal of the first storage capacitor C1 is connected to the gate driving signal OUTPUT terminal OUTPUT;
the gate of the second OUTPUT transistor M3 ' is connected to the second pull-up node PU2, the drain of the second OUTPUT transistor M3 ' is connected to the OUTPUT clock signal CLKA, and the source of the second OUTPUT transistor M3 ' is connected to the gate driving signal OUTPUT terminal OUTPUT;
a first terminal of the second storage capacitor C2 is connected to the second pull-up node PU2, and a second terminal of the second storage capacitor C2 is connected to the gate driving signal OUTPUT terminal OUTPUT;
the pull-down node control circuit 13 includes a pull-down node control sub-circuit 131, a first pull-down node control sub-circuit 132, and a second pull-down node control sub-circuit 133, wherein,
the pull-down node control sub-circuit 131 includes a first pull-down control transistor M9 and a second pull-down control transistor M5; the first pull-down node control sub-circuit 131 includes a first pull-down node control transistor M8 and a second pull-down node control transistor M6; the second pull-down node control sub-circuit 132 includes a third pull-down node control transistor M8 'and a fourth pull-down node control transistor M6';
the grid electrode of the first pull-down control transistor M9 and the drain electrode of the first pull-down control transistor M9 are both connected to a pull-down control clock signal CLKB, and the source electrode of the first pull-down control transistor M9 is connected with a pull-down control node PDCN;
the gate of the second pull-down control transistor M6 is connected to the pull-down control node PDCN, and the drain of the second pull-down control transistor M6 is connected to the pull-down control clock signal CLKB;
the gate of the first pull-down node control transistor M8 is connected to a first pull-up node PU1, the drain of the first pull-down node control transistor M8 is connected to the pull-down control node PDCN, and the source of the first pull-down node control transistor M8 is connected to a low voltage VSS;
the gate of the second pull-down node control transistor M6 is connected to the first pull-up node PU1, the drain of the second pull-down node control transistor M6 is connected to the source of the second pull-down node control transistor M5, and the source of the second pull-down node control transistor M6 is connected to a low voltage VSS;
the gate of the third pull-down node control transistor M8 ' is connected to the second pull-up node PU2, the drain of the third pull-down node control transistor M8 ' is connected to the pull-down control node PDCN, and the source of the third pull-down node control transistor M8 ' is connected to a low voltage VSS;
the gate of the fourth pull-down node control transistor M6 ' is connected to the second pull-up node PU2, the drain of the fourth pull-down node control transistor M6 ' is connected to the source of the second pull-down control transistor M5, and the source of the fourth pull-down node control transistor M6 ' is connected to a low voltage VSS;
the pull-up node reset circuit 12 includes a first pull-up node reset sub-circuit and a second pull-up node reset sub-circuit;
the first pull-up node reset sub-circuit comprises a first pull-up reset transistor M2 and a second pull-up reset transistor M10; the second pull-up node reset sub-circuit includes a third pull-up reset transistor M13 and a fourth pull-up reset transistor M12;
the gate of the first pull-up Reset transistor M2 is connected to the Reset terminal Reset, the drain of the first pull-up Reset transistor M2 is connected to the first pull-up node PU1, and the source of the first pull-up Reset transistor M2 is connected to a low voltage VSS;
the gate of the second pull-up reset transistor M10 is connected to the pull-down node PD, the drain of the second pull-up reset transistor M10 is connected to the first pull-up node PU1, and the source of the second pull-up reset transistor M10 is connected to a low voltage VSS;
the gate of the third pull-up Reset transistor M13 is connected to the Reset terminal Reset, the drain of the third pull-up Reset transistor M13 is connected to the second pull-up node PU2, and the source of the third pull-up Reset transistor M13 is connected to a low voltage VSS;
the gate of the fourth pull-up reset transistor M12 is connected to the pull-down node PD, the drain of the fourth pull-up reset transistor M12 is connected to the second pull-up node PU2, and the source of the fourth pull-up reset transistor M12 is connected to a low voltage VSS;
the output reset circuit 14 includes a first output reset transistor M7 and a second output reset transistor M4, wherein,
the gate of the first OUTPUT reset transistor M7 is connected to the pull-down node PD, the drain of the first OUTPUT reset transistor M7 is connected to the gate driving signal OUTPUT terminal OUTPUT, and the source of the first OUTPUT reset transistor M7 is connected to a low voltage VSS;
the gate of the second OUTPUT Reset transistor M4 is connected to the Reset terminal Reset, the drain of the second OUTPUT Reset transistor M4 is connected to the gate driving signal OUTPUT terminal OUTPUT, and the source of the first OUTPUT Reset transistor M4 is connected to a low voltage VSS.
In the embodiment of the shift register unit shown in fig. 4, all the transistors are n-type TFTs, but not limited thereto.
The specific embodiment of the shift register unit is additionally provided with one pull-up node, two pull-up nodes are adopted, VDDO, VDDE, M8 ', M6', M3 ', M15, M16 and M14 are added, M15 and M16 are respectively controlled through VDDO and VDDE (polarity inversion period is 2s-3s) with opposite polarities, M3 and M3' are ensured to work alternately, full discharge of the pull-up nodes can be ensured, the working time of a TFT with a grid connected to each pull-up node is shortened, and therefore characteristic drift of the TFT is improved, and the service life and the stability of the TFT are enhanced.
In particular implementations, CLKA and CLKB may be inverted with respect to each other.
As shown in fig. 5, in operation of the embodiment of the shift register cell of the present invention shown in fig. 4, during the first display period VDDO is high, VDDE is low,
at an INPUT stage S51 included in the first display period, INPUT high level, Reset INPUT low level, M15 is turned on, M16 and M14 are turned off, communication is made between the gate of M1 and INPUT, M1 is turned on, the potential of PU1 is high level, the potential of PU2 is maintained at low level, M3 is turned on, M3' is turned off, CLKA is low level, CLKB is high level, M6 and M8 are turned on, M9 is turned on, the potential of PDCN is low level, M5 is turned off, the potential of PD is low level, OUTPUT low level;
in an OUTPUT stage S52 included in the first display period, INPUT is low, Reset is low, M15, M1, M16, and M14 are all turned off, the potential of PU1 is further pulled up by the bootstrap action of C1, the potential of PU1 is high, the potential of PU2 is kept low, CLKA is high, CLKB is low, M9 and M5 are turned off, M8 and M6 are turned on, M8 'and M6' are turned off, the potential of PD and the potential of PDCN are both low, OUTPUT is high, and the charging rate of thin film transistors in pixel circuits on the display panel is ensured;
at a Reset stage S53 included in the first display period, INPUT is low level, Reset is high level, CLKA is low level, CLKB is high level, M15, M1, M16, and M14 are all turned off, M2, M4, and M13 are all turned on to pull down both the potential of PU1 and the potential of PU2 to VSS and cause OUTPUT to OUTPUT low voltage VSS, M9 is turned on, M8, M6, M8 ', and M6' are all turned off, the potential of PDCN is high level, M5 is turned on, the potential of PD is high level, M7 is turned on;
in an output off hold stage S54 included in the first display period, INPUT is low, Reset is low, M15, M1, M16, and M14 are all turned off, M2, M4, and M13 are all turned off, the potential of PU1 and the potential of PU2 are all maintained at low, M3 and M3' are all turned off, CLKB is divided into low and high, when CLKB is low, M9 is turned off, and the potential of PD is maintained at high; when CLKB is high level, M9 is turned on, the potential of PDCN is high level, M5 is turned on, PD is switched in CLKB, and the potential of PD is high level.
When the shift register unit shown in fig. 4 of the present invention is operating, in the first display period, in the input stage and the output stage, the potential of PU1 is at a high level, and the potential of PU2 is at a low level; in the Reset phase, Reset pulls down the potential of PU1, the potential of PU2 and the potential of the gate driving signal OUTPUT by OUTPUT to VSS, and in the OUTPUT off hold phase, when CLKB is at high level, pulls down the potential of PU1, the potential of PU2 and the potential of the gate driving signal OUTPUT by OUTPUT to VSS, ensuring that the transistor whose gate is connected to PU1 and the transistor whose gate is connected to PU2 included in the shift register unit are all turned off.
As shown in fig. 6, in operation of the embodiment of the shift register cell of the present invention shown in fig. 4, during the second display period VDDO is low, VDDE is high,
at an INPUT stage S61 included in the second display period, INPUT high level, Reset INPUT low level, M16 is turned on, M15 and M1 are turned off, the gate of M14 is communicated with INPUT, M14 is turned on, the potential of PU2 is high level, the potential of PU1 is maintained at low level, M3 is turned off, M3 ' is turned on, CLKA is low level, CLKB is high level, M6 ' and M8 ' are turned on, M9 is turned on, the potential of PDCN is low level, M5 is turned off, the potential of PD is low level, OUTPUT low level;
in an OUTPUT stage S62 included in the second display period, INPUT is low, Reset is low, M15, M1, M16, and M14 are all turned off, the potential of PU2 is further pulled up by the bootstrap action of C2, the potential of PU2 is high, the potential of PU1 is kept low, CLKA is high, CLKB is low, M9 and M5 are turned off, M8 'and M6' are turned on, M8 and M6 are turned off, the potential of PD and the potential of PDCN are both low, OUTPUT is high, and the charging rate of thin film transistors in pixel circuits on the display panel is ensured;
at a Reset stage S63 included in the second display period, INPUT INPUTs a low level, Reset INPUTs a high level, CLKA is a low level, CLKB is a high level, M15, M1, M16, and M14 are all turned off, M2, M4, and M13 are all turned on to pull down both the potential of PU1 and the potential of PU2 to VSS and cause OUTPUT of low voltage VSS, M9 is turned on, M8, M6, M8 ', and M6' are all turned off, the potential of PDCN is a high level, M5 is turned on, the potential of PD is a high level, M7 is turned on;
in the output off hold stage S64 included in the second display period, INPUT is low, Reset is low, M15, M1, M16, and M14 are all turned off, M2, M4, and M13 are all turned off, the potential of PU1 and the potential of PU2 are all maintained at low, M3 and M3' are all turned off, CLKB is divided into low and high, when CLKB is low, M9 is turned off, and the potential of PD is maintained at high; when CLKB is high level, M9 is turned on, the potential of PDCN is high level, M5 is turned on, PD is switched in CLKB, and the potential of PD is high level.
When the shift register unit shown in fig. 4 of the present invention is in operation, in the second display period, in the input stage and the output stage, the potential of PU2 is at a high level, and the potential of PU1 is at a low level; in the Reset phase, Reset pulls down the potential of PU1, the potential of PU2 and the potential of the gate driving signal OUTPUT by OUTPUT to VSS, and in the OUTPUT off hold phase, when CLKB is at high level, pulls down the potential of PU1, the potential of PU2 and the potential of the gate driving signal OUTPUT by OUTPUT to VSS, ensuring that the transistor whose gate is connected to PU1 and the transistor whose gate is connected to PU2 included in the shift register unit are all turned off.
When the specific embodiment of the shift register unit shown in fig. 4 of the present invention is in operation, the display period includes a plurality of display phases, as shown in fig. 7, the display phases include a first display period S71 and a second display period S72, which are sequentially set;
in the first display period S71, VDDO is high level, VDDE is low level, the potential of the PU2 is always low level, in the input phase and the output phase included in the first display period S71, the potential of the PU1 is high level, and in the reset phase and the output off hold phase included in the first display period S71, the potential of the PU1 is low level;
VDDO is low level, VDDE is high level, the potential of the PU1 is always high level in the second display period S72, the potential of the PU2 is high level in the input phase and the output phase included in the second display period S72, and the potential of the PU2 is low level in the reset phase and the output off-hold phase included in the second display period S72.
In fig. 5, 6, and 7, a horizontal line corresponding to 0V is shown by a dot-dash line.
The driving method of the shift register unit according to the embodiment of the present invention is applied to the shift register unit, and the display period includes a plurality of display stages, where each display stage includes N display time periods sequentially set; the driving method of the shift register unit comprises the following steps:
in the nth display time period, the nth control voltage end outputs effective voltage, and the other control voltage ends except the nth control voltage end output ineffective voltage so as to control the communication between the nth pull-up node and the input end when the effective voltage is input into the input end;
n is an integer greater than 1, and N is a positive integer less than or equal to N.
The gate driving circuit comprises a plurality of cascaded shift register units;
except the first stage of shift register unit, the input end of each stage of shift register unit is connected with the grid drive signal output end of the adjacent upper stage of shift register unit;
except the last stage of shift register unit, the reset terminal of each stage of shift register unit is connected with the gate drive signal output terminal of the next stage of shift register unit.
As shown in fig. 8, the gate driving circuit according to the embodiment of the present invention includes an N-1 th stage shift register unit SN-1, an nth stage shift register unit SN, and an N +1 th stage shift register unit SN + 1;
in fig. 8, a gate driving signal output terminal of the nth-1 stage is denoted by G (N-1), a gate driving signal output terminal of the nth stage is denoted by G (N), a gate driving signal output terminal of the nth +1 stage is denoted by G (N +1), an input terminal of SN-1 is denoted by INPUTN-1, and a reset terminal of SN +1 is denoted by ResetN + 1;
the input terminal INPUTN of SN is connected with G (N-1), the reset terminal ResetN-1 of SN-1 is connected with G (N),
the input end INPUTN +1 of the SN +1 is connected with G (N), and the reset end ResetN of the SN is connected with G (N + 1);
in fig. 8, VDDO is the first control voltage, VDDE is the second control voltage, CLKA output clock signal is the output clock signal, and CLKB is the pull-down control clock signal.
The display device provided by the embodiment of the invention comprises the gate drive circuit.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A shift register unit comprises N control voltage terminals, N output circuits, and N pull-up node control circuits,
the nth pull-up node control circuit is respectively connected with the nth control voltage end, the nth pull-up node and the input end and is used for controlling the communication between the nth pull-up node and the input end under the control of the nth control voltage end and the input end in the nth display time period;
the nth output circuit is respectively connected with the nth pull-up node, the grid driving signal output end and the output signal end and is used for controlling the grid driving signal output end to be communicated with the output signal end under the control of the nth pull-up node;
n is an integer greater than 1, N is a positive integer less than or equal to N;
the shift register unit is characterized by further comprising a pull-up node reset circuit, a pull-down node control circuit and an output reset circuit;
the pull-up node reset circuit is respectively connected with a reset terminal, a pull-down node and N pull-up nodes and is used for controlling the potentials of the N pull-up nodes to be reset under the control of the reset terminal and/or the pull-down node;
the pull-down node control circuit is respectively connected with a pull-down control clock signal end, a pull-down node and the N pull-up nodes and is used for controlling the potential of the pull-down node under the control of the N pull-up nodes and the pull-down control clock signal end;
the output reset circuit is respectively connected with the pull-down node, the reset end, the grid driving signal output end and the reset voltage end and is used for controlling the grid driving signal output end and the reset voltage end to be communicated under the control of the pull-down node and the reset end;
the pull-up node reset circuit comprises N pull-up node reset sub-circuits;
the nth pull-up node reset sub-circuit includes a 2n-1 th pull-up reset transistor and a 2 nth pull-up reset transistor, wherein,
a control electrode of the 2n-1 pull-up reset transistor is connected with the reset end, a first electrode of the 2n-1 pull-up reset transistor is connected with the nth pull-up node, and a second electrode of the 2n-1 pull-up reset transistor is connected with the first voltage end;
the control electrode of the 2n pull-up reset transistor is connected with the pull-down node, the first electrode of the 2n pull-up reset transistor is connected with the n pull-up node, and the second electrode of the 2n pull-up reset transistor is connected with the first voltage end.
2. The shift register cell of claim 1, wherein the nth pull-up node control circuit includes a 2n-1 control transistor and a 2 nth control transistor, wherein,
the control electrode of the 2n-1 control transistor is connected with the nth control voltage end, and the first electrode of the 2n-1 control transistor is connected with the input end;
a control electrode of the 2 n-th control transistor and a first electrode of the 2 n-th control transistor are both connected to a second electrode of the 2 n-1-th control transistor, and a second electrode of the 2 n-th control transistor is connected to the nth pull-up node.
3. The shift register cell of claim 1, wherein the nth output circuit includes an nth output transistor and an nth storage capacitor, wherein,
a control electrode of the nth output transistor is connected with the nth pull-up node, a first electrode of the nth output transistor is connected with the output signal end, and a second electrode of the nth output transistor is connected with the gate drive signal output end;
the first end of the nth storage capacitor is connected with the nth pull-up node, and the second end of the nth storage capacitor is connected with the gate driving signal output end.
4. The shift register cell of any one of claims 1 to 3, wherein the pull-down node control circuit comprises a pull-down control sub-circuit and N pull-down node control sub-circuits;
the pull-down control sub-circuit comprises a first pull-down control transistor and a second pull-down control transistor, and the nth pull-down node control sub-circuit comprises a 2n-1 pull-down node control transistor and a 2 nth pull-down node control transistor;
a control electrode of the first pull-down control transistor and a first electrode of the first pull-down control transistor are both connected with the pull-down control clock signal end, and a second electrode of the first pull-down control transistor is connected with a pull-down control node;
a control electrode of the second pull-down control transistor is connected with the pull-down control node, and a first electrode of the second pull-down control transistor is connected with the pull-down control clock signal end;
a control electrode of the 2n-1 pull-down node control transistor is connected with an nth pull-up node, a first electrode of the 2n-1 pull-down node control transistor is connected with the pull-down control node, and a second electrode of the 2n-1 pull-down node control transistor is connected with a first voltage end;
the control electrode of the 2 nth pull-down node control transistor is connected with the nth pull-up node, the first electrode of the 2 nth pull-down node control transistor is connected with the second electrode of the second pull-down control transistor, and the second electrode of the 2 nth pull-down node control transistor is connected with the first voltage end.
5. The shift register cell of any one of claims 1-3, wherein the output reset circuit comprises a first output reset transistor and a second output reset transistor, wherein,
a control electrode of the first output reset transistor is connected with the pull-down node, a first electrode of the first output reset transistor is connected with the grid drive signal output end, and a second electrode of the first output reset transistor is connected with a first voltage end;
the control electrode of the second output reset transistor is connected with the reset end, the first electrode of the second output reset transistor is connected with the grid drive signal output end, and the second electrode of the first output reset transistor is connected with the first voltage end.
6. A driving method of a shift register unit is applied to the shift register unit according to any one of claims 1 to 5, wherein a display period comprises a plurality of display phases, and the display phases comprise N display time periods which are sequentially set; the driving method of the shift register unit comprises the following steps:
in the nth display time period, the nth control voltage end outputs effective voltage, and the other control voltage ends except the nth control voltage end output ineffective voltage so as to control the communication between the nth pull-up node and the input end when the effective voltage is input into the input end;
n is an integer greater than 1, and N is a positive integer less than or equal to N.
7. A gate drive circuit comprising a plurality of cascaded shift register cells according to any one of claims 1 to 5.
8. A display device comprising the gate driver circuit according to claim 7.
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