CN104282285A - Shifting register circuit and drive method, gate drive circuit and display device thereof - Google Patents
Shifting register circuit and drive method, gate drive circuit and display device thereof Download PDFInfo
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- CN104282285A CN104282285A CN201410596879.0A CN201410596879A CN104282285A CN 104282285 A CN104282285 A CN 104282285A CN 201410596879 A CN201410596879 A CN 201410596879A CN 104282285 A CN104282285 A CN 104282285A
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Abstract
The invention provides a shifting register circuit and a drive method, a gate drive circuit and a display device of the shifting register circuit. The shifting register circuit comprises an input control unit, a first node pull-up unit, a first node pull-down unit, a second node pull-up unit, a second node pull-down unit, an output drive unit and an output pull-down unit. When the shifting register circuit works, a second node is pulled upwards or downwards in an alternated mode within the drive time of one grid line, so that the output pull-down unit is opened or closed in an alternated mode and does not work continuously, drifting of the threshold voltage of a thin film transistor in the output pull-down unit can be prevented effectively, electric leakage caused by the drifting of the threshold voltage is reduced, and the overall power dissipation of the gate drive circuit is reduced.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of shift-register circuit and driving method, gate driver circuit, display device.
Background technology
TFT-LCD (Thin Film Transistor Liquid Crystal Display, thin-film transistor LCD device) advantage that is low with its operating voltage, fast response time has become absolutely main force's technology of flat panel display technology.
The gate driver circuit of TFT-LCD comprises the shift register of multiple cascade, and every grade of shift register is all connected on corresponding grid line, to export gate drive signal driven grid line, and then realizes the driving of lining by line scan to gate line.The cascade system of multiple shift register is: when the input end of preceding shift register is connected to the output terminal of upper level shift register, the output terminal of next stage shift register is connected to the reset terminal when preceding shift register, namely the shift register at different levels output signal that utilizes upper level shift register to produce is as the input signal of self, utilizes the reset signal of output signal as self of next stage shift register.
Along with the development of science and technology and consumer are to the demand of high image quality, TFT-LCD is also towards large scale, energy-conservation, frivolous, high-resolution future development, this requires that the gate driver circuit of TFT-LCD will have higher vertical sweep frequency, because gate driver circuit mainly comprises multiple TFT (Thin Film Trans istor, thin film transistor (TFT)), therefore require that TFT will have higher mobility.Not only mobility is high for oxide TFT, stable performance, and homogeneity is good, technique is simple and easy to realization, cost is low, the circuit design of high vertical sweep frequency can be met well, but oxide TFT long-time in running order time, its threshold voltage vt h easily drifts about, cause the electric leakage of TFT to increase, the power consumption of gate driver circuit is larger.
Summary of the invention
For overcoming above-mentioned defect of the prior art, technical matters to be solved by this invention is: provide a kind of shift-register circuit and driving method, gate driver circuit, display device, to reduce the power consumption of gate driver circuit.
For achieving the above object, the present invention adopts following technical scheme:
A first aspect of the present invention provides a kind of shift-register circuit, comprising: the Input Control Element be connected with input signal end, for the input of control inputs signal; The first node pull-up unit be connected with first node with the first clock signal terminal, reset signal end, described Input Control Element, low level power signal end, for being pulled to high level by the voltage of described first node; The first node drop-down unit be connected with described first node with Section Point, described low level power signal end, for being pulled down to low level by the voltage of described first node; The Section Point pull-up unit be connected with Section Point with described input signal end, described first clock signal terminal, described low level power signal end, high level power supply signal end, for being pulled to high level by the voltage of described Section Point; The Section Point drop-down unit be connected with described Section Point with second clock signal end, described low level power signal end, for being pulled down to low level by the voltage of described Section Point; The output driver element be connected with output signal end with described first node, described high level power supply signal end, for exporting the output signal of high level when described first node is high level; The output be connected with described output signal end with described Section Point, described low level power signal end drags down unit, for the voltage of described output signal being pulled down to low level when described first node is low level; Wherein, described first node is the common port of described first node pull-up unit, described first node drop-down unit and described output driver element, the common port that described Section Point is described Section Point pull-up unit, described Section Point drop-down unit, described first node drop-down unit and described output drag down unit.
Preferably, described Input Control Element comprises: the first film transistor, and the control end of described the first film transistor is all connected with described input signal end with input end, and output terminal is connected with described first node pull-up unit.
Preferably, described first node pull-up unit comprises: the second thin film transistor (TFT), and the control end of described second thin film transistor (TFT) is connected with described first clock signal terminal, and input end is connected with described Input Control Element, and output terminal is connected with described first node; Memory capacitance, the first end of described memory capacitance is connected with described first node, and the second end is connected with described reset signal end; 3rd thin film transistor (TFT), the control end of described 3rd thin film transistor (TFT) is connected with described reset signal end, and input end is connected with described low level power signal end, and output terminal is connected with the input end of described second thin film transistor (TFT).
Preferably, described first node drop-down unit comprises: the 4th thin film transistor (TFT), and the control end of described 4th thin film transistor (TFT) is connected with described Section Point, and input end is connected with described low level power signal end, and output terminal is connected with described first node.
Preferably, described Section Point pull-up unit comprises: the 5th thin film transistor (TFT), and the control end of described 5th thin film transistor (TFT) is connected with described input signal end, input end is connected with described low level power signal end; 6th thin film transistor (TFT), the control end of described 6th thin film transistor (TFT) is all connected with described high level power supply signal end with input end, and output terminal is connected with the output terminal of described 5th thin film transistor (TFT); 7th thin film transistor (TFT), the common port that the control end of described 7th thin film transistor (TFT) is connected with the output terminal of described 6th thin film transistor (TFT) with the output terminal of described 5th thin film transistor (TFT) is connected, and input end is connected with the control end of described 6th thin film transistor (TFT); 8th thin film transistor (TFT), the control end of described 8th thin film transistor (TFT) is connected with described first clock signal terminal, and input end is connected with the output terminal of described 7th thin film transistor (TFT), and output terminal is connected with described Section Point.
Preferably, described Section Point drop-down unit comprises: the 9th thin film transistor (TFT), and the control end of described 9th thin film transistor (TFT) is connected with described second clock signal end, and input end is connected with described low level power signal end, and output terminal is connected with described Section Point.
Preferably, described output driver element comprises: the tenth thin film transistor (TFT), and the control end of described tenth thin film transistor (TFT) is connected with described first node, and input end is connected with described high level power supply signal end, and output terminal is connected with described output signal end.
Preferably, described output drags down unit and comprises: the 11 thin film transistor (TFT), and the control end of described 11 thin film transistor (TFT) is connected with described Section Point, and input end is connected with described low level power signal end, and output terminal is connected with described output signal end.
A second aspect of the present invention provides a kind of driving method of shift-register circuit, for driving above-described shift-register circuit, described driving method comprises: the first stage, input signal end and second clock signal end output low level, reset signal end and the first clock signal terminal export high level, input signal control module is closed, first node pull-up unit no signal exports, the voltage of first node is pulled down to low level by first node drop-down unit, output driver element is closed, Section Point drop-down unit is closed, the voltage of Section Point is pulled to high level by Section Point pull-up unit, output drags down unit and the voltage of output signal end is pulled down to low level, subordinate phase, described input signal end and described second clock signal end export high level, described reset signal end and described first clock signal terminal output low level, described input signal control module is opened, described first node pull-up unit no signal exports, described first node drop-down unit is closed, the voltage of described first node keeps low level, described output driver element is closed, described Section Point pull-up unit no signal exports, the voltage of described Section Point is pulled down to low level by described Section Point drop-down unit, described output drags down unit and closes, the voltage of described output signal end keeps low level, phase III, described input signal end and described first clock signal terminal export high level, described reset signal end and described second clock signal end output low level, described Section Point pull-up unit no signal exports, described Section Point drop-down unit is closed, the voltage of described Section Point keeps low level, described output drags down unit and closes, described first node drop-down unit is closed, described input signal control module is opened, the voltage of described first node is pulled to high level by described first node pull-up unit, the voltage of described output signal end is pulled to high level by described output driver element, fourth stage, described input signal end and described first clock signal terminal output low level, described reset signal end and described second clock signal end export high level, described Section Point pull-up unit no signal exports, the voltage of described Section Point is pulled down to low level by described Section Point drop-down unit, described output drags down unit and closes, described input signal control module is closed, described first node drop-down unit is closed, the voltage of described first node is continued to be pulled to more high level by described first node pull-up unit, described output driver element keeps the voltage of described output signal end to be pulled to high level, five-stage, described input signal end and described second clock signal end output low level, described reset signal end and described first clock signal terminal export high level, described input signal control module is closed, described first node pull-up unit no signal exports, the voltage of described first node is pulled down to low level by described first node drop-down unit, described output driver element is closed, described Section Point drop-down unit is closed, the voltage of described Section Point is pulled to high level by described Section Point pull-up unit, described output drags down unit and the voltage of described output signal end is pulled down to low level, 6th stage, described input signal end, described reset signal end and described first clock signal terminal output low level, described second clock signal end exports high level, described input signal control module is closed, described first node pull-up unit no signal exports, described first node drop-down unit is closed, described first node keeps low level, described output driver element is closed, described Section Point pull-up unit no signal exports, the voltage of described Section Point is pulled down to low level by described Section Point drop-down unit, described output drags down unit and closes, the voltage of described output signal end keeps low level.
Preferably, described Input Control Element comprises the first film transistor, described first node pull-up unit comprises the second thin film transistor (TFT), memory capacitance and the 3rd thin film transistor (TFT), described first node drop-down unit comprises the 4th thin film transistor (TFT), described Section Point pull-up unit comprises the 5th thin film transistor (TFT), 6th thin film transistor (TFT), 7th thin film transistor (TFT) and the 8th thin film transistor (TFT), described Section Point drop-down unit comprises the 9th thin film transistor (TFT), described output driver element comprises the tenth thin film transistor (TFT), described output drags down unit and comprises the 11 thin film transistor (TFT), described driving method specifically comprises: the first stage, described input signal end and described second clock signal end output low level, described reset signal end and described first clock signal terminal export high level, described the first film transistor, described 3rd thin film transistor (TFT), described 5th thin film transistor (TFT) and described 9th thin film transistor (TFT) are closed, described second thin film transistor (TFT), described 4th thin film transistor (TFT), described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 8th thin film transistor (TFT) are opened, the voltage of described first node is pulled down to low level, described tenth thin film transistor (TFT) cuts out, the voltage of described Section Point is pulled to high level, described 11 thin film transistor (TFT) is opened, the voltage of described output signal end is pulled down to low level, subordinate phase, described input signal end and described second clock signal end export high level, described reset signal end and described first clock signal terminal output low level, described second thin film transistor (TFT), described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 8th thin film transistor (TFT) are closed, described the first film transistor, described 5th thin film transistor (TFT), described 6th thin film transistor (TFT) and described 9th thin film transistor (TFT) are opened, the voltage of described first node keeps low level, described tenth thin film transistor (TFT) cuts out, the voltage of described Section Point is pulled down to low level, described 11 thin film transistor (TFT) cuts out, the voltage of described output signal end keeps low level, phase III, described input signal end and described first clock signal terminal export high level, described reset signal end and described second clock signal end output low level, described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 9th thin film transistor (TFT) are closed, described the first film transistor, described second thin film transistor (TFT), described 5th thin film transistor (TFT), described 6th thin film transistor (TFT) and described 8th thin film transistor (TFT) are opened, the voltage of described Section Point keeps low level, described 11 thin film transistor (TFT) cuts out, the voltage of described first node is pulled to high level, described tenth thin film transistor (TFT) is opened, the voltage of described output signal end is pulled to high level, fourth stage, described input signal end and described first clock signal terminal output low level, described reset signal end and described second clock signal end export high level, described the first film transistor, described second thin film transistor (TFT), described 4th thin film transistor (TFT), described 5th thin film transistor (TFT) and described 8th thin film transistor (TFT) are closed, described 3rd thin film transistor (TFT), described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 9th thin film transistor (TFT) are opened, the voltage of described Section Point is pulled down to low level, described 11 thin film transistor (TFT) cuts out, the voltage of described first node is continued to be pulled to more high level, described tenth thin film transistor (TFT) is opened, the voltage of described output signal end keeps high level, five-stage, described input signal end and described second clock signal end output low level, described reset signal end and described first clock signal terminal export high level, described the first film transistor, described 5th thin film transistor (TFT) and described 9th thin film transistor (TFT) are closed, described second thin film transistor (TFT), described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 8th thin film transistor (TFT) are opened, the voltage of described first node is pulled down to low level, described tenth thin film transistor (TFT) cuts out, the voltage of described Section Point is pulled to high level, described 11 thin film transistor (TFT) is opened, the voltage of described output signal end is pulled down to low level, 6th stage, described input signal end, described reset signal end and described first clock signal terminal output low level, described second clock signal end exports high level, described the first film transistor, described second thin film transistor (TFT), described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 5th thin film transistor (TFT) and described 8th thin film transistor (TFT) are closed, described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 9th thin film transistor (TFT) are opened, described first node keeps low level, described tenth thin film transistor (TFT) cuts out, the voltage of described Section Point is pulled down to low level, described 11 thin film transistor (TFT) cuts out, the voltage of described output signal end keeps low level.
A third aspect of the present invention provides a kind of gate driver circuit, comprise: the multiple above-described shift-register circuit of cascade mutually, except first order shift-register circuit and afterbody shift-register circuit, the input signal end of every one-level shift-register circuit is connected with the output signal end of upper level shift-register circuit, and the reset signal end of every one-level shift register is connected with the output signal end of next stage shift-register circuit.
Preferably, the whole shift-register circuits included by described gate driver circuit are connected with same one end of whole grid lines of display panel all one to one.
Preferably, the half shift-register circuit of described gate driver circuit is connected with same one end of whole grid lines of display panel one to one, and second half shift-register circuit of described gate driver circuit is connected with the other end of whole grid lines of display panel one to one.
Preferably, the half shift-register circuit of described gate driver circuit is connected with same one end of the odd-numbered line grid line of display panel one to one, and second half shift-register circuit of described gate driver circuit is connected with the other end of the even number line grid line of display panel one to one.
A fourth aspect of the present invention provides a kind of display device, comprises above-described gate driver circuit.
In shift-register circuit provided by the present invention and driving method thereof, gate driver circuit, display device, by in the driving time of a grid line, alternately draw high or drag down Section Point, make to export the unlatching or closedown that drag down units alternately, not continuous firing, thus effectively prevent the drift exporting and drag down thin film transistor (TFT) threshold voltage in unit, decrease the electric leakage caused by the drift of threshold voltage, reduce the overall power of gate driver circuit.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural drawing of the shift-register circuit that Fig. 1 provides for the embodiment of the present invention;
The driver' s timing figure of the shift-register circuit that Fig. 2 provides for the embodiment of the present invention;
A kind of concrete structural drawing of the shift-register circuit that Fig. 3 provides for the embodiment of the present invention;
Monolateral single cascade graphs driving the gate driver circuit of type that Fig. 4 provides for the embodiment of the present invention;
Fig. 5 moves the cascade graphs of the gate driver circuit of type for two-sided dual-drive that the embodiment of the present invention provides;
Monolateral single driver' s timing figure driving type and two-sided dual-drive to move the gate driver circuit of type that Fig. 6 provides for the embodiment of the present invention;
Bilateral single cascade graphs driving the gate driver circuit of type that Fig. 7 provides for the embodiment of the present invention;
Bilateral single driver' s timing figure driving the gate driver circuit of type that Fig. 8 provides for the embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, below in conjunction with the accompanying drawing in the embodiment of the present invention, are clearly and completely described the technical scheme in the embodiment of the present invention.Obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, other embodiments all that those of ordinary skill in the art obtain under the prerequisite of not making creative work, all belong to the scope of protection of the invention.
Present embodiments provide a kind of shift-register circuit, as shown in Figure 1, this shift register circuit comprises: the Input Control Element 101 be connected with input signal end Vg_n-1, for the input of control inputs signal Vg_n-1; The first node pull-up unit 102 be connected with first node PU with the first clock signal terminal CK, reset signal end Vg_n+1, Input Control Element 101, low level power signal end VGL, for being pulled to high level by the voltage of first node PU; The first node drop-down unit 103 be connected with first node PU with Section Point PD, low level power signal end VGL, for being pulled down to low level by the voltage of first node PU; The Section Point pull-up unit 104 be connected with Section Point PD with input signal end Vg_n-1, the first clock signal terminal CK, low level power signal end VGL, high level power supply signal end VGH, for being pulled to high level by the voltage of Section Point PD; The Section Point drop-down unit 105 be connected with Section Point PD with second clock signal end CKB, low level power signal end VGL, for being pulled down to low level by the voltage of Section Point PD; The output driver element 106 be connected with output signal end Vg_n with first node PU, high level power supply signal end VGH, for exporting the output signal Vg_n of high level when first node PU is high level; The output be connected with output signal end Vg_n with Section Point PD, low level power signal end VGL drags down unit 107, for the voltage of output signal Vg_n being pulled down to low level when first node PU is low level; Wherein, first node PU is first node pull-up unit 102, first node drop-down unit 103 and export the common port of driver element 106, and Section Point PD is Section Point pull-up unit 104, Section Point drop-down unit 105, first node drop-down unit 103 and export the common port dragging down unit 107.
It should be noted that, the shift-register circuit of multiple mutual cascade is comprised at gate driver circuit, except first and last shift-register circuit, the input signal end of middle every grade of shift-register circuit is all connected with the output signal end of upper level shift-register circuit, reset signal end is all connected with the output signal end of next stage shift-register circuit, and output terminal is all connected with one end of a grid line; The input signal termination of first shift-register circuit receives an initialize signal STV, and the reset signal termination of last shift-register circuit receives a reset signal Reset.Therefore, if the shift-register circuit described in this enforcement is the n-th shift-register circuit, then its input signal Vg_n-1 is the output signal of (n-1)th shift-register circuit, its reset signal Vg (n+1) is the output signal of (n+1)th shift-register circuit, and its output signal is Vg_n.
In addition, the first clock signal C K and second clock signal CKB is the control signal of shift-register circuit, and the two is inversion signal.High level power supply signal VGH is the access voltage of shift-register circuit, is high level; Low level power signal VGL is another access voltage of shift-register circuit, is low level.
The driving method of above-mentioned shift-register circuit comprises six stages, and as shown in Figure 2, these six stages are followed successively by:
First stage t
1, input signal end Vg_n-1 and second clock signal end CKB output low level, reset signal end Vg_n+1 and the first clock signal terminal CK exports high level, input signal control module 101 is closed, first node pull-up unit 102 no signal exports, the voltage of first node PU is pulled down to low level by first node drop-down unit 103, export driver element 106 to close, Section Point drop-down unit 105 is closed, the voltage of Section Point PD is pulled to high level by Section Point pull-up unit 104, output drags down unit 107 and the voltage of output signal end Vg_n is pulled down to low level.
Subordinate phase t
2, input signal end Vg_n-1 and second clock signal end CKB exports high level, reset signal end Vg_n+1 and the first clock signal terminal CK output low level, input signal control module 101 is opened, first node pull-up unit 102 no signal exports, first node drop-down unit 103 is closed, the voltage of first node PU keeps low level, export driver element 106 to close, Section Point pull-up unit 104 no signal exports, the voltage of Section Point PD is pulled down to low level by Section Point drop-down unit 105, output drags down unit 107 and closes, the voltage of output signal end Vg_n keeps low level.
Phase III t
3, input signal end Vg_n-1 and the first clock signal terminal CK exports high level, reset signal end Vg_n+1 and second clock signal end CKB output low level, Section Point pull-up unit 104 no signal exports, Section Point drop-down unit 105 is closed, the voltage of Section Point PD keeps low level, output drags down unit 107 and closes, first node drop-down unit 103 is closed, input signal control module 101 is opened, the voltage of first node PU is pulled to high level by first node pull-up unit 102, export driver element 106 and the voltage of output signal end Vg_n is pulled to high level.
Fourth stage t
4, input signal end Vg_n-1 and the first clock signal terminal CK output low level, reset signal end Vg_n+1 and second clock signal end CKB exports high level, Section Point pull-up unit 104 no signal exports, the voltage of Section Point PD is pulled down to low level by Section Point drop-down unit 105, output drags down unit 107 and closes, input signal control module 101 is closed, first node drop-down unit 103 is closed, the voltage of first node PU is continued to be pulled to more high level by first node pull-up unit 102, export driver element 106 to keep the voltage of output signal end Vg_n to be pulled to high level.
Five-stage t
5, input signal end Vg_n-1 and second clock signal end CKB output low level, reset signal end Vg_n+1 and the first clock signal terminal CK exports high level, input signal control module 101 is closed, first node pull-up unit 102 no signal exports, the voltage of first node PU is pulled down to low level by first node drop-down unit 103, export driver element 106 to close, Section Point drop-down unit 105 is closed, the voltage of Section Point PD is pulled to high level by Section Point pull-up unit 104, output drags down unit 107 and the voltage of output signal end Vg_n is pulled down to low level.
6th stage t
6, input signal end Vg_n-1, reset signal end Vg_n+1 and the first clock signal terminal CK output low level, second clock signal end CKB exports high level, input signal control module 101 is closed, first node pull-up unit 102 no signal exports, first node drop-down unit 103 is closed, first node PU keeps low level, export driver element 106 to close, Section Point pull-up unit 104 no signal exports, the voltage of Section Point PD is pulled down to low level by Section Point drop-down unit 105, output drags down unit 107 and closes, the voltage of output signal end Vg_n keeps low level.
Can be obtained by above-mentioned shift register circuit and driving method thereof, ensureing under the prerequisite that output signal end Vg_n outputs signal on request, in whole driving process, the voltage of Section Point PD is drawn high by alternating or dragged down, namely export and drag down the alternating unlatching of unit 107 or closedown, therefore the alternating unlatching of thin film transistor (TFT) dragged down included by unit 107 or closedown is exported, can't be in running order for a long time, avoiding problems the problem due to long-time in running order caused thin film transistor (TFT) threshold voltage shift, thus decrease the electric leakage that threshold voltage shift causes, reduce the overall power of the gate driver circuit comprising shift-register circuit.
Below the specific implementation structure of each functional unit of shift-register circuit that the present embodiment provides is illustrated.As shown in Figure 3, Input Control Element 101 can comprise: the first film transistor T1, and the control end of this first film transistor T1 is all connected with input signal end Vg_n-1 with input end, and output terminal is connected with first node pull-up list 102 yuan.
First node pull-up unit 102 can comprise: the second thin film transistor (TFT) T2, the control end of this second thin film transistor (TFT) T2 is connected with the first clock signal terminal CK, input end is connected with Input Control Element 102, be can be connected with the output terminal of the first film transistor T1 more specifically, output terminal is connected with first node PU; The first end of memory capacitance Cst, this memory capacitance Cst is connected with first node PU, and the second end is connected with reset signal end Vg_n+1; The control end of the 3rd thin film transistor (TFT) T3, the 3rd thin film transistor (TFT) T3 is connected with reset signal end Vg_n+1, and input end is connected with low level power signal end VGL, and output terminal is connected with the input end of the second thin film transistor (TFT) T2.
First node drop-down unit 103 can comprise: the 4th thin film transistor (TFT) T4, and the control end of the 4th thin film transistor (TFT) T4 is connected with Section Point PD, and input end is connected with low level power signal end VGL, and output terminal is connected with first node PD.
Section Point pull-up unit 104 can comprise: the 5th thin film transistor (TFT) T5, and the control end of the 5th thin film transistor (TFT) T5 is connected with input signal end Vg_n-1, input end is connected with low level power signal end VGL; The control end of the 6th thin film transistor (TFT) T6, the 6th thin film transistor (TFT) T6 is all connected with high level power supply signal end VGH with input end, and output terminal is connected with the output terminal of the 5th thin film transistor (TFT) T5; The common port that the control end of the 7th thin film transistor (TFT) T7, the 7th thin film transistor (TFT) T7 is connected with the output terminal of the 6th thin film transistor (TFT) T6 with the output terminal of the 5th thin film transistor (TFT) T5 is connected, and input end is connected with the control end of the 6th thin film transistor (TFT) T6; The control end of the 8th thin film transistor (TFT) T8, the 8th thin film transistor (TFT) T8 is connected with the first clock signal terminal CK, and input end is connected with the output terminal of the 7th thin film transistor (TFT) T7, and output terminal is connected with Section Point PD.
Section Point drop-down unit 105 can comprise: the 9th thin film transistor (TFT) T9, and the control end of the 9th thin film transistor (TFT) T9 is connected with second clock signal end CKB, and input end is connected with low level power signal end VGL, and output terminal is connected with Section Point PD.
Export driver element 106 can comprise: the tenth thin film transistor (TFT) T10, the control end of the tenth thin film transistor (TFT) T10 is connected with first node PU, and input end is connected with high level power supply signal end VGH, and output terminal is connected with output signal end Vg_n.
Output drags down unit 107 and can comprise: the 11 thin film transistor (TFT) T11, and the control end of the 11 thin film transistor (TFT) T11 is connected with Section Point PD, and input end is connected with low level power signal end VGL, and output terminal is connected with output signal end Vg_n.
See Fig. 2, the driving process of the shift-register circuit of above-mentioned concrete structure can be as follows:
First stage t
1, input signal end Vg_n-1 and second clock signal end CKB output low level, reset signal end Vg_n+1 and the first clock signal terminal CK exports high level, the first film transistor T1 and the 3rd thin film transistor (TFT) T3 closes, second thin film transistor (TFT) T2 opens, first node pull-up unit 102 no signal exports, 5th thin film transistor (TFT) T5 closes, 6th thin film transistor (TFT) T6, 7th thin film transistor (TFT) T7 and the 8th thin film transistor (TFT) T8 opens, the voltage of Section Point PD is pulled to high level, 11 thin film transistor (TFT) T11 opens, the voltage of output signal end Vg_n is pulled down to low level, 4th thin film transistor (TFT) T4 opens simultaneously, the voltage of first node PU is pulled down to low level, tenth thin film transistor (TFT) T10 closes.It should be noted that, this first stage t
1act as and utilize reset signal Vg_n+1 to the voltage amplitude of first node PU, this point voltage is reset.
Subordinate phase t
2, input signal end Vg_n-1 and second clock signal end CKB exports high level, reset signal end Vg_n+1 and the first clock signal terminal CK output low level, 5th thin film transistor (TFT) T5 and the 6th thin film transistor (TFT) T6 opens, 7th thin film transistor (TFT) T7 and the 8th thin film transistor (TFT) T8 closes, Section Point pull-up unit 104 no signal exports, 9th thin film transistor (TFT) T9 opens, the voltage of Section Point PD is pulled down to low level, 11 thin film transistor (TFT) T11 closes, 4th thin film transistor (TFT) T4 closes simultaneously, the first film transistor T1 opens, second thin film transistor (TFT) T2, described 3rd thin film transistor (TFT) T3 closes, first node pull-up unit 102 no signal exports, thus first node PU is in floating state, continue to keep low level, tenth thin film transistor (TFT) T10 closes, the voltage of output signal end Vg_n keeps low level.It should be noted that, this subordinate phase t
2act as the voltage floating making first node PU, prepare for subsequent charge electric capacity Cst carries out charging to draw high this point voltage.
Phase III t
3, input signal end Vg_n-1 and the first clock signal terminal CK exports high level, reset signal end Vg_n+1 and second clock signal end CKB output low level, the first film transistor T1 and the second thin film transistor (TFT) T2 opens, 3rd thin film transistor (TFT) T3 closes, first node pull-up unit 102 exports high level, the voltage of first node PU is pulled to high level, tenth thin film transistor (TFT) T10 opens, the voltage of output signal end Vg_n is pulled to high level, 5th thin film transistor (TFT) T5, 6th thin film transistor (TFT) T6 and the 8th thin film transistor (TFT) T8 opens, 7th thin film transistor (TFT) T7 closes, Section Point pull-up unit 104 no signal exports, 9th thin film transistor (TFT) T9 closes, thus Section Point PD is in floating state, continue to maintain low level, 11 thin film transistor (TFT) T11 closes, 4th thin film transistor (TFT) T4 closes simultaneously.It should be noted that, at this phase III t
3in, charging capacitor Cst carries out first time charging, and the voltage of first node PU is carried out first time pull-up.
Fourth stage t
4, input signal end Vg_n-1 and the first clock signal terminal CK output low level, reset signal end Vg_n+1 and second clock signal end CKB exports high level, 5th thin film transistor (TFT) T5 and the 8th thin film transistor (TFT) T8 closes, 6th thin film transistor (TFT) T6 and the 7th thin film transistor (TFT) T7 opens, Section Point pull-up unit 104 no signal exports, 9th thin film transistor (TFT) T9 opens, the voltage of Section Point PD is pulled down to low level, 11 thin film transistor (TFT) T11 closes, 4th thin film transistor (TFT) T4 closes simultaneously, and the first film transistor T1 and the second thin film transistor (TFT) T2 closes, 3rd thin film transistor (TFT) T3 and opening, first node pull-up unit 102 no signal exports, thus Section Point PU is in floating state, its voltage is pulled to more high level, tenth thin film transistor (TFT) T10 opens, the voltage of output signal end Vg_n keeps high level.It should be noted that, at this fourth stage t
4in, after Section Point PU is in floating state, due to the electric capacity bootstrap effect of charging capacitor Cst, charging capacitor Cst can carry out second time charging, and the voltage of Section Point PU is carried out second time pull-up.
Five-stage t
5, input signal end Vg_n-1 and second clock signal end CKB output low level, reset signal end Vg_n+1 and the first clock signal terminal CK exports high level, the first film transistor T1 closes, second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3 opens, first node pull-up unit 102 no signal exports, 5th thin film transistor (TFT) T5 closes, 6th thin film transistor (TFT) T6, 7th thin film transistor (TFT) T7 and the 8th thin film transistor (TFT) T8 opens, the voltage of Section Point PD is pulled to high level by Section Point pull-up unit 104, 11 thin film transistor (TFT) T11 opens, output signal end Vg_n output low level, 4th thin film transistor (TFT) T4 opens simultaneously, the voltage of first node PU is pulled down to low level, tenth thin film transistor (TFT) T10 closes.
6th stage t
6, input signal end Vg_n-1, reset signal end Vg_n+1 and the first clock signal terminal CK output low level, second clock signal end CKB exports high level, the first film transistor T1, second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3 closes, first node pull-up unit 102 no signal exports, 5th thin film transistor (TFT) T5 and the 8th thin film transistor (TFT) T8 closes, 6th thin film transistor (TFT) T6 and the 7th thin film transistor (TFT) T7 opens, Section Point pull-up unit 104 no signal exports, 9th thin film transistor (TFT) T9 opens, thus the voltage of Section Point PD is pulled down to low level, 11 thin film transistor (TFT) T11 closes, 4th thin film transistor (TFT) T4 opens simultaneously, first node PU keeps low level, tenth thin film transistor (TFT) T10 closes, the voltage of output signal end Vg_n keeps low level.It should be noted that, the 6th stage t
6the output acting as the low level voltage maintaining output signal end Vg_n.
Through first stage t
1~ the six stage t
6, in the driving time of a grid line of a frame, it is t that output signal end Vg_n exports a duration
3+ t
4high level pulse signal, this high level pulse signal is output to the grid line be connected with this grade of shift-register circuit, thus completes the driving to this grid line.Repeat first stage t
1~ the six stage t
6namely the driving of this grid line of next frame can be completed.
Can as apparent from above-mentioned driving process, the voltage of Section Point PD is drawn high by alternating or dragged down, thus make to drag down the 11 thin film transistor (TFT) T11 of unit 107 by alternating unlatching or closedown as output, can't continue in running order, decrease electric leakage, reduce the overall power of shift-register circuit.
In addition, what it is pointed out that the shift-register circuit that the present embodiment provides also has relative to shift-register circuit of the prior art the advantage that structure is simple, drive low, the easy realization of difficulty.
Based on above-mentioned shift-register circuit, the present embodiment additionally provides a kind of gate driver circuit, comprise: the shift-register circuit that multiple the present embodiment of mutually cascade provide, except first order shift-register circuit and afterbody shift-register circuit, the input signal end of every one-level shift-register circuit is connected with the output signal end of upper level shift-register circuit, and the reset signal end of every one-level shift register is connected with the output signal end of next stage shift-register circuit; The input signal termination of first order shift-register circuit is by an initial input signal, and the reset signal termination of afterbody shift-register circuit receives a reset signal.
Owing to have employed the shift-register circuit of the low-power consumption that the present embodiment provides, therefore the overall power of above-mentioned gate driver circuit is also lowered.
The gate driver circuit that the present embodiment provides preferably can be monolateral list and drives type, as shown in Figure 4, the wherein n of SR1 ~ SRn included by a gate driver circuit shift-register circuit, A/A is the active area of display panel, the n bar grid line of GL1 ~ GLn included by display panel, STV is the input signal of first order shift-register circuit SR1, Reset is the reset signal of n-th grade of shift-register circuit SRn, whole shift-register circuit SR1 ~ SRn included by gate driver circuit is connected with same one end of whole grid line GL1 ~ GLn of display panel all one to one, thus register circuit completes the driving work of a grid line.The gate driver circuit of this kind of cascade system is only positioned at one end of display panel, the over all Integration Du Genggao of circuit.
The gate driver circuit that the present embodiment provides preferably also can be two-sided dual-drive and moves type, as shown in Figure 5, gate driver circuit comprises two parts, every part comprises n shift-register circuit SR1 ~ SRn, namely 2n shift-register circuit is comprised altogether, STV is the input signal of the first order shift-register circuit SR1 in two parts, Reset is the reset signal of n-th grade of shift-register circuit SRn in two parts, the half shift-register circuit SR1 ~ SRn of this gate driver circuit is connected with same one end of whole grid line GL1 ~ GLn one to one, second half shift-register circuit SR1 ~ SRn is connected with the other end of whole grid line GL1 ~ GLn one to one.Two parts of the gate driver circuit of this kind of cascade system lay respectively at the relative two ends of display panel, thus the driving work of every bar grid line is completed jointly by two shift-register circuits, two shift-register circuits are simultaneously from the two ends driven grid line of grid line, greatly can improve actuating speed, reduce signal delay, therefore adopt the gate driver circuit of above-mentioned cascade structure to be particularly useful for large-sized display panel.
It should be noted that, the type of drive that monolateral single gate driver circuit driving the gate driver circuit of type and two-sided dual-drive to move type is positioned at every part at display panel two ends is identical, and driver' s timing figure can be as shown in Figure 6.
The gate driver circuit that the present embodiment provides preferably also can be bilateral list and drives type, as shown in Figure 7, gate driver circuit comprises two parts, every part comprises n shift-register circuit SR1 ~ SRn, namely 2n shift-register circuit is comprised altogether, half shift-register circuit SR1 ~ SRn one to one with the odd-numbered line grid line GL1 of display panel, GL3, GL5, same one end of GLn-1 is connected, subject clock signal CK1, the control of CKB1, second half shift-register circuit one to one with the other end GL2 of even number line grid line, GL4, GL6, GLn is connected, subject clock signal CK2, the control of CKB2, STV1 is the input signal of the first order shift-register circuit SR1 be connected with odd-numbered line grid line, STV2 is the input signal of the first order shift-register circuit SR1 be connected with even number line grid line, Reset1 is the reset signal of the n-th grade of shift-register circuit SRn be connected with odd-numbered line grid line, Reset2 is the reset signal of the n-th grade of shift-register circuit SRn be connected with even number line grid line.Two parts of the gate driver circuit of this kind of cascade system are positioned at the relative two ends of display panel, the shift-register circuit of one end completes the driving work of odd-numbered line grid line, the shift-register circuit of the other end completes the driving work of even number line grid line, be equivalent to monolateral single two ends driving the shift-register circuit being originally all positioned at display panel the same side in the gate driver circuit of type to be separated into display panel, thus display panel rim area changes into by original whole frames being positioned at same one end the frame being positioned at two ends for the periphery circuit connecting gate driver circuit, the complexity of display panel rim area periphery circuit is reduced, be conducive to the narrow frame of display panel.
It should be noted that, bilateral single gate driver circuit of type that drives is relative to monolateral single gate driver circuit driving type and two-sided dual-drive to move type, many an initial input signal, a reset signal, also need increase by one group of clock signal (CK2 and CKB2) accordingly, its driver' s timing figure can be as shown in Figure 8.
In addition, based on above-mentioned gate driver circuit, the present embodiment also provides a kind of display device, this display device comprises above-mentioned gate driver circuit, shift-register circuit included by the gate driver circuit in the present embodiment has the advantage of low-power consumption, and the display device that therefore the present embodiment provides also has the advantage of low-power consumption.
It should be noted that, the display device that the present embodiment provides can be liquid crystal panel, Electronic Paper or OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) panel, be applied to any product or parts with Presentation Function such as mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
The foregoing is only the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the present invention discloses, the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (15)
1. a shift-register circuit, is characterized in that, comprising:
The Input Control Element be connected with input signal end, for the input of control inputs signal;
The first node pull-up unit be connected with first node with the first clock signal terminal, reset signal end, described Input Control Element, low level power signal end, for being pulled to high level by the voltage of described first node;
The first node drop-down unit be connected with described first node with Section Point, described low level power signal end, for being pulled down to low level by the voltage of described first node;
The Section Point pull-up unit be connected with Section Point with described input signal end, described first clock signal terminal, described low level power signal end, high level power supply signal end, for being pulled to high level by the voltage of described Section Point;
The Section Point drop-down unit be connected with described Section Point with second clock signal end, described low level power signal end, for being pulled down to low level by the voltage of described Section Point;
The output driver element be connected with output signal end with described first node, described high level power supply signal end, for exporting the output signal of high level when described first node is high level;
The output be connected with described output signal end with described Section Point, described low level power signal end drags down unit, for the voltage of described output signal being pulled down to low level when described first node is low level;
Wherein, described first node is the common port of described first node pull-up unit, described first node drop-down unit and described output driver element, the common port that described Section Point is described Section Point pull-up unit, described Section Point drop-down unit, described first node drop-down unit and described output drag down unit.
2. shift-register circuit according to claim 1, it is characterized in that, described Input Control Element comprises: the first film transistor, and the control end of described the first film transistor is all connected with described input signal end with input end, and output terminal is connected with described first node pull-up unit.
3. shift-register circuit according to claim 1, is characterized in that, described first node pull-up unit comprises:
Second thin film transistor (TFT), the control end of described second thin film transistor (TFT) is connected with described first clock signal terminal, and input end is connected with described Input Control Element, and output terminal is connected with described first node;
Memory capacitance, the first end of described memory capacitance is connected with described first node, and the second end is connected with described reset signal end;
3rd thin film transistor (TFT), the control end of described 3rd thin film transistor (TFT) is connected with described reset signal end, and input end is connected with described low level power signal end, and output terminal is connected with the input end of described second thin film transistor (TFT).
4. shift-register circuit according to claim 1, it is characterized in that, described first node drop-down unit comprises: the 4th thin film transistor (TFT), the control end of described 4th thin film transistor (TFT) is connected with described Section Point, input end is connected with described low level power signal end, and output terminal is connected with described first node.
5. shift-register circuit according to claim 1, is characterized in that, described Section Point pull-up unit comprises:
5th thin film transistor (TFT), the control end of described 5th thin film transistor (TFT) is connected with described input signal end, input end is connected with described low level power signal end;
6th thin film transistor (TFT), the control end of described 6th thin film transistor (TFT) is all connected with described high level power supply signal end with input end, and output terminal is connected with the output terminal of described 5th thin film transistor (TFT);
7th thin film transistor (TFT), the common port that the control end of described 7th thin film transistor (TFT) is connected with the output terminal of described 6th thin film transistor (TFT) with the output terminal of described 5th thin film transistor (TFT) is connected, and input end is connected with the control end of described 6th thin film transistor (TFT);
8th thin film transistor (TFT), the control end of described 8th thin film transistor (TFT) is connected with described first clock signal terminal, and input end is connected with the output terminal of described 7th thin film transistor (TFT), and output terminal is connected with described Section Point.
6. shift-register circuit according to claim 1, it is characterized in that, described Section Point drop-down unit comprises: the 9th thin film transistor (TFT), the control end of described 9th thin film transistor (TFT) is connected with described second clock signal end, input end is connected with described low level power signal end, and output terminal is connected with described Section Point.
7. shift-register circuit according to claim 1, it is characterized in that, described output driver element comprises: the tenth thin film transistor (TFT), the control end of described tenth thin film transistor (TFT) is connected with described first node, input end is connected with described high level power supply signal end, and output terminal is connected with described output signal end.
8. shift-register circuit according to claim 1, it is characterized in that, described output drags down unit and comprises: the 11 thin film transistor (TFT), the control end of described 11 thin film transistor (TFT) is connected with described Section Point, input end is connected with described low level power signal end, and output terminal is connected with described output signal end.
9. a driving method for shift-register circuit, is characterized in that, for driving the shift-register circuit described in any one of claim 1 ~ 8, described driving method comprises:
First stage, input signal end and second clock signal end output low level, reset signal end and the first clock signal terminal export high level, input signal control module is closed, first node pull-up unit no signal exports, the voltage of first node is pulled down to low level by first node drop-down unit, output driver element is closed, Section Point drop-down unit is closed, the voltage of Section Point is pulled to high level by Section Point pull-up unit, and output drags down unit and the voltage of output signal end is pulled down to low level;
Subordinate phase, described input signal end and described second clock signal end export high level, described reset signal end and described first clock signal terminal output low level, described input signal control module is opened, described first node pull-up unit no signal exports, described first node drop-down unit is closed, the voltage of described first node keeps low level, described output driver element is closed, described Section Point pull-up unit no signal exports, the voltage of described Section Point is pulled down to low level by described Section Point drop-down unit, described output drags down unit and closes, the voltage of described output signal end keeps low level,
Phase III, described input signal end and described first clock signal terminal export high level, described reset signal end and described second clock signal end output low level, described Section Point pull-up unit no signal exports, described Section Point drop-down unit is closed, the voltage of described Section Point keeps low level, described output drags down unit and closes, described first node drop-down unit is closed, described input signal control module is opened, the voltage of described first node is pulled to high level by described first node pull-up unit, the voltage of described output signal end is pulled to high level by described output driver element,
Fourth stage, described input signal end and described first clock signal terminal output low level, described reset signal end and described second clock signal end export high level, described Section Point pull-up unit no signal exports, the voltage of described Section Point is pulled down to low level by described Section Point drop-down unit, described output drags down unit and closes, described input signal control module is closed, described first node drop-down unit is closed, the voltage of described first node is continued to be pulled to more high level by described first node pull-up unit, described output driver element keeps the voltage of described output signal end to be pulled to high level,
Five-stage, described input signal end and described second clock signal end output low level, described reset signal end and described first clock signal terminal export high level, described input signal control module is closed, described first node pull-up unit no signal exports, the voltage of described first node is pulled down to low level by described first node drop-down unit, described output driver element is closed, described Section Point drop-down unit is closed, the voltage of described Section Point is pulled to high level by described Section Point pull-up unit, described output drags down unit and the voltage of described output signal end is pulled down to low level,
6th stage, described input signal end, described reset signal end and described first clock signal terminal output low level, described second clock signal end exports high level, described input signal control module is closed, described first node pull-up unit no signal exports, described first node drop-down unit is closed, described first node keeps low level, described output driver element is closed, described Section Point pull-up unit no signal exports, the voltage of described Section Point is pulled down to low level by described Section Point drop-down unit, described output drags down unit and closes, the voltage of described output signal end keeps low level.
10. the driving method of shift-register circuit according to claim 9, it is characterized in that, described Input Control Element comprises the first film transistor, described first node pull-up unit comprises the second thin film transistor (TFT), memory capacitance and the 3rd thin film transistor (TFT), described first node drop-down unit comprises the 4th thin film transistor (TFT), described Section Point pull-up unit comprises the 5th thin film transistor (TFT), 6th thin film transistor (TFT), 7th thin film transistor (TFT) and the 8th thin film transistor (TFT), described Section Point drop-down unit comprises the 9th thin film transistor (TFT), described output driver element comprises the tenth thin film transistor (TFT), described output drags down unit and comprises the 11 thin film transistor (TFT), described driving method specifically comprises:
First stage, described input signal end and described second clock signal end output low level, described reset signal end and described first clock signal terminal export high level, described the first film transistor, described 3rd thin film transistor (TFT), described 5th thin film transistor (TFT) and described 9th thin film transistor (TFT) are closed, described second thin film transistor (TFT), described 4th thin film transistor (TFT), described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 8th thin film transistor (TFT) are opened, the voltage of described first node is pulled down to low level, described tenth thin film transistor (TFT) cuts out, the voltage of described Section Point is pulled to high level, described 11 thin film transistor (TFT) is opened, the voltage of described output signal end is pulled down to low level,
Subordinate phase, described input signal end and described second clock signal end export high level, described reset signal end and described first clock signal terminal output low level, described second thin film transistor (TFT), described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 8th thin film transistor (TFT) are closed, described the first film transistor, described 5th thin film transistor (TFT), described 6th thin film transistor (TFT) and described 9th thin film transistor (TFT) are opened, the voltage of described first node keeps low level, described tenth thin film transistor (TFT) cuts out, the voltage of described Section Point is pulled down to low level, described 11 thin film transistor (TFT) cuts out, the voltage of described output signal end keeps low level,
Phase III, described input signal end and described first clock signal terminal export high level, described reset signal end and described second clock signal end output low level, described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 9th thin film transistor (TFT) are closed, described the first film transistor, described second thin film transistor (TFT), described 5th thin film transistor (TFT), described 6th thin film transistor (TFT) and described 8th thin film transistor (TFT) are opened, the voltage of described Section Point keeps low level, described 11 thin film transistor (TFT) cuts out, the voltage of described first node is pulled to high level, described tenth thin film transistor (TFT) is opened, the voltage of described output signal end is pulled to high level,
Fourth stage, described input signal end and described first clock signal terminal output low level, described reset signal end and described second clock signal end export high level, described the first film transistor, described second thin film transistor (TFT), described 4th thin film transistor (TFT), described 5th thin film transistor (TFT) and described 8th thin film transistor (TFT) are closed, described 3rd thin film transistor (TFT), described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 9th thin film transistor (TFT) are opened, the voltage of described Section Point is pulled down to low level, described 11 thin film transistor (TFT) cuts out, the voltage of described first node is continued to be pulled to more high level, described tenth thin film transistor (TFT) is opened, the voltage of described output signal end keeps high level,
Five-stage, described input signal end and described second clock signal end output low level, described reset signal end and described first clock signal terminal export high level, described the first film transistor, described 5th thin film transistor (TFT) and described 9th thin film transistor (TFT) are closed, described second thin film transistor (TFT), described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 8th thin film transistor (TFT) are opened, the voltage of described first node is pulled down to low level, described tenth thin film transistor (TFT) cuts out, the voltage of described Section Point is pulled to high level, described 11 thin film transistor (TFT) is opened, the voltage of described output signal end is pulled down to low level,
6th stage, described input signal end, described reset signal end and described first clock signal terminal output low level, described second clock signal end exports high level, described the first film transistor, described second thin film transistor (TFT), described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 5th thin film transistor (TFT) and described 8th thin film transistor (TFT) are closed, described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 9th thin film transistor (TFT) are opened, described first node keeps low level, described tenth thin film transistor (TFT) cuts out, the voltage of described Section Point is pulled down to low level, described 11 thin film transistor (TFT) cuts out, the voltage of described output signal end keeps low level.
11. 1 kinds of gate driver circuits, it is characterized in that, comprise: multiple shift-register circuits as described in any one of claim 1 ~ 8 of cascade mutually, except first order shift-register circuit and afterbody shift-register circuit, the input signal end of every one-level shift-register circuit is connected with the output signal end of upper level shift-register circuit, and the reset signal end of every one-level shift register is connected with the output signal end of next stage shift-register circuit.
12. gate driver circuits according to claim 11, is characterized in that, the whole shift-register circuits included by described gate driver circuit are connected with same one end of whole grid lines of display panel all one to one.
13. gate driver circuits according to claim 11, it is characterized in that, the half shift-register circuit of described gate driver circuit is connected with same one end of whole grid lines of display panel one to one, and second half shift-register circuit of described gate driver circuit is connected with the other end of whole grid lines of display panel one to one.
14. gate driver circuits according to claim 11, it is characterized in that, the half shift-register circuit of described gate driver circuit is connected with same one end of the odd-numbered line grid line of display panel one to one, and second half shift-register circuit of described gate driver circuit is connected with the other end of the even number line grid line of display panel one to one.
15. 1 kinds of display device, is characterized in that, comprise the gate driver circuit described in any one of claim 11 ~ 14.
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