CN106328074B - Image display system and gate driving circuit - Google Patents
Image display system and gate driving circuit Download PDFInfo
- Publication number
- CN106328074B CN106328074B CN201510357109.5A CN201510357109A CN106328074B CN 106328074 B CN106328074 B CN 106328074B CN 201510357109 A CN201510357109 A CN 201510357109A CN 106328074 B CN106328074 B CN 106328074B
- Authority
- CN
- China
- Prior art keywords
- signal
- grades
- shift register
- control
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A kind of image display system and gate driving circuit.The gate driving circuit, including multiple shift registers, sequentially to export gate drive signal, shift register is distinguished into multiple groups of shift registers of sequential；And multiple compensation circuits, it is arranged in a compensation circuit every one group of shift register, each compensation circuit is connected to first shift register in the last one shift register and N+1 group shift register in N group shift register, to according to first control signal and second control signal, one in the two shift registers is caused to be pre-charged, and another progress signal maintenance in the two shift registers.
Description
Technical field
The present invention relates to a kind of shift register module, in particular to the gate driving of a kind of avoidable shift register is believed
Number rising edge and/or failing edge be touched sense period influence gate driving circuit.
Background technique
Shift register (shift register) is widely used in data-signal transmitting circuit and gate driving circuit,
The timing of data-signal is received to control each data signal line respectively, and generates scanning signal for each gate line.?
In data-signal transmitting circuit, shift register is to export a selection signal to each data signal line, so that image data can
Sequentially it is written into each data signal line.On the other hand, in gate driving circuit, shift register is to generate scan signal
To each gate line, sequentially to open picture element matrix the picture signal of each data signal line is written.
In recent years, the integrated gate drivers of amorphous silicon (Amorphous Silicon Gate driver, letter are developed
Claim ASG) technology.ASG technology be in the thin film transistor (TFT) technique of amorphous silicon directly by include these thin film transistor (TFT)s grid
Pole driving circuit is integrated on display panel (such as glass substrate of display), to replace the use of gate drivers chip,
This technology is referred to as the gate drivers (Gate driver On Panel, abbreviation GOP) on panel.Therefore, using ASG and
GOP technology can reduce the use of the chip of liquid crystal display, and then can reduce manufacturing cost and shorten the manufacturing cycle.
Touch function is integrated into display unit by embedded (in-cell) touch-control display panel now, and is being shown
In addition the construction of touch control unit is not set except unit, such as touch function is integrated into liquid crystal display or organic electroluminescence hair
Optical element (OLED) unit, the electrode structure that usually touch function often utilizes display unit existing under such structure come real
It is existing, therefore do not need additional touch-control construction.For example, when In-cell touch display panel is fringe field switch type (Fringe
Field Switching, FFS) liquid crystal display panel when, it will usually its common electrode pattern is done with being distinguished into multiple pieces
For the use of touch-control sensing electrode, the thickness and weight of touch-control display panel entirety can be so reduced.Due to touch function and liquid
Brilliant display unit combines, each frame (frame) need to be cut into one or more touch-control sensing periods progress touch-control senses
It surveys.However, in the touch-control sensing period, multiple clock signals supplied to the shift register in gate driving circuit will be by
Pause, therefore the rising edge or failing edge of the gate drive signal that certain shift registers can be made to be exported undeservedly are extended,
And cause the decline of display picture quality.Therefore, it is necessary to a kind of completely new shift register frameworks, can improve above-mentioned
Problem.
Summary of the invention
This specification provides an a kind of embodiment of image display system.The image display system, including a touch-control are shown
Panel, multiple pixels comprising a picture element matrix；And a gate driving circuit, it is multiple to be generated according to one group of clock signal
Gate drive signal, to drive the multiple pixels for being located at the touch-control display panel, which includes: that multiple displacements are posted
Storage, sequentially to export the grade gate drive signals, which is distinguished into multiple displacements of sequentially number arrangement
Register group, wherein N group displacement is posted in two adjacent N group shift register groups and N+1 group shift register group
The gate drive signal of the afterbody shift register of storage group and the first order displacement of the N+1 group shift register group are posted
The gate drive signal of storage is continuous；And at least one first compensation circuit, first compensation circuit are arranged in the two adjacent shifting
Between bit register group, which is connected to the afterbody shift register of the N group shift register group
With the first order shift register of the N+1 group shift register group, wherein first compensation circuit provides one first control
Signal gives the afterbody shift register of the N group shift register group to carry out signal maintenance (holding), compensation electricity
Road and provide a second control signal be pre-charged to the first order shift register of the N+1 group shift register group,
Wherein N is the positive integer greater than zero.
This specification provides an a kind of embodiment of gate driving circuit.The gate driving circuit, when to according to one group
Clock signal generates multiple gate drive signals, to drive the multiple pixels for the picture element matrix being located on a touch-control display panel,
The gate driving circuit includes: multiple shift registers, sequentially to export the grade gate drive signals, the equal shift registers
Multiple groups of shift register groups of sequentially number arrangement are distinguished into, wherein two adjacent N group shift register groups and N+1 group
In shift register group, the gate drive signal and the N+1 of the afterbody shift register of the N group shift register group
The gate drive signal of the first order shift register of group shift register group is continuous；And at least one first compensation circuit, it should
First compensation circuit is arranged between the two adjacent shift registers group, which is connected to N group displacement and posts
The afterbody shift register of storage group and the first order shift register of the N+1 group shift register group, wherein
First compensation circuit provide a first control signal to the N group shift register group the afterbody shift register into
Row signal maintains (holding), which simultaneously provides a second control signal being somebody's turn to do to the N+1 group shift register group
First order shift register is pre-charged.
This specification provides an a kind of embodiment of gate driving circuit.The gate driving circuit is located at a touch-control and shows
On panel, which includes: a K grades of shift registers, is set in a rim area of the touch-control display panel,
To export a K grades of gate drive signals；One K+1 grades of shift registers, are set in the rim area, to export one
K+1 grades of gate drive signals；And one first compensation circuit, it is set to the K grades of shift registers and K+1 in the rim area
Between grade shift register, moved with the K grades of gate drive signals to avoid the K grades of shift registers with this K+1 grades
One rising edge and/or a failing edge of the K+1 grades of gate drive signals of bit register are by the embedded touch display surface
The influence in one touch-control sensing period of plate, wherein K is the positive integer greater than zero, which includes one first son compensation electricity
Road and one second sub- compensation circuit, the first sub- compensation circuit are integrated into the K grades of shift registers, and second son
Compensation circuit is integrated into the K+1 grades of shift registers.
Detailed description of the invention
Figure 1A is the schematic diagram of image display system of the invention.
Figure 1B is the schematic diagram of image display system of the invention.
Fig. 1 C is the schematic diagram of image display system of the invention.
Fig. 2 is to show gate driving circuit schematic diagram described in Figure 1A according to the present invention.
Fig. 3 is to show shift-register circuit figure described in an embodiment according to the present invention.
Fig. 4 is the signal waveforms for showing shift register as shown in Figure 3 when forward scan.
Fig. 5 is to show the shift-register circuit figure described according to another embodiment of the present invention.
Fig. 6 is the signal waveforms for showing shift register as shown in Figure 5 when reverse scan.
Fig. 7 is the schematic diagram of a frame (frame) for touch-control display panel in the embodiment of the present invention.
Fig. 8 is another schematic diagram of gate driving circuit of the invention.
Fig. 9 is a schematic diagram of compensation circuit in the application.
Figure 10 is an embodiment of the first sub- compensation circuit SPHC1.
Figure 11 is an embodiment of the second sub- compensation circuit SPHC2.
The operation timing figure that Figure 12 A is the 10th, the first, second sub- compensation circuit SPHC1 and SPHC2 in 11 figures.
The figure of another operation timing that Figure 12 B is the 10th, the first, second sub- compensation circuit SPHC1 and SPHC2 in 11 figures.
Figure 13 is another embodiment of compensation circuit.
Figure 14 is another embodiment of compensation circuit.
Figure 15 is wiring schematic diagram of the invention.
[symbol description]
100~electronic device；
101~touch-control display panel；
102~power supply unit；
110A, 110B, 110C~gate driving circuit；
120~data-signal transmitting circuit；
130~picture element matrix；
140~control chip；
150~touch control detection circuit；
SR[1]、SR[2]、SR[3]、SR[35]、SR[36]、SR[K]、SR[K+1]、SR[K+2]、SR[2K]、SR[X-2]、
SR [X-1], SR [X]~shift register；
501,701~forward direction input circuit；
702 502 ,~reversed input circuit；
503,703~output circuit；
CK, IN_F, IN_R, N, OUT, P, P35, P36, PP35, PP36, RSET_F, RSET_R, VG~endpoint；
CK1、CK2、CK3、CK4、CK5、CK6、N(1)、N(2)、N(3)、N(4)、N(5)、N(6)、N(K-3)、N(K-1)、N
(K)、N(K+1)、N(K+3)、N(X-5)、N(X-3)、N(X-2)、N(X-1)、N(X)、OUT(1)、OUT(2)、OUT(3)、OUT
(32)、OUT(33)、OUT(34)、OUT(35)、OUT(36)、OUT(37)、OUT(38)、OUT(39)、OUT(K-3)、OUT(K-
2)、OUT(K-1)、OUT(K)、OUT(K+1)、OUT(K+2)、OUT(K+3)、OUT(K+4)、OUT(2K)、OUT(2K+1)、OUT
(X-2), OUT (X-1), OUT (X), P (3), P (X-2), VGL, VGH, P1, P2, S1, S2~signal；
PHC, PHC [1], PHC [2]~compensation circuit；
The sub- compensation circuit of SPHC1, SPHC1A, SPHC1B~first；
The sub- compensation circuit of SPHC2, SPHC2A, SPHC2B~second；
M1、M2、M3、M4、M5、M6、M7、M8、M9、M10、MP1、MP2、MP3、MP4、MP5、MP6、MP7、MP8、MP9、
MP10~transistor；
The circuit of C1, C1 "~first；
C2, C2 "~second circuit；
GL1, GL2, GL3, GL4, GLK, GLK+1, GLK+2, GL2K, GLX-2, GLX-1, GLX~gate line；
STV1, STV2~initial pulse.
Specific embodiment
Fig. 1 is the embodiment for showing the image display system in the present invention.As shown, image display system may include
One touch-control display panel 101, whether to show image and induction one exterior object touching.In one embodiment of the invention
In, touch-control display panel 101 is an In-cell touch display panel (in-cell touch display panel), but unlimited
Due to this, be also possible to externally embedded type touch-control display panel (on/out-cell touch display panel) or interior/
Externally embedded type touch-control display panel (in/on-cell touch display panel), so-called inside/outside embedded touch-control display panel
It is the detection that a direction is carried out using gate driving circuit；And the sensing in another direction is set in colored optical filtering substrates
Electrode structure.Touch-control display panel 101 includes a gate driving circuit 110, a data-signal transmitting circuit 120, a pixel square
Battle array 130, one controls chip 140 and a touch control detection circuit 150.Here, data drive circuit 120, one control chip 140 with
And one touch control detection circuit 150 can be chip independent, or three is combined into an one chip by integrating, but not
As limit, a single core can also be integrated by being also possible to data-signal transmitting circuit 120 and a touch control detection circuit 150
Piece.
Gate driving circuit 110 drives multiple pixels of picture element matrix 130 to generate multiple gate drive signals.Number
Multiple pixels of picture element matrix 130 are provided data to generate multiple data-signals according to signal transfer circuit 120.Citing and
Speech, picture element matrix 130 can be made of multiple gate lines, multiple data signal lines and multiple pixels.In certain implementations
In example, the pixel of picture element matrix 130 is combined with the induction electrode to sense touch-control, so that touch-control display panel 101,
Whether being able to display image and incude exterior object touching.Chip 140 is controlled to generate multiple control signal, including clock
Signal and initial pulse etc..Touch control detection circuit 150 generates a touching position by the voltage or charge variation of sensing induction electrode
Data are set, and touch position data are sent to a ppu and carry out subsequent processing.For example, induction electrode is to sense
One stylus or finger touch the small capacitance variations occurred when touch-control display panel 101, the capacitance variations that will be sensed
Voltage form is converted to, and this variation is detected by touch control detection circuit 150.In one embodiment of this invention, picture element matrix
130 are located on a substrate, and gate driving circuit 110 is with the integrated gate drivers of amorphous silicon (Amorphous Silicon
Gate driver, abbreviation ASG) technology is made on the substrate, to form (the Gate driver of the gate drivers on panel
On Panel, abbreviation GOP).
In addition, image display system of the invention may include in an electronic device 100.Electronic device 100 may include touch-control
Display panel 101 and a power supply unit 102.Power supply unit 102 is to be powered touch-control display panel 101.According to this hair
Bright embodiment, electronic device 100 can for a mobile phone, a digital camera, a personal digital assistant, a mobile computer,
One desktop PC, a television set, an automobile display, a portable optic disk dial put device or it is any include image show
The device of function.An embodiment according to the present invention, the scanning sequency that gate driving circuit 110 can be different is (for example, forward direction is swept
Retouch sequence and reverse scan order) sequentially output gate drive signal is to each gate line, to be sequentially supplied to each number
In pixel according to the picture signal writing pixel matrix 130 of signal wire.
Figure 1B is another embodiment for showing the image display system in the present invention.As shown, image display system
It may include gate driving circuit 110A and 110B, grid of the gate driving circuit 110A to drive odd number in picture element matrix 130
Signal wire (such as GL1, GL3 ... GLX-1), and grid of the gate driving circuit 110B to drive even number in picture element matrix 130
Signal wire (such as GL2, GL4 ... GLX-2, GLX).Gate driving circuit 110A and 110B are set to touch-control display panel 101
It is not ipsilateral, so that frame is symmetrical.By gate driving circuit output drive signal with the setting of design method as odd number, even number
Active area (area Active Area, i.e. display area) can be all disposed within to avoid gate driving circuit same one side cause it is non-
The setting area of display area circuit, which is excessively stopped up, squeezes, and therefore, can achieve narrow frame (narrow border), and wiring
Area equalization, and then make the consistent purpose of design of frame area on both sides.
Fig. 1 C is another embodiment for showing the image display system in the present invention.As shown, image display system
It may include the two sides that gate driving circuit 110A and 110B are separately positioned on active area, each grid in picture element matrix 130
Signal wire is by the shift register institute in the shift register and gate driving circuit 110B in gate driving circuit 110A
Common driving, the case where when to be applied to load larger.For example, for large size panel (such as more than 30 inch), respectively
Each gate line GL1 is because length is longer, therefore heavier loads (i.e. electric group-capacitive load weight), therefore each gate line GL1
It is driven jointly by the shift register SR1 of gate driving circuit 110A and both 110B, and so on.
Fig. 2 is the schematic diagram for showing gate driving circuit 110A described in Figure 1A according to the present invention.Gate driving circuit
110A include X grades concatenation shift registers 300, i.e. shift register SR [1], SR [2], SR [3] ... SR [X-2], SR [X-
1] with SR [X], wherein X is a positive integer.Each shift register respectively includes several input end of clock point CK, voltage signal input
Endpoint VG, forward signal input endpoint IN_F, non-inverting signal input thereof point IN_R, exit point OUT, signal transmitting endpoint N, just
To reset signal input endpoint RSET_F and reversed reset signal input endpoint RSET_R.The signal of shift registers at different levels transmits
Endpoint N will export driving signal identical with exit point OUT, the pulse of driving signal is sequentially transmitted to displacements at different levels
Between register.
In gate driving circuit 110A when forward scan, each shift register 300 with one first sequence, sequentially drive by output
Dynamic signal, for example, shift register SR [1] to SR [X] will sequentially output drive signal OUT (1), OUT (2), OUT (3) ... OUT
(X-2), OUT (X-1) and OUT (X).On the other hand, when reverse scan, each shift register 300 is with opposite one second
Sequence sequentially output drive signal, for example, shift register SR [X] to SR [1] sequentially output drive signal OUT (X), OUT (X-
1), OUT (X-2) ... OUT (3), OUT (2) and OUT (1).
110 automatic control coremaking piece 140 of gate driving circuit receive multiple control signal, including clock signal CK1, CK2, CK3,
CK4, CK5 and CK6, initial pulse STV1, STV2 and determining voltage signal VGL.In general, clock signal CK1, CK2,
CK3, CK4, CK5 have half of pulse period Chong Die two-by-two with CK6, for example, with reference to the waveform diagram of Fig. 4, before clock signal CK2
Rear half of pulse overlap of half of pulse and clock signal CK1, and rear half of pulse of clock signal CK2 and clock signal CK3
Preceding half of pulse overlap.Usual clock signal CK1, CK3 and CK5 are provided to the shift register of odd (idol) several levels, and clock
Signal CK2, CK4 and CK6 are provided to the shift register of even (surprise) several levels.
Initial pulse STV1 and STV2 is to starting gate driving circuit 110A.As shown, gate driving circuit 110A
First order shift register SR [1] receive initial pulse STV1 as positive input letter in forward signal input endpoint IN_F
Number, afterbody shift register SR [X] receives initial pulse STV2 as reversed input in non-inverting signal input thereof point IN_R
Signal.In addition, shift register SR [2]-SR [X-1] receives previous stage shift LD respectively at forward signal input endpoint IN_F
Device receives rear stage displacement as positive input signal, and in non-inverting signal input thereof point IN_R in the driving signal exported
The driving signal that register is exported is as reversed input signal.
In one embodiment of this invention, shift register is usually after positive reset signal input endpoint RSET_F reception
The driving signal that two-stage or rear three-level shift register are exported is inputted as positive reset signal, and in reversed reset signal
The driving signal that two-stage or preceding three-level shift register are exported before endpoint RSET_R is received is as reversed reset signal.In this hair
In bright another embodiment, shift register also can receive the driving signal that latter or multi-stage shift register is exported and be used as just
To reset signal, and the driving signal that the previous or multi-stage shift register of reception is exported is as reversed reset signal.In addition,
It is worth noting that, the positive and reversed reset signal coupling of one or more shift registers in gate driving circuit 110A end to end
The method of connecing can also make special design, to avoid timing error is generated.
For example, as shown in Figure 2, the reversed reset signal input terminal of shift register SR [1], SR [2] and SR [3]
Point RSET_R is connected to initial pulse STV1, and shift register SR [1], SR [2] and the positive reset signal of SR [3] input
Endpoint RSET_F is respectively connected to signal transmitting endpoint N [4], N [5] and the N of shift register SR [4], SR [5] and SR [6]
[6].The positive reset signal input endpoint RSET_F of shift register SR [X-2], SR [X-1] and SR [X] are connected to starting
Pulse STV2, and the reversed reset signal input endpoint RSET_R of shift register SR [X-2], SR [X-1] and SR [X] connect respectively
It is connected to signal transmitting endpoint N [X-4] of shift register SR [X-3], SR [X-4] and SR [X-5], N [X-5] and N [X-6].It removes
Except shift register SR [1] to SR [3] and SR [X-2] to SR [X], other shift registers (SR [4] to SR [X-3]) exist
The driving signal that two-stage or rear three-level shift register are exported after positive reset signal input endpoint RSET_F is received is as just
To reset signal, and before reversed reset signal input endpoint RSET_R is received, two-stage or preceding three-level shift register are exported
Driving signal as reversed reset signal.For example, the positive reset signal input endpoint of shift register SR [4]
RSET_F and reversed reset signal input endpoint RSET_R be separately connected signal transmitting endpoint N [7] of shift register SR [7] with
The signal of shift register SR [1] transmits endpoint N [1], and the positive reset signal input endpoint of shift register SR [5]
RSET_F and reversed reset signal input endpoint RSET_R be separately connected signal transmitting endpoint N [8] of shift register SR [8] with
The signal of shift register SR [2] transmits endpoint N [2], and so on.
Fig. 3 is to show the shift-register circuit figure described according to another embodiment of the present invention.Fig. 4 is display such as Fig. 3
Shown in signal waveforms of the shift register in forward scan.In this embodiment, shift register SR [3] represents grid
The shift register of 3rd level in driving circuit 110 comprising positive input circuit 501, reversed input circuit 502 and output electricity
Road 503, and realized with NMOS transistor M1-M10.In forward scan, transistor M3 is first because clock signal CK1 is drawn
Rise pulse and be connected, control endpoint P be coupled to positive input signal N (2).At this time since positive input signal N (2) still maintains
In low voltage level, therefore the voltage for controlling endpoint P is maintained at low voltage level.Pulse to positive input signal N (2) is arrived at
Afterwards, transistor M1 is switched on, and starts will to control the voltage pre-charge of endpoint P to the first high-voltage level ((3) signal P in such as Fig. 4
Waveform).
Since control endpoint P has high-voltage level, transistor M7 and M8 can be switched on, so that the arteries and veins of clock signal CK3
Punching can be transferred to exit point OUT and signal transmits endpoint N.Therefore, during transistor M7 and M8 is switched on, driving signal
OUT (3) and signal N (3) will be with clock signal CK3 phases having the same.In addition, there is high voltage electricity in clock signal CK3
Flat pulse section, the voltage of control endpoint P can more further pass through parasitic capacitance (or the capacitor additionally coupled) to be believed by clock
Number CK3 fills height to the second high-voltage level, to further increase the grid voltage of transistor M7 and M8.Higher grid voltage
Help speed up the charge/discharge speed of exit point OUT and signal transmitting endpoint N.
After the end-of-pulsing of clock signal CK3, since the drain voltage of transistor M7 and M8 are restored to low voltage level,
The voltage of control endpoint P starts to be discharged back the first high-voltage level by the second high-voltage level.Then, to positive reset signal
After the pulse of N (6) is arrived at, transistor M5 is switched on, and control endpoint P is coupled to the determining voltage signal with low voltage level
The tension discharge for controlling endpoint P is further returned low voltage level by VGL.
As above-mentioned, in forward scan, positive input circuit is the circuit of the voltage of main control control endpoint, and reversed
Input circuit can become the circuit of auxiliary, to assist the operation of positive input circuit.It is referenced to Fig. 3, signal N (4) and clock
The transistor M2 of reversed input circuit can be connected with M4 respectively for the pulse of signal CK5, to assist the signal dimension of control endpoint P
Hold (signal holding) and electric discharge.
Fig. 5 is to show the shift-register circuit figure described according to another embodiment of the present invention.Fig. 6 is display such as Fig. 5
Shown in signal waveforms of shift register when reverse scan.In this embodiment, shift register SR [X-2] represents grid
The shift register of (X-2) grade in pole driving circuit 110 comprising positive input circuit 701, reversed input circuit 702 with
Output circuit 703, and realized with NMOS transistor M1-M10.In reverse scan, grid are originated by initial pulse STV2
The running of pole driving circuit 110, and the pulse sequence of clock signal CK1-CK6 overturns (as shown in Figure 6).Transistor M4 is first
It is connected because of the pulse of clock signal CK6 pull-up, control endpoint P is coupled to positive input signal N (X-1).At this time due to reversed
Input signal N (X-1) is still maintained at low voltage level, therefore the voltage for controlling endpoint P is maintained at low voltage level.To reversed defeated
After the pulse arrival for entering signal N (X-1), transistor M2 is switched on, and the voltage pre-charge for starting to control endpoint P is electric to the first height
Voltage level (waveform of signal P (X-2) in such as Fig. 6).
Since control endpoint P has high-voltage level, transistor M7 and M8 can be switched on, so that the arteries and veins of clock signal CK4
Punching can be transferred to exit point OUT and signal transmits endpoint N.Therefore, during transistor M7 and M8 is switched on, driving signal
OUT (X-2) and signal N (X-2) will be with clock signal CK4 phases having the same.In addition, there is high electricity in clock signal CK4
The pulse section of voltage level, control endpoint P voltage can more further pass through parasitic capacitance (or the capacitor additionally coupled) by when
Clock signal CK4 fills height to the second high-voltage level, to further increase the grid voltage of transistor M7 and M8.Higher grid
Voltage helps speed up the charge/discharge speed of exit point OUT and signal transmitting endpoint N.
After the end-of-pulsing of clock signal CK4, since the drain voltage of transistor M7 and M8 are restored to low voltage level,
The voltage of control endpoint P starts to be discharged back the first high-voltage level by the second high-voltage level.Then, to positive reset signal
After the pulse of N (X-5) is arrived at, transistor M6 is switched on, and control endpoint P is coupled to the determining voltage signal with low voltage level
The tension discharge for controlling endpoint P is further returned low voltage level by VGL.
As above-mentioned, in reverse scan, reversed input circuit is the circuit of the voltage of main control control endpoint, and positive
Input circuit can become the circuit of auxiliary, to assist the operation of reversed input circuit.Be referenced to Fig. 5, signal N (X-3) and when
The transistor M1 of positive input circuit can be connected with M3 respectively for the pulse of clock signal CK2, to assist the signal of control endpoint P
Maintain (signal holding) and electric discharge.
Although in addition, Fig. 2~Fig. 6 of the present invention illustrate can with the shift register of positive and negative bilateral scanning, not as
The type of limit, the shift register of only positive (unidirectional) scanning is also within the scope of the present invention.
Fig. 7 is the schematic diagram of a frame (frame) for touch-control display panel in the embodiment of the present invention.Due to touch-control display surface
Plate 101 is an In-cell touch display panel, so each frame can include at least one display cycle and at least one touching
Control sense period.As shown, several touch-control sensing periods alternately arrange with several display cycles in a frame (frame)
Column.It further explains, the touch-control sensing period is alternately arranged with display cycle property in a frame, for example, will operate in aobvious
Show that the N grade shift register in period is divided into M shift register group, and the shift register quantity in each group is equal.
In another embodiment, the touch-control sensing period can also be alternately arranged with display in aperiodicity, for example, the period will be operated in
The N grade shift register of display is divided into M shift register group, and the shift register quantity in each group is unequal.
In addition, in another embodiment, the touch-control sensing period can be only one, and the display cycle is in an interior quilt of frame (frame)
It is divided into twoth area, and the touch-control sensing period was routed in the display cycle in this twoth area, likewise, in the display cycle in this twoth area
Shift register quantity can be equal or unequal.It refer again to Fig. 7, in each display cycle, gate driving circuit
One group of shift register in 110A can sequentially defeated one group of gate drive signal, with drive in picture element matrix 103 one group it is corresponding
Gate line, and in each touch-control sensing period, induction electrode carries out touch-control sensing.In a certain embodiment, each touching
Sense period is controlled between two display cycles.In Fig. 7, display cycle and touch-control sensing amount of cycles are all even numbers, but
In another embodiment, being also possible to display cycle quantity is even number, and touch-control sensing amount of cycles is odd number, so that
The last one period of one frame end can maintain to be efficiency of the display cycle without influencing whether former display.
Fig. 8 is another schematic diagram of gate driving circuit of the invention.As shown, gate driving circuit includes multiple strings
The shift register connect, such as SR [1], SR [2] ... SR [2K+1] and multiple compensation circuits, such as PHC [1], PHC [2],
Wherein K is the positive integer greater than zero (in the example of fig. 8, K is greater than the positive integer equal to 3).Shifting in gate driving circuit
Bit register to according to control the provided clock signal CK1~CK6 of chip 140, sequentially generate multiple gate drive signals, with
Drive multiple pixels of picture element matrix 130.For example, the exit point of shift register SR [1] is (i.e. to export OUT (1)
Endpoint) be connected to gate line GL1, the exit point of shift register SR [2] is connected to gate line GL2, according to this
Analogize.These shift registers are distinguished into multiple groups of shift registers of sequential.For example, shift register SR
[1], [2] SR ... SR [K] constitutes one group of shift register (first group of shift register group), shift register SR [K+1], SR [K
+ 2] ... SR [2K] constitutes next group of shift register (second group of shift register group), and so on.In every group of shift register
Shift register circuit connecting mode it is all identical as person shown in Fig. 2, and its circuit structure and mode of operation are all such as Fig. 3
To shown in Fig. 6, do not stated tired in this.It is noted that in this embodiment, at the touch-control sensing period, controlling 140 meeting of chip
Suspend the clock signal of the gate driving circuit provided, such as pause provides clock signal CK1, CK2, CK3, CK4, CK5 and CK6
And/or initial pulse STV1, STV2, but not limited thereto.
Compensation circuit PHC [1] is set to the last one shift register SR [K] and second of first group of shift register group
Between first shift register SR [K+1] of group shift register group, compensation circuit PHC [2] is set to second group of displacement and posts
The last one shift register of storage group is posted to SR [2K] and first displacement of third group shift register group (not shown)
Between storage SR [2K+1], and so on, the compensation circuit between two shift register groups is arranged in quilt of the present invention in this kind
It is defined as the first compensation circuit；However, compensation circuit of the invention is also possible to that afterbody is arranged in gate driving circuit
After shift register, signal maintenance is carried out to the afterbody shift register to provide third control signal
(holding), this kind of compensation circuits being arranged in after afterbody shift register only need provide afterbody shifting
Bit register carries out signal maintenance, without being pre-charged, therefore is defined as the second compensation circuit in the present invention.Each compensation
Circuit, such as PHC [1], PHC [2], to according to the first control signal S1 and 1 the different from clock signal CK1~CK6
Two control signal S2, cause one of two connected shift registers to be pre-charged, and two connected displacement is posted
Another of storage carries out signal maintenance (holding), to avoid the gate drive signal of two shift registers connected
A rising edge and/or a failing edge influenced by a touch-control sensing period of In-cell touch display panel.For example,
Compensation circuit PHC [1] is to cause shift register SR [K] and SR according to first control signal S1 and second control signal S2
One of [K+1] is pre-charged, and another of shift register SR [K] and SR [K+1] carry out signal maintenance, to avoid shifting
A rising edge and/or a failing edge for the gate drive signal of bit register SR [K] and SR [K+1] is touched sense period
It influences, and so on.Here, please refer to Figure 12 A, maintains and be pre-charged to define so-called signal of the invention.So-called letter
Number maintain be have due to the signal between clock signal CK3 and first control signal S1 it is overlapping, clock signal CK4 interrupt
When, first control signal S1 can maintain the 35th grade of shift register output (assuming that be first group of shift register group most
The latter shift register SR [35])；And so-called precharge is due to the letter between second control signal S2 and clock signal CK4
Number there is overlapping, therefore when clock signal CK4 is interrupted, second control signal S2 can maintain the output of the 36th grade of shift register
(assuming that being first shift register SR [36] of second group of shift register group).In addition, refer again to Fig. 8, supplement herein
Failing edge/rising edge can be promoted by design of the invention by, which illustrating, improves the demonstration example of efficiency, moves by measurement output
The fall time of the output signal of bit register SR [K] is by 10% (initial time) of failing edge to 90% (end time), example
It is such as about 2.8632us.And by the rise time of the output signal of measurement Output Shift Register SR [K+1] by rising edge
10% (initial time) to 90% (end time), such as about 2.0828us.It follows that by design of the invention
It can make the rise time and fall time not have too big difference, such as allow fall time of Output Shift Register SR [K]
It is differed within 0.2us with the fall time of the Output Shift Register of shift register SR [K-1]；In another example output displacement is allowed to post
The rise time of storage SR [K+1] differs within 0.2us with the rise time of shift register SR [K+2].
It refer again to Fig. 8, and with reference to Fig. 9, in this embodiment, the exit point of shift register SR [K] (is used
To export the endpoint of OUT (K)) and/or signal transmitting endpoint N (K) (for example, please refer to SR in Fig. 2 [3] signal transmitting endpoint N
(6)) it is connected to compensation circuit PHC [1], and is not connected directly to the forward signal input endpoint of shift register SR [K+1], is moved
Exit point (endpoint i.e. to export OUT (K+1)) and/or signal transmitting the endpoint N of bit register SR [K+1] is also connected to
Compensation circuit PHC [1], and it is not connected directly to the non-inverting signal input thereof point of shift register [K].In other words, displacement is posted
The driving signal OUT (K) of storage SR [K] will not be exported to the forward signal input endpoint of shift register SR [K+1], and be shifted
The driving signal OUT (K+1) of register SR [K+1] will not be exported to the non-inverting signal input thereof point of shift register SR [K].Together
Sample, the exit point of shift register SR [2K] is connected to compensation circuit PHC [2], and is not connected directly to shift register
Exit point and/or signal transmitting the endpoint N of the forward signal input endpoint of SR [2K+1], shift register SR [2K+1] also connect
Compensation circuit PHC [2] are connected to, and are not connected directly to the non-inverting signal input thereof point of shift register SR [2K], and so on.
In other words, the driving signal of shift register SR [2K] will not be exported to the forward signal input of shift register SR [2K+1]
Endpoint, and the driving signal of shift register SR [2K+1] will not be exported to the non-inverting signal input thereof of shift register [2K]
Point, and so on.
It refer again to Fig. 8 and Fig. 9, when gate driving circuit operates in a forward scan, compensation circuit PHC [1] is being touched
It controls in sense period, a reverse signal of one first signal P1 to shift register SR [K] is exported according to first control signal S1
Input terminal to cause shift register SR [K] to carry out signal maintenance, and exports a second signal P2 according to second control signal S2
To a forward signal input terminal of shift register SR [K+1], to cause shift register SR [K+1] to be pre-charged.Work as grid
Pole driving circuit is operated in a reverse scan, and compensation circuit PHC [1] is in the touch-control sensing period, according to second control signal
S2 exports the forward signal input terminal of second signal P2 to shift register SR [2K+1], to cause shift register SR [2K+1]
Signal maintenance is carried out, and defeated according to the reverse signal that first control signal S1 exports the first signal P1 to shift register SR [K]
Enter end, to cause shift register SR [K] to be pre-charged.The movement and compensation circuit of other compensation circuits (such as PHC [2])
PHC [1] is similar, therefore is not repeated in this.
It refer again to Fig. 9, be a schematic diagram of compensation circuit in the application.As shown, compensation circuit PHC [1] is wrapped
Include one first sub- compensation circuit SPHC1 and one second sub- compensation circuit SPHC2, and the first sub- compensation circuit SPHC1 and second
Sub- compensation circuit SPHC2 all has one first circuit C1/C1 " and a second circuit C2/C2 ".In certain embodiments, compensation electricity
The sub- compensation circuit SPHC1 of the first of road PHC [1] and the second sub- compensation circuit SPHC2 can be integrated into one or more displacements respectively and post
In storage.For example, the first sub- compensation circuit SPHC1 can be integrated into shift register SR [K], and the second sub- compensation circuit
SPHC2 can be integrated into shift register SR [K+1], and but not limited thereto.In certain embodiments, the first sub- compensation circuit
The sub- compensation circuit SPHC2 of SPHC1 and second can also be integrated into together in one in shift register [K] and [K+1].
When gate driving circuit operation is in a forward scan, in the touch-control sensing period, the first sub- compensation circuit SPHC1
The first circuit C1 the first signal P1 is exported according to the driving signal of first control signal S1 and W grades of shift registers, cause
Shift register SR [K] is set to carry out signal maintenance, and the first circuit C1 " of the second sub- compensation circuit SPHC2 is according to the second control
The driving signal of signal C2 and M grades of shift registers exports second signal P2, and shift register SR [K+1] is caused to carry out preliminary filling
Electricity.In certain embodiments, W and M is positive integer, and W is less than K, and M is less than K+1.When gate driving circuit operates in a reverse scan
When, in the touch-control sensing period, the second circuit C2 " of the second sub- compensation circuit SPHC2 is according to second control signal S2 and a Y
The driving signal of grade shift register exports second signal P2, and shift register SR [K+1] is caused to carry out signal maintenance, and first
The second circuit C2 of sub- compensation circuit SPHC1 is defeated according to first control signal S1 and the driving signal of a Z grades of shift registers
First signal P1 out causes shift register SR [K] to be pre-charged.In certain embodiments, Y and Z is positive integer, and Y is greater than K
+ 1, Z are greater than K.For example, in the embodiment in figure 11, W is equal to K-1, and M is equal to K, and Y is equal to K+2, and Z is equal to K+1, but not
It is defined in this.In the embodiment in fig. 9, the first circuit C1 and second circuit C2 of the first sub- compensation circuit SPHC1 also distinguishes root
It is reset according to driving signal OUT (K+3) and the OUT (K-3) of shift register SR [K+3] and SR [K-3].In addition, the second son
The the first circuit C1 " and second circuit C2 " of compensation circuit SPHC2 is also respectively according to shift register SR [K+4] and SR [K-4]
Driving signal OUT (K+4) and OUT (K-4) is reset.
Figure 10 is an embodiment of the first sub- compensation circuit SPHC1, it is assumed that is illustrated with the 35th grade of shift register.
As shown, the first sub- compensation circuit SPHC1 includes transistor MP1 to MP5.It is noted that transistor MP1 to MP5 is visual
It is switched for 5, and these switches can also be realized by double junction rectifiers, diode and/or IGBT.Implementation in Figure 10
Example, the sub- compensation circuit SPHC1 of the first of compensation circuit PHC [1] couple the reversed input circuit 302 in shift register SR [35]
Non-inverting signal input thereof point (i.e. the connection end point of switch 421 and 422, the IN_R corresponding to Fig. 8).Transistor MP1 has the
One end couples first control signal S1, and control terminal coupling control endpoint PP35 and second end are to export the first signal P1.It is brilliant
The driving signal OUT (34) and second that there is body pipe MP2 first end shift register SR [34] is coupled to together with control terminal
End is coupled to control endpoint PP35.There is transistor MP3 first end to be coupled to shift register SR's [36] together with control terminal
Driving signal OUT (36) and second end are coupled to control endpoint PP35.Transistor MP4 has first end together with control terminal
The driving signal OUT (38) and second end for being coupled to shift register SR [38] are coupled to determining voltage signal VGL.Transistor
The driving signal OUT (32) and second end coupling that there is MP5 first end shift register SR [32] is coupled to together with control terminal
It is connected to determining voltage signal VGL.Transistor MP1, MP2, MP4 constitute the first circuit C1, and transistor MP1, MP3, MP5 constitute second
Circuit C2.
Figure 11 is an embodiment of the second sub- compensation circuit SPHC2, it is assumed that is illustrated with the 36th grade of shift register.
As shown, the second sub- compensation circuit SPHC2 includes transistor MP6 to MP10.It is noted that transistor MP6 to MP10 can
It is considered as 5 switches, and these switches can also be realized by double junction rectifiers, diode and/or IGBT.Reality in Figure 11
Apply example, the positive input circuit in sub- compensation circuit SPHC2 coupling shift register SR [36] of the second of compensation circuit PHC [1]
301 forward signal input endpoint (i.e. the connection end point of switch 412 and 411, the IN_F corresponding to Fig. 8).Transistor MP6 has
First end couples second control signal S2, and control terminal coupling control endpoint PP36 and second end are to export second signal P2.
The driving signal OUT (35), Yi Ji that there is transistor MP7 first end shift register SR [35] is coupled to together with control terminal
Two ends are coupled to control endpoint PP36.There is transistor MP8 first end shift register SR [37] are coupled to together with control terminal
Driving signal OUT (37) and second end be coupled to control endpoint PP35.Transistor MP9 has first end and control terminal one
It is coupled to the driving signal OUT (39) of shift register SR [39] together and second end is coupled to determining voltage signal VGL.Crystal
The driving signal OUT (33) and second that there is pipe MP10 first end shift register SR [33] is coupled to together with control terminal
End is coupled to determining voltage signal VGL.Transistor MP6, MP7, MP9 the first circuit C1 " of composition, and transistor MP6, MP8, MP10 structure
At second circuit C2 ".As previously mentioned, shift registers at different levels signal transmitting endpoint N can export it is identical with exit point OUT
Driving signal, the pulse of driving signal to be sequentially transmitted between shift registers at different levels.Therefore, [1] compensation circuit PHC
The driving signal or output that endpoint N is exported can be transmitted by the signal of shift register with driving signal received by PHC [2]
The driving signal that endpoint OUT is exported.
The operation timing figure that Figure 12 A is the first, second sub- compensation circuit SPHC1 and SPHC2 in Figure 10, Figure 11.Time
When t1~t2, transistor MP2 can be connected according to driving signal OUT (34), so that control endpoint PP35 is precharged to first
High-voltage level.Similarly, the control endpoint P35 of shift register SR [35] can also be precharged to the first high-voltage level.
When time t2~t3, shift register SR [35] controls endpoint according to clock signal CK3 output drive signal OUT (35)
P35 also can be by electricity to the second high-voltage level.At this point, the transistor MP6 of the second sub- compensation circuit SPHC2 can be according to driving signal
OUT (35) and be connected so that control endpoint PP36 be precharged to the first high-voltage level.When time t3~t4, transistor MP1
It exports first control signal S1 as the first signal P1 to the non-inverting signal input thereof point IN_R of shift register SR [35], makes
Switch 421 is obtained to be switched on to carry out signal maintenance.At this point, the control endpoint PP35 of the first sub- compensation circuit SPHC1 also can be by
In first control signal S1, the second high-voltage level is risen to by the first high-voltage level.
When time t4~t7, touch-control display panel 101 enters a touch-control sensing period, therefore controls chip 104 and suspend clock
Signal CK1 to CK6.At this point, since the switch 421 in shift register SR [35] is switched on, so becoming in clock signal CK3
When low voltage level, it is high that the control endpoint P35 in shift register SR [35] only can drop to first by the second high-voltage level
Voltage level, without dropping to determining voltage signal VGL.In other words, in time t4~t5, shift register SR [35] into
The signal of row control endpoint P35 is kept.When time t5~t6, first control signal S1 becomes low level, control terminal from high level
Point PP35 can be dropped to the first high-voltage level, and the control endpoint in shift register SR [35] by the second high-voltage level
P35 can be dropped to determining voltage signal VGL (i.e. end signal maintenance) by the first high-voltage level.The 11st and 12A are referred at the same time
Figure, since the control endpoint PP36 of the second sub- compensation circuit SPHC2 has been precharged to the first high-voltage level when the time t2, therefore
In time t6~t7, transistor MP6 can be exported second control signal S2 as second signal P2 to shift register SR
[36] forward signal input endpoint, so that switch 411 is switched on to be pre-charged, i.e. the control terminal of shift register SR [36]
Point P36 can also be precharged to the first high-voltage level.
When time t7 starts, touch-control display panel 101 terminates touch-control sensing period into next display cycle, therefore controls
The output of 104 recovered clock signal CK1 to CK6 of chip.At this point, in time t7~t8 section, due to shift register SR [36]
Control endpoint P36 be precharged to the first high-voltage level, so when clock signal CK4 becomes high-voltage level, move
Bit register SR [36] can (36) output drive signal OUT immediately.Furthermore the control endpoint P36 in shift register SR [36]
Also the second high-voltage level can be risen to by the first high-voltage level.When time t8~t9, second control signal S2 becomes low electricity
Voltage level, control endpoint PP36 can drop to the first high-voltage level by the second high-voltage level.When time t9~t10, so
When clock signal CK4 becomes low voltage level, the control endpoint P36 in shift register SR [36] only can be by the second high voltage
Level drops to the first high-voltage level.In short, the first sub- compensation circuit SPHC1 can be in the time in the touch-control sensing period
For t4~t5 according to first control signal S1, exporting the first signal P1 causes shift register SR [35] to carry out signal maintenance.Second
Sub- compensation circuit SPHC2 can be in time t6~t7 according to second control signal S2, and exporting second signal P2 causes shift register
SR [36] is pre-charged.
From the foregoing, it will be observed that even if clock signal CK1, CK2, CK3, CK4, CK5 and CK6 can be suspended in the touch-control sensing period,
Compensation circuit (such as PHC [1], PHC [2]) can maintain the transmitting of driving signal between shift register.Therefore, all shift LDs
Device (such as: driving signal (the i.e. driving that signal transmitting endpoint N is exported SR [1]~SR [K], SR [K+1]~SR [2K] ...)
The driving signal that signal and exit point OUT are exported) can all have normal rising edge and failing edge, sense will not be touched
It surveys the influence in period and improperly extends, cause the decline of display picture quality.In addition, in the first sub- compensation circuit SPHC1
Transistor MP4 and MP5 reset respectively according to driving signal OUT (38) and OUT (32) so that control endpoint PP35 decline
To the level of determining voltage signal VGL.Transistor MP9 and MP10 in second sub- compensation circuit SPHC2 is respectively according to driving signal
OUT (39) and OUT (33) is reset, so that control endpoint PP36 drops to the level of determining voltage signal VGL.It should be noted
It is that the timing in Figure 12 A is movement when gate driving circuit operates in forward scan；And gate driving circuit operates in reversely
The movement when movement and forward scan that (can refer to Figure 12 B) when scanning is similar, therefore is not repeated in this.
Figure 13 is another embodiment of compensation circuit.As shown, the in the first sub- compensation circuit SPHC1A and Figure 10
One sub- compensation circuit SPHC1 is similar, and difference is that transistor MP2 and MP5 are coupled to driving signal OUT (33), transistor MP3
It is coupled to driving signal OUT (37) with MP4, the first sub- compensation circuit in the operation and Figure 10 of the first sub- compensation circuit SPHC1A
SPHC1 is similar, therefore is not repeated in this.The second sub- compensation circuit SPHC2 phase in second sub- compensation circuit SPHC2A and Figure 10
Seemingly, difference is that transistor MP7 and MP10 are coupled to driving signal OUT (34), and transistor MP8 and MP9 are coupled to driving letter
Number OUT (38), the operation of the second sub- compensation circuit SPHC2A is similar to the second sub- compensation circuit SPHC2 in Figure 10, therefore in this
It is not repeated.In this embodiment, W is equal to K-2, and M is equal to K-1, and Y is equal to K+3, and Z is equal to K+2, and but not limited thereto.
Figure 14 is another embodiment of compensation circuit.As shown, the in the first sub- compensation circuit SPHC1B and Figure 10
One sub- compensation circuit SPHC1 is similar, and difference is that the first end of transistor MP2 is coupled to a high-voltage level VGH rather than drives
Dynamic signal OUT (34), and the first end of transistor MP3 is coupled to high-voltage level VGH rather than driving signal OUT (36).The
The operation of one sub- compensation circuit SPHC1B is similar to the first sub- compensation circuit SPHC1 in Figure 10, therefore is not repeated in this.Second
Sub- compensation circuit SPHC2A is similar to the second sub- compensation circuit SPHC2 in Figure 10, and difference is the first end of transistor MP7
It is coupled to a high-voltage level VGH rather than driving signal OUT (35), and the first end of transistor MP8 is coupled to high voltage electricity
Flat VGH rather than driving signal OUT (37).The operation of second sub- compensation circuit SPHC2A and the second sub- compensation circuit in Figure 12 A
SPHC2 is similar, therefore is not repeated herein.
Figure 15 is wiring schematic diagram of the invention.As shown, shift register SR [K] and SR [K+1] is set to
In one rim area of touch-control display panel 101, sequentially to export gate drive signal.Compensation circuit PHC is set to rim area
Between middle shift register SR [K] and SR [K+1], with the gate drive signal to avoid shift register SR [K] and SR [K+1]
A rising edge and/or a failing edge be touched the influence of sense period.The sub- compensation circuit of the first of compensation circuit PHC
SPHC1 is integrated into shift register SR [K], and the second of compensation circuit PHC the sub- compensation circuit SPHC2 is integrated into shift LD
In device SR [K+1], in wiring, since the first sub- compensation circuit SPHC1 and the second sub- compensation circuit SPHC2 element are typically less than
Shift register SR, and the first sub- sub- compensation circuit SPHC2 element of compensation circuit SPHC1 and second is not required to be provided to grid signal
Line, therefore the area (such as W/L ratio) of its element can be smaller than shift register SR, therefore can be such as the mode of Figure 15, using mutual
Design adjustment overall routing area is mended, so as to reduce layout area, but not limited thereto.It is noted that the shifting in Figure 15
The operation of bit register and compensation circuit as previously mentioned, therefore be not repeated herein.
Though the present invention is disclosed as above with preferred embodiment, the range that however, it is not to limit the invention, art technology
Personnel without departing from the spirit and scope of the present invention, when can do a little change and retouching, therefore protection scope of the present invention
Subject to view the appended claims confining spectrum.
Claims (18)
1. a kind of image display system, comprising:
Touch-control display panel, multiple pixels comprising picture element matrix；And
It is aobvious to be located at the touch-control with driving to generate multiple gate drive signals according to one group of clock signal for gate driving circuit
Show multiple pixels of panel, which includes:
Multiple shift registers, sequentially to export the gate drive signal, the shift register is distinguished into sequentially number
Multiple shift register groups of arrangement, wherein in two adjacent N group shift register groups and N+1 group shift register group
In, the gate drive signal and the N+1 group shift register of the afterbody shift register of the N group shift register group
The gate drive signal of the first order shift register of group is continuous；And
At least one first compensation circuit, first compensation circuit are arranged between the two adjacent shift registers group, first benefit
Repay the afterbody shift register and the N+1 group shift register group of circuit connection to the N group shift register group
The first order shift register, wherein first compensation circuit provide the first signal to the N group shift register group this
Afterbody shift register carry out signal maintenance (holding), the compensation circuit and provide second signal give the N+1 group shifting
The first order shift register of bit register group is pre-charged, and wherein N is the positive integer greater than zero；
Wherein the afterbody shift register in the N group shift register is K grades of shiftings in the shift register
Bit register, and the first order shift register in the N+1 group shift register is the K+1 in the shift register
Grade shift register, but the driving signal of the K grades of shift registers does not export to the K+1 grades of shift registers, and the K
The driving signal of+1 grade of shift register does not export to the K grades of shift registers, and wherein K is the positive integer greater than zero；
Wherein when the gate driving circuit operates in forward scan, first compensation circuit in the touch-control sensing period, according to
First control signal exports the non-inverting signal input thereof of first signal to the K grades of shift registers, to cause this K grades shiftings
Bit register carries out signal maintenance, and exports the second signal to the K+1 grades of shift registers according to second control signal
Forward signal input terminal, to cause the K+1 grades of shift registers to be pre-charged.
2. image display system as described in claim 1, wherein this when the gate driving circuit operates in reverse scan
One compensation circuit exports the second signal to this K+1 grades displacements in the touch-control sensing period, according to the second control signal
Forward signal input terminal of register, to cause the K+1 grades of shift registers to carry out signal maintenance, and according to first control
Signal processed exports the non-inverting signal input thereof of first signal to the K grades of shift registers, to cause this K grades displacements to post
Storage is pre-charged.
3. image display system as described in claim 1, wherein first compensation circuit include the first sub- compensation circuit and
Second sub- compensation circuit, the first sub- compensation circuit and the second sub- compensation circuit all have the first circuit and second circuit, when
When the gate driving circuit operates in forward scan, first circuit of the first sub- compensation circuit is in the touch-control sensing period
In, according to the driving signal of the first control signal and W grades of shift registers, the K grades of shift registers is caused to carry out
Signal maintains, and first circuit of the second sub- compensation circuit is in the touch-control sensing period, according to the second control signal
With the driving signal of M grades of shift registers, the K+1 grades of shift registers are caused to be pre-charged, wherein W and M is positive
Integer, M are less than K+1, and W is less than K.
4. image display system as claimed in claim 3, wherein this when the gate driving circuit operates in reverse scan
The second circuit of two sub- compensation circuits is in the touch-control sensing period, according to the second control signal and Y grades of shift LDs
The driving signal of device causes K+1 grades of shift registers to carry out signal maintenances, and the first sub- compensation circuit this second
Circuit, according to the driving signal of the first control signal and Z grades of shift registers, causes this in the touch-control sensing period
K grades of shift registers are pre-charged, and wherein Y and Z is positive integer, and Y is greater than K+1, and Z is greater than K.
5. image display system as claimed in claim 4, wherein the first sub- compensation circuit includes:
First switch couples the first clock with a first end and second end couples the reversed letter of the K grades of shift registers
Number input terminal；
Second switch is coupled between the control terminal of the first switch and the driving signal of W grades of shift registers；
Third switch, is coupled between the control terminal of the first switch and the driving signal of the Z grades of shift registers；
4th switch, is coupled between the control terminal of the first switch and determining voltage signal；And
5th switch, is coupled between the control terminal of the first switch and the determining voltage signal, wherein the 4th switchs and is somebody's turn to do
The control terminal of 5th switch couples corresponding driving signal.
6. image display system as claimed in claim 5, wherein the first sub- compensation circuit includes:
6th switch couples the positive letter of the K+1 grades of shift registers with first end coupling second clock and second end
Number input terminal；
7th switch, is coupled between the control terminal of the first switch and the driving signal of the M grades of shift registers；
8th switch, is coupled between the control terminal of the first switch and the driving signal of the Y grades of shift registers；
9th switch, is coupled between the control terminal of the first switch and the determining voltage signal；And
Tenth switch, is coupled between the control terminal of the first switch and the determining voltage signal, wherein the 9th switchs and is somebody's turn to do
The control terminal of tenth switch couples corresponding driving signal.
7. image display system as described in claim 1, wherein the touch-control display panel includes:
The gate driving circuit, to generate the gate drive signal according to this group of clock signal；
Data-signal transmitting circuit provides data to the pixel of the picture element matrix to generate multiple data-signals；With
And
Chip is controlled, this group of clock signal is provided, to control the movement of the shift register, wherein in the touch-control display surface
When the touch-control sensing period of plate, which can suspend this group of clock signal.
8. image display system as described in claim 1 further includes the second compensation circuit, is connected in the gate driving circuit
After afterbody shift register, signal maintenance is carried out to the afterbody shift register to provide third control signal
(holding)。
9. a kind of gate driving circuit is located at touching to generate multiple gate drive signals according to one group of clock signal with driving
Multiple pixels of the picture element matrix on display panel are controlled, which includes:
Multiple shift registers, sequentially to export the gate drive signal, the shift register is distinguished into sequentially number
Multiple groups of shift register groups of arrangement, wherein two adjacent N group shift register groups and N+1 group shift register group
In, the gate drive signal and the N+1 group shift register of the afterbody shift register of the N group shift register group
The gate drive signal of the first order shift register of group is continuous；And
At least one first compensation circuit, first compensation circuit are arranged between the two adjacent shift registers group, first benefit
Repay the afterbody shift register and the N+1 group shift register group of circuit connection to the N group shift register group
The first order shift register, wherein first compensation circuit provide one first signal to the N group shift register group
Afterbody shift register progress signal maintenance (holding), the compensation circuit and one second signal of offer give the N+1
The first order shift register of group shift register group is pre-charged；
Wherein the afterbody shift register in the N group shift register is K grades of shiftings in the shift register
Bit register, and the first order shift register in the N+1 group shift register is the K+1 in the shift register
Grade shift register, but the driving signal of the K grades of shift registers does not export to the K+1 grades of shift registers, and the K
The driving signal of+1 grade of shift register does not export to the K grades of shift registers, and wherein K is the positive integer greater than zero；
Wherein when the gate driving circuit operates in forward scan, first compensation circuit in the touch-control sensing period, according to
First control signal exports the non-inverting signal input thereof of first signal to the K grades of shift registers, to cause this K grades shiftings
Bit register carries out signal maintenance, and exports the second signal to the K+1 grades of shift registers according to second control signal
Forward signal input terminal, to cause the K+1 grades of shift registers to be pre-charged.
10. gate driving circuit as claimed in claim 9, wherein when the gate driving circuit operates in reverse scan, it should
First compensation circuit exports the second signal to this K+1 grades shiftings in the touch-control sensing period, according to the second control signal
The forward signal input terminal of bit register, to cause K+1 grades of shift registers to carry out signal maintenances, and according to this first
Control signal exports the non-inverting signal input thereof of first signal to the K grades of shift registers, to cause this K grades displacements
Register is pre-charged.
11. gate driving circuit as claimed in claim 9, wherein first compensation circuit include the first sub- compensation circuit and
Second sub- compensation circuit, the first sub- compensation circuit and the second sub- compensation circuit all have the first circuit and second circuit, when
When the gate driving circuit operates in forward scan, first circuit of the first sub- compensation circuit is in the touch-control sensing period
In, according to the driving signal of the first control signal and W grades of shift registers, the K grades of shift registers is caused to carry out
Signal maintains, and first circuit of the second sub- compensation circuit is in the touch-control sensing period, according to the second control signal
With the driving signal of M grades of shift registers, the K+1 grades of shift registers are caused to be pre-charged, wherein W and X is positive
Integer, M are less than K+1, and W is less than K.
12. gate driving circuit as claimed in claim 11, wherein when the gate driving circuit operates in reverse scan, it should
The second circuit of second sub- compensation circuit is posted in the touch-control sensing period according to the second control signal and Y grades of displacements
The driving signal of storage causes K+1 grades of shift registers to carry out signal maintenances, and the first sub- compensation circuit this
Two circuits, according to the driving signal of the first control signal and Z grades of shift registers, cause in the touch-control sensing period
The K grades of shift registers are pre-charged, and wherein Y and Z is positive integer, and Y is greater than K+1, and Z is greater than K.
13. gate driving circuit as claimed in claim 12, wherein the first sub- compensation circuit is integrated into this K grades displacements and posts
In storage, and the second sub- compensation circuit is integrated into the K+1 grades of shift registers.
14. gate driving circuit as claimed in claim 12, wherein the first sub- compensation circuit includes:
First switch couples the first clock with first end and second end couples the reverse signal of the K grades of shift registers
Input terminal；
Second switch is coupled between the control terminal of the first switch and the driving signal of W grades of shift registers；
Third switch, is coupled between the control terminal of the first switch and the driving signal of the Z grades of shift registers；
4th switch, is coupled between the control terminal of the first switch and determining voltage signal；And
5th switch, is coupled between the control terminal of the first switch and the determining voltage signal, wherein the 4th switchs and is somebody's turn to do
The control terminal of 5th switch couples corresponding driving signal.
15. gate driving circuit as claimed in claim 14, wherein the first sub- compensation circuit includes:
6th switch couples the positive letter of the K+1 grades of shift registers with first end coupling second clock and second end
Number input terminal；
7th switch, is coupled between the control terminal of the first switch and the driving signal of the M grades of shift registers；
8th switch, is coupled between the control terminal of the first switch and the driving signal of the Y grades of shift registers；
One the 9th switch, is coupled between the control terminal of the first switch and the determining voltage signal；And
1 the tenth switch, be coupled between the control terminal of the first switch and the determining voltage signal, wherein the 9th switch with
The control terminal of tenth switch couples corresponding driving signal.
16. gate driving circuit as claimed in claim 9, wherein at the touch-control sensing period of the touch-control display panel,
The control chip of the touch-control display panel can suspend this group of clock signal.
17. gate driving circuit as claimed in claim 9 is connected to the gate driving wherein including also the second compensation circuit
In circuit after afterbody shift register, letter is carried out to the afterbody shift register to provide third control signal
Number maintain (holding).
18. a kind of gate driving circuit is located on touch-control display panel, which includes:
K grades of shift registers, are set in the rim area of the touch-control display panel, to export K grades of gate drive signals；
K+1 grades of shift registers are set in the rim area, to export K+1 grades of gate drive signals；And
First compensation circuit is set in the rim area between the K grades of shift registers and K+1 grades of shift registers, is used
To avoid the K grades of gate drive signals of the K grades of shift registers and this K+1 grades of the K+1 grades of shift registers
One rising edge and/or failing edge of gate drive signal are influenced by the one touch-control sensing period of touch-control display panel,
Middle K is the positive integer greater than zero, which includes the first sub- compensation circuit and the second sub- compensation circuit, this first
Sub- compensation circuit is integrated into the K grades of shift registers, and the second sub- compensation circuit is integrated into this K+1 grades displacements and posts
In storage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510357109.5A CN106328074B (en) | 2015-06-25 | 2015-06-25 | Image display system and gate driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510357109.5A CN106328074B (en) | 2015-06-25 | 2015-06-25 | Image display system and gate driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106328074A CN106328074A (en) | 2017-01-11 |
| CN106328074B true CN106328074B (en) | 2019-06-25 |
Family
ID=57728740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510357109.5A Active CN106328074B (en) | 2015-06-25 | 2015-06-25 | Image display system and gate driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106328074B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10403382B2 (en) | 2016-08-05 | 2019-09-03 | Hannstar Display Corporation | Gate driving circuit and display apparatus |
| CN107689213B (en) * | 2016-08-05 | 2020-07-07 | 瀚宇彩晶股份有限公司 | Gate drive circuit and display device |
| CN106875918B (en) * | 2017-04-28 | 2019-11-26 | 厦门天马微电子有限公司 | Pulse generation unit, array substrate, display device, driving circuit and method |
| CN108206002B (en) * | 2018-01-03 | 2022-01-11 | 京东方科技集团股份有限公司 | Grid driving circuit compensation device and method, grid driving circuit and display device |
| CN108022548B (en) * | 2018-02-01 | 2021-04-23 | 京东方科技集团股份有限公司 | Scanning direction control circuit, grid drive circuit and display device |
| CN111899697A (en) * | 2019-05-06 | 2020-11-06 | 瀚宇彩晶股份有限公司 | Grid driving circuit and driving method of touch display panel |
| CN112530332A (en) * | 2019-09-18 | 2021-03-19 | 群创光电股份有限公司 | Electronic device |
| CN115691437A (en) * | 2021-07-27 | 2023-02-03 | 北京京东方显示技术有限公司 | Display panel driving method, display panel and display device |
| CN114283726B (en) * | 2021-12-29 | 2023-09-05 | Tcl华星光电技术有限公司 | Driving circuit |
| WO2023159557A1 (en) * | 2022-02-28 | 2023-08-31 | 京东方科技集团股份有限公司 | Driving method for display panel, driving circuit, and display device |
| CN115719585A (en) * | 2022-11-15 | 2023-02-28 | 武汉华星光电技术有限公司 | Display panel and display device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5758825B2 (en) * | 2012-03-15 | 2015-08-05 | 株式会社ジャパンディスプレイ | Display device, display method, and electronic apparatus |
| CN104517556A (en) * | 2013-09-29 | 2015-04-15 | 友达光电股份有限公司 | Shift register circuit and gate driving circuit comprising same |
| CN203456069U (en) * | 2013-09-29 | 2014-02-26 | 京东方科技集团股份有限公司 | Grid drive circuit and display device |
| CN103943055B (en) * | 2014-03-27 | 2016-05-11 | 京东方科技集团股份有限公司 | A kind of gate driver circuit and driving method thereof, display unit |
| CN203746393U (en) * | 2014-03-27 | 2014-07-30 | 京东方科技集团股份有限公司 | Gate drive circuit and display device |
| JP6188647B2 (en) * | 2014-07-15 | 2017-08-30 | シナプティクス・ジャパン合同会社 | Semiconductor device |
| CN104485080B (en) * | 2014-12-31 | 2017-02-22 | 深圳市华星光电技术有限公司 | GOA (Gate Driver On Array) circuit for liquid crystal display device |
-
2015
- 2015-06-25 CN CN201510357109.5A patent/CN106328074B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN106328074A (en) | 2017-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106328074B (en) | Image display system and gate driving circuit | |
| CN110007792B (en) | Display device | |
| EP3611720B1 (en) | Shift register unit, gate driving circuit, and driving method | |
| JP6804127B2 (en) | Image display system and gate drive circuit | |
| TWI567608B (en) | Display device, method and driving device for driving the same | |
| US9218779B2 (en) | Liquid crystal display device with improved integrated touch panel and driving method thereof | |
| KR102207142B1 (en) | Gate driver integrated on display panel | |
| CN107015683B (en) | Display device including touch screen and driving circuit for driving the display device | |
| WO2019161669A1 (en) | Gate drive circuit, touch display device, and driving method | |
| US10429993B2 (en) | Touch display driving integrated circuit and operation method thereof | |
| CN103489425B (en) | Level shifting circuit, array base palte and display device | |
| CN108021275B (en) | Gate driver and display device having in-cell touch sensor using the same | |
| US10120482B2 (en) | Driving method for in-cell type touch display panel | |
| CN105957470B (en) | Shift register cell, gate driving circuit and its driving method, display device | |
| CN104978943A (en) | Shift register, display panel driving method and related device | |
| KR20130107528A (en) | A gate driving circuit and a display apparatus using the same | |
| CN104282285A (en) | Shifting register circuit and drive method, gate drive circuit and display device thereof | |
| US10699616B2 (en) | Scan driver | |
| TW201701255A (en) | Image display system and gate driving circuit | |
| CN106328075B (en) | Image display system and gate driving circuit | |
| CN103310734A (en) | Active matrix/organic light emitting diode (AMOLED) pixel circuit, driving method thereof and display device | |
| WO2019134450A1 (en) | Shift register unit, gate drive circuit, display device and drive method | |
| CN105575329A (en) | Shift register and driving method thereof, driving circuit, array substrate and display device | |
| US10127874B2 (en) | Scan driver and display device using the same | |
| US9990075B2 (en) | Display device and method of driving the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |