CN104517556A - Shift register circuit and gate driving circuit comprising same - Google Patents
Shift register circuit and gate driving circuit comprising same Download PDFInfo
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- CN104517556A CN104517556A CN201310454905.1A CN201310454905A CN104517556A CN 104517556 A CN104517556 A CN 104517556A CN 201310454905 A CN201310454905 A CN 201310454905A CN 104517556 A CN104517556 A CN 104517556A
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Abstract
The invention provides a shift register circuit and a gate driving circuit comprising the same. The shift register circuit includes a plurality of shift registers, a first switching circuit and a second switching circuit; the plurality of shift registers are electrically coupled in cascade; each shift register is provided with a signal input end and a signal output end; the first switching circuit transfer positively transmits scanning signals outputted by the shift registers at each level by means of the control of triggering signals; the second switching circuit reversely transmits the scanning signals outputted by the shift registers at each level by means of the control of the triggering signals; when the triggering signals are high potential, the first switching circuit is enabled; and when the triggering signals are low potential, the second switching circuit is enabled. According to the shift register circuit and the gate driving circuit comprising the same of the invention, the shift register circuit is redesigned, so that the use of control signals can be effectively reduced, and therefore, the gate driving circuit of the invention can realize a bidirectional scanning switching function with only one control signal required.
Description
Technical field
The present invention relates to display driver technical field, especially a kind of utilizes a control signal namely can realize the shift-register circuit of bilateral scanning handoff functionality and comprise its gate driver circuit.
Background technology
Along with the update of display device, display driver technology is as technology indispensable in a display technique, also develop with quickish speed, in general, for liquid crystal indicator, it includes display unit, gate driver circuit and data drive circuit, gate driver circuit is used for providing sweep signal to open the driving transistors in pixel cell to the pixel cell in display unit, and then the data voltage making each pixel cell can accept data drive circuit to provide, thus namely the liquid crystal in each pixel cell can deflect under the electric field force effect of data voltage correspondence formation, thus, display unit just corresponding can demonstrate the image frame of different GTG.
Wherein, in gate driver circuit, a topmost circuit module is shift-register circuit, as shown in Figure 1, for a kind of in prior art partial circuit Organization Chart of shift-register circuit, general shift-register circuit can comprise a plurality of shift register, each shift register correspondence exports one scan signal, as shown in Figure 1 be (n-1)th grade of shift register SR (n-1), the circuit framework be electrically connected between n-th grade of shift register SR (n) and (n+1)th grade of shift register SR (n+1), furtherly, between every two shift registers, all switch element is set, such as between (n-1)th grade of shift register SR (n-1) and n-th grade of shift register SR (n), be provided with transistor Ta, Tb ', transistor Tb is then provided with between n-th grade of shift register SR (n) and (n+1)th grade of shift register SR (n+1), Ta ', and the break-make of transistor Ta and Tb is controlled by control signal A, and the break-make of transistor Ta ' and Tb ' is controlled by control signal B, in simple terms, when control signal A is in noble potential and control signal B is in electronegative potential, this shift-register circuit can carry out the forward transmission of sweep signal step by step, namely every one-level shift register can export sweep signal by forward step by step, otherwise, when control signal B is in noble potential and control signal A is in electronegative potential, this shift-register circuit then carries out the reverse transmission of sweep signal step by step.
Therefore, by the setting of switch element, shift-register circuit can realize the switching of bilateral scanning, and but, it needs to utilize two control signals could meet design, so the use that how can reduce control signal is further a problem being worth research.
Summary of the invention
In order to further reduce the use of control signal, the present invention proposes a kind of and utilizing a control signal namely can realize the shift-register circuit of bilateral scanning handoff functionality and comprise its gate driver circuit.
The invention provides a kind of shift-register circuit, this shift-register circuit comprises:
A plurality of shift register, this plurality of shift register electric property coupling in cascaded fashion, each shift register has signal input part and signal output part;
First on-off circuit, there is the first input switch unit and the first output switching element, this first input switch unit and this signal input part are electrically connected, this first output switching element and this signal output part are electrically connected, wherein, this first input switch unit, in order to respond a trigger pip, extremely works as level shift register to transmit this upper level sweep signal, this first output switching element, in order to respond this trigger pip, deserves level sweep signal to next stage shift register to transmit; And
Second switch circuit, there is the second input switch unit and the second output switching element, this second input switch unit and this signal input part are electrically connected, this second output switching element and this signal output part are electrically connected, wherein, this second input switch unit, in order to respond this trigger pip, extremely deserves level shift register to transmit this next stage sweep signal, this second output switching element, in order to respond this trigger pip, deserves level sweep signal to upper level shift register to transmit;
Wherein, when this trigger pip is noble potential, this shift-register circuit carries out the forward transmission of sweep signal step by step; When this trigger pip is electronegative potential, this shift-register circuit carries out the reverse transmission of sweep signal step by step.
Alternatively, this first switch input unit comprises the first transistor, this the first transistor has control end, first end and the second end, the control end of this first transistor receives this trigger pip, the first end of this first transistor is electrically connected the signal output part of this upper level shift register, and the second end of this first transistor is electrically connected the signal input part deserving level shift register.
Alternatively, this second output switching element:
Transistor seconds, this transistor seconds has control end, first end and the second end, the control end of this transistor seconds is electrically connected to first node, the first end of this transistor seconds is electrically connected the signal input part of this upper level shift register, and the second end of this transistor seconds is electrically connected the signal output part deserving level shift register;
Third transistor, this third transistor has control end, first end and the second end, the control end of this third transistor receives this trigger pip, and the first end of this third transistor is electrically connected to this first node, and the second termination of this third transistor receives the first voltage; And
4th transistor, 4th transistor has control end, first end and the second end, the control end of the 4th transistor is electrically connected the second end of the 4th transistor, and the first end of the 4th transistor receives the second voltage, and the second end of the 4th transistor is electrically connected to this first node.
Alternatively, this second voltage is greater than this first voltage.
Alternatively, the ratio of this third transistor channel width and channel length is greater than the ratio of the 4th transistor channel width and channel length.
Alternatively, in described shift-register circuit, this each shift register comprises:
Control circuit, for responding this upper level sweep signal, to export when level control signal;
Output circuit, this output circuit and this control circuit are electrically connected to Section Point, deserve level control signal for response, deserve level sweep signal to export;
Pull-down circuit, this pull-down circuit and this control circuit are electrically connected to this Section Point and this pull-down circuit and this output circuit are electrically connected to the signal output part deserving level shift register, for responding the first pulse signal and the second pulse signal, be pulled down to preset potential to make the current potential of this Section Point with the current potential of the signal output part deserving level shift register; And
Reset circuit, this reset circuit and this control circuit are electrically connected to this Section Point and this reset circuit and this output circuit are electrically connected to the signal output part deserving level shift register, for responding this next stage sweep signal and this first voltage, with the current potential of this Section Point that resets and the current potential of signal output part deserving level shift register.
Alternatively, this control circuit comprises: the 5th transistor, 5th transistor has control end, first end and the second end, the control end of the 5th transistor and first end are all electrically connected to the signal input part deserving level shift register, and the second end of the 5th transistor is electrically connected to this Section Point.
Alternatively, this output circuit comprises: the 6th transistor, 6th transistor has control end, first end and the second end, the control end of the 6th transistor is electrically connected to this Section Point, the first end of the 6th transistor receives this first pulse signal or this second pulse signal, and the second end of the 6th transistor is electrically connected to the signal output part deserving level shift register.
Alternatively, this reset circuit comprises: the 7th transistor, 7th transistor has control end, first end and the second end, the control end of the 7th transistor is electrically connected to the 3rd node, the first end of the 7th transistor is electrically connected to the 3rd node, and the second termination of the 7th transistor receives this first voltage;
8th transistor, 8th transistor has control end, first end and the second end, the control end of the 8th transistor is electrically connected to the 3rd node, the first end of the 8th transistor is electrically connected to the signal output part deserving level shift register, and the second termination of the 8th transistor receives this first voltage;
Wherein, the current potential of the 3rd node corresponds to the current potential of this next stage sweep signal.
Present invention also offers a kind of gate driver circuit, this gate driver circuit comprises:
Shift-register circuit described above, this plurality of shift register is in order to export a plurality of sweep signal;
Trigger signal source, in order to provide this trigger pip; And
Start trigger signal source, this start trigger signal source in order to provide a start trigger signal to the first order shift register in this shift-register circuit or afterbody shift register, to start this first order shift register or this afterbody shift register.
Compared with prior art, the present invention is by the redesign to shift-register circuit, effectively decrease the use of control signal, gate driver circuit of the present invention is made only to need a control signal namely can realize bilateral scanning handoff functionality, in other words, the present invention reduce further the control complexity in display driver circuit on the basis of existing technology, and the shift-register circuit impelling the present invention to propose and the gate driver circuit comprising it have better application prospect.
Accompanying drawing explanation
Fig. 1 is the partial circuit Organization Chart of a kind of shift-register circuit in prior art;
Fig. 2 is the circuit framework figure of gate driver circuit in one embodiment of the invention;
Fig. 3 is the circuit framework figure of n-th grade of shift register in one embodiment of the invention shift-register circuit;
Fig. 4 is the circuit framework figure of the first on-off circuit and second switch circuit when this n-th grade of shift register is electrically connected mutually with (n-1)th grade of shift register, (n+1)th grade of shift register in Fig. 3;
Signal waveform sequential chart when Fig. 5 A, 5B are gate driver circuit execution forward scan and reverse scanning in one embodiment of the invention.
Embodiment
For making there is further understanding to object of the present invention, structure, feature and function thereof, embodiment is hereby coordinated to be described in detail as follows.
Please refer to Fig. 2, is the circuit framework figure of gate driver circuit in one embodiment of the invention.In the present embodiment, gate driver circuit 10, it mainly comprises and couples by a plurality of shift register SR (1) ~ SR (n+m) shift-register circuit 11 formed in cascaded fashion, trigger signal source, start trigger signal source, first voltage source and the second voltage source, wherein, trigger signal source is in order to provide trigger pip A to shift-register circuit 11, start trigger signal source in order to provide a start trigger signal ST to the 1st in this shift-register circuit grade shift register SR (1) or afterbody shift register, to start first order shift register SR (1) or afterbody shift register, first voltage source is in order to provide the first voltage VSS to shift-register circuit 11, and the second voltage source is then in order to provide the second voltage VGH to shift-register circuit 11, wherein, second voltage VGH is greater than the first voltage VSS, and shift-register circuit 11 is in order to export a plurality of sweep signal G (1) ~ G (n+m), wherein, n, m is natural number, in addition, more precisely, in the present embodiment, switch module 12 is all electrically connected between every two shift registers in this plurality of shift register SR (1) ~ SR (n+m), export with the positive reverse scanning signal realizing shift-register circuit 11.It should be noted that, the gate driver circuit that the present invention proposes more can be applied in the various display device such as liquid crystal indicator, OLED display, to provide the sweep signal needed for it, relevant design is common in the design of display device in prior art, therefore does not repeat at this.
As shown in Figure 2, shift-register circuit 11 in the present invention comprises a plurality of shift register SR (1) ~ SR (n+m), each shift register is in order to produce a sweep signal, therefore a plurality of shift register SR (1) ~ SR (n+m) namely correspondingly can export a plurality of sweep signal G (1) ~ G (n+m), and further, as described above, a switch module 12 is electrically connected between any two shift registers, say accurately, please with further reference to Fig. 3, it is the circuit framework figure of n-th grade of shift register in one embodiment of the invention shift-register circuit, in the present embodiment, the circuit framework of each shift register SR (1) ~ SR (n+m) is identical, therefore at this for n-th grade of shift register SR (n), as shown in Figure 3, this n-th grade of shift register SR (n) has signal input part Vin (n) and signal output part Vout (n), in addition, what be electrically connected with this n-th grade of shift register SR (n) also includes:
First on-off circuit, there is the first input switch unit SW1 and the first output switching element SW1 ', and signal input part Vin (n) of the first input switch unit SW1 and shift register SR (n) is electrically connected, first output switching element SW1 ' is then electrically connected with signal output part Vout (n) of shift register SR (n), in simple terms, first input switch unit SW is in order to respond trigger pip X, to transmit (n-1)th grade of sweep signal G (n-1) to n-th grade of shift register SR (n), first output switching element SW1 ' is then in order to respond trigger pip X, to transmit n-th grade of sweep signal G (n) to (n+1)th grade of shift register SR (n+1), using the enabling signal as (n+1)th grade of shift register SR (n+1),
Second switch circuit, there is the second input switch unit SW2 and the second output switching element SW2 ', signal input part Vin (n) of the second input switch unit SW2 and shift register SR (n) is electrically connected, second output switching element SW2 ' is electrically connected with signal output part Vout (n) of shift register SR (n), contrary with the first on-off circuit, second input switch unit SW2 is in order to respond trigger pip X, to transmit (n+1)th grade of sweep signal G (n+1) to n-th grade of shift register SR (n), second output switching element SW2 ' is then in order to respond trigger pip X, to transmit n-th grade of sweep signal G (n) to (n-1)th grade of shift register SR (n-1), using the enabling signal as this (n-1)th grade of shift register SR (n-1).
Wherein, in the present embodiment, the signal waveform of trigger pip X as shown in Fig. 5 A, 5B, can be respectively signal waveform sequential chart when gate driver circuit execution forward scan and reverse scanning in one embodiment of the invention.Therefore trigger pip X can be high potential signal or low-potential signal, and when trigger pip X is noble potential, by the forward transmission effect of the first input switch unit SW1 and the first output switching element SW1 ' to sweep signal, (n-1)th grade of shift register SR (n-1), n-th grade of shift register SR (n) and (n+1)th grade of shift register SR (n+1) can realize the output step by step of (n-1)th grade of sweep signal G (n-1), n-th grade of sweep signal G (n), (n+1)th grade of sweep signal G (n+1) forward; Otherwise, when trigger pip X is electronegative potential, by the reverse transmission effect of the second input switch unit SW2 and the second output switching element SW2 ' to sweep signal, (n+1)th grade of shift register SR (n+1), n-th grade of shift register SR (n) and (n-1)th grade of shift register SR (n-1) then can realize (n+1)th grade of sweep signal G (n+1), n-th grade of sweep signal G (n), output step by step that (n-1)th grade of sweep signal G (n-1) is reverse.
In addition, also it should be noted that, the mentioned above switch module 12 be arranged between any two shift registers generally comprises the first input switch unit SW1 and the second output switching element SW2 ', or the second input switch unit SW2 and the first output switching element SW1 ', it should be noted that, in order to draw conveniently in Fig. 1, first input switch unit and the first output switching element all represent with SW1, and the second input switch unit and the second output switching element then all represent with SW2.
Just the principle of work of shift-register circuit 11 of the present invention is described in further detail below, also please referring again to Fig. 3, first the circuit structure of n-th grade of shift register SR (n), in an embodiment, this n-th grade of shift register SR (n) comprising: control circuit 100, output circuit 200, reset circuit 300 and pull-down circuit 400.
Based on the setting of the first on-off circuit and second switch circuit, control circuit 100 can be used for (n-1)th grade of sweep signal G (n-1) that response (n-1)th grade of shift register SR (n-1) exports, to export n-th grade of control signal Q (n).Specifically, as shown in Figure 4, in the present embodiment, control circuit 100 comprises transistor T11, wherein, transistor T11 has control end, first end and the second end, the control end of this transistor T11 is electrically connected to signal input part Vin (n) of shift register SR (n), to receive (n-1)th grade of sweep signal G (n-1) that (n-1)th grade of shift register SR (n-1) exports, thus control transistor T11 conducting to complete the action of startup n-th grade of shift register SR (n); The first end of this transistor T11 is electrically connected signal input part Vin (n) of shift register SR (n) equally, to receive the voltage that (n-1)th grade of sweep signal G (n-1) pours into; Second end of this transistor T11 is then electrically connected to node Q, and to export n-th grade of control signal Q (n), therefore n-th grade of control signal Q (n) is corresponding to the current potential of this node Q.
In the present embodiment, as shown in Figure 2, gate driver circuit 10 also comprises the first pulse signal source and the second pulse signal source, first pulse signal source and the second pulse signal source are in order to provide the first pulse signal CK and the second pulse signal XCK, output circuit 200 and control circuit 100 are all electrically connected to node Q, for responding n-th grade of control signal Q (n), to export n-th grade of sweep signal G (n).Specifically, output circuit 200 comprises transistor T21, wherein, transistor T21 has control end, first end and the second end equally, and the control end of this transistor T21 is electrically connected to node Q, to accept n-th grade of sweep signal G (n) that control circuit 100 exports, and then respond this n-th grade of control signal Q (n) with break-make third transistor T21, the first end of this transistor T21 receives the first pulse signal CK or the second pulse signal XCK, it should be noted that, in the present embodiment, the first end of this transistor T21 receives the first pulse signal CK, but not as limit, the first pulse signal CK in the present embodiment and the second pulse signal XCK, be periodic clock signal, and both are anti-phase each other, as shown in Fig. 5 A or 5B, answer actual demand and determine, only need according to the demand of n-th grade of sweep signal G (n) (corresponding output time point needs logic high voltage or logic low-voltage), and then select the first pulse signal CK or the second pulse signal XCK to meet this demand at corresponding output time point, second end of transistor T21 is then electrically connected to signal output part Vout (n) of shift register SR (n), to export n-th grade of sweep signal G (n).
Reset circuit 300 and control circuit 100 are electrically connected to node Q, and be electrically connected to signal output part Vout (n) of shift register SR (n) with output circuit 200, for responding the (n+1)th grade of sweep signal G (n+1) and the first voltage VSS that (n+1)th grade of shift register SR (n+1) export, with the current potential of signal output part Vout (n) of the current potential of reset node Q and shift register SR (n), in the present embodiment, the first voltage VSS can be ground voltage.Concrete, reset circuit 300 comprises transistor T31 and transistor T32, wherein, transistor T31 and transistor T32 all has control end, first end and the second end, and the control end of transistor T31 and transistor T32 is all electrically connected to node P, to respond (n+1)th grade of sweep signal G (n+1), and then break-make transistor T31 and transistor T32; Second end of transistor T31 and transistor T32 then all receives the first voltage VSS; Unlike, the first end of transistor T31 is electrically connected to node Q, and the first end of transistor T32 is then electrically connected to signal output part Vout (n) of shift register SR (n).Therefore by the conducting of transistor T31 and transistor T32, the current potential of the current potential of node Q and signal output part Vout (n) of shift register SR (n) just can be pulled down to an electronegative potential, but because reset circuit 300 operating time is limited to (n+1)th grade of sweep signal G (n+1), so the drop-down action of the current potential of signal output part Vout (n) of reset circuit 300 couples of node Q and shift register SR (n) can not settle at one go, therefore also need pull-down circuit 400 to come to do further drop-down to these two current potentials, preset potential is pulled down to make these two current potentials, in the present embodiment, this preset potential refers to current potential corresponding to the first voltage VSS.
Identical with reset circuit 300 is, pull-down circuit 400 is also electrically connected to node Q with control circuit 100, and be electrically connected to signal output part Vout (n) of shift register SR (n) with output circuit 200, for responding the first pulse signal CK and the second pulse signal XCK, be pulled down to preset potential with the current potential of signal output part Vout (n) of the current potential and shift register SR (n) that make node Q.It should be noted that, because pull-down circuit 400 is not by the control of (n+1)th grade of sweep signal G (n+1), so it further can go to perform the drop-down action also do not completed after reset circuit 300 terminates drop-down action.In addition, because the inner structure of pull-down circuit 400 is common in prior art, it can be made up of transistor circuit or other selectivity breakover elements form, therefore does not repeat at this.
Then, carry out incorporated by reference to Fig. 3 the circuit framework figure that reference diagram 4, Fig. 4 is the first on-off circuit and second switch circuit when this n-th grade of shift register is electrically connected mutually with (n-1)th grade of shift register, (n+1)th grade of shift register in Fig. 3.Fig. 4 is in order to highlight the feature of switch module, therefore shift register all with box indicating, as shown in Figure 4, first on-off circuit comprises the first input switch unit SW1 and the first output switching element SW1 ', and the first input switch unit SW1 comprises transistor T1a, wherein, transistor T1a has control end, first end and the second end, the control end of transistor T1a receives trigger pip X, in order to respond this trigger pip X, and then starts the first input switch SW1; The first end of transistor T1a is electrically connected the signal output part Vout (n-1) of (n-1)th grade of shift register SR (n-1); Second end of transistor T1a is then electrically connected to signal input part Vin (n) of n-th grade of shift register SR (n); And the first output switching element SW1 ' comprises transistor T1b, wherein, transistor T1b has control end, first end and the second end, and the control end of transistor T1b receives trigger pip X, in order to respond this trigger pip X, and then starts the first output switch SW1 '; The first end of transistor T1b is electrically connected signal output part Vout (n) of n-th grade of shift register SR (n); Second end of transistor T1b is then electrically connected to the signal input part Vin (n+1) of (n+1)th grade of shift register SR (n+1).
To sum up illustrate, first input switch unit SW1 is identical with the circuit framework of the first output switching element SW1 ', same, in the present embodiment, second input switch unit SW2 is also identical with the circuit framework of the second output switching element SW2 ', but the circuit framework unlike the second input switch unit SW2 and the second output switching element SW2 ' is different from the circuit framework of the first input switch unit SW1 and the first output switching element SW1 ', second input switch unit SW2 and the second output switching element SW2 ' is all made up of three transistors, namely the second input switch unit SW2 comprises transistor T2a, transistor T3a and transistor T4a, wherein:
Transistor T2a has control end, first end and the second end, the control end of transistor T2a is electrically connected to node Y1, in order to respond the current potential of this node Y1 to control the break-make of transistor T2a, the first end of transistor T2a is electrically connected signal input part Vin (n) of n-th grade of shift register SR (n), and second end of transistor T2a is electrically connected the signal output part Vout (n+1) of (n+1)th grade of shift register SR (n+1);
Transistor T3a has control end, first end and the second end, the control end of transistor T3a receives trigger pip X, in order to respond this trigger pip X to control the break-make of transistor T3a, the first end of transistor T3a is electrically connected to node Y1, and second termination of transistor T3a receives the first voltage VSS;
Transistor T4a has control end, first end and the second end, the control end of transistor T4a is electrically connected second end of transistor T4a, the first end of transistor T4a receives the second voltage VGH, and second end of transistor T4a is electrically connected to node Y1, namely the control end of transistor T4a is also electrically connected to node Y1.
On the other hand, the second output switching element SW2 ' comprises transistor T2b, transistor T3b and transistor T4b, wherein:
Transistor T2b has control end, first end and the second end, the control end of transistor T2b is electrically connected to node Y2, in order to respond the current potential of this node Y2 to control the break-make of transistor T2b, the first end of transistor T2b is electrically connected the signal input part Vin (n-1) of (n-1)th grade of shift register SR (n), and second end of transistor T2b is electrically connected signal output part Vout (n) of n-th grade of shift register SR (n);
Transistor T3b has control end, first end and the second end, the control end of transistor T3b receives trigger pip X, in order to respond this trigger pip X to control the break-make of transistor T3b, the first end of transistor T3b is electrically connected to node Y2, and second termination of transistor T3b receives the first voltage VSS;
Transistor T4b has control end, first end and the second end, the control end of transistor T4b is electrically connected second end of transistor T4b, the first end of transistor T4b receives the second voltage VGH, and second end of transistor T4b is electrically connected to node Y2, namely the control end of transistor T4b is also electrically connected to node Y2.
In simple terms, the second input switch unit SW2 is controlled by the break-make of transistor T2a, and the second output switching element SW2 ' is controlled by the break-make of transistor T2b.For the second input switch unit SW2, the break-make of transistor T2a is controlled by the current potential of node Y1, when the current potential of node Y1 is in noble potential, transistor T2a conducting, thus start the second input switch unit SW2, and when the current potential of node Y1 is in electronegative potential, transistor T2a ends, thus close the second input switch unit SW2.The principle of start-stop of the second output switching element SW2 ' is identical with the second input switch unit SW2, therefore does not repeat at this.
Below in the lump with reference to figure 4, Fig. 5 A and Fig. 5 B, describe the principle that gate driver circuit 10 of the present invention performs forward scan and reverse scanning in detail.As shown in Figure 5A, when trigger pip X is in noble potential, transistor T1a and transistor T1b is in conducting state, the first corresponding input switch unit SW1 and the first output switching element SW1 ' starts, and for the second input switch unit SW2 and the second output switching element SW2 ', the trigger pip X being in noble potential can make transistor T3a and transistor T3b conducting, for the second input switch unit SW2, now transistor T4a is also in conducting state, but in the present embodiment, the ratio that transistor T3a channel width and the ratio of channel length are greater than this transistor T4a channel width and channel length is (same, the ratio of transistor T3b channel width and channel length is greater than the ratio of this transistor T4b channel width and channel length), so, transistor T3a has better current capacity than transistor T4a, namely the electric current I 3 flowing through transistor T3a is greater than the electric current I 4 flowing through transistor T4a, therefore based on the effect that electric current is pullled, the current potential of node Y1 can be pulled low to electronegative potential corresponding to the first voltage VSS, simultaneously, transistor T4a control end current potential also can be dragged down further, thus transistor T4a is also ended, so just further make the second voltage VGH cannot pour into node Y1, therefore, node Y1 current potential is dragged down means that transistor T2a cannot conducting, so the second input switch unit SW2 cannot start, in like manner, the current potential of node Y2 also can be in electronegative potential, therefore the second output switching element SW2 ' also cannot start.
In brief, when trigger pip X is in noble potential, by the first input switch unit SW1 started and the first output switching element SW1 ', gate driver circuit 10 can carry out the forward transmission that forward scan and shift-register circuit 11 carry out sweep signal step by step, precisely, intersegmental when T0 to T1, (n-1)th grade of shift register SR (n-1) exports (n-1)th grade of sweep signal G (n-1) to the first input switch unit SW1, and (n-1)th grade of sweep signal G (n-1) is in noble potential, therefore based on the first input switch unit SW1 started, (n-1)th grade of sweep signal G (n-1) namely can input to signal input part Vin (n) of n-th grade of shift register SR (n), and then start this n-th grade of shift register SR (n), and when intersegmental when T1 to T2, by the input of (n-1)th grade of sweep signal G (n-1) as enabling signal, n-th grade of shift register SR (n) correspondingly can export n-th grade of sweep signal G (n), simultaneously, in this period, n-th grade of sweep signal G (n) that n-th grade of shift register SR (n) exports can input to the first output switching element SW1 ', and n-th grade of sweep signal G (n) is in noble potential, based on the first output switching element SW1 ' started, n-th grade of sweep signal G (n) inputs to the signal input part Vin (n+1) of (n+1)th grade of shift register SR (n+1), and then start this (n+1)th grade of shift register SR (n+1), in addition, because now n-th grade of sweep signal G (n) is in noble potential, so it can trigger the reset circuit of (n-1)th grade of shift register SR (n-1), and then drag down the current potential of (n-1)th grade of sweep signal G (n-1), the output of (n-1)th grade of shift register SR (n-1) is ended, and then, intersegmental when T2 to T3, namely when the enabling signal of n-th grade of sweep signal G (n) as (n+1)th grade of shift register SR (n+1), (n+1)th grade of shift register SR (n+1) correspondingly can export (n+1)th grade of sweep signal G (n+1), same, the (n+1)th grade of sweep signal G (n+1) being in noble potential can trigger the reset circuit in n-th grade of shift register SR (n), and then drag down the current potential of n-th grade of sweep signal G (n), the output of n-th grade of shift register SR (n) is ended.
Therefore, as described above, under the control of trigger pip X being in noble potential, by the effect of the first input switch unit SW1 in the first on-off circuit and the first output switching element SW1 ' to sweep signal forward transmission step by step, in shift-register circuit 11, namely a plurality of shift register can complete the output of forward step by step of the corresponding sweep signal of each shift register, so in other words, namely the gate driver circuit 10 comprising shift-register circuit 11 can perform forward scan output action.
Contrary, as shown in Figure 5 B, when trigger pip X is in electronegative potential, transistor T1a and transistor T1b is in cut-off state, the first corresponding input switch unit SW1 and the first output switching element SW1 ' closes, and for the second input switch unit SW2 and the second output switching element SW2 ', the trigger pip X being in electronegative potential can make transistor T3a and transistor T3b end, for the second input switch unit SW2, now transistor T4a is still in conducting state, although transistor T3a has better current capacity than transistor T4a, but it is intersegmental at this time, because transistor T3a is cut-off state, so the electric current I 3 flowing through transistor T3a is less than the electric current I 4 flowing through transistor T4a, further, based on the effect that electric current is pullled, second voltage VGH can pour into node Y1 via transistor T4a, thus the noble potential that current potential to the second voltage VGH drawing high node Y1 is corresponding, therefore, now transistor T2a will conducting, so the second input switch unit SW2 starts, in like manner, the current potential of node Y2 also can be in noble potential, therefore the second output switching element SW2 ' also starts simultaneously.
Furtherly, when trigger pip X is in electronegative potential, by the second input switch unit SW2 started and the second output switching element SW2 ', gate driver circuit 10 can carry out the forward transmission that forward scan and shift-register circuit 11 carry out sweep signal step by step, specifically, as shown in Figure 5 B, intersegmental when T0 to T1, (n+1)th grade of shift register SR (n+1) exports (n+1)th grade of sweep signal G (n+1) to the second input switch unit SW2, and (n+1)th grade of sweep signal G (n+1) is in noble potential, therefore based on the second input switch unit SW2 started, (n+1)th grade of sweep signal G (n+1) namely can input to signal input part Vin (n) of n-th grade of shift register SR (n), and then start this n-th grade of shift register SR (n), and when intersegmental when T1 to T2, by the input of (n+1)th grade of sweep signal G (n+1) as enabling signal, n-th grade of shift register SR (n) correspondingly can export n-th grade of sweep signal G (n), simultaneously, in this period, n-th grade of sweep signal G (n) that n-th grade of sweep signal G (n) exports can input to the second output switching element SW2 ', and n-th grade of sweep signal G (n) is in noble potential, so based on the second output switching element SW2 ' started, n-th grade of sweep signal G (n) inputs to the signal input part Vin (n-1) of (n-1)th grade of shift register SR (n-1), and then start this (n-1)th grade of shift register SR (n-1), in addition, because now n-th grade of sweep signal G (n) is in noble potential, so it can trigger the reset circuit of (n+1)th grade of shift register SR (n+1), and then drag down the current potential of (n+1)th grade of sweep signal G (n+1), the output of (n+1)th grade of shift register SR (n+1) is ended, and then, intersegmental when T2 to T3, namely when the enabling signal of n-th grade of sweep signal G (n) as (n-1)th grade of shift register SR (n-1), (n-1)th grade of shift register SR (n-1) correspondingly can export (n-1)th grade of sweep signal G (n-1), same, the (n-1)th grade of sweep signal G (n-1) being in noble potential can trigger the reset circuit in n-th grade of shift register SR (n), and then drag down the current potential of n-th grade of sweep signal G (n), the output of n-th grade of shift register SR (n) is ended.
Therefore, similar to forward scan, shift-register circuit 11 is under the control of trigger pip X being in electronegative potential, by the second input switch unit SW2 in second switch circuit and the second output switching element SW2 ' to the effect of the reverse transmission of sweep signal step by step, namely a plurality of shift register can complete the Inverted Output step by step of the corresponding sweep signal of each shift register, so, in other words, namely the gate driver circuit 10 comprising shift-register circuit 11 can perform reverse scanning output action.
It will be further appreciated that, the second input switch unit SW2 in the first input switch unit SW1 in the first on-off circuit as shown in Figure 4 and the first output switching element SW1 ' and second switch circuit and the second output switching element SW2 ', whole control gate driving circuit 10 is just inverse sweeps the on-off circuit of switching all based on the control of a trigger pip X, in other words, gate driver circuit of the present invention only need utilize a control signal namely can complete the forward scan output of gate driver circuit and the switching of reverse scanning output, successfully decrease the use of control signal.
Therefore, in sum, the present invention is by the redesign to shift-register circuit, effectively decrease the use of control signal, gate driver circuit of the present invention is made only to need a control signal namely can realize bilateral scanning handoff functionality, in other words, the present invention reduce further the control complexity in display driver circuit on the basis of existing technology, and the shift-register circuit impelling the present invention to propose and the gate driver circuit comprising it have better application prospect.
The present invention is described by above-mentioned related embodiment, but above-described embodiment is only enforcement example of the present invention.Must it is noted that the embodiment disclosed limit the scope of the invention.On the contrary, change done without departing from the spirit and scope of the present invention and retouching, all belong to scope of patent protection of the present invention.
Claims (10)
1. a shift-register circuit, is characterized in that this shift-register circuit comprises:
A plurality of shift register, this plurality of shift register electric property coupling in cascaded fashion, each shift register has signal input part and signal output part;
First on-off circuit, there is the first input switch unit and the first output switching element, this first input switch unit and this signal input part are electrically connected, this first output switching element and this signal output part are electrically connected, wherein, this first input switch unit, in order to respond a trigger pip, extremely works as level shift register to transmit this upper level sweep signal, this first output switching element, in order to respond this trigger pip, deserves level sweep signal to next stage shift register to transmit; And
Second switch circuit, there is the second input switch unit and the second output switching element, this second input switch unit and this signal input part are electrically connected, this second output switching element and this signal output part are electrically connected, wherein, this second input switch unit, in order to respond this trigger pip, extremely deserves level shift register to transmit this next stage sweep signal, this second output switching element, in order to respond this trigger pip, deserves level sweep signal to upper level shift register to transmit;
Wherein, when this trigger pip is noble potential, this shift-register circuit carries out the forward transmission of sweep signal step by step; When this trigger pip is electronegative potential, this shift-register circuit carries out the reverse transmission of sweep signal step by step.
2. shift-register circuit as claimed in claim 1, it is characterized in that this first switch input unit comprises the first transistor, this the first transistor has control end, first end and the second end, the control end of this first transistor receives this trigger pip, the first end of this first transistor is electrically connected the signal output part of this upper level shift register, and the second end of this first transistor is electrically connected the signal input part deserving level shift register.
3. shift-register circuit as claimed in claim 2, is characterized in that this second output switching element:
Transistor seconds, this transistor seconds has control end, first end and the second end, the control end of this transistor seconds is electrically connected to first node, the first end of this transistor seconds is electrically connected the signal input part of this upper level shift register, and the second end of this transistor seconds is electrically connected the signal output part deserving level shift register;
Third transistor, this third transistor has control end, first end and the second end, the control end of this third transistor receives this trigger pip, and the first end of this third transistor is electrically connected to this first node, and the second termination of this third transistor receives the first voltage; And
4th transistor, 4th transistor has control end, first end and the second end, the control end of the 4th transistor is electrically connected the second end of the 4th transistor, and the first end of the 4th transistor receives the second voltage, and the second end of the 4th transistor is electrically connected to this first node.
4. shift-register circuit as claimed in claim 3, is characterized in that this second voltage is greater than this first voltage.
5. shift-register circuit as claimed in claim 3, is characterized in that the ratio of this third transistor channel width and channel length is greater than the ratio of the 4th transistor channel width and channel length.
6. shift-register circuit as claimed in claim 5, is characterized in that this each shift register comprises:
Control circuit, for responding this upper level sweep signal, to export when level control signal;
Output circuit, this output circuit and this control circuit are electrically connected to Section Point, deserve level control signal for response, deserve level sweep signal to export;
Pull-down circuit, this pull-down circuit and this control circuit are electrically connected to this Section Point and this pull-down circuit and this output circuit are electrically connected to the signal output part deserving level shift register, for responding the first pulse signal and the second pulse signal, be pulled down to preset potential to make the current potential of this Section Point with the current potential of the signal output part deserving level shift register; And
Reset circuit, this reset circuit and this control circuit are electrically connected to this Section Point and this reset circuit and this output circuit are electrically connected to the signal output part deserving level shift register, for responding this next stage sweep signal and this first voltage, with the current potential of this Section Point that resets and the current potential of signal output part deserving level shift register.
7. shift-register circuit as claimed in claim 6, is characterized in that this control circuit comprises:
5th transistor, 5th transistor has control end, first end and the second end, the control end of the 5th transistor and first end are all electrically connected to the signal input part deserving level shift register, and the second end of the 5th transistor is electrically connected to this Section Point.
8. shift-register circuit as claimed in claim 7, is characterized in that this output circuit comprises:
6th transistor, 6th transistor has control end, first end and the second end, the control end of the 6th transistor is electrically connected to this Section Point, the first end of the 6th transistor receives this first pulse signal or this second pulse signal, and the second end of the 6th transistor is electrically connected to the signal output part deserving level shift register.
9. shift-register circuit as claimed in claim 8, is characterized in that this reset circuit comprises:
7th transistor, 7th transistor has control end, first end and the second end, the control end of the 7th transistor is electrically connected to the 3rd node, and the first end of the 7th transistor is electrically connected to the 3rd node, and the second termination of the 7th transistor receives this first voltage;
8th transistor, 8th transistor has control end, first end and the second end, the control end of the 8th transistor is electrically connected to the 3rd node, the first end of the 8th transistor is electrically connected to the signal output part deserving level shift register, and the second termination of the 8th transistor receives this first voltage;
Wherein, the current potential of the 3rd node corresponds to the current potential of this next stage sweep signal.
10. a gate driver circuit, is characterized in that this gate driver circuit comprises:
Shift-register circuit as in one of claimed in any of claims 1 to 9, this plurality of shift register is in order to export a plurality of sweep signal;
Trigger signal source, in order to provide this trigger pip; And
Start trigger signal source, this start trigger signal source in order to provide a start trigger signal to the first order shift register in this shift-register circuit or afterbody shift register, to start this first order shift register or this afterbody shift register.
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| CN201310454905.1A CN104517556A (en) | 2013-09-29 | 2013-09-29 | Shift register circuit and gate driving circuit comprising same |
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| CN201310454905.1A CN104517556A (en) | 2013-09-29 | 2013-09-29 | Shift register circuit and gate driving circuit comprising same |
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| CN104517556A true CN104517556A (en) | 2015-04-15 |
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| CN104821159A (en) * | 2015-05-07 | 2015-08-05 | 京东方科技集团股份有限公司 | Gate driving circuit, display panel and touch display device |
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