CN103050077B - A kind of gate driver circuit, driving method and liquid crystal indicator - Google Patents
A kind of gate driver circuit, driving method and liquid crystal indicator Download PDFInfo
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- CN103050077B CN103050077B CN201210545763.5A CN201210545763A CN103050077B CN 103050077 B CN103050077 B CN 103050077B CN 201210545763 A CN201210545763 A CN 201210545763A CN 103050077 B CN103050077 B CN 103050077B
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 83
- 239000010409 thin film Substances 0.000 claims description 88
- 239000010408 film Substances 0.000 claims description 10
- 101100214497 Solanum lycopersicum TFT5 gene Proteins 0.000 description 12
- 101100268327 Solanum lycopersicum TFT6 gene Proteins 0.000 description 12
- 101100268330 Solanum lycopersicum TFT7 gene Proteins 0.000 description 12
- 101100489584 Solanum lycopersicum TFT1 gene Proteins 0.000 description 11
- 101100214488 Solanum lycopersicum TFT2 gene Proteins 0.000 description 11
- 101100214491 Solanum lycopersicum TFT3 gene Proteins 0.000 description 11
- 101100214494 Solanum lycopersicum TFT4 gene Proteins 0.000 description 11
- 238000010586 diagram Methods 0.000 description 11
- 101100268333 Solanum lycopersicum TFT8 gene Proteins 0.000 description 10
- 230000002146 bilateral effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000017105 transposition Effects 0.000 description 1
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Abstract
The invention discloses a kind of gate driver circuit, driving method and liquid crystal indicator.Gate driver circuit comprises: multistage bidirectional shift register, the first reset circuit and the second reset circuit; First reset circuit comprises the first input end and the second input end that are electrically connected with input end and the reverse impulse input end of first order bidirectional shift register respectively, the the first clock control end be connected with second clock signal, the reset output terminal be connected with the output terminal of first order bidirectional shift register, and low level signal end.Described gate driver circuit, driving method and liquid crystal indicator, solving bidirectional shift register circuit can not the problem of proper reset to first order bidirectional shift register and afterbody bidirectional shift register by STV signal.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly a kind of gate driver circuit, driving method and liquid crystal indicator.
Background technology
Bilateral scanning gate driver circuit, original shift register can be utilized to do simple structural adjustment to realize, but original reset circuit is no longer applicable.In existing bilateral scanning gate driver circuit, be used alone gated sweep start signal (STV signal) when first order bidirectional shift register and afterbody shift register are resetted, because there is blank (Dummy) time, STV signal is not just in time the signal of a unit time of the first order or afterbody shift register output, such as corresponding STV signal, resolution is the sweep time of panel one frame of 1920*1080 is (a N × mono-unit time), N>1080, { (N-1080) × mono-unit time } is time of Dummy.Wherein, a unit time is 1/ frame frequency/vertical resolution.
For the problems referred to above, the solution of existing technology is above first order bidirectional shift register, and the below of last column register respectively increases a pseudo-level (Dummy).Although the output in pseudo-level is incorrect, can ensure normal scan line exports correctly.This method does not fundamentally solve the output abnormality problem of last column and the first row yet, and adds implementation cost.
Summary of the invention
(1) technical matters that will solve
The technical problem to be solved in the present invention is: provide a kind of gate driver circuit, driving method and liquid crystal indicator, can not the problem of normal reset to solve the first order bidirectional shift register of bidirectional shift register circuit and afterbody bidirectional shift register.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of gate driver circuit, it comprises:
Multistage bidirectional shift register, connect according to so a kind of mode mutually: the output signal from each bidirectional shift register output terminal is input to the reverse impulse input end of bidirectional shift register described in previous stage, and be input to the direct impulse input end of bidirectional shift register described in rear stage, described bidirectional shift register at different levels works under the control of the first clock signal and second clock signal, and the phase place of described first clock signal and described second clock signal is contrary;
First reset circuit, described first reset circuit comprises the first input end and the second input end that are electrically connected with direct impulse input end and the reverse impulse input end of the first order shift register of described multistage bidirectional shift register respectively, the the first clock control end be connected with described second clock signal, the first reset output terminal be electrically connected with the output terminal of described first order shift register, and low level signal end;
Second reset circuit, described second reset circuit comprises the 3rd input end and the four-input terminal be electrically connected with direct impulse input end and the reverse impulse input end of the afterbody shift register of described multistage bidirectional shift register respectively, the second clock control end be connected with described second clock signal, the second reset output terminal be electrically connected with the output terminal of described afterbody shift register, and low level signal end;
Described first input end and described four-input terminal are for receiving scanning start signal.
Wherein, described first reset circuit comprises: the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT);
The grid of described the first film transistor and source electrode are all electrically connected with described first clock control end;
The source electrode of the drain electrode of described the first film transistor, the source electrode of described second thin film transistor (TFT), described 3rd thin film transistor (TFT) and the grid of described 4th thin film transistor (TFT) are electrically connected to each other;
The drain electrode of described second thin film transistor (TFT), the drain electrode of described 3rd thin film transistor (TFT) and the drain electrode of the 4th thin film transistor (TFT) are all electrically connected with described low level signal end;
The grid of described second thin film transistor (TFT) is electrically connected with described first input end;
The grid of described 3rd thin film transistor (TFT) is electrically connected with described second input end;
The source electrode of described 4th thin film transistor (TFT) is electrically connected with described first reset output terminal.
Wherein, described second reset circuit comprises: the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT) and the 8th thin film transistor (TFT);
Grid and the source electrode of described 5th thin film transistor (TFT) are all electrically connected with described second clock control end;
The drain electrode of described 5th thin film transistor (TFT), the source electrode of described 6th thin film transistor (TFT), the source electrode of described 7th thin film transistor (TFT) and the grid of described 8th thin film transistor (TFT) are electrically connected to each other;
The drain electrode of described 6th thin film transistor (TFT), the drain electrode of described 7th thin film transistor (TFT) and the drain electrode of the 8th thin film transistor (TFT) are all electrically connected with described low level signal end;
The grid of described 6th thin film transistor (TFT) is electrically connected with described 3rd input end;
The grid of described 7th thin film transistor (TFT) is electrically connected with described four-input terminal;
The source electrode of described 8th thin film transistor (TFT) is electrically connected with described second reset output terminal.
Wherein, all described thin film transistor (TFT)s all adopt N-type TFT.
The present invention also provides a kind of liquid crystal indicator, and described liquid crystal indicator comprises described gate driver circuit.
Wherein, described gate driver circuit is integrated on the array base palte of described liquid crystal indicator.
The present invention also provides a kind of for providing the driving method of gate drive signal to the display device comprising described gate driver circuit, and described driving method comprises:
When carrying out from first order bidirectional shift register to the forward scan of afterbody bidirectional shift register, the second reset enable signal afterbody bidirectional shift register proper reset that the second reset circuit exports;
When carrying out from afterbody bidirectional shift register to the reverse scan of first order bidirectional shift register, the bidirectional shift register proper reset of the first reset enable signal first order that the first reset circuit exports.
(3) beneficial effect
Gate driver circuit of the present invention, driving method and liquid crystal indicator, in the front end of first order bidirectional shift register, the first reset circuit is set, and the rear end of in the end one-level bidirectional shift register arranges the second reset circuit, utilize existing clock signal, this bidirectional shift register circuit can proper reset to first order bidirectional shift register and afterbody bidirectional shift register by STV signal, and does not affect other output at different levels.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of existing bilateral scanning gate driver circuit;
Fig. 2 is the circuit diagram of gate driver circuit described in the embodiment of the present invention;
Fig. 3 is the electrical block diagram of the first reset circuit of embodiments of the invention;
Fig. 4 is the electrical block diagram of the second reset circuit of embodiments of the invention;
Fig. 5 a is the sequential chart of first reset circuit when forward scan of gate driver circuit described in the embodiment of the present invention;
Fig. 5 b is the sequential chart of second reset circuit when forward scan of gate driver circuit described in the embodiment of the present invention;
Fig. 6 a is the sequential chart of second reset circuit when reverse scan of gate driver circuit described in the embodiment of the present invention;
Fig. 6 b is the sequential chart of first reset circuit when reverse scan of gate driver circuit described in the embodiment of the present invention;
Fig. 7 is for providing the driving method process flow diagram of gate drive signal to the display device of the gate driver circuit comprised in Fig. 2 described in the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but are not used for limiting the scope of the invention.
Fig. 2 is the circuit diagram of gate driver circuit described in the embodiment of the present invention, and as shown in Figure 2, described gate driver circuit comprises:
Multistage bidirectional shift register (SR1, SR2, SRN), connect according to so a kind of mode mutually: the output signal from each bidirectional shift register output terminal OUTPUT is input to the reverse impulse input end INPUT_B of bidirectional shift register described in previous stage, and be input to the direct impulse input end INPUT_F of bidirectional shift register described in rear stage, described bidirectional shift register at different levels works under the control of the first clock signal clk and second clock signal CLKB, the phase place of described first clock signal clk and described second clock signal CLKB is contrary,
First reset circuit RESETUnit1, described first reset circuit RESETUnit1 comprises the first input end INPUT1 and the second input end INPUT2 that are electrically connected with direct impulse input end INPUT_F and the reverse impulse input end INPUT_B of the first order shift register SR1 of described multistage bidirectional shift register respectively, the the first clock control end CLKM be connected with described second clock signal CLKB, the the first reset output terminal OUTPUT-RESET1 be electrically connected with the output terminal OUTPUT of described first order shift register SR1, and low level signal end VSS;
Second reset circuit RESETUnit2, described second reset circuit RESETUnit2 comprises the 3rd input end INPUT3 and four-input terminal INPUT4 be electrically connected with direct impulse input end INPUT_F and the reverse impulse input end INPUT_B of the afterbody shift register SRN of described multistage bidirectional shift register respectively, the second clock control end CLKN be connected with described second clock signal CLKB, the the second reset output terminal OUTPUT-RESET2 be electrically connected with the output terminal OUTPUT of described afterbody shift register SRN, and low level signal end VSS;
Described first input end INPUT1 and described four-input terminal INPUT4 is for receiving scanning start signal STV.It should be noted that all low level signal ends in the present invention are all represent with VSS.
In the present embodiment, bilateral scanning gate driver circuit does not mark by two direction of scanning control end Vd1 and Vd2(Fig. 2) gated sweep direction.Particularly, when Vd1 is high level, when Vd2 is low level, gate driver circuit carries out the forward scan by first order shift register SR1 to afterbody shift register SRN, now the direct impulse input end INPUT_F of first order bidirectional shift register SR1 receives scanning start signal STV, the reverse impulse input end INPUT_B of SR1 receives the output signal of second level shift register SR2, and INPUT_B end is now used as the reset signal input end of SR1; The INPUT_F end of other shift registers at different levels is all for receiving the output signal of upper level, and INPUT_B termination accepts the output signal of one-level for resetting to shift register at the corresponding levels.
When Vd1 is low level, when Vd2 is high level, gate driver circuit carries out the reverse scan from afterbody shift register SRN to first order shift register SR1, now the reverse impulse input end INPUT_B of afterbody bidirectional shift register SRN receives the direct impulse input end INPUT_F scanning start signal STV, SRN and accepts the output signal of penultimate stage shift register SRN-1 for resetting to the output signal of SRN; The INPUT_B end of other shift registers at different levels is all for receiving the output signal of next stage, and the output signal that INPUT_F termination receives upper level is used for resetting to shift register at the corresponding levels.
Fig. 3 is the electrical block diagram of the first reset circuit described in embodiments of the invention.As shown in Figure 3, described first reset circuit, comprising: the first film transistor TFT1, the second thin film transistor (TFT) TFT2, the 3rd thin film transistor (TFT) TFT3 and the 4th thin film transistor (TFT) TFT4.
Particularly, the grid of the first film transistor TFT1 and source electrode are all electrically connected with the first clock control end CLKM; The drain electrode of the first film transistor TFT1, the source electrode of the second thin film transistor (TFT) TFT2, the source electrode of the 3rd thin film transistor (TFT) TFT3 and the grid of the 4th thin film transistor (TFT) TFT4 are electrically connected to each other; The drain electrode of the drain electrode of TFT2, the drain electrode of TFT3 and TFT4 is all electrically connected with low level signal end VSS; The grid of the second thin film transistor (TFT) TFT2 is connected with first input end electricity INPUT1; The grid of the 3rd thin film transistor (TFT) TFT3 is electrically connected with the second input end INPUT2; The source electrode of the 4th thin film transistor (TFT) TFT4 is connected with the first reset output terminal electricity OUTPUT-RESET1.
Fig. 4 is the electrical block diagram of the second reset circuit described in embodiments of the invention.Second reset circuit comprises as shown in Figure 4: the 5th thin film transistor (TFT) TFT5, the 6th thin film transistor (TFT) TFT6, the 7th thin film transistor (TFT) TFT7 and the 8th thin film transistor (TFT) TFT8.
Particularly, the grid of the 5th thin film transistor (TFT) TFT5 and source electrode are all electrically connected with second clock control end CLKN; The drain electrode of the 5th thin film transistor (TFT) TFT5, the source electrode of the 6th thin film transistor (TFT) TFT6, the source electrode of the 7th thin film transistor (TFT) TFT7 and the grid of the 8th thin film transistor (TFT) TFT8 are electrically connected to each other; The drain electrode of the drain electrode of TFT6, the drain electrode of TFT7 and TFT8 is all electrically connected with low level signal end VSS; The grid of the 6th thin film transistor (TFT) TFT6 is electrically connected with the 3rd input end INPUT3; The grid of the 7th thin film transistor (TFT) TFT7 is electrically connected with four-input terminal INPUT4; The source electrode of the 8th thin film transistor (TFT) TFT8 is electrically connected with described second reset output terminal OUTPUT-RESET2.
Preferably, the first reset circuit in the present invention and/or all thin film transistor (TFT)s in the second reset circuit are all N-type TFT, and it should be noted that the source electrode of above-mentioned all thin film transistor (TFT)s and drain electrode can transpositions.In addition, the particular circuit configurations of the first reset circuit and the second reset circuit is not limited to the circuit structure in the embodiment of the present invention, and the first reset circuit and the second reset circuit also can be that other have the reset circuit of similar functions.
In gate driver circuit of the present invention, the VSS end of the first reset circuit and the VSS end of described second reset circuit are all held with the VSS of bidirectional shift register at different levels and are electrically connected to each other.The CLKM end of the first reset circuit and the CLKN end of the second reset circuit are for inputting CLKB signal.
The bidirectional shift register of the embodiment of the present invention can adopt number of patent application to be shift-register circuit in CN201110241400.8.It should be noted that, the circuit structure of bidirectional shift register is not limited to above-mentioned patent documentation, and other the shift-register circuit with similar functions according to the invention is all applicable to the present invention.
Fig. 5 a is the sequential chart of first reset circuit when forward scan of gate driver circuit described in the embodiment of the present invention.In fig 5 a, CLKB inputs the waveform of the clock signal of the first clock control end CLKM of the first reset circuit when representing forward scan, namely STV/INPUT1 represents the waveform of scanning start signal, also be the input waveform of the first input end INPUT1 of the first reset circuit, INPUT2 represents the signal output waveform of the output terminal OUTPUT of second level bidirectional shift register SR2, OUT1 is the signal output waveform of first order bidirectional shift register SR1, and RESET represents the signal waveform of RESET point in the first reset circuit in Fig. 3.Particularly, the circuit structure diagram of the first reset circuit of the sequential chart composition graphs 3 of Fig. 5 a, within the t1 time period, CLKB is high level, the first film transistor TFT1 conducting in the first reset circuit now in Fig. 3, STV signal and INPUT1 are high level, the second thin film transistor (TFT) TFT2 also conducting in the first reset circuit now in Fig. 3, INPUT2 is low level, OUT1 is low level, the 3rd thin film transistor (TFT) TFT3 in the first reset circuit now in Fig. 3 ends, now in the first reset circuit, thin film transistor (TFT) TFT1 and TFT2 wants to make the RESET point in now Fig. 3 in the first reset circuit be low level, such 4th thin film transistor (TFT) TFT4 ends, therefore inoperative in the output of t1 period first reset circuit to first order bidirectional shift register.In the t2 time period, CLKB becomes low level, and TFT1 ends, STV signal and INPUT1 become low level, now TFT2 cut-off, and INPUT2 is still low level, now TFT3 still remain off state, so now the current potential of RESET point still remains on low level, TFT4 is still cut-off.Within the t3 period, CLKB becomes high level, TFT1 conducting, STV signal and INPUT1 still keep low level, now TFT2 still remain off state, INPUT2 now becomes high level, now TFT3 conducting, and TFT1 and TFT3 wants to make the current potential of the point of the RESET within the t3 period still keep low level, and TFT4 is still in cut-off state.Within the t4 period, CLKB, STV/INPUT1, INPUT2 and OUT1 are low level, and now TFT1, TFT2 and TFT3 are all in cut-off state, and RESET point current potential now still remains on low level, and therefore TFT4 is also cut-off.Within other periods, RESET current potential keeps high level under the control of CLKB, and now TFT4 is conducting, and now the output terminal of first order shift register SR1 is also electronegative potential.In sum, in fig 5 a, the current potential of RESET point can not affect the normal output of first order bidirectional shift register, and that is when forward scan, the first reset circuit can not affect the normal output of first order bidirectional shift register.
Fig. 5 b is the sequential chart of second reset circuit when forward scan of gate driver circuit described in the embodiment of the present invention.In figure 5b, CLKB inputs the waveform of the clock signal of the second clock control end CLKN of the second reset circuit when representing forward scan, namely STV/INPUT4 represents the waveform of scanning start signal, also be the input waveform of the four-input terminal INPUT4 of the second reset circuit, INPUT3 represents penultimate stage bidirectional shift register SR(N-1) the signal output waveform of output terminal OUTPUT, OUTN is the signal output waveform of afterbody bidirectional shift register SRN, and RESET represents the signal waveform of RESET point in the second reset circuit in Fig. 4.Particularly, the circuit structure diagram of the second reset circuit of the sequential chart composition graphs 4 of Fig. 5 b is described, within the t5 time period, CLKB is high level, the 5th thin film transistor (TFT) TFT5 conducting in the second reset circuit now in Fig. 4, STV signal and INPUT4 are low level, the 7th thin film transistor (TFT) TFT7 in the second reset circuit now in Fig. 4 ends, INPUT3 is high level, therefore the 6th thin film transistor (TFT) TFT6 conducting in the second reset circuit in Fig. 4, now in the second reset circuit, thin film transistor (TFT) TFT5 and TFT6 will meet the RESET point in now Fig. 4 in the second reset circuit can be made to be low level, so now the 8th thin film transistor (TFT) TFT8 ends, therefore inoperative in the output of t5 period second reset circuit to level bidirectional shift register last.In the t6 time period, CLKB becomes low level, and TFT5 ends, STV signal and INPUT4 are still low level, now TFT7 still remain off state, and INPUT3 becomes low level, therefore TFT6 cut-off, so now the current potential of RESET point still remains on low level, so TFT8 is still cut-off.Within the t7 period, CLKB is high level, STV/INPUT4, INPUT3 are low level, now TFT5 conducting, TFT6, TFT7 are all cut-offs, so now RESET point is high level, and TFT8 conducting, the OUTPUT-RESET2 current potential of the second reset circuit is low level, and therefore OUTN is now reset to low level.When t8 in end, CLKB becomes low level, and now RESET point still keeps high level, so OUTN still keeps low level, within the t9 period, CLKB and STV/INPUT4 is high level, and INPUT3 is low level, now TFT5 and TFT7 conducting, TFT6 ends, now TFT5 and TFT7 will meet the current potential of RESET point can be made to be electronegative potential, such TFT8 cut-off, and the output of OUTN still remains on low level; Within the t10 period, CLKB and STV/INPUT4 becomes low level, and INPUT3 is still low level, and TFT5, TFT6, TFT7 all end, and RESET point still maintains low level, and it is still low level that OUTN exports; Within other periods, RESET point is all in high level under the control of CLKB, and the output of such OUTN also remains on current potential always.Above-mentioned for forward scan time, the second reset circuit is to the explanation of the reset principle of afterbody shift register.
Fig. 6 a is the sequential chart of second reset circuit when reverse scan of gate driver circuit described in the embodiment of the present invention.In Fig. 6 a, CLKB inputs the waveform of the clock signal of the second clock control end CLKN of the second reset circuit when representing reverse scan, namely STV/INPUT4 represents the waveform of scanning start signal, also be the input waveform of the four-input terminal INPUT4 of the second reset circuit, INPUT3 represents the waveform of the 3rd input end of the second reset circuit, also be penultimate stage bidirectional shift register SR(N-1) the signal output waveform of output terminal OUTPUT, OUTN is the signal output waveform of afterbody bidirectional shift register SRN, RESET represents the signal waveform of RESET point in the second reset circuit in Fig. 4.Now in the second reset circuit, in the principle of work of each TFT and Fig. 5 a, the principle of each TFT of the first reset circuit is similar, concrete, and the corresponding TFT4 of TFT5 corresponding TFT1, TFT7 corresponding TFT2, TFT6 corresponding TFT3, TFT8, concrete principle no longer describes in detail here.Similar with the situation of the first reset circuit during forward scan, when reverse scan, the current potential of the RESET point in the second reset circuit can not affect the normal output of afterbody bidirectional shift register equally.
Fig. 6 b is the sequential chart of first reset circuit when reverse scan of gate driver circuit described in the embodiment of the present invention.In figure 6b, CLKB inputs the waveform of the clock signal of the first clock control end CLKM of the first reset circuit when representing reverse scan, namely STV/INPUT1 represents the waveform of scanning start signal, also be the input waveform of the first input end INPUT1 of the first reset circuit, OUT2/INPUT2 represents the signal output waveform of the output terminal OUTPUT of second level bidirectional shift register SR2, is also the input waveform of the second input end of the first reset circuit; OUT1 is the signal output waveform of first order bidirectional shift register SR1, and RESET represents the signal waveform of RESET point in the first reset circuit in Fig. 3.Now when the principle of work of the first reset circuit and forward scan, the principle of work of the second reset circuit is similar, the TFT5 of corresponding second reset circuit of TFT1 of the first reset circuit, the TFT7 of corresponding second reset circuit of TFT2 of the first reset circuit, the TFT6 of corresponding second reset circuit of TFT3 of the first reset circuit, the TFT8 of corresponding second reset circuit of TFT4 of the first reset circuit, concrete principle with reference to the specific descriptions to Fig. 5 b, no longer can describe in detail herein.Therefore the first reset circuit when reverse scan can realize proper reset to first order bidirectional shift register.
The present invention also provides a kind of liquid crystal indicator, and described liquid crystal indicator comprises above-mentioned gate driver circuit, and preferably, described gate driver circuit is integrated on the array base palte of described liquid crystal indicator.
Fig. 7 is that as shown in Figure 7, described method comprises step for providing the driving method process flow diagram of gate drive signal to the display device of the gate driver circuit comprised in Fig. 2 described in the embodiment of the present invention:
When carrying out the forward scan from the first order bidirectional shift register of described multistage bidirectional shift register to afterbody bidirectional shift register, second reset circuit exports the bidirectional shift register proper reset of the second reset enable signal afterbody, and concrete reset principle is see the detailed description to Fig. 5 b sequential chart.
When carrying out the reverse scan from the afterbody bidirectional shift register of described multistage bidirectional shift register to first order bidirectional shift register, first reset circuit exports the bidirectional shift register proper reset of the first reset enable signal first order, and concrete reset principle is see the explanation to Fig. 6 b sequential chart.
Gate driver circuit, driving method and liquid crystal indicator described in the embodiment of the present invention, by arranging the first reset circuit in the front end of first order bidirectional shift register, and the rear end of in the end one-level bidirectional shift register arranges the second reset circuit, utilize existing clock signal, this bidirectional shift register circuit can proper reset to first order bidirectional shift register and afterbody bidirectional shift register by STV signal, and does not affect other output at different levels.
Above embodiment is only for illustration of the present invention; and be not limitation of the present invention; the those of ordinary skill of relevant technical field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all equivalent technical schemes also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (6)
1. a gate driver circuit, is characterized in that, comprising:
Multistage bidirectional shift register, connect according to so a kind of mode mutually: the output signal from each bidirectional shift register output terminal is input to the reverse impulse input end of bidirectional shift register described in previous stage, and be input to the direct impulse input end of bidirectional shift register described in rear stage, described bidirectional shift register at different levels works under the control of the first clock signal and second clock signal, and the phase place of described first clock signal and described second clock signal is contrary;
First reset circuit, described first reset circuit comprises the first input end and the second input end that are electrically connected with direct impulse input end and the reverse impulse input end of the first order shift register of described multistage bidirectional shift register respectively, the the first clock control end be connected with described second clock signal, the first reset output terminal be electrically connected with the output terminal of described first order shift register, and low level signal end;
Second reset circuit, described second reset circuit comprises the 3rd input end and the four-input terminal be electrically connected with direct impulse input end and the reverse impulse input end of the afterbody shift register of described multistage bidirectional shift register respectively, the second clock control end be connected with described second clock signal, the second reset output terminal be electrically connected with the output terminal of described afterbody shift register, and low level signal end;
Described first input end and described four-input terminal are for receiving scanning start signal;
Wherein, described first reset circuit comprises: the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT);
The grid of described the first film transistor and source electrode are all electrically connected with described first clock control end;
The source electrode of the drain electrode of described the first film transistor, the source electrode of described second thin film transistor (TFT), described 3rd thin film transistor (TFT) and the grid of described 4th thin film transistor (TFT) are electrically connected to each other;
The drain electrode of described second thin film transistor (TFT), the drain electrode of described 3rd thin film transistor (TFT) and the drain electrode of the 4th thin film transistor (TFT) are all electrically connected with described low level signal end;
The grid of described second thin film transistor (TFT) is electrically connected with described first input end;
The grid of described 3rd thin film transistor (TFT) is electrically connected with described second input end;
The source electrode of described 4th thin film transistor (TFT) is electrically connected with described first reset output terminal.
2. gate driver circuit as claimed in claim 1, it is characterized in that, described second reset circuit comprises: the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT) and the 8th thin film transistor (TFT);
Grid and the source electrode of described 5th thin film transistor (TFT) are all electrically connected with described second clock control end;
The drain electrode of described 5th thin film transistor (TFT), the source electrode of described 6th thin film transistor (TFT), the source electrode of described 7th thin film transistor (TFT) and the grid of described 8th thin film transistor (TFT) are electrically connected to each other;
The drain electrode of described 6th thin film transistor (TFT), the drain electrode of described 7th thin film transistor (TFT) and the drain electrode of the 8th thin film transistor (TFT) are all electrically connected with described low level signal end;
The grid of described 6th thin film transistor (TFT) is electrically connected with described 3rd input end;
The grid of described 7th thin film transistor (TFT) is electrically connected with described four-input terminal;
The source electrode of described 8th thin film transistor (TFT) is electrically connected with described second reset output terminal.
3. gate driver circuit as claimed in claim 1 or 2, it is characterized in that, all described thin film transistor (TFT)s all adopt N-type TFT.
4. a liquid crystal indicator, is characterized in that, described liquid crystal indicator comprises the gate driver circuit described in any one of claim 1-3.
5. liquid crystal indicator as claimed in claim 4, it is characterized in that, described gate driver circuit is integrated on the array base palte of described liquid crystal indicator.
6. for providing a driving method for gate drive signal to the display device comprising gate driver circuit as claimed in claim 1, it is characterized in that, described driving method comprises:
When carrying out the forward scan from the first order bidirectional shift register of described multistage bidirectional shift register to afterbody bidirectional shift register, afterbody bidirectional shift register proper reset described in the second reset enable signal that the second reset circuit exports;
When carrying out the reverse scan from the afterbody bidirectional shift register of described multistage bidirectional shift register to first order bidirectional shift register, first order bidirectional shift register proper reset described in the first reset enable signal that the first reset circuit exports.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210545763.5A CN103050077B (en) | 2012-12-14 | 2012-12-14 | A kind of gate driver circuit, driving method and liquid crystal indicator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210545763.5A CN103050077B (en) | 2012-12-14 | 2012-12-14 | A kind of gate driver circuit, driving method and liquid crystal indicator |
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| CN103050077B true CN103050077B (en) | 2015-12-23 |
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| CN103943085B (en) * | 2014-04-02 | 2016-05-04 | 京东方科技集团股份有限公司 | The driving method that a kind of gate driver circuit, display unit and subregion show |
| CN104616616B (en) | 2015-02-12 | 2017-12-15 | 京东方科技集团股份有限公司 | Gate driving circuit and its driving method, array base palte, display device |
| CN105047120B (en) * | 2015-06-30 | 2019-01-18 | 上海天马微电子有限公司 | Grid driving circuit, driving method thereof and display device |
| CN105245089B (en) * | 2015-11-06 | 2018-08-03 | 京东方科技集团股份有限公司 | Supplement reseting module, gate driving circuit and display device |
| CN108133694B (en) * | 2018-01-26 | 2020-03-31 | 京东方科技集团股份有限公司 | Gate drive circuit, drive method and display device |
| CN109686334B (en) * | 2019-02-18 | 2021-01-22 | 京东方科技集团股份有限公司 | Gate drive circuit, drive method thereof and display device |
| CN111477181B (en) * | 2020-05-22 | 2021-08-27 | 京东方科技集团股份有限公司 | Gate driving circuit, display substrate, display device and gate driving method |
| CN111653236B (en) * | 2020-06-16 | 2021-09-17 | 厦门天马微电子有限公司 | Display device |
| CN115206244B (en) * | 2021-04-09 | 2023-11-17 | 京东方科技集团股份有限公司 | Display panel, driving method thereof and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1868003A (en) * | 2002-06-10 | 2006-11-22 | 三星电子株式会社 | Shift register, liquid crystal display device having the shift register and method of driving scan lines using the same |
| CN102651238A (en) * | 2011-04-18 | 2012-08-29 | 京东方科技集团股份有限公司 | Shift register unit, shift register, display panel and display |
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| JP4846348B2 (en) * | 2005-11-18 | 2011-12-28 | 株式会社 日立ディスプレイズ | Display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1868003A (en) * | 2002-06-10 | 2006-11-22 | 三星电子株式会社 | Shift register, liquid crystal display device having the shift register and method of driving scan lines using the same |
| CN102651238A (en) * | 2011-04-18 | 2012-08-29 | 京东方科技集团股份有限公司 | Shift register unit, shift register, display panel and display |
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