CN103050077A - Grid electrode driving circuit, driving method and liquid crystal display device - Google Patents
Grid electrode driving circuit, driving method and liquid crystal display device Download PDFInfo
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- CN103050077A CN103050077A CN2012105457635A CN201210545763A CN103050077A CN 103050077 A CN103050077 A CN 103050077A CN 2012105457635 A CN2012105457635 A CN 2012105457635A CN 201210545763 A CN201210545763 A CN 201210545763A CN 103050077 A CN103050077 A CN 103050077A
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Abstract
The invention discloses a grid electrode driving circuit, a driving method and a liquid crystal display device. The grid electrode driving circuit comprises a multi-stage bidirectional shift register, a first reset circuit and a second reset circuit, wherein the first reset circuit comprises a first input end, a second input end, a first clock control end, a reset output end and a low level signal end, the first input end and the second input end are electrically connected with an input end of a primary bidirectional shift register and a reverse pulse input end respectively, the first clock control end is in signal connection with a second clock, and the reset output end is connected with an output end of the primary bidirectional shift register. The problem that the primary bidirectional shift register and the last bidirectional shift register in the circuit of the bidirectional shift register cannot be correctly reset through STV (Subscription TeleVision) signals is solved by the grid electrode driving circuit, the driving method and the liquid crystal display device.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly a kind of gate driver circuit, driving method and liquid crystal indicator.
Background technology
The bilateral scanning gate driver circuit can utilize original shift register to do simple structural adjustment and realize, but original reset circuit is no longer applicable.In the existing bilateral scanning gate driver circuit, when using separately gated sweep start signal (STV signal) that first order bidirectional shift register and afterbody shift register are resetted, because blank (Dummy) time is arranged, the STV signal just in time is not the signal of a unit time of the first order or afterbody shift register output, such as corresponding STV signal, resolution is that be (N * one a unit time) sweep time of panel one frame of 1920*1080, N〉1080, { (N-1080) * one a unit time } is the time of Dummy.Wherein, a unit time is 1/ frame frequency/vertical resolution.
For the problems referred to above, the solution of existing technology is above first order bidirectional shift register, and the below of last column register respectively increases a pseudo-level (Dummy).Although the output on the pseudo-level is incorrect, can guarantee that output is correct on the normal scan line.This method does not fundamentally solve the output abnormality problem of last column and the first row yet, and has increased implementation cost.
Summary of the invention
The technical matters that (one) will solve
The technical problem to be solved in the present invention is: provide a kind of gate driver circuit, driving method and liquid crystal indicator, the problem that can not normally reset with the first order bidirectional shift register that solves the bidirectional shift register circuit and afterbody bidirectional shift register.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of gate driver circuit, it comprises:
The multistage bidirectional shift register, connect according to a kind of like this mode mutually: the reverse impulse input end that is input to the described bidirectional shift register of previous stage from the output signal of each bidirectional shift register output terminal, and be input to the direct impulse input end of the described bidirectional shift register of rear one-level, described bidirectional shift registers at different levels are to work under the control of the first clock signal and second clock signal, the single spin-echo of described the first clock signal and described second clock signal;
The first reset circuit, described the first reset circuit comprises respectively and the direct impulse input end of the first order shift register of described multistage bidirectional shift register and first input end and the second input end that the reverse impulse input end is electrically connected, the the first clock control end that is connected with described second clock signal, the first reset output terminal that is electrically connected with the output terminal of described first order shift register, and low level signal end;
The second reset circuit, described the second reset circuit comprises respectively and the direct impulse input end of the afterbody shift register of described multistage bidirectional shift register and the 3rd input end and the four-input terminal that the reverse impulse input end is electrically connected, the second clock control end that is connected with described second clock signal, the second reset output terminal that is electrically connected with the output terminal of described afterbody shift register, and low level signal end;
Described first input end and described four-input terminal are used for receiving the scanning start signal.
Wherein, described the first reset circuit comprises: the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT);
The transistorized grid of described the first film and source electrode all are electrically connected with described the first clock control end;
The grid of the source electrode of the transistorized drain electrode of described the first film, described the second thin film transistor (TFT), the source electrode of described the 3rd thin film transistor (TFT) and described the 4th thin film transistor (TFT) is electrically connected mutually;
The drain electrode of the drain electrode of the drain electrode of described the second thin film transistor (TFT), described the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT) all is electrically connected with described low level signal end;
The grid of described the second thin film transistor (TFT) is electrically connected with described first input end;
The grid of described the 3rd thin film transistor (TFT) is electrically connected with described the second input end;
The source electrode of described the 4th thin film transistor (TFT) is electrically connected with described the first reset output terminal.
Wherein, described the second reset circuit comprises: the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT) and the 8th thin film transistor (TFT);
The grid of described the 5th thin film transistor (TFT) and source electrode all are electrically connected with described second clock control end;
The grid of the source electrode of the source electrode of the drain electrode of described the 5th thin film transistor (TFT), described the 6th thin film transistor (TFT), described the 7th thin film transistor (TFT) and described the 8th thin film transistor (TFT) is electrically connected mutually;
The drain electrode of the drain electrode of the drain electrode of described the 6th thin film transistor (TFT), described the 7th thin film transistor (TFT) and the 8th thin film transistor (TFT) all is electrically connected with described low level signal end;
The grid of described the 6th thin film transistor (TFT) is electrically connected with described the 3rd input end;
The grid of described the 7th thin film transistor (TFT) is electrically connected with described four-input terminal;
The source electrode of described the 8th thin film transistor (TFT) is electrically connected with described the second reset output terminal.
Wherein, all described thin film transistor (TFT)s all adopt the N-type thin film transistor (TFT).
The present invention also provides a kind of liquid crystal indicator, and described liquid crystal indicator comprises described gate driver circuit.
Wherein, described gate driver circuit is integrated on the array base palte of described liquid crystal indicator.
The present invention also provides a kind of driving method for gate drive signal is provided to the display device that comprises described gate driver circuit, and described driving method comprises:
When the forward scan carried out from first order bidirectional shift register to the afterbody bidirectional shift register, the second reset enable signal afterbody bidirectional shift register proper reset of the second reset circuit output;
When the reverse scan carried out from the afterbody bidirectional shift register to first order bidirectional shift register, the bidirectional shift register proper reset of the first reset enable signal first order of the first reset circuit output.
(3) beneficial effect
Gate driver circuit of the present invention, driving method and liquid crystal indicator, front end at first order bidirectional shift register arranges the first reset circuit, and in the end the rear end of one-level bidirectional shift register arranges the second reset circuit, utilize existing clock signal, this bidirectional shift register circuit can proper reset to first order bidirectional shift register and afterbody bidirectional shift register by the STV signal, and does not affect other output at different levels.
Description of drawings
Fig. 1 is the circuit diagram of existing bilateral scanning gate driver circuit;
Fig. 2 is the circuit diagram of the described gate driver circuit of the embodiment of the invention;
Fig. 3 is the electrical block diagram of the first reset circuit of embodiments of the invention;
Fig. 4 is the electrical block diagram of the second reset circuit of embodiments of the invention;
Fig. 5 a is the sequential chart of the described gate driver circuit of the embodiment of the invention first reset circuit when forward scan;
Fig. 5 b is the sequential chart of the described gate driver circuit of the embodiment of the invention second reset circuit when forward scan;
Fig. 6 a is the sequential chart of the described gate driver circuit of the embodiment of the invention second reset circuit when reverse scan;
Fig. 6 b is the sequential chart of the described gate driver circuit of the embodiment of the invention first reset circuit when reverse scan;
Fig. 7 is the described driving method process flow diagram that gate drive signal is provided for the display device to the gate driver circuit that comprises Fig. 2 of the embodiment of the invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for explanation the present invention, but are not used for limiting the scope of the invention.
Fig. 2 is the circuit diagram of the described gate driver circuit of the embodiment of the invention, and as shown in Figure 2, described gate driver circuit comprises:
Multistage bidirectional shift register (SR1, SR2, SRN), connect according to a kind of like this mode mutually: the reverse impulse input end INPUT_B that is input to the described bidirectional shift register of previous stage from the output signal of each bidirectional shift register output terminal OUTPUT, and be input to the direct impulse input end INPUT_F of the described bidirectional shift register of rear one-level, described bidirectional shift registers at different levels are to work under the control of the first clock signal clk and second clock signal CLKB, the single spin-echo of described the first clock signal clk and described second clock signal CLKB;
The first reset circuit RESET Unit1, described the first reset circuit RESET Unit1 comprises respectively and the direct impulse input end INPUT_F of the first order shift register SR1 of described multistage bidirectional shift register and first input end INPUT1 and the second input end INPUT2 that reverse impulse input end INPUT_B is electrically connected, the the first clock control end CLKM that is connected with described second clock signal CLKB, the the first reset output terminal OUTPUT-RESET1 that is electrically connected with the output terminal OUTPUT of described first order shift register SR1, and low level signal end VSS;
The second reset circuit RESET Unit2, described the second reset circuit RESET Unit2 comprises respectively and the direct impulse input end INPUT_F of the afterbody shift register SRN of described multistage bidirectional shift register and the 3rd input end INPUT3 and the four-input terminal INPUT4 that reverse impulse input end INPUT_B is electrically connected, the second clock control end CLKN that is connected with described second clock signal CLKB, the the second reset output terminal OUTPUT-RESET2 that is electrically connected with the output terminal OUTPUT of described afterbody shift register SRN, and low level signal end VSS;
Described first input end INPUT1 and described four-input terminal INPUT4 are used for receiving scanning start signal STV.Need to prove that all the low level signal ends among the present invention all are to represent with VSS.
The bilateral scanning gate driver circuit is by not marking among two direction of scanning control end Vd1 and Vd2(Fig. 2 in the present embodiment) the gated sweep direction.Particularly, when Vd1 is high level, when Vd2 is low level, gate driver circuit carries out the forward scan to afterbody shift register SRN by first order shift register SR1, this moment, the direct impulse input end INPUT_F of first order bidirectional shift register SR1 received scanning start signal STV, the reverse impulse input end INPUT_B of SR1 receives the output signal of second level shift register SR2, and the INPUT_B end is used as the reset signal input end of SR1 this moment; The INPUT_F end of other shift registers at different levels all is used for receiving the output signal of upper level, and the output signal that the INPUT_B termination is accepted one-level is used for shift register at the corresponding levels is resetted.
When Vd1 is low level, when Vd2 is high level, gate driver circuit carries out the reverse scan from afterbody shift register SRN to first order shift register SR1, this moment, the reverse impulse input end INPUT_B of afterbody bidirectional shift register SRN received scanning start signal STV, and the output signal that the direct impulse input end INPUT_F of SRN accepts penultimate stage shift register SRN-1 is used for the output signal of SRN is resetted; The INPUT_B end of other shift registers at different levels all is used for receiving the output signal of next stage, and the output signal that the INPUT_F termination is received upper level is used for shift register at the corresponding levels is resetted.
Fig. 3 is the electrical block diagram of described the first reset circuit of embodiments of the invention.As shown in Figure 3, described the first reset circuit comprises: the first film transistor T FT1, the second thin film transistor (TFT) TFT2, the 3rd thin film transistor (TFT) TFT3 and the 4th thin film transistor (TFT) TFT4.
Particularly, the grid of the first film transistor T FT1 and source electrode all are electrically connected with the first clock control end CLKM; The source electrode of the drain electrode of the first film transistor T FT1, the source electrode of the second thin film transistor (TFT) TFT2, the 3rd thin film transistor (TFT) TFT3 and the grid of the 4th thin film transistor (TFT) TFT4 are electrically connected mutually; The drain electrode of the drain electrode of TFT2, the drain electrode of TFT3 and TFT4 all is electrically connected with low level signal end VSS; The grid of the second thin film transistor (TFT) TFT2 is connected with first input end electricity INPUT1; The grid of the 3rd thin film transistor (TFT) TFT3 is electrically connected with the second input end INPUT2; The source electrode of the 4th thin film transistor (TFT) TFT4 is connected with the first reset output terminal electricity OUTPUT-RESET1.
Fig. 4 is the electrical block diagram of described the second reset circuit of embodiments of the invention.The second reset circuit comprises as shown in Figure 4: the 5th thin film transistor (TFT) TFT5, the 6th thin film transistor (TFT) TFT6, the 7th thin film transistor (TFT) TFT7 and the 8th thin film transistor (TFT) TFT8.
Particularly, the grid of the 5th thin film transistor (TFT) TFT5 and source electrode all are electrically connected with second clock control end CLKN; The grid of the source electrode of the source electrode of the drain electrode of the 5th thin film transistor (TFT) TFT5, the 6th thin film transistor (TFT) TFT6, the 7th thin film transistor (TFT) TFT7 and the 8th thin film transistor (TFT) TFT8 is electrically connected mutually; The drain electrode of the drain electrode of TFT6, the drain electrode of TFT7 and TFT8 all is electrically connected with low level signal end VSS; The grid of the 6th thin film transistor (TFT) TFT6 is electrically connected with the 3rd input end INPUT3; The grid of the 7th thin film transistor (TFT) TFT7 is electrically connected with four-input terminal INPUT4; The source electrode of the 8th thin film transistor (TFT) TFT8 is electrically connected with described the second reset output terminal OUTPUT-RESET2.
Preferably, the first reset circuit among the present invention and/or all thin film transistor (TFT)s in the second reset circuit all are the N-type thin film transistor (TFT)s, and need to prove that the source electrode of above-mentioned all thin film transistor (TFT)s and drain electrode can transpositions.In addition, the particular circuit configurations of the first reset circuit and the second reset circuit is not limited to the circuit structure in the embodiment of the invention, and the first reset circuit and the second reset circuit also can be other reset circuits with similar functions.
The VSS end of the VSS of the first reset circuit end and described the second reset circuit all is electrically connected mutually with the VSS end of bidirectional shift registers at different levels in the gate driver circuit of the present invention.The CLKM end of the first reset circuit and the CLKN end of the second reset circuit are used for input CLKB signal.
It is shift-register circuit among the CN201110241400.8 that the bidirectional shift register of the embodiment of the invention can adopt number of patent application.Need to prove that the circuit structure of bidirectional shift register is not limited to above-mentioned patent documentation, the according to the invention of other has the shift-register circuit of similar functions all applicable to the present invention.
Fig. 5 a is the sequential chart of the described gate driver circuit of the embodiment of the invention first reset circuit when forward scan.In Fig. 5 a, when representing forward scan, CLKB inputs the waveform of clock signal of the first clock control end CLKM of the first reset circuit, STV/INPUT1 namely represents to scan the waveform of start signal, it also is the input waveform of the first input end INPUT1 of the first reset circuit, INPUT2 represents the signal output waveform of the output terminal OUTPUT of second level bidirectional shift register SR2, OUT1 is the signal output waveform of first order bidirectional shift register SR1, the signal waveform that RESET is ordered in the first reset circuit in the RESET presentation graphs 3.Particularly, the sequential chart of Fig. 5 a is in conjunction with the circuit structure diagram of the first reset circuit of Fig. 3, at t1 in the time period, CLKB is high level, the at this moment the first film transistor T FT1 conducting in the first reset circuit among Fig. 3, STV signal and INPUT1 are high level, at this moment the second also conducting of thin film transistor (TFT) TFT2 in the first reset circuit among Fig. 3, INPUT2 is low level, OUT1 is low level, at this moment the 3rd thin film transistor (TFT) TFT3 cut-off in the first reset circuit among Fig. 3, thin film transistor (TFT) TFT1 and TFT2 want to make that the RESET point in the first reset circuit is low level among Fig. 3 this moment in this moment the first reset circuit, such the 4th thin film transistor (TFT) TFT4 cut-off, therefore inoperative to the output of first order bidirectional shift register at t1 period first reset circuit.In the t2 time period, CLKB becomes low level, the TFT1 cut-off, STV signal and INPUT1 become low level, TFT2 cut-off this moment, and INPUT2 still is low level, TFT3 this moment remain off state still, so the current potential that this moment, RESET was ordered still remains on low level, TFT4 is still cut-off.At t3 in the period, CLKB becomes high level, the TFT1 conducting, STV signal and INPUT1 still keep low level, TFT2 this moment remain off state still, INPUT2 becomes high level at this moment, TFT3 conducting this moment, and TFT1 and TFT3 want to make the current potential of ordering at the RESET of t3 in the period still keep low level, and TFT4 still is in cut-off state.In period, CLKB, STV/INPUT1, INPUT2 and OUT1 are low level at t4, and this moment, TFT1, TFT2 and TFT3 all were in cut-off state, and the RESET point current potential of this moment still remains on low level, so TFT4 also ends.Within other periods, the RESET current potential keeps high level under the control of CLKB, and this moment, TFT4 was conducting, and the output terminal of first order shift register SR1 also is electronegative potential at this moment.In sum, in Fig. 5 a, the current potential that RESET is ordered can not affect the normal output of first order bidirectional shift register, that is to say that when forward scan the first reset circuit can not affect the normal output of first order bidirectional shift register.
Fig. 5 b is the sequential chart of the described gate driver circuit of the embodiment of the invention second reset circuit when forward scan.In Fig. 5 b, when representing forward scan, CLKB inputs the waveform of clock signal of the second clock control end CLKN of the second reset circuit, STV/INPUT4 namely represents to scan the waveform of start signal, it also is the input waveform of the four-input terminal INPUT4 of the second reset circuit, INPUT3 represents penultimate stage bidirectional shift register SR(N-1) the signal output waveform of output terminal OUTPUT, OUTN is the signal output waveform of afterbody bidirectional shift register SRN, the signal waveform that RESET is ordered in the second reset circuit in the RESET presentation graphs 4.Particularly, the sequential chart of Fig. 5 b describes in conjunction with the circuit structure diagram of the second reset circuit of Fig. 4, at t5 in the time period, CLKB is high level, at this moment the 5th thin film transistor (TFT) TFT5 conducting in the second reset circuit among Fig. 4, STV signal and INPUT4 are low level, at this moment the 7th thin film transistor (TFT) TFT7 cut-off in the second reset circuit among Fig. 4, INPUT3 is high level, therefore the 6th thin film transistor (TFT) TFT6 conducting in the second reset circuit among Fig. 4, thin film transistor (TFT) TFT5 and TFT6 will satisfy and can make that the RESET point in the second reset circuit is low level among Fig. 4 this moment in this moment the second reset circuit, like this 8th thin film transistor (TFT) TFT8 cut-off this moment, therefore inoperative to the output of level bidirectional shift register last at t5 period second reset circuit.In the t6 time period, CLKB becomes low level, the TFT5 cut-off, STV signal and INPUT4 still are low level, TFT7 this moment remain off state still, and INPUT3 becomes low level, therefore TFT6 cut-off is so the current potential that this moment, RESET was ordered still remains on low level, so TFT8 is still cut-off.At t7 in the period, CLKB is high level, STV/INPUT4, INPUT3 are low level, TFT5 conducting this moment, TFT6, TFT7 all end, so this moment, the RESET point was high level, and the TFT8 conducting, the OUTPUT-RESET2 current potential of the second reset circuit is low level, so OUTN is reset to low level at this moment.In when t8, holding, CLKB becomes low level, and this moment, the RESET point still kept high level, so OUTN still keeps low level, at t9 in the period, CLKB and STV/INPUT4 are high level, and INPUT3 is low level, this moment TFT5 and TFT7 conducting, the TFT6 cut-off, this moment TFT5 and TFT7 will to satisfy the current potential that RESET order be electronegative potential, TFT8 ends like this, the output of OUTN still remains on low level; In period, CLKB and STV/INPUT4 become low level at t10, and INPUT3 still is low level, and TFT5, TFT6, TFT7 all end, and the RESET point still maintains low level, and OUTN output still is low level; Within other periods, the RESET point all is in high level under the control of CLKB, and the output of OUTN also remains on current potential always like this.Above-mentioned when the forward scan, the second reset circuit is to the explanation of the principle that resets of afterbody shift register.
Fig. 6 a is the sequential chart of the described gate driver circuit of the embodiment of the invention second reset circuit when reverse scan.In Fig. 6 a, when representing reverse scan, CLKB inputs the waveform of clock signal of the second clock control end CLKN of the second reset circuit, STV/INPUT4 namely represents to scan the waveform of start signal, it also is the input waveform of the four-input terminal INPUT4 of the second reset circuit, INPUT3 represents the waveform of the 3rd input end of the second reset circuit, also be penultimate stage bidirectional shift register SR(N-1) the signal output waveform of output terminal OUTPUT, OUTN is the signal output waveform of afterbody bidirectional shift register SRN, the signal waveform that RESET is ordered in the second reset circuit in the RESET presentation graphs 4.In this moment the second reset circuit among principle of work and Fig. 5 a of each TFT the principle of each TFT of the first reset circuit similar, concrete, the corresponding TFT1 of TFT5, the corresponding TFT2 of TFT7, the corresponding TFT3 of TFT6, the corresponding TFT4 of TFT8, concrete principle is detailed description no longer here.The situation of the first reset circuit is similar during with forward scan, and when reverse scan, the current potential that the RESET in the second reset circuit is ordered can not affect the normal output of afterbody bidirectional shift register equally.
Fig. 6 b is the sequential chart of the described gate driver circuit of the embodiment of the invention first reset circuit when reverse scan.In Fig. 6 b, when representing reverse scan, CLKB inputs the waveform of clock signal of the first clock control end CLKM of the first reset circuit, STV/INPUT1 namely represents to scan the waveform of start signal, it also is the input waveform of the first input end INPUT1 of the first reset circuit, OUT2/INPUT2 represents the signal output waveform of the output terminal OUTPUT of second level bidirectional shift register SR2, also is the input waveform of the second input end of the first reset circuit; OUT1 is the signal output waveform of first order bidirectional shift register SR1, the signal waveform that RESET is ordered in the first reset circuit in the RESET presentation graphs 3.The principle of work of the second reset circuit is similar during the at this moment principle of work of the first reset circuit and forward scan, the TFT5 of corresponding the second reset circuit of the TFT1 of the first reset circuit, the TFT7 of corresponding the second reset circuit of the TFT2 of the first reset circuit, the TFT6 of corresponding the second reset circuit of the TFT3 of the first reset circuit, the TFT8 of corresponding the second reset circuit of the TFT4 of the first reset circuit, concrete principle can with reference to the specific descriptions to Fig. 5 b, no longer describe in detail herein.Therefore the first reset circuit when reverse scan can be realized proper reset to first order bidirectional shift register.
The present invention also provides a kind of liquid crystal indicator, and described liquid crystal indicator comprises above-mentioned gate driver circuit, and preferred, described gate driver circuit is integrated on the array base palte of described liquid crystal indicator.
Fig. 7 is that the embodiment of the invention is described provides the driving method process flow diagram of gate drive signal for the display device to the gate driver circuit that comprises Fig. 2, and as shown in Figure 7, described method comprises step:
When the forward scan carried out from the first order bidirectional shift register of described multistage bidirectional shift register to the afterbody bidirectional shift register, the second reset circuit is exported the bidirectional shift register proper reset of the second reset enable signal afterbody, and the concrete principle that resets is referring to the detailed description to Fig. 5 b sequential chart.
When the reverse scan carried out from the afterbody bidirectional shift register of described multistage bidirectional shift register to first order bidirectional shift register, the first reset circuit is exported the bidirectional shift register proper reset of the first reset enable signal first order, and the concrete principle that resets is referring to the explanation to Fig. 6 b sequential chart.
The described gate driver circuit of the embodiment of the invention, driving method and liquid crystal indicator, by the front end at first order bidirectional shift register the first reset circuit is set, and in the end the rear end of one-level bidirectional shift register arranges the second reset circuit, utilize existing clock signal, this bidirectional shift register circuit can proper reset to first order bidirectional shift register and afterbody bidirectional shift register by the STV signal, and does not affect other output at different levels.
Above embodiment only is used for explanation the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; in the situation that does not break away from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (7)
1. a gate driver circuit is characterized in that, comprising:
The multistage bidirectional shift register, connect according to a kind of like this mode mutually: the reverse impulse input end that is input to the described bidirectional shift register of previous stage from the output signal of each bidirectional shift register output terminal, and be input to the direct impulse input end of the described bidirectional shift register of rear one-level, described bidirectional shift registers at different levels are to work under the control of the first clock signal and second clock signal, the single spin-echo of described the first clock signal and described second clock signal;
The first reset circuit, described the first reset circuit comprises respectively and the direct impulse input end of the first order shift register of described multistage bidirectional shift register and first input end and the second input end that the reverse impulse input end is electrically connected, the the first clock control end that is connected with described second clock signal, the first reset output terminal that is electrically connected with the output terminal of described first order shift register, and low level signal end;
The second reset circuit, described the second reset circuit comprises respectively and the direct impulse input end of the afterbody shift register of described multistage bidirectional shift register and the 3rd input end and the four-input terminal that the reverse impulse input end is electrically connected, the second clock control end that is connected with described second clock signal, the second reset output terminal that is electrically connected with the output terminal of described afterbody shift register, and low level signal end;
Described first input end and described four-input terminal are used for receiving the scanning start signal.
2. gate driver circuit as claimed in claim 1 is characterized in that, described the first reset circuit comprises: the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT);
The transistorized grid of described the first film and source electrode all are electrically connected with described the first clock control end;
The grid of the source electrode of the transistorized drain electrode of described the first film, described the second thin film transistor (TFT), the source electrode of described the 3rd thin film transistor (TFT) and described the 4th thin film transistor (TFT) is electrically connected mutually;
The drain electrode of the drain electrode of the drain electrode of described the second thin film transistor (TFT), described the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT) all is electrically connected with described low level signal end;
The grid of described the second thin film transistor (TFT) is electrically connected with described first input end;
The grid of described the 3rd thin film transistor (TFT) is electrically connected with described the second input end;
The source electrode of described the 4th thin film transistor (TFT) is electrically connected with described the first reset output terminal.
3. gate driver circuit as claimed in claim 1 is characterized in that, described the second reset circuit comprises: the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT) and the 8th thin film transistor (TFT);
The grid of described the 5th thin film transistor (TFT) and source electrode all are electrically connected with described second clock control end;
The grid of the source electrode of the source electrode of the drain electrode of described the 5th thin film transistor (TFT), described the 6th thin film transistor (TFT), described the 7th thin film transistor (TFT) and described the 8th thin film transistor (TFT) is electrically connected mutually;
The drain electrode of the drain electrode of the drain electrode of described the 6th thin film transistor (TFT), described the 7th thin film transistor (TFT) and the 8th thin film transistor (TFT) all is electrically connected with described low level signal end;
The grid of described the 6th thin film transistor (TFT) is electrically connected with described the 3rd input end;
The grid of described the 7th thin film transistor (TFT) is electrically connected with described four-input terminal;
The source electrode of described the 8th thin film transistor (TFT) is electrically connected with described the second reset output terminal.
4. gate driver circuit as claimed in claim 2 or claim 3 is characterized in that all described thin film transistor (TFT)s all adopt the N-type thin film transistor (TFT).
5. a liquid crystal indicator is characterized in that, described liquid crystal indicator comprises each described gate driver circuit of claim 1-4.
6. liquid crystal indicator as claimed in claim 5 is characterized in that, described gate driver circuit is integrated on the array base palte of described liquid crystal indicator.
7. driving method that is used for providing to the display device that comprises gate driver circuit as claimed in claim 1 gate drive signal is characterized in that described driving method comprises:
When the forward scan carried out from the first order bidirectional shift register of described multistage bidirectional shift register to the afterbody bidirectional shift register, the described afterbody bidirectional shift register of the second reset enable signal proper reset of the second reset circuit output;
When the reverse scan carried out from the afterbody bidirectional shift register of described multistage bidirectional shift register to first order bidirectional shift register, the described first order bidirectional shift register of the first reset enable signal proper reset of the first reset circuit output.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210545763.5A CN103050077B (en) | 2012-12-14 | 2012-12-14 | A kind of gate driver circuit, driving method and liquid crystal indicator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210545763.5A CN103050077B (en) | 2012-12-14 | 2012-12-14 | A kind of gate driver circuit, driving method and liquid crystal indicator |
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| Publication Number | Publication Date |
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| CN103050077A true CN103050077A (en) | 2013-04-17 |
| CN103050077B CN103050077B (en) | 2015-12-23 |
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| CN201210545763.5A Active CN103050077B (en) | 2012-12-14 | 2012-12-14 | A kind of gate driver circuit, driving method and liquid crystal indicator |
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| CN103943085A (en) * | 2014-04-02 | 2014-07-23 | 京东方科技集团股份有限公司 | Grid driving circuit, display device and driving method for zoning display |
| CN104616616A (en) * | 2015-02-12 | 2015-05-13 | 京东方科技集团股份有限公司 | Gate drive circuit, drive method of gate drive circuit, array substrate and display device |
| CN105047120A (en) * | 2015-06-30 | 2015-11-11 | 上海天马微电子有限公司 | Gate drive circuit and drive method thereof, and display device |
| WO2017076111A1 (en) * | 2015-11-06 | 2017-05-11 | 京东方科技集团股份有限公司 | Supplementary reset module, gate drive circuit, and display device |
| CN108133694A (en) * | 2018-01-26 | 2018-06-08 | 京东方科技集团股份有限公司 | Gate driving circuit, driving method and display device |
| CN109686334A (en) * | 2019-02-18 | 2019-04-26 | 京东方科技集团股份有限公司 | Gate driving circuit and its driving method and display device |
| CN111653236A (en) * | 2020-06-16 | 2020-09-11 | 厦门天马微电子有限公司 | Display device |
| WO2021232871A1 (en) * | 2020-05-22 | 2021-11-25 | 京东方科技集团股份有限公司 | Gate drive circuit, display substrate, display apparatus, and gate drive method |
| CN115206244A (en) * | 2021-04-09 | 2022-10-18 | 京东方科技集团股份有限公司 | Display panel, driving method thereof and display device |
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| CN103943085A (en) * | 2014-04-02 | 2014-07-23 | 京东方科技集团股份有限公司 | Grid driving circuit, display device and driving method for zoning display |
| CN104616616A (en) * | 2015-02-12 | 2015-05-13 | 京东方科技集团股份有限公司 | Gate drive circuit, drive method of gate drive circuit, array substrate and display device |
| CN104616616B (en) * | 2015-02-12 | 2017-12-15 | 京东方科技集团股份有限公司 | Gate driving circuit and its driving method, array base palte, display device |
| US9905155B2 (en) | 2015-02-12 | 2018-02-27 | Boe Technology Group Co., Ltd. | Gate driver circuit, its driving method, array substrate and display device |
| CN105047120B (en) * | 2015-06-30 | 2019-01-18 | 上海天马微电子有限公司 | A kind of gate driving circuit and its driving method, display device |
| CN105047120A (en) * | 2015-06-30 | 2015-11-11 | 上海天马微电子有限公司 | Gate drive circuit and drive method thereof, and display device |
| WO2017076111A1 (en) * | 2015-11-06 | 2017-05-11 | 京东方科技集团股份有限公司 | Supplementary reset module, gate drive circuit, and display device |
| US10255985B2 (en) | 2015-11-06 | 2019-04-09 | Boe Technology Group Co., Ltd. | Supplement resetting module, gate driver circuit and display device |
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| CN108133694B (en) * | 2018-01-26 | 2020-03-31 | 京东方科技集团股份有限公司 | Gate drive circuit, drive method and display device |
| CN109686334A (en) * | 2019-02-18 | 2019-04-26 | 京东方科技集团股份有限公司 | Gate driving circuit and its driving method and display device |
| CN109686334B (en) * | 2019-02-18 | 2021-01-22 | 京东方科技集团股份有限公司 | Gate drive circuit, drive method thereof and display device |
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| CN115206244A (en) * | 2021-04-09 | 2022-10-18 | 京东方科技集团股份有限公司 | Display panel, driving method thereof and display device |
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