CN104282285B - Shift-register circuit and driving method, gate driver circuit, display device - Google Patents

Shift-register circuit and driving method, gate driver circuit, display device Download PDF

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Publication number
CN104282285B
CN104282285B CN201410596879.0A CN201410596879A CN104282285B CN 104282285 B CN104282285 B CN 104282285B CN 201410596879 A CN201410596879 A CN 201410596879A CN 104282285 B CN104282285 B CN 104282285B
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film transistor
tft
thin film
nodal point
unit
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CN201410596879.0A
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CN104282285A (en
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周全国
祁小敬
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Abstract

The invention provides a kind of shift-register circuit and driving method, gate driver circuit, display device, wherein shift-register circuit includes input control unit, primary nodal point pull-up unit, primary nodal point drop-down unit, secondary nodal point pull-up unit, secondary nodal point drop-down unit, output driver element and output and drags down unit。During the work of this shift-register circuit, by in the driving time of a grid line, alternately draw high or drag down secondary nodal point, make to export and drag down being turned on and off of units alternately, not continuous firing, thus effectively prevent output to drag down the drift of thin film transistor (TFT) threshold voltage in unit, decreasing the electric leakage caused by the drift of threshold voltage, reducing the overall power of gate driver circuit。

Description

Shift-register circuit and driving method, gate driver circuit, display device

Technical field

The present invention relates to Display Technique field, particularly relate to a kind of shift-register circuit and driving method, gate driver circuit, display device。

Background technology

TFT-LCD (ThinFilmTransistorLiquidCrystalDisplay, thin-film transistor LCD device) advantage low with its running voltage, fast response time has become as absolutely main force's technology of flat panel display technology。

The gate driver circuit of TFT-LCD includes the shift register of multiple cascade, and every grade of shift register is all connected on corresponding grid line, to export gate drive signal driven grid line, and then realizes the progressive scan of gate line is driven。The cascade system of multiple shift registers is: when the input of preceding shift register is connected to the outfan of upper level shift register, the outfan of next stage shift register is connected to work as the reset terminal of preceding shift register, namely shift registers at different levels utilize upper level shift register produced output signal as the input signal of self, utilize the output signal reset signal as self of next stage shift register。

Development and consumer's demand to high image quality along with science and technology, TFT-LCD is also developing towards large scale, direction energy-conservation, frivolous, high-resolution, this requires that the gate driver circuit of TFT-LCD to have higher vertical sweep frequency, multiple TFT (ThinFilmTransistor is mainly included due to gate driver circuit, thin film transistor (TFT)), therefore it is required that TFT to have higher mobility。Oxide TFT not only mobility is high, stable performance, and homogeneity is good, technique simply easily realizes, cost is low, the circuit design of high vertical sweep frequency can be met well, but oxide TFT long-time in running order time, its threshold voltage vt h is susceptible to drift, the electric leakage causing TFT increases, and the power consumption of gate driver circuit is bigger。

Summary of the invention

For overcoming above-mentioned defect of the prior art, the technical problem to be solved is: provide a kind of shift-register circuit and driving method, gate driver circuit, display device, to reduce the power consumption of gate driver circuit。

For reaching above-mentioned purpose, the present invention adopts the following technical scheme that

A first aspect of the present invention provides a kind of shift-register circuit, including: the input control unit being connected with input signal end, for controlling the input of input signal;The primary nodal point pull-up unit being connected with the first clock signal terminal, reset signal end, described input control unit, low level power signal end and primary nodal point, for being pulled to high level by the voltage of described primary nodal point;The primary nodal point drop-down unit being connected with secondary nodal point, described low level power signal end and described primary nodal point, for being pulled down to low level by the voltage of described primary nodal point;The secondary nodal point pull-up unit being connected with described input signal end, described first clock signal terminal, described low level power signal end, high level power supply signal end and secondary nodal point, for being pulled to high level by the voltage of described secondary nodal point;The secondary nodal point drop-down unit being connected with second clock signal end, described low level power signal end and described secondary nodal point, for being pulled down to low level by the voltage of described secondary nodal point;The output driver element being connected with described primary nodal point, described high level power supply signal end and output signal end, for exporting the output signal of high level when described primary nodal point is high level;The output being connected with described secondary nodal point, described low level power signal end and described output signal end drags down unit, for the voltage of described output signal being pulled down to low level when described primary nodal point is low level;Wherein, described primary nodal point is the common port of described primary nodal point pull-up unit, described primary nodal point drop-down unit and described output driver element, and described secondary nodal point is the common port that described secondary nodal point pull-up unit, described secondary nodal point drop-down unit, described primary nodal point drop-down unit and described output drag down unit。

Preferably, described input control unit includes: the first film transistor, and the control end of described the first film transistor is all connected with described input signal end with input, and outfan is connected with described primary nodal point pull-up unit。

Preferably, described primary nodal point pull-up unit includes: the second thin film transistor (TFT), and the control end of described second thin film transistor (TFT) is connected with described first clock signal terminal, and input is connected with described input control unit, and outfan is connected with described primary nodal point;Storage electric capacity, the first end of described storage electric capacity is connected with described primary nodal point, and the second end is connected with described reset signal end;3rd thin film transistor (TFT), the control end of described 3rd thin film transistor (TFT) is connected with described reset signal end, and input is connected with described low level power signal end, and outfan is connected with the input of described second thin film transistor (TFT)。

Preferably, described primary nodal point drop-down unit includes: the 4th thin film transistor (TFT), and the control end of described 4th thin film transistor (TFT) is connected with described secondary nodal point, and input is connected with described low level power signal end, and outfan is connected with described primary nodal point。

Preferably, described secondary nodal point pull-up unit includes: the 5th thin film transistor (TFT), and the control end of described 5th thin film transistor (TFT) is connected with described input signal end, input is connected with described low level power signal end;6th thin film transistor (TFT), the control end of described 6th thin film transistor (TFT) is all connected with described high level power supply signal end with input, and outfan is connected with the outfan of described 5th thin film transistor (TFT);7th thin film transistor (TFT), the common port that the control end of described 7th thin film transistor (TFT) is connected with the outfan of described 5th thin film transistor (TFT) and the outfan of described 6th thin film transistor (TFT) is connected, and input is connected with the control end of described 6th thin film transistor (TFT);8th thin film transistor (TFT), the control end of described 8th thin film transistor (TFT) is connected with described first clock signal terminal, and input is connected with the outfan of described 7th thin film transistor (TFT), and outfan is connected with described secondary nodal point。

Preferably, described secondary nodal point drop-down unit includes: the 9th thin film transistor (TFT), and the control end of described 9th thin film transistor (TFT) is connected with described second clock signal end, and input is connected with described low level power signal end, and outfan is connected with described secondary nodal point。

Preferably, described output driver element includes: the tenth thin film transistor (TFT), and the control end of described tenth thin film transistor (TFT) is connected with described primary nodal point, and input is connected with described high level power supply signal end, and outfan is connected with described output signal end。

Preferably, described output drags down unit and includes: the 11st thin film transistor (TFT), and the control end of described 11st thin film transistor (TFT) is connected with described secondary nodal point, and input is connected with described low level power signal end, and outfan is connected with described output signal end。

A second aspect of the present invention provides the driving method of a kind of shift-register circuit, for driving above-described shift-register circuit, described driving method includes: the first stage, input signal end and second clock signal end output low level, reset signal end and the first clock signal terminal output high level, input control unit is closed, primary nodal point pull-up unit no signal exports, the voltage of primary nodal point is pulled down to low level by primary nodal point drop-down unit, output driver element is closed, secondary nodal point drop-down unit is closed, the voltage of secondary nodal point is pulled to high level by secondary nodal point pull-up unit, output drags down unit and the voltage of output signal end is pulled down to low level;Second stage, described input signal end and described second clock signal end output high level, described reset signal end and described first clock signal terminal output low level, described input control unit is opened, described primary nodal point pull-up unit no signal exports, described primary nodal point drop-down unit is closed, the voltage of described primary nodal point keeps low level, described output driver element is closed, described secondary nodal point pull-up unit no signal exports, the voltage of described secondary nodal point is pulled down to low level by described secondary nodal point drop-down unit, described output drags down unit and closes, the voltage of described output signal end keeps low level;Phase III, described input signal end and described first clock signal terminal output high level, described reset signal end and described second clock signal end output low level, described secondary nodal point pull-up unit no signal exports, described secondary nodal point drop-down unit is closed, the voltage of described secondary nodal point keeps low level, described output drags down unit and closes, described primary nodal point drop-down unit is closed, described input control unit is opened, the voltage of described primary nodal point is pulled to high level by described primary nodal point pull-up unit, the voltage of described output signal end is pulled to high level by described output driver element;Fourth stage, described input signal end and described first clock signal terminal output low level, described reset signal end and described second clock signal end output high level, described secondary nodal point pull-up unit no signal exports, the voltage of described secondary nodal point is pulled down to low level by described secondary nodal point drop-down unit, described output drags down unit and closes, described input control unit is closed, described primary nodal point drop-down unit is closed, the voltage of described primary nodal point is continued to pull up to more high level by described primary nodal point pull-up unit, described output driver element keeps the voltage of described output signal end is pulled to high level;5th stage, described input signal end and described second clock signal end output low level, described reset signal end and described first clock signal terminal output high level, described input control unit is closed, described primary nodal point pull-up unit no signal exports, the voltage of described primary nodal point is pulled down to low level by described primary nodal point drop-down unit, described output driver element is closed, described secondary nodal point drop-down unit is closed, the voltage of described secondary nodal point is pulled to high level by described secondary nodal point pull-up unit, described output drags down unit and the voltage of described output signal end is pulled down to low level;6th stage, described input signal end, described reset signal end and described first clock signal terminal output low level, described second clock signal end output high level, described input control unit is closed, described primary nodal point pull-up unit no signal exports, described primary nodal point drop-down unit is closed, described primary nodal point keeps low level, described output driver element is closed, described secondary nodal point pull-up unit no signal exports, the voltage of described secondary nodal point is pulled down to low level by described secondary nodal point drop-down unit, described output drags down unit and closes, the voltage of described output signal end keeps low level。

Preferably, described input control unit includes the first film transistor, described primary nodal point pull-up unit includes the second thin film transistor (TFT), storage electric capacity and the 3rd thin film transistor (TFT), described primary nodal point drop-down unit includes the 4th thin film transistor (TFT), described secondary nodal point pull-up unit includes the 5th thin film transistor (TFT), 6th thin film transistor (TFT), 7th thin film transistor (TFT) and the 8th thin film transistor (TFT), described secondary nodal point drop-down unit includes the 9th thin film transistor (TFT), described output driver element includes the tenth thin film transistor (TFT), described output drags down unit and includes the 11st thin film transistor (TFT), described driving method specifically includes: the first stage, described input signal end and described second clock signal end output low level, described reset signal end and described first clock signal terminal output high level, described the first film transistor, described 3rd thin film transistor (TFT), described 5th thin film transistor (TFT) and described 9th thin film transistor (TFT) are closed, described second thin film transistor (TFT), described 4th thin film transistor (TFT), described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 8th thin film transistor (TFT) are opened, the voltage of described primary nodal point is pulled down to low level, described tenth thin film transistor (TFT) cuts out, the voltage of described secondary nodal point is pulled to high level, described 11st thin film transistor (TFT) is opened, the voltage of described output signal end is pulled down to low level;Second stage, described input signal end and described second clock signal end output high level, described reset signal end and described first clock signal terminal output low level, described second thin film transistor (TFT), described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 8th thin film transistor (TFT) are closed, described the first film transistor, described 5th thin film transistor (TFT), described 6th thin film transistor (TFT) and described 9th thin film transistor (TFT) are opened, the voltage of described primary nodal point keeps low level, described tenth thin film transistor (TFT) cuts out, the voltage of described secondary nodal point is pulled down to low level, described 11st thin film transistor (TFT) cuts out, the voltage of described output signal end keeps low level;Phase III, described input signal end and described first clock signal terminal output high level, described reset signal end and described second clock signal end output low level, described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 9th thin film transistor (TFT) are closed, described the first film transistor, described second thin film transistor (TFT), described 5th thin film transistor (TFT), described 6th thin film transistor (TFT) and described 8th thin film transistor (TFT) are opened, the voltage of described secondary nodal point keeps low level, described 11st thin film transistor (TFT) cuts out, the voltage of described primary nodal point is pulled to high level, described tenth thin film transistor (TFT) is opened, the voltage of described output signal end is pulled to high level;Fourth stage, described input signal end and described first clock signal terminal output low level, described reset signal end and described second clock signal end output high level, described the first film transistor, described second thin film transistor (TFT), described 4th thin film transistor (TFT), described 5th thin film transistor (TFT) and described 8th thin film transistor (TFT) are closed, described 3rd thin film transistor (TFT), described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 9th thin film transistor (TFT) are opened, the voltage of described secondary nodal point is pulled down to low level, described 11st thin film transistor (TFT) cuts out, the voltage of described primary nodal point continues to be pulled to more high level, described tenth thin film transistor (TFT) is opened, the voltage of described output signal end keeps high level;5th stage, described input signal end and described second clock signal end output low level, described reset signal end and described first clock signal terminal output high level, described the first film transistor, described 5th thin film transistor (TFT) and described 9th thin film transistor (TFT) are closed, described second thin film transistor (TFT), described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 8th thin film transistor (TFT) are opened, the voltage of described primary nodal point is pulled down to low level, described tenth thin film transistor (TFT) cuts out, the voltage of described secondary nodal point is pulled to high level, described 11st thin film transistor (TFT) is opened, the voltage of described output signal end is pulled down to low level;6th stage, described input signal end, described reset signal end and described first clock signal terminal output low level, described second clock signal end output high level, described the first film transistor, described second thin film transistor (TFT), described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 5th thin film transistor (TFT) and described 8th thin film transistor (TFT) are closed, described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 9th thin film transistor (TFT) are opened, described primary nodal point keeps low level, described tenth thin film transistor (TFT) cuts out, the voltage of described secondary nodal point is pulled down to low level, described 11st thin film transistor (TFT) cuts out, the voltage of described output signal end keeps low level。

A third aspect of the present invention provides a kind of gate driver circuit, including: the multiple above-described shift-register circuit of cascade mutually, except first order shift-register circuit and afterbody shift-register circuit, the input signal end of every one-level shift-register circuit is connected with the output signal end of upper level shift-register circuit, and the reset signal end of every one-level shift register is connected with the output signal end of next stage shift-register circuit。

Preferably, the whole shift-register circuits included by described gate driver circuit are connected with same one end of whole grid lines of display floater all one to one。

Preferably, the half shift-register circuit of described gate driver circuit is connected with same one end of whole grid lines of display floater one to one, and second half shift-register circuit of described gate driver circuit is connected with the other end of whole grid lines of display floater one to one。

Preferably, the half shift-register circuit of described gate driver circuit is connected with same one end of the odd-numbered line grid line of display floater one to one, and second half shift-register circuit of described gate driver circuit is connected with the other end of the even number line grid line of display floater one to one。

A fourth aspect of the present invention provides a kind of display device, including above-described gate driver circuit。

In shift-register circuit provided by the present invention and driving method, gate driver circuit, display device, by in the driving time of a grid line, alternately draw high or drag down secondary nodal point, make to export and drag down being turned on and off of units alternately, not continuous firing, thus effectively prevent output to drag down the drift of thin film transistor (TFT) threshold voltage in unit, decreasing the electric leakage caused by the drift of threshold voltage, reducing the overall power of gate driver circuit。

Accompanying drawing explanation

In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings。

The structure chart of the shift-register circuit that Fig. 1 provides for the embodiment of the present invention;

The driver' s timing figure of the shift-register circuit that Fig. 2 provides for the embodiment of the present invention;

A kind of concrete structure chart of the shift-register circuit that Fig. 3 provides for the embodiment of the present invention;

The cascade graphs of monolateral single gate driver circuit driving type that Fig. 4 provides for the embodiment of the present invention;

The cascade graphs of the gate driver circuit of the dynamic type of two-sided dual-drive that Fig. 5 provides for the embodiment of the present invention;

The driver' s timing figure of monolateral single gate driver circuit driving type and the dynamic type of two-sided dual-drive that Fig. 6 provides for the embodiment of the present invention;

The cascade graphs of bilateral single gate driver circuit driving type that Fig. 7 provides for the embodiment of the present invention;

The driver' s timing figure of bilateral single gate driver circuit driving type that Fig. 8 provides for the embodiment of the present invention。

Detailed description of the invention

Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described。Obviously, described embodiment is only a part of embodiment of the present invention, rather than whole embodiments。Based on the embodiment in the present invention, all other embodiments that those of ordinary skill in the art obtain under the premise not making creative work, belong to the scope of protection of the invention。

Present embodiments provide a kind of shift-register circuit, as it is shown in figure 1, this shift register circuit includes: with the input signal end Vg_n-1 input control unit 101 being connected, for controlling to input the input of signal Vg_n-1;The primary nodal point pull-up unit 102 being connected with the first clock signal terminal CK, reset signal end Vg_n+1, input control unit 101, low level power signal end VGL and primary nodal point PU, for being pulled to high level by the voltage of primary nodal point PU;The primary nodal point drop-down unit 103 being connected with secondary nodal point PD, low level power signal end VGL and primary nodal point PU, for being pulled down to low level by the voltage of primary nodal point PU;The secondary nodal point pull-up unit 104 being connected with input signal end Vg_n-1, the first clock signal terminal CK, low level power signal end VGL, high level power supply signal end VGH and secondary nodal point PD, for being pulled to high level by the voltage of secondary nodal point PD;The secondary nodal point drop-down unit 105 being connected with second clock signal end CKB, low level power signal end VGL and secondary nodal point PD, for being pulled down to low level by the voltage of secondary nodal point PD;The output driver element 106 being connected with primary nodal point PU, high level power supply signal end VGH and output signal end Vg_n, for exporting the output signal Vg_n of high level when primary nodal point PU is high level;The output being connected with secondary nodal point PD, low level power signal end VGL and output signal end Vg_n drags down unit 107, for the voltage of output signal Vg_n being pulled down to low level when primary nodal point PU is low level;Wherein, primary nodal point PU is the common port of primary nodal point pull-up unit 102, primary nodal point drop-down unit 103 and output driver element 106, and secondary nodal point PD is the common port that secondary nodal point pull-up unit 104, secondary nodal point drop-down unit 105, primary nodal point drop-down unit 103 and output drag down unit 107。

It should be noted that, the shift-register circuit of multiple mutual cascade is included at gate driver circuit, except first and last shift-register circuit, the input signal end of middle every grade of shift-register circuit is all connected with the output signal end of upper level shift-register circuit, reset signal end is all connected with the output signal end of next stage shift-register circuit, and outfan is all connected with one end of a grid line;The input signal end of first shift-register circuit receives an initial signal STV, and the reset signal termination of last shift-register circuit receives a reset signal Reset。Therefore, if the shift-register circuit described in this enforcement is the n-th shift-register circuit, then its input signal Vg_n-1 is the output signal of (n-1)th shift-register circuit, its reset signal Vg (n+1) is the output signal of (n+1)th shift-register circuit, and its output signal is Vg_n。

It addition, the first clock signal CK and second clock signal CKB is the control signal of shift-register circuit, the two is inversion signal。High level power supply signal VGH is the access voltage of shift-register circuit, for high level;Low level power signal VGL is another access voltage of shift-register circuit, for low level。

The driving method of above-mentioned shift-register circuit includes six stages, as in figure 2 it is shown, these six stages are followed successively by:

First stage t1, input signal end Vg_n-1 and second clock signal end CKB output low level, reset signal end Vg_n+1 and the first clock signal terminal CK exports high level, input control unit 101 is closed, primary nodal point pull-up unit 102 no signal exports, the voltage of primary nodal point PU is pulled down to low level by primary nodal point drop-down unit 103, output driver element 106 is closed, secondary nodal point drop-down unit 105 is closed, the voltage of secondary nodal point PD is pulled to high level by secondary nodal point pull-up unit 104, output drags down unit 107 and the voltage of output signal end Vg_n is pulled down to low level。

Second stage t2, input signal end Vg_n-1 and second clock signal end CKB exports high level, reset signal end Vg_n+1 and the first clock signal terminal CK output low level, input control unit 101 is opened, primary nodal point pull-up unit 102 no signal exports, primary nodal point drop-down unit 103 is closed, the voltage of primary nodal point PU keeps low level, output driver element 106 is closed, secondary nodal point pull-up unit 104 no signal exports, the voltage of secondary nodal point PD is pulled down to low level by secondary nodal point drop-down unit 105, output drags down unit 107 and closes, the voltage of output signal end Vg_n keeps low level。

Phase III t3, input signal end Vg_n-1 and the first clock signal terminal CK exports high level, reset signal end Vg_n+1 and second clock signal end CKB output low level, secondary nodal point pull-up unit 104 no signal exports, secondary nodal point drop-down unit 105 is closed, the voltage of secondary nodal point PD keeps low level, output drags down unit 107 and closes, primary nodal point drop-down unit 103 is closed, input control unit 101 is opened, the voltage of primary nodal point PU is pulled to high level by primary nodal point pull-up unit 102, the voltage of output signal end Vg_n is pulled to high level by output driver element 106。

Fourth stage t4, input signal end Vg_n-1 and the first clock signal terminal CK output low level, reset signal end Vg_n+1 and second clock signal end CKB exports high level, secondary nodal point pull-up unit 104 no signal exports, the voltage of secondary nodal point PD is pulled down to low level by secondary nodal point drop-down unit 105, output drags down unit 107 and closes, input control unit 101 is closed, primary nodal point drop-down unit 103 is closed, the voltage of primary nodal point PU is continued to pull up to more high level by primary nodal point pull-up unit 102, output driver element 106 keeps the voltage by output signal end Vg_n to be pulled to high level。

5th stage t5, input signal end Vg_n-1 and second clock signal end CKB output low level, reset signal end Vg_n+1 and the first clock signal terminal CK exports high level, input control unit 101 is closed, primary nodal point pull-up unit 102 no signal exports, the voltage of primary nodal point PU is pulled down to low level by primary nodal point drop-down unit 103, output driver element 106 is closed, secondary nodal point drop-down unit 105 is closed, the voltage of secondary nodal point PD is pulled to high level by secondary nodal point pull-up unit 104, output drags down unit 107 and the voltage of output signal end Vg_n is pulled down to low level。

6th stage t6, input signal end Vg_n-1, reset signal end Vg_n+1 and the first clock signal terminal CK output low level, second clock signal end CKB exports high level, input control unit 101 is closed, primary nodal point pull-up unit 102 no signal exports, primary nodal point drop-down unit 103 is closed, primary nodal point PU keeps low level, output driver element 106 is closed, secondary nodal point pull-up unit 104 no signal exports, the voltage of secondary nodal point PD is pulled down to low level by secondary nodal point drop-down unit 105, output drags down unit 107 and closes, the voltage of output signal end Vg_n keeps low level。

Can be obtained by above-mentioned shift register circuit and driving method thereof, under ensureing the output signal end Vg_n premise exporting signal on request, in whole driving process, the voltage of secondary nodal point PD is drawn high by alternating or dragged down, namely output drags down that unit 107 is alternating to be turned on and off, therefore output drags down that thin film transistor (TFT) included by unit 107 is alternating to be turned on and off, can't be in running order for a long time, avoiding problems due to the problem of long-time in running order caused thin film transistor (TFT) threshold voltage shift, thus decreasing the electric leakage that threshold voltage shift causes, reduce the overall power of the gate driver circuit including shift-register circuit。

The structure that implements of each functional unit of shift-register circuit below the present embodiment provided is illustrated。As it is shown on figure 3, input control unit 101 comprises the steps that the first film transistor T1, the control end of this first film transistor T1 is all connected with input signal end Vg_n-1 with input, and outfan is connected with single 102 yuan of primary nodal point pull-up。

Primary nodal point pull-up unit 102 comprises the steps that the second thin film transistor (TFT) T2, the control end of this second thin film transistor (TFT) T2 and the first clock signal terminal CK are connected, input is connected with input control unit 102, being can be connected with the outfan of the first film transistor T1 more specifically, outfan is connected with primary nodal point PU;Storage electric capacity Cst, first end of this storage electric capacity Cst is connected with primary nodal point PU, and the second end is connected with reset signal end Vg_n+1;3rd thin film transistor (TFT) T3, the control end of the 3rd thin film transistor (TFT) T3 is connected with reset signal end Vg_n+1, and input is connected with low level power signal end VGL, and the input of outfan and the second thin film transistor (TFT) T2 is connected。

Primary nodal point drop-down unit 103 comprises the steps that the 4th thin film transistor (TFT) T4, and the control end of the 4th thin film transistor (TFT) T4 is connected with secondary nodal point PD, and input is connected with low level power signal end VGL, and outfan is connected with primary nodal point PD。

Secondary nodal point pull-up unit 104 comprises the steps that the 5th thin film transistor (TFT) T5, and signal end Vg_n-1's control end of the 5th thin film transistor (TFT) T5 is connected, input is connected with low level power signal end VGL with input;6th thin film transistor (TFT) T6, the control end of the 6th thin film transistor (TFT) T6 and input are all connected with high level power supply signal end VGH, and the outfan of outfan and the 5th thin film transistor (TFT) T5 is connected;The common port that the outfan controlling end and the 5th thin film transistor (TFT) T5 of the 7th thin film transistor (TFT) T7, the 7th thin film transistor (TFT) T7 and the outfan of the 6th thin film transistor (TFT) T6 are connected is connected, and the control end of input and the 6th thin film transistor (TFT) T6 is connected;The control end of the 8th thin film transistor (TFT) T8, the 8th thin film transistor (TFT) T8 and the first clock signal terminal CK are connected, and the outfan of input and the 7th thin film transistor (TFT) T7 is connected, and outfan is connected with secondary nodal point PD。

Secondary nodal point drop-down unit 105 comprises the steps that the 9th thin film transistor (TFT) T9, and the control end of the 9th thin film transistor (TFT) T9 is connected with second clock signal end CKB, and input is connected with low level power signal end VGL, and outfan is connected with secondary nodal point PD。

Output driver element 106 comprises the steps that the tenth thin film transistor (TFT) T10, and the control end of the tenth thin film transistor (TFT) T10 is connected with primary nodal point PU, and input is connected with high level power supply signal end VGH, and outfan is connected with output signal end Vg_n。

Output drags down unit 107 and comprises the steps that the 11st thin film transistor (TFT) T11, and the control end of the 11st thin film transistor (TFT) T11 is connected with secondary nodal point PD, and input is connected with low level power signal end VGL, and outfan is connected with output signal end Vg_n。

Referring to Fig. 2, the driving process of the shift-register circuit of above-mentioned concrete structure can be as follows:

First stage t1, input signal end Vg_n-1 and second clock signal end CKB output low level, reset signal end Vg_n+1 and the first clock signal terminal CK exports high level, the first film transistor T1 and the three thin film transistor (TFT) T3 closes, second thin film transistor (TFT) T2 opens, primary nodal point pull-up unit 102 no signal exports, 5th thin film transistor (TFT) T5 closes, 6th thin film transistor (TFT) T6, 7th thin film transistor (TFT) T7 and the eight thin film transistor (TFT) T8 opens, the voltage of secondary nodal point PD is pulled to high level, 11st thin film transistor (TFT) T11 opens, the voltage of output signal end Vg_n is pulled down to low level, 4th thin film transistor (TFT) T4 opens simultaneously, the voltage of primary nodal point PU is pulled down to low level, tenth thin film transistor (TFT) T10 closes。It should be noted that this first stage t1's act as the voltage amplitude utilizing reset signal Vg_n+1 to primary nodal point PU, this point voltage is made to reset。

Second stage t2, input signal end Vg_n-1 and second clock signal end CKB exports high level, reset signal end Vg_n+1 and the first clock signal terminal CK output low level, 5th thin film transistor (TFT) T5 and the six thin film transistor (TFT) T6 opens, 7th thin film transistor (TFT) T7 and the eight thin film transistor (TFT) T8 closes, secondary nodal point pull-up unit 104 no signal exports, 9th thin film transistor (TFT) T9 opens, the voltage of secondary nodal point PD is pulled down to low level, 11st thin film transistor (TFT) T11 closes, 4th thin film transistor (TFT) T4 closes simultaneously, the first film transistor T1 opens, second thin film transistor (TFT) T2, described 3rd thin film transistor (TFT) T3 closes, primary nodal point pull-up unit 102 no signal exports, thus primary nodal point PU is in floating state, continue to keep low level, tenth thin film transistor (TFT) T10 closes, the voltage of output signal end Vg_n keeps low level。It should be noted that this second stage t2's act as the voltage floating making primary nodal point PU, it is charged drawing high this point voltage for subsequent charge electric capacity Cst and prepares。

Phase III t3, input signal end Vg_n-1 and the first clock signal terminal CK exports high level, reset signal end Vg_n+1 and second clock signal end CKB output low level, the first film transistor T1 and the second thin film transistor (TFT) T2 opens, 3rd thin film transistor (TFT) T3 closes, primary nodal point pull-up unit 102 exports high level, the voltage of primary nodal point PU is pulled to high level, tenth thin film transistor (TFT) T10 opens, the voltage of output signal end Vg_n is pulled to high level, 5th thin film transistor (TFT) T5, 6th thin film transistor (TFT) T6 and the eight thin film transistor (TFT) T8 opens, 7th thin film transistor (TFT) T7 closes, secondary nodal point pull-up unit 104 no signal exports, 9th thin film transistor (TFT) T9 closes, thus secondary nodal point PD is in floating state, continue to low level, 11st thin film transistor (TFT) T11 closes, 4th thin film transistor (TFT) T4 closes simultaneously。It should be noted that in this phase III t3, charging capacitor Cst carries out first time charging, the voltage of primary nodal point PU is carried out first time pull-up。

Fourth stage t4, input signal end Vg_n-1 and the first clock signal terminal CK output low level, reset signal end Vg_n+1 and second clock signal end CKB exports high level, 5th thin film transistor (TFT) T5 and the eight thin film transistor (TFT) T8 closes, 6th thin film transistor (TFT) T6 and the seven thin film transistor (TFT) T7 opens, secondary nodal point pull-up unit 104 no signal exports, 9th thin film transistor (TFT) T9 opens, the voltage of secondary nodal point PD is pulled down to low level, 11st thin film transistor (TFT) T11 closes, 4th thin film transistor (TFT) T4 closes simultaneously, and the first film transistor T1 and the second thin film transistor (TFT) T2 closes, 3rd thin film transistor (TFT) T3 and opening, primary nodal point pull-up unit 102 no signal exports, thus secondary nodal point PU is in floating state, its voltage is pulled to more high level, tenth thin film transistor (TFT) T10 opens, the voltage of output signal end Vg_n keeps high level。It should be noted that in this fourth stage t4, after secondary nodal point PU is in floating state, due to the electric capacity bootstrap effect of charging capacitor Cst, charging capacitor Cst can carry out second time charging, and the voltage of secondary nodal point PU carries out second time pull-up。

5th stage t5, input signal end Vg_n-1 and second clock signal end CKB output low level, reset signal end Vg_n+1 and the first clock signal terminal CK exports high level, the first film transistor T1 closes, second thin film transistor (TFT) T2 and the three thin film transistor (TFT) T3 opens, primary nodal point pull-up unit 102 no signal exports, 5th thin film transistor (TFT) T5 closes, 6th thin film transistor (TFT) T6, 7th thin film transistor (TFT) T7 and the eight thin film transistor (TFT) T8 opens, the voltage of secondary nodal point PD is pulled to high level by secondary nodal point pull-up unit 104, 11st thin film transistor (TFT) T11 opens, output signal end Vg_n output low level, 4th thin film transistor (TFT) T4 opens simultaneously, the voltage of primary nodal point PU is pulled down to low level, tenth thin film transistor (TFT) T10 closes。

6th stage t6, input signal end Vg_n-1, reset signal end Vg_n+1 and the first clock signal terminal CK output low level, second clock signal end CKB exports high level, the first film transistor T1, second thin film transistor (TFT) T2 and the three thin film transistor (TFT) T3 closes, primary nodal point pull-up unit 102 no signal exports, 5th thin film transistor (TFT) T5 and the eight thin film transistor (TFT) T8 closes, 6th thin film transistor (TFT) T6 and the seven thin film transistor (TFT) T7 opens, secondary nodal point pull-up unit 104 no signal exports, 9th thin film transistor (TFT) T9 opens, thus the voltage of secondary nodal point PD is pulled down to low level, 11st thin film transistor (TFT) T11 closes, 4th thin film transistor (TFT) T4 opens simultaneously, primary nodal point PU keeps low level, tenth thin film transistor (TFT) T10 closes, the voltage of output signal end Vg_n keeps low level。It should be noted that the output acting as the low level voltage maintaining output signal end Vg_n of the 6th stage t6。

Through first stage t1~the 6th stage t6, in the driving time of a grid line of a frame, output signal end Vg_n exports the high level pulse signal that a persistent period is t3+t4, this high level pulse signal is output to the grid line being connected with this grade of shift-register circuit, thus completing the driving to this grid line。Repeat first stage t1~the 6th stage t6 driving that namely can complete this article of grid line of next frame。

Can will become apparent from from above-mentioned driving process, the voltage of secondary nodal point PD is drawn high by alternating or dragged down, so that being turned on and off by alternating as exporting the 11st thin film transistor (TFT) T11 dragging down unit 107, duty can't be continuously in, decrease electric leakage, reduce the overall power of shift-register circuit。

In addition, it is necessary to it is noted that relative to shift-register circuit of the prior art, also there is simple in construction, drive that difficulty is low, the advantage of easy realization of the shift-register circuit that provides of the present embodiment。

Based on above-mentioned shift-register circuit, the present embodiment additionally provides a kind of gate driver circuit, including: the shift-register circuit that multiple the present embodiment of cascade provide mutually, except first order shift-register circuit and afterbody shift-register circuit, the input signal end of every one-level shift-register circuit is connected with the output signal end of upper level shift-register circuit, and the reset signal end of every one-level shift register is connected with the output signal end of next stage shift-register circuit;The input signal end of first order shift-register circuit accepts an original input signal, and the reset signal termination of afterbody shift-register circuit receives a reset signal。

Owing to have employed the shift-register circuit of the low-power consumption that the present embodiment provides, therefore the overall power of above-mentioned gate driver circuit is also reduced by。

The gate driver circuit that the present embodiment provides preferably can drive type for monolateral list, as shown in Figure 4, wherein SR1~SRn is n shift-register circuit included by gate driver circuit, A/A is the active area of display floater, GL1~GLn is the n bar grid line included by display floater, STV is the input signal of first order shift-register circuit SR1, Reset is the reset signal of n-th grade of shift-register circuit SRn, whole shift-register circuit SR1~SRn included by gate driver circuit is connected with same one end of whole grid line GL1~GLn of display floater all one to one, thus register circuit completes the driving work of a grid line。The gate driver circuit of this kind of cascade system is only located at one end of display floater, the over all Integration Du Genggao of circuit。

The gate driver circuit that the present embodiment provides preferably also can for the dynamic type of two-sided dual-drive, as shown in Figure 5, gate driver circuit includes two parts, every part includes n shift-register circuit SR1~SRn, namely 2n shift-register circuit is included altogether, STV is the input signal of the first order shift-register circuit SR1 in two parts, Reset is the reset signal of n-th grade of shift-register circuit SRn in two parts, the half shift-register circuit SR1~SRn of this gate driver circuit is connected with same one end of whole grid line GL1~GLn one to one, second half shift-register circuit SR1~SRn is connected with the other end of whole grid line GL1~GLn one to one。Two parts of the gate driver circuit of this kind of cascade system lay respectively at the two ends that display floater is relative, thus the driving work of every grid line is completed jointly by two shift-register circuits, two shift-register circuits are simultaneously from the two ends driven grid line of grid line, actuating speed can be greatly enhanced, reduce signal delay, therefore adopt the gate driver circuit of above-mentioned cascade structure to be particularly suited for large-sized display floater。

It should be noted that every type of drive partly that the gate driver circuit that monolateral single gate driver circuit driving type moves type with two-sided dual-drive is positioned at display floater two ends is identical, driver' s timing figure can be as shown in Figure 6。

The gate driver circuit that the present embodiment provides preferably also can drive type for bilateral list, as shown in Figure 7, gate driver circuit includes two parts, every part includes n shift-register circuit SR1~SRn, namely 2n shift-register circuit is included altogether, half shift-register circuit SR1~SRn one to one with the odd-numbered line grid line GL1 of display floater, GL3, GL5, ..., same one end of GLn-1 is connected, subject clock signal CK1, the control of CKB1, second half shift-register circuit one to one with the other end GL2 of even number line grid line, GL4, GL6, ..., GLn is connected, subject clock signal CK2, the control of CKB2, STV1 is the input signal of the first order shift-register circuit SR1 being connected with odd-numbered line grid line, STV2 is the input signal of the first order shift-register circuit SR1 being connected with even number line grid line, Reset1 is the reset signal of the n-th grade of shift-register circuit SRn being connected with odd-numbered line grid line, Reset2 is the reset signal of the n-th grade of shift-register circuit SRn being connected with even number line grid line。Two parts of the gate driver circuit of this kind of cascade system are positioned at the two ends that display floater is relative, the shift-register circuit of one end completes the driving work of odd-numbered line grid line, the shift-register circuit of the other end completes the driving work of even number line grid line, be equivalent to the shift-register circuit by being originally entirely located in display floater the same side in monolateral single gate driver circuit driving type separately to the two ends of display floater, thus display floater rim area is changed into, by the original frame being entirely located in same one end, the frame being positioned at two ends for the periphery circuit connecting gate driver circuit, the complexity making display floater rim area periphery circuit reduces, be conducive to the narrow frame of display floater。

It should be noted that, bilateral single gate driver circuit gate driver circuit relative to monolateral single driving type and the dynamic type of two-sided dual-drive driving type, many an original input signal, reset signals, also needing to accordingly increase by one group of clock signal (CK2 and CKB2), its driver' s timing figure can be as shown in Figure 8。

Additionally, based on above-mentioned gate driver circuit, the present embodiment also provides for a kind of display device, this display device includes above-mentioned gate driver circuit, shift-register circuit included by the gate driver circuit in the present embodiment has the advantage of low-power consumption, the advantage that the display device that therefore the present embodiment provides also has low-power consumption。

It should be noted that, the display device that the present embodiment provides can be liquid crystal panel, Electronic Paper or OLED (OrganicLight-EmittingDiode, Organic Light Emitting Diode) panel, it is applied to any product with display function or the parts such as mobile phone, panel computer, television set, display, notebook computer, DPF, navigator。

The foregoing is only the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; any those familiar with the art in the technical scope that the invention discloses, the change that can readily occur in or replacement, all should be encompassed within protection scope of the present invention。Therefore, protection scope of the present invention should be as the criterion with described scope of the claims。

Claims (15)

1. a shift-register circuit, it is characterised in that including:
The input control unit being connected with input signal end, for controlling the input of input signal;
The primary nodal point pull-up unit being connected with the first clock signal terminal, reset signal end, described input control unit, low level power signal end and primary nodal point, for being pulled to high level by the voltage of described primary nodal point;
The primary nodal point drop-down unit being connected with secondary nodal point, described low level power signal end and described primary nodal point, for being pulled down to low level by the voltage of described primary nodal point;
The secondary nodal point pull-up unit being connected with described input signal end, described first clock signal terminal, described low level power signal end, high level power supply signal end and secondary nodal point, for being pulled to high level by the voltage of described secondary nodal point;
The secondary nodal point drop-down unit being connected with second clock signal end, described low level power signal end and described secondary nodal point, for being pulled down to low level by the voltage of described secondary nodal point;
The output driver element being connected with described primary nodal point, described high level power supply signal end and output signal end, for exporting the output signal of high level when described primary nodal point is high level;
The output being connected with described secondary nodal point, described low level power signal end and described output signal end drags down unit, for the voltage of described output signal being pulled down to low level when described primary nodal point is low level;
Wherein, described primary nodal point is the common port of described primary nodal point pull-up unit, described primary nodal point drop-down unit and described output driver element, and described secondary nodal point is the common port that described secondary nodal point pull-up unit, described secondary nodal point drop-down unit, described primary nodal point drop-down unit and described output drag down unit。
2. shift-register circuit according to claim 1, it is characterized in that, described input control unit includes: the first film transistor, and the control end of described the first film transistor is all connected with described input signal end with input, and outfan is connected with described primary nodal point pull-up unit。
3. shift-register circuit according to claim 1, it is characterised in that described primary nodal point pull-up unit includes:
Second thin film transistor (TFT), the control end of described second thin film transistor (TFT) is connected with described first clock signal terminal, and input is connected with described input control unit, and outfan is connected with described primary nodal point;
Storage electric capacity, the first end of described storage electric capacity is connected with described primary nodal point, and the second end is connected with described reset signal end;
3rd thin film transistor (TFT), the control end of described 3rd thin film transistor (TFT) is connected with described reset signal end, and input is connected with described low level power signal end, and outfan is connected with the input of described second thin film transistor (TFT)。
4. shift-register circuit according to claim 1, it is characterized in that, described primary nodal point drop-down unit includes: the 4th thin film transistor (TFT), the control end of described 4th thin film transistor (TFT) is connected with described secondary nodal point, input is connected with described low level power signal end, and outfan is connected with described primary nodal point。
5. shift-register circuit according to claim 1, it is characterised in that described secondary nodal point pull-up unit includes:
5th thin film transistor (TFT), the control end of described 5th thin film transistor (TFT) is connected with described input signal end, input is connected with described low level power signal end;
6th thin film transistor (TFT), the control end of described 6th thin film transistor (TFT) is all connected with described high level power supply signal end with input, and outfan is connected with the outfan of described 5th thin film transistor (TFT);
7th thin film transistor (TFT), the common port that the control end of described 7th thin film transistor (TFT) is connected with the outfan of described 5th thin film transistor (TFT) and the outfan of described 6th thin film transistor (TFT) is connected, and input is connected with the control end of described 6th thin film transistor (TFT);
8th thin film transistor (TFT), the control end of described 8th thin film transistor (TFT) is connected with described first clock signal terminal, and input is connected with the outfan of described 7th thin film transistor (TFT), and outfan is connected with described secondary nodal point。
6. shift-register circuit according to claim 1, it is characterized in that, described secondary nodal point drop-down unit includes: the 9th thin film transistor (TFT), the control end of described 9th thin film transistor (TFT) is connected with described second clock signal end, input is connected with described low level power signal end, and outfan is connected with described secondary nodal point。
7. shift-register circuit according to claim 1, it is characterized in that, described output driver element includes: the tenth thin film transistor (TFT), the control end of described tenth thin film transistor (TFT) is connected with described primary nodal point, input is connected with described high level power supply signal end, and outfan is connected with described output signal end。
8. shift-register circuit according to claim 1, it is characterized in that, described output drags down unit and includes: the 11st thin film transistor (TFT), the control end of described 11st thin film transistor (TFT) is connected with described secondary nodal point, input is connected with described low level power signal end, and outfan is connected with described output signal end。
9. the driving method of a shift-register circuit, it is characterised in that for driving the shift-register circuit described in any one of claim 1~8, described driving method includes:
First stage, input signal end and second clock signal end output low level, reset signal end and the first clock signal terminal output high level, input control unit is closed, and primary nodal point pull-up unit no signal exports, and the voltage of primary nodal point is pulled down to low level by primary nodal point drop-down unit, output driver element is closed, secondary nodal point drop-down unit is closed, and the voltage of secondary nodal point is pulled to high level by secondary nodal point pull-up unit, and output drags down unit and the voltage of output signal end is pulled down to low level;
Second stage, described input signal end and described second clock signal end output high level, described reset signal end and described first clock signal terminal output low level, described input control unit is opened, described primary nodal point pull-up unit no signal exports, described primary nodal point drop-down unit is closed, the voltage of described primary nodal point keeps low level, described output driver element is closed, described secondary nodal point pull-up unit no signal exports, the voltage of described secondary nodal point is pulled down to low level by described secondary nodal point drop-down unit, described output drags down unit and closes, the voltage of described output signal end keeps low level;
Phase III, described input signal end and described first clock signal terminal output high level, described reset signal end and described second clock signal end output low level, described secondary nodal point pull-up unit no signal exports, described secondary nodal point drop-down unit is closed, the voltage of described secondary nodal point keeps low level, described output drags down unit and closes, described primary nodal point drop-down unit is closed, described input control unit is opened, the voltage of described primary nodal point is pulled to high level by described primary nodal point pull-up unit, the voltage of described output signal end is pulled to high level by described output driver element;
Fourth stage, described input signal end and described first clock signal terminal output low level, described reset signal end and described second clock signal end output high level, described secondary nodal point pull-up unit no signal exports, the voltage of described secondary nodal point is pulled down to low level by described secondary nodal point drop-down unit, described output drags down unit and closes, described input control unit is closed, described primary nodal point drop-down unit is closed, the voltage of described primary nodal point is continued to pull up to more high level by described primary nodal point pull-up unit, described output driver element keeps the voltage of described output signal end is pulled to high level;
5th stage, described input signal end and described second clock signal end output low level, described reset signal end and described first clock signal terminal output high level, described input control unit is closed, described primary nodal point pull-up unit no signal exports, the voltage of described primary nodal point is pulled down to low level by described primary nodal point drop-down unit, described output driver element is closed, described secondary nodal point drop-down unit is closed, the voltage of described secondary nodal point is pulled to high level by described secondary nodal point pull-up unit, described output drags down unit and the voltage of described output signal end is pulled down to low level;
6th stage, described input signal end, described reset signal end and described first clock signal terminal output low level, described second clock signal end output high level, described input control unit is closed, described primary nodal point pull-up unit no signal exports, described primary nodal point drop-down unit is closed, described primary nodal point keeps low level, described output driver element is closed, described secondary nodal point pull-up unit no signal exports, the voltage of described secondary nodal point is pulled down to low level by described secondary nodal point drop-down unit, described output drags down unit and closes, the voltage of described output signal end keeps low level。
10. the driving method of shift-register circuit according to claim 9, it is characterized in that, described input control unit includes the first film transistor, described primary nodal point pull-up unit includes the second thin film transistor (TFT), storage electric capacity and the 3rd thin film transistor (TFT), described primary nodal point drop-down unit includes the 4th thin film transistor (TFT), described secondary nodal point pull-up unit includes the 5th thin film transistor (TFT), 6th thin film transistor (TFT), 7th thin film transistor (TFT) and the 8th thin film transistor (TFT), described secondary nodal point drop-down unit includes the 9th thin film transistor (TFT), described output driver element includes the tenth thin film transistor (TFT), described output drags down unit and includes the 11st thin film transistor (TFT), described driving method specifically includes:
First stage, described input signal end and described second clock signal end output low level, described reset signal end and described first clock signal terminal output high level, described the first film transistor, described 3rd thin film transistor (TFT), described 5th thin film transistor (TFT) and described 9th thin film transistor (TFT) are closed, described second thin film transistor (TFT), described 4th thin film transistor (TFT), described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 8th thin film transistor (TFT) are opened, the voltage of described primary nodal point is pulled down to low level, described tenth thin film transistor (TFT) cuts out, the voltage of described secondary nodal point is pulled to high level, described 11st thin film transistor (TFT) is opened, the voltage of described output signal end is pulled down to low level;
Second stage, described input signal end and described second clock signal end output high level, described reset signal end and described first clock signal terminal output low level, described second thin film transistor (TFT), described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 8th thin film transistor (TFT) are closed, described the first film transistor, described 5th thin film transistor (TFT), described 6th thin film transistor (TFT) and described 9th thin film transistor (TFT) are opened, the voltage of described primary nodal point keeps low level, described tenth thin film transistor (TFT) cuts out, the voltage of described secondary nodal point is pulled down to low level, described 11st thin film transistor (TFT) cuts out, the voltage of described output signal end keeps low level;
Phase III, described input signal end and described first clock signal terminal output high level, described reset signal end and described second clock signal end output low level, described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 9th thin film transistor (TFT) are closed, described the first film transistor, described second thin film transistor (TFT), described 5th thin film transistor (TFT), described 6th thin film transistor (TFT) and described 8th thin film transistor (TFT) are opened, the voltage of described secondary nodal point keeps low level, described 11st thin film transistor (TFT) cuts out, the voltage of described primary nodal point is pulled to high level, described tenth thin film transistor (TFT) is opened, the voltage of described output signal end is pulled to high level;
Fourth stage, described input signal end and described first clock signal terminal output low level, described reset signal end and described second clock signal end output high level, described the first film transistor, described second thin film transistor (TFT), described 4th thin film transistor (TFT), described 5th thin film transistor (TFT) and described 8th thin film transistor (TFT) are closed, described 3rd thin film transistor (TFT), described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 9th thin film transistor (TFT) are opened, the voltage of described secondary nodal point is pulled down to low level, described 11st thin film transistor (TFT) cuts out, the voltage of described primary nodal point continues to be pulled to more high level, described tenth thin film transistor (TFT) is opened, the voltage of described output signal end keeps high level;
5th stage, described input signal end and described second clock signal end output low level, described reset signal end and described first clock signal terminal output high level, described the first film transistor, described 5th thin film transistor (TFT) and described 9th thin film transistor (TFT) are closed, described second thin film transistor (TFT), described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 8th thin film transistor (TFT) are opened, the voltage of described primary nodal point is pulled down to low level, described tenth thin film transistor (TFT) cuts out, the voltage of described secondary nodal point is pulled to high level, described 11st thin film transistor (TFT) is opened, the voltage of described output signal end is pulled down to low level;
6th stage, described input signal end, described reset signal end and described first clock signal terminal output low level, described second clock signal end output high level, described the first film transistor, described second thin film transistor (TFT), described 3rd thin film transistor (TFT), described 4th thin film transistor (TFT), described 5th thin film transistor (TFT) and described 8th thin film transistor (TFT) are closed, described 6th thin film transistor (TFT), described 7th thin film transistor (TFT) and described 9th thin film transistor (TFT) are opened, described primary nodal point keeps low level, described tenth thin film transistor (TFT) cuts out, the voltage of described secondary nodal point is pulled down to low level, described 11st thin film transistor (TFT) cuts out, the voltage of described output signal end keeps low level。
11. a gate driver circuit, it is characterized in that, including: multiple shift-register circuits as described in any one of claim 1~8 of cascade mutually, except first order shift-register circuit and afterbody shift-register circuit, the input signal end of every one-level shift-register circuit is connected with the output signal end of upper level shift-register circuit, and the reset signal end of every one-level shift register is connected with the output signal end of next stage shift-register circuit。
12. gate driver circuit according to claim 11, it is characterised in that the whole shift-register circuits included by described gate driver circuit are connected with same one end of whole grid lines of display floater all one to one。
13. gate driver circuit according to claim 11, it is characterized in that, the half shift-register circuit of described gate driver circuit is connected with same one end of whole grid lines of display floater one to one, and second half shift-register circuit of described gate driver circuit is connected with the other end of whole grid lines of display floater one to one。
14. gate driver circuit according to claim 11, it is characterized in that, the half shift-register circuit of described gate driver circuit is connected with same one end of the odd-numbered line grid line of display floater one to one, and second half shift-register circuit of described gate driver circuit is connected with the other end of the even number line grid line of display floater one to one。
15. a display device, it is characterised in that include the gate driver circuit described in any one of claim 11~14。
CN201410596879.0A 2014-10-29 2014-10-29 Shift-register circuit and driving method, gate driver circuit, display device CN104282285B (en)

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