CN109817153A - Drive element of the grid, grid drive method, gate driving circuit and display device - Google Patents
Drive element of the grid, grid drive method, gate driving circuit and display device Download PDFInfo
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- CN109817153A CN109817153A CN201910301068.6A CN201910301068A CN109817153A CN 109817153 A CN109817153 A CN 109817153A CN 201910301068 A CN201910301068 A CN 201910301068A CN 109817153 A CN109817153 A CN 109817153A
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Abstract
The present invention provides a kind of drive element of the grid, grid drive method, gate driving circuit and display device.The drive element of the grid includes pull-up node reset circuit, pull-up node pull-down circuit and control circuit；The control circuit is used in output stage, the gate source voltage of the transistor connecting with pull-up node in the pull-up node reset circuit is controlled in the first predetermined voltage range, and controls the gate source voltage of the transistor connecting with pull-up node in the pull-up node pull-down circuit in the second predetermined voltage range.The present invention can keep well the current potential of pull-up node in output stage, guarantee the driving capability of drive element of the grid.
Description
Technical field
The present invention relates to display actuation techniques field more particularly to a kind of drive element of the grid, grid drive method, grids
Driving circuit and display device.
Background technique
Existing drive element of the grid at work, when the pulse signal of input terminal arrives, charges for pull-up node, with
When the current potential of input signal is set low afterwards, the current potential of pull-up node is kept, when the row clock signal arrives, since bootstrapping is made
With the current potential of pull-up node is further pulled up.However it is true this during, due to the crystalline substance being electrically connected with pull-up node
Body pipe is numerous, and in existing GOA (Gate On Array, the gate driving circuit being set in array substrate) architecture design
In the case of, the gate source voltage Vgs for the transistor connecting with pull-up node is generally in 0V or more (using the transistor as N-shaped crystal
For pipe), so the current potential decline of pull-up node caused by the leakage current of the transistor be can not ignore.The current potential of pull-up node
Height directly determines whether the unlatching of output transistor is abundant, and the current potential decline of pull-up node just directly results in the output crystal
The fan-out capability of pipe declines, it cannot be guaranteed that the driving capability of drive element of the grid.
Summary of the invention
The main purpose of the present invention is to provide a kind of drive element of the grid, grid drive method, gate driving circuit and
Display device, solving in the prior art can not be in the current potential of output stage maintenance pull-up node, thus it cannot be guaranteed that gate driving
The problem of driving capability of unit.
In order to achieve the above object, the present invention provides a kind of drive element of the grid, including pull-up node reset circuit, on
Draw node pull-down circuit and control circuit；
The control circuit is used to control connecting with pull-up node in the pull-up node reset circuit in output stage
Transistor gate source voltage in the first predetermined voltage range, and control in the pull-up node pull-down circuit with pull-up save
The gate source voltage of the transistor of point connection is in the second predetermined voltage range.
When implementation, the transistor connecting with pull-up node in the pull-up node reset circuit is n-type transistor, described
First predetermined voltage range is less than or equal to 0；Alternatively,
The transistor connecting with pull-up node in the pull-up node reset circuit is p-type transistor, and described first is pre-
Constant voltage range is more than or equal to 0.
When implementation, the transistor connecting with pull-up node in the pull-up node pull-down circuit is n-type transistor, described
Second predetermined voltage range is less than or equal to 0；Alternatively,
The transistor connecting with pull-up node in the pull-up node pull-down circuit is p-type transistor, and described second is pre-
Constant voltage range is more than or equal to 0.
When implementation, the pull-up node reset circuit includes pull-up node reset transistor；
The control electrode of the pull-up node reset transistor is connect with reset terminal, and the of the pull-up node reset transistor
One pole is connect with the pull-up node, and the second pole of the pull-up node reset transistor is connect with first voltage end；
The control circuit includes circuit for providing voltage；
The circuit for providing voltage is used to provide first voltage to the first voltage end, so that in output stage, it should
The gate source voltage of pull-up node reset transistor is in the first predetermined voltage range.
When implementation, the pull-up node pull-down circuit includes pull-up node pull-down transistor；
The control electrode of the pull-up node pull-down transistor is connect with pull-down node, the pull-up node pull-down transistor
First pole is connect with the pull-up node, and the second pole of the pull-up node pull-down transistor is connect with second voltage end；
The control circuit includes circuit for providing voltage；The circuit for providing voltage is used to provide to the second voltage end
Second voltage, so that the gate source voltage of the pull-up node pull-down transistor is in the second predetermined voltage range in output stage；
And/or
The control circuit includes voltage control circuit；The voltage control circuit is used to pass through control in output stage
The voltage of the pull-down node, so that the gate source voltage of the pull-up node pull-down transistor is in the second predetermined voltage range.
When implementation, the drive element of the grid further includes pull-down node control circuit, and the pull-down node control circuit is used
Under the control of the input signal inputted in input terminal, controls and be connected between the pull-down node and tertiary voltage end；
The control circuit includes voltage control circuit；The voltage control circuit is used to provide third to tertiary voltage end
Voltage, so that the voltage of the pull-down node is the tertiary voltage in the output stage.
The present invention also provides a kind of grid drive methods, applied to above-mentioned drive element of the grid, the gate driving
Method includes:
In output stage, control circuit controls the grid of the transistor connecting with pull-up node in pull-up node reset circuit
Source voltage controls the transistor connecting with pull-up node in pull-up node pull-down circuit in the first predetermined voltage range
Gate source voltage is in the second predetermined voltage range.
When implementation, the transistor connecting with pull-up node in the pull-up node reset circuit is n-type transistor, described
First predetermined voltage range is less than or equal to 0；Alternatively,
The transistor connecting with pull-up node in the pull-up node reset circuit is p-type transistor, and described first is pre-
Constant voltage range is more than or equal to 0.
When implementation, the transistor connecting with pull-up node in the pull-up node pull-down circuit is n-type transistor, described
Second predetermined voltage range is less than or equal to 0；Alternatively,
The transistor connecting with pull-up node in the pull-up node pull-down circuit is p-type transistor, and described second is pre-
Constant voltage range is more than or equal to 0.
The present invention also provides a kind of gate driving circuits, including multistage above-mentioned drive element of the grid.
The present invention also provides a kind of display devices, including above-mentioned gate driving circuit.
Compared with prior art, drive element of the grid of the present invention, grid drive method, gate driving circuit and aobvious
Showing device reduces the electric leakage of the transistor connecting with pull-up node in the pull-up node reset circuit in output stage, control
Stream, and the leakage current for reducing the transistor connecting with pull-up node in the pull-up node pull-down circuit is controlled, so as to
The current potential of pull-up node is kept well in output stage, guarantees the driving capability of the drive element of the grid.
Detailed description of the invention
Fig. 1 is the structure chart of drive element of the grid described in the embodiment of the present invention；
Fig. 2A is the waveform diagram of the current potential of the pull-up node PU in existing drive element of the grid；
Fig. 2 B is the waveform diagram of the gate drive signal of existing drive element of the grid output；
Fig. 3 is the circuit diagram of drive element of the grid described in another embodiment of the present invention；
Fig. 4 is the circuit diagram of drive element of the grid described in further embodiment of this invention；
Fig. 5 is the circuit diagram of the first specific embodiment of drive element of the grid of the present invention；
Fig. 6 A is the current potential of the pull-up node PU in the first specific embodiment of drive element of the grid of the present invention
Waveform diagram；
Fig. 6 B is the wave of the gate drive signal of the first specific embodiment output of drive element of the grid of the present invention
Shape figure；
Fig. 7 is the circuit diagram of the second specific embodiment of drive element of the grid of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The transistor used in all embodiments of the invention all can be triode, thin film transistor (TFT) or field-effect tube or its
The identical device of his characteristic.In embodiments of the present invention, to distinguish the two poles of the earth of transistor in addition to control electrode, will wherein claim a pole
For the first pole, another pole is known as the second pole.
In practical operation, when the transistor is triode, the control electrode can be base stage, and first pole can
Think collector, second pole can be with emitter；Alternatively, the control electrode can be base stage, described first can be extremely hair
Emitter-base bandgap grading, second pole can be with collector.
In practical operation, when the transistor is thin film transistor (TFT) or field-effect tube, the control electrode can be grid
Pole, described first can be extremely drain electrode, and described second extremely can be source electrode；Alternatively, the control electrode can be grid, described the
One extremely can be source electrode, and described second can be extremely drain electrode.
As shown in Figure 1, drive element of the grid described in the embodiment of the present invention includes pull-up node reset circuit 11, pull-up section
Point pull-down circuit 12 and control circuit 13；
The control circuit 13 is used to control in the pull-up node reset circuit 11 and pull-up node in output stage
The gate source voltage of the transistor of connection in the first predetermined voltage range, and control in the pull-up node pull-down circuit 12 with
The gate source voltage of the transistor of pull-up node connection is in the second predetermined voltage range, to control the pull-up in output stage
The transistor connecting with pull-up node in node reset circuit 11 complete switches off, and controls and reduce the pull-up node reset electricity
The leakage current of the transistor being connect with pull-up node in road 11, and in the output stage, control the pull-up node drop-down
The transistor connecting with pull-up node in circuit 12 complete switches off, and controls and reduce in the pull-up node pull-down circuit 12
The leakage current for the transistor being connect with pull-up node.
Drive element of the grid described in the embodiment of the present invention reduces the pull-up node reset circuit in output stage, control
The leakage current of the transistor being connect with pull-up node in 11, and control reduce in the pull-up node pull-down circuit 12 with it is upper
The leakage current of the transistor of node connection is drawn, so as to keep the current potential of pull-up node well in output stage, guarantees institute
State the driving capability of drive element of the grid.
In the prior art, as shown in Figure 2 A, due in the output stage S2, the pull-up node pull-down circuit 12 with
The transistor connecting with pull-up node in the transistor and/or the pull-up node reset circuit 11 of pull-up node connection exists
Leakage current it is larger, then the current potential holding capacity of pull-up node PU is poor, and the electricity of PU is in the state that pressure is fallen in electric leakage, direct result
It is the rise time Tr of the gate drive signal of the drive element of the grid output and fall time Tf of the gate drive signal
Increase, reduces gate driving ability.
Fig. 2 B is the waveform diagram of the gate drive signal of gate drive signal output end OUT1 output in the prior art.
According to a kind of specific embodiment, the transistor connecting with pull-up node in the pull-up node reset circuit can
Think that n-type transistor, first predetermined voltage range are less than or equal to 0；Alternatively,
The transistor connecting with pull-up node in the pull-up node reset circuit can be p-type transistor, described the
One predetermined voltage range is more than or equal to 0.
The transistor being connect with pull-up node according to another specific embodiment, in the pull-up node pull-down circuit
It can be n-type transistor, second predetermined voltage range is less than or equal to 0；Alternatively,
The transistor connecting with pull-up node in the pull-up node pull-down circuit can be p-type transistor, described the
Two predetermined voltage ranges are more than or equal to 0.
Specifically, the pull-up node reset circuit may include pull-up node reset transistor；
The control electrode of the pull-up node reset transistor is connect with reset terminal, and the of the pull-up node reset transistor
One pole is connect with the pull-up node, and the second pole of the pull-up node reset transistor is connect with first voltage end；
The control circuit includes circuit for providing voltage；
The circuit for providing voltage is used to provide first voltage to the first voltage end, so that in output stage, it should
The gate source voltage of pull-up node reset transistor is in the first predetermined voltage range.
In the specific implementation, the pull-up node reset circuit may include pull-up node reset transistor, the control
Circuit may include circuit for providing voltage, and the circuit for providing voltage is used to provide to the second pole of the pull-up node reset terminal
First voltage, so that the gate source voltage of the pull-up node reset transistor is in the first predetermined voltage range in output stage.
Specifically, the pull-up node pull-down circuit may include pull-up node pull-down transistor；
The control electrode of the pull-up node pull-down transistor is connect with pull-down node, the pull-up node pull-down transistor
First pole is connect with the pull-up node, and the second pole of the pull-up node pull-down transistor is connect with second voltage end；
The control circuit includes circuit for providing voltage；The circuit for providing voltage is used to provide to the second voltage end
Second voltage, so that the gate source voltage of the pull-up node pull-down transistor is in the second predetermined voltage range in output stage；
And/or
The control circuit includes voltage control circuit；The voltage control circuit is used to pass through control in output stage
The voltage of the pull-down node, so that the gate source voltage of the pull-up node pull-down transistor is in the second predetermined voltage range.
In the specific implementation, the pull-up node pull-down circuit may include pull-up node pull-down transistor, the control
Circuit may include circuit for providing voltage, and the circuit for providing voltage is used for the second pole of the pull-up node pull-down transistor
Second voltage is provided, so that the gate source voltage of the pull-up node pull-down transistor is in the second predetermined voltage model in output stage
In enclosing；
In the specific implementation, the pull-up node pull-down circuit may include pull-up node pull-down transistor, the control
Circuit may include voltage control circuit, and the voltage control circuit is used to control the voltage of pull-down node in output stage, with
So that the gate source voltage of the pull-up node pull-down transistor is in the second predetermined voltage range in output stage.
Specifically, drive element of the grid described in the embodiment of the present invention can also include pull-down node control circuit, it is described
Pull-down node control circuit is used under the control for the input signal that input terminal inputs, and controls the pull-down node and tertiary voltage
It is connected between end；
When the control circuit includes voltage control circuit, the voltage control circuit is used to provide to tertiary voltage end
Tertiary voltage, so that the voltage of the pull-down node is the tertiary voltage in the output stage.
As shown in figure 3, the pull-up node resets electricity on the basis of the embodiment of drive element of the grid shown in Fig. 1
Road 11 includes the first pull-up node reset transistor M2 and the second pull-up node reset transistor M15；The pull-up node drop-down
Circuit 12 includes the first pull-up node pull-down transistor M8A and the second pull-up node pull-down transistor M8B；The control circuit packet
Include circuit for providing voltage 131；
The grid of M2 is connect with the first reset terminal RST, and the drain electrode of M2 is connect with pull-up node PU, and the source electrode of M2 is low with first
Voltage end connection；First low-voltage end is for inputting the first low-voltage VGL；
The grid of M15 is connect with the second reset terminal TGOA_RST, and the drain electrode of M15 is connect with pull-up node PU, the source electrode of M15
It is connect with the first low-voltage end；First low-voltage end is for inputting the first low-voltage VGL；
The grid of M8A is connect with the first pull-down node PD_A, and the drain electrode of M8A is connect with the pull-up node PU, the source of M8A
Pole is connect with first low-voltage end；
The grid of M8B is connect with the second pull-down node PD_B, and the drain electrode of M8B is connect with the pull-up node PU, the source of M8B
Pole is connect with first low-voltage end；
The circuit for providing voltage 131 is connect with first low-voltage end, is used to provide the described the first low-voltage VGL,
So that the gate source voltage of M8A and the gate source voltage of M8B are both less than in the gate source voltage of output stage M2, the gate source voltage of M15
Or it is equal to 0, so that M2, M15, M8A and M8B are complete switched off in output stage, reduce the electric leakage of the leakage current, M15 of M2
The leakage current of stream, the leakage current of M8A and M8B.
In the embodiment shown in fig. 3, first voltage end and second voltage end are all first low-voltage end, but not with
This is limited；
In the embodiment shown in fig. 3, M2, M15, M8A and M8B are that (N-type Metal-oxide-semicondutor is brilliant for NMOS tube
Body pipe), but not limited to this.
As shown in figure 4, on the basis of the embodiment of drive element of the grid shown in Fig. 1, described in the embodiment of the present invention
Drive element of the grid further includes pull-down node control circuit 14；Pull-down node includes the drop-down section of the first pull-down node PD_A and second
Point PD_B；
The pull-down node control circuit 14 is used under the control of the input terminal INPUT input signal inputted, controls institute
It states and is connected between the first pull-down node PD_A and third low-voltage end, control the second pull-down node PD_B and third low-voltage
It is connected between end；
The pull-up node reset circuit 11 includes that the first pull-up node reset transistor M2 and the second pull-up node reset
Transistor M15；The pull-up node pull-down circuit 12 includes under the first pull-up node pull-down transistor M8A and the second pull-up node
Pull transistor M8B；
The grid of M2 is connect with the first reset terminal RST, and the drain electrode of M2 is connect with pull-up node PU, and the source electrode of M2 is low with first
Voltage end connection；First low-voltage end is for inputting the first low-voltage VGL；
The grid of M15 is connect with the second reset terminal TGOA_RST, and the drain electrode of M15 is connect with pull-up node PU, the source electrode of M15
It is connect with the first low-voltage end；First low-voltage end is for inputting the first low-voltage VGL；
The grid of M8A is connect with the first pull-down node PD_A, and the drain electrode of M8A is connect with the pull-up node PU, the source of M8A
Pole is connect with the second low-voltage end；
The grid of M8B is connect with the second pull-down node PD_B, and the drain electrode of M8B is connect with the pull-up node PU, the source of M8B
Pole is connect with second low-voltage end；Second low-voltage end is for inputting the second low-voltage LVGL；
The control circuit includes circuit for providing voltage 131 and voltage control circuit 132；
The circuit for providing voltage 131 is connect with first low-voltage end, is used to provide the described the first low-voltage VGL,
So that in the gate source voltage of output stage M2 and the gate source voltage of M15 both less than or equal to 0, so that in output stage, M2
It is all complete switched off with M15, reduces the leakage current of M2 and the leakage current of M15；
The voltage control circuit 132 is used to provide third low-voltage LLVGL to third low-voltage end, so that described
Output stage, the voltage of the first pull-down node PD_A are the third low-voltage LLVGL, the second pull-down node PD_B
Voltage be the third low-voltage LLVGL；
The third low-voltage LLVGL is less than the second low-voltage LVGL, so that in output stage, the grid source of M8A
Gate source voltage of the voltage less than or equal to 0, M8B is less than or equal to 0, so that M8A and M8B are complete switched off in output stage,
Reduce the leakage current of M8A and the leakage current of M8B.
In the embodiment shown in fig. 4, first voltage end is the first low-voltage end, and second voltage end is the second low-voltage
End, tertiary voltage end are third low-voltage end, and but not limited to this.
In the embodiment shown in fig. 4, M2, M15, M8A and M8B are NMOS tube, and but not limited to this.
Specifically, the pull-down node control circuit may include the first pull-down node control transistor and the second drop-down section
Point control transistor；
The control electrode of the first pull-down node control transistor is connect with the input terminal, the first pull-down node control
First pole of transistor processed is connect with first pull-down node, the second pole of first pull-down node control transistor and the
The connection of three voltage ends；
The control electrode of the second pull-down node control transistor is connect with the input terminal, the second pull-down node control
First pole of transistor processed is connect with second pull-down node, the second pole of second pull-down node control transistor and the
The connection of three voltage ends.
Specifically, drive element of the grid described in the embodiment of the present invention can also include input circuit, the first drop-down control
Circuit, the second pull-down control circuit, gate drive signal output circuit and carry signal output circuit, wherein
The input circuit is used under the control of input terminal, is controlled and is connected between pull-up node and input terminal；
First pull-down control circuit is used under the control of the first control voltage of the first control voltage end input, control
It makes and is connected between the first control voltage end and the first pull-down node, and for controlling under the control of the voltage of pull-up node
Make the current potential of the first pull-down node；
Second pull-down control circuit is used under the control of the second control voltage of the second control voltage end input, control
It makes and is connected between the second control voltage end and the second pull-down node, and for controlling under the control of the voltage of pull-up node
Make the current potential of the second pull-down node；
The gate drive signal output circuit is used under the control of the current potential of pull-up node, controls gate drive signal
Output end is connect with clock signal terminal, under the control of the current potential of the first pull-down node, control grid driving signal output end with
It is connected between second low-voltage end, under the control of the current potential of the second pull-down node, control grid driving signal output end and the
It is connected between two low-voltage ends, under the control of the third reset signal of third reset terminal input, controls the gate driving letter
It number is connected between output end and first low-voltage end；
The carry signal output circuit be used under the control of the current potential of pull-up node, control carry signal output end with
Clock signal terminal connection, under the control of the current potential of the first pull-down node, control carry signal output end and the first low-voltage end
Between be connected to, under the control of the current potential of the second pull-down node, control and connect between carry signal output end and the first low-voltage end
It is logical.
In the specific implementation, the input circuit may include input transistors；
The control electrode of the input transistors and the first pole are all connect with the input terminal, and the second of the input transistors
Pole is connect with the pull-up node；
First pull-down control circuit includes the first control transistor and the second control transistor；
The control electrode of the first control transistor is connect with the first control voltage end, the first control transistor
The first pole with it is described first control voltage end connect, it is described first control transistor the second pole and first pull-down node
Connection；
The control electrode of the second control transistor is connect with the pull-up node, and the first of the second control transistor
Pole is connect with first pull-down node, and the second pole of the second control transistor is connect with the second low-voltage end；
Second pull-down control circuit includes third control transistor and the 4th control transistor；
The control electrode of the third control transistor is connect with the second control voltage end, and the third controls transistor
The first pole connect with the second control voltage end, the second pole of third control transistor and second pull-down node
Connection；
The control electrode of the 4th control transistor is connect with the pull-up node, and the first of the 4th control transistor
Pole is connect with second pull-down node, and the second pole of the 4th control transistor is connect with the second low-voltage end；
The gate drive signal output circuit includes the first output transistor, the first output pull-down transistor, second defeated
Pull-down transistor, output reset transistor and storage capacitance out；
The control electrode of first output transistor is connect with the pull-up node, and the first of first output transistor
Pole is connect with the clock signal terminal, and the second pole of first output transistor is connect with gate drive signal output end；
The control electrode of the first output pull-down transistor is connect with first pull-down node, the first output drop-down
First pole of transistor is connect with the gate drive signal output end, the second pole of the first output pull-down transistor and institute
State the connection of the first low-voltage end；
The control electrode of the second output pull-down transistor is connect with second pull-down node, the second output drop-down
First pole of transistor is connect with the gate drive signal output end, the second pole of the second output pull-down transistor and institute
State the connection of the first low-voltage end；
The control electrode of the output reset transistor is connect with the third reset terminal, described to export the of reset transistor
One pole is connect with the gate drive signal output end, the second pole of the output reset transistor and first low-voltage end
Connection；
The carry signal output circuit includes under the second output transistor, third output pull-down transistor and the 4th output
Pull transistor；
The control electrode of second output transistor is connect with the pull-up node, and the first of second output transistor
Pole is connect with the clock signal terminal, and the second pole of second output transistor is connect with carry signal output end；
The control electrode of the third output pull-down transistor is connect with first pull-down node, the third output drop-down
First pole of transistor is connect with the carry signal output end, the second pole of third output pull-down transistor and described the
The connection of two low-voltage ends；
The control electrode of the 4th output pull-down transistor is connect with second pull-down node, the 4th output drop-down
First pole of transistor is connect with the carry signal output end, the second pole and described the of the 4th output pull-down transistor
The connection of two low-voltage ends.
Illustrate drive element of the grid of the present invention below by two specific embodiments.
As shown in figure 5, the first specific embodiment of drive element of the grid of the present invention includes that pull-up node resets electricity
Road 11, pull-up node pull-down circuit 12, pull-down node control circuit 14, input circuit, the first pull-down control circuit, the second drop-down
Control circuit, gate drive signal output circuit, carry signal output circuit and control circuit；
The pull-up node reset circuit 11 includes that the first pull-up node reset transistor M2 and the second pull-up node reset
Transistor M15；The pull-up node pull-down circuit 12 includes under the first pull-up node pull-down transistor M8A and the second pull-up node
Pull transistor M8B；The control circuit includes circuit for providing voltage (circuit for providing voltage is not shown in Fig. 5)；
The grid of M2 is connect with the first reset terminal RST, and the drain electrode of M2 is connect with pull-up node PU, and the source electrode of M2 is low with first
Voltage end connection；First low-voltage end is for inputting the first low-voltage VGL；
The grid of M15 is connect with the second reset terminal TGOA_RST, and the drain electrode of M15 is connect with pull-up node PU, the source electrode of M15
It is connect with the first low-voltage end；First low-voltage end is for inputting the first low-voltage VGL；
The grid of M8A is connect with the first pull-down node PD_A, and the drain electrode of M8A is connect with the pull-up node PU, the source of M8A
Pole is connect with first low-voltage end；
The grid of M8B is connect with the second pull-down node PD_B, and the drain electrode of M8B is connect with the pull-up node PU, the source of M8B
Pole is connect with first low-voltage end；
The pull-down node control circuit 14 includes the first pull-down node control transistor M7A and the control of the second pull-down node
Transistor M7B；
The grid of the first pull-down node control transistor M7A is connect with input terminal INPUT, first pull-down node
The drain electrode of control transistor M7A is connect with the first pull-down node PD_A, the first pull-down node control transistor M7A's
Source electrode is connect with the second low-voltage end；Second low-voltage end is for inputting the second low-voltage LVGL；
The grid of the second pull-down node control transistor M7B is connect with the input terminal INPUT, second drop-down
The drain electrode of node control transistor M7B is connect with the second pull-down node PD_B, and second pull-down node controls transistor
The source electrode of M7B is connect with second low-voltage end；
The input circuit includes input transistors M1；
The grid of the input transistors M1 and drain electrode are all connect with the input terminal INPUT, the input transistors M1
Source electrode connect with the pull-up node PU；
First pull-down control circuit includes the first control transistor M5A and the second control transistor M6A；
The grid of the first control transistor M5A is connect with the first control voltage end, the first control crystal
The drain electrode of pipe M5A is connect with the first control voltage end, under the second pole and described first of the first control transistor M5A
Draw node PD_A connection；The first control voltage end is for inputting the first control voltage VDD_A；
The grid of the second control transistor M6A is connect with the pull-up node PU, the second control transistor M6A
Drain electrode connect with the first pull-down node PD_A, it is described second control transistor M6A source electrode and the second low-voltage end company
It connects；
Second pull-down control circuit includes the third control of control transistor M5B and the 4th transistor M6B；
The grid of the third control transistor M5B is connect with the second control voltage end, and the third controls crystal
The drain electrode of pipe M5B is connect with the second control voltage end, the source electrode of the third control transistor M5B and second drop-down
Node PD_B connection；The second control voltage end is for inputting the second control voltage VDD_B；
The grid of the 4th control transistor M6B is connect with the pull-up node PU, the 4th control transistor M6B
Drain electrode connect with the second pull-down node PD_B, it is described 4th control transistor M6B the second pole and the second low-voltage end
Connection；
The gate drive signal output circuit include the first output transistor M3, first output pull-down transistor M13A,
Second output pull-down transistor M13B, output reset transistor M4 and storage capacitance Cs；
The grid of the first output transistor M3 is connect with the pull-up node PU, the first output transistor M3's
Drain electrode is connect with the clock signal terminal, and the source electrode and gate drive signal output end OUT1 of the first output transistor M3 connects
It connects；The clock signal terminal is used for input clock signal CLK；
The grid of the first output pull-down transistor M13A is connect with the first pull-down node PD_A, and described first is defeated
The drain electrode of pull-down transistor M13A is connect with the gate drive signal output end OUT1 out, the first output pull-down transistor
The source electrode of M13A is connect with first low-voltage end；
The grid of the second output pull-down transistor M13B is connect with the second pull-down node PD_B, and described second is defeated
The drain electrode of pull-down transistor M13B is connect with the gate drive signal output end OUT1 out, the second output pull-down transistor
The source electrode of M13B is connect with first low-voltage end；
The grid of the output reset transistor M4 is connect with the third reset terminal RST_2, and the output resets crystal
The drain electrode of pipe M4 is connect with the gate drive signal output end OUT1, the source electrode and described the of the output reset transistor M4
The connection of one low-voltage end；
The carry signal output circuit includes the second output transistor M11, third output pull-down transistor M13A and the
Four output pull-down transistor M13B；
The grid of the second output transistor M11 is connect with the pull-up node PU, the second output transistor M11
Drain electrode connect with the clock signal terminal, the source electrode of the second output transistor M11 and carry signal output end OUT_C connect
It connects；
The grid of the third output pull-down transistor M13A is connect with the first pull-down node PD_A, and the third is defeated
The drain electrode of pull-down transistor M13 is connect with the carry signal output end OUT_C out, and the third exports pull-down transistor M13A
Source electrode connect with second low-voltage end；
The grid of the 4th output pull-down transistor M13B is connect with the second pull-down node PD_B, and the described 4th is defeated
The drain electrode of pull-down transistor M13B is connect with the carry signal output end OUT_C out, the 4th output pull-down transistor
The source electrode of M13B is connect with second low-voltage end；
The circuit for providing voltage is connect with first low-voltage end, is used to provide the described the first low-voltage VGL, so that
In output stage, the gate source voltage of the gate source voltage of M2, M15, the gate source voltage of the gate source voltage of M8A and M8B both less than or
Equal to 0 so that M2, M15, M8A and M8B are complete switched off in output stage, reduce the leakage current of M2, the leakage current of M15,
The leakage current of M8A and the leakage current of M8B.
In the first specific embodiment of present invention drive element of the grid as shown in Figure 5, all transistors are all
NMOS tube, but not limited to this.
At work, the voltage provides electricity to first specific embodiment of present invention drive element of the grid as shown in Figure 5
First low-voltage end described in road direction provides the first low-voltage VGL, so that in output stage, the gate source voltage of M2, M15
Gate source voltage, the gate source voltage of M8A and the gate source voltage of M8B are both less than or are equal to 0, so that in output stage, M2, M15,
M8A and M8B are complete switched off, and reduce the leakage current of the leakage current of M2, the leakage current of M15, the leakage current of M8A and M8B.
First specific embodiment of present invention drive element of the grid as shown in Figure 5 at work, in output stage, M15
The current potential of grid and the current potential of grid of M2 be all VGL, the current potential of the grid of the current potential and M8B of the grid of M8A is slightly above
The current potential of the source electrode of LVGL, M15, the current potential of the source electrode of M2, the current potential of source electrode of M8A and the current potential of source electrode of M8B are all VGL,
The circuit for providing voltage provides VGL, and VGL is higher than LVGL so that the gate source voltage of the gate source voltage of M15 and M2 be equal to 0,
The gate source voltage of M8A and the gate source voltage of M8B are both less than 0, to reduce the leakage current of the leakage current of M15, the leakage current of M2, M8A
With the leakage current of M8B.
In the specific implementation, VGL can be -8V, and LVGL can be -11V, and but not limited to this.
First specific embodiment of present invention drive element of the grid as shown in Figure 5 at work, as shown in Figure 6A, defeated
The current potential of stage S2 out, PU can be good at remaining high potential.
Also, the first specific embodiment of present invention drive element of the grid as shown in Figure 5 is at work, and 6B is OUT1 defeated
The waveform diagram of gate drive signal out.
By Fig. 6 B it is found that compared with Fig. 2 B, rise time Tr of the gate drive signal reduces, the gate driving letter
Number fall time Tf reduce.
As shown in fig. 7, the second specific embodiment of drive element of the grid of the present invention includes that pull-up node resets electricity
Road 11, pull-up node pull-down circuit 12, pull-down node control circuit 14, input circuit, the first pull-down control circuit, the second drop-down
Control circuit, gate drive signal output circuit, carry signal output circuit and control circuit；The control circuit includes voltage
Circuit and voltage control circuit (circuit for providing voltage and voltage control circuit are not shown in Fig. 7) are provided；
The pull-up node reset circuit 11 includes that the first pull-up node reset transistor M2 and the second pull-up node reset
Transistor M15；The pull-up node pull-down circuit 12 includes under the first pull-up node pull-down transistor M8A and the second pull-up node
Pull transistor M8B；
The grid of M2 is connect with the first reset terminal RST, and the drain electrode of M2 is connect with pull-up node PU, and the source electrode of M2 is low with first
Voltage end connection；First low-voltage end is for inputting the first low-voltage VGL；
The grid of M15 is connect with the second reset terminal TGOA_RST, and the drain electrode of M15 is connect with pull-up node PU, the source electrode of M15
It is connect with the first low-voltage end；First low-voltage end is for inputting the first low-voltage VGL；
The grid of M8A is connect with the first pull-down node PD_A, and the drain electrode of M8A is connect with the pull-up node PU, the source of M8A
Pole is connect with first low-voltage end；
The grid of M8B is connect with the second pull-down node PD_B, and the drain electrode of M8B is connect with the pull-up node PU, the source of M8B
Pole is connect with first low-voltage end；
The circuit for providing voltage is connect with first low-voltage end, is used to provide the described the first low-voltage VGL, so that
In output stage, the gate source voltage of the gate source voltage of M2 and M15 both less than or are equal to 0 so that in output stage, M2 and
M15 is complete switched off, and reduces the leakage current of M2 and the leakage current of M15；
The pull-down node control circuit 14 includes the first pull-down node control transistor M7A and the control of the second pull-down node
Transistor M7B；
The grid of the first pull-down node control transistor M7A is connect with input terminal INPUT, first pull-down node
The drain electrode of control transistor M7A is connect with the first pull-down node PD_A, the first pull-down node control transistor M7A's
Source electrode is connect with third low-voltage end；The third low-voltage end is for inputting third low-voltage LLVGL；
The grid of the second pull-down node control transistor M7B is connect with the input terminal INPUT, second drop-down
The drain electrode of node control transistor M7B is connect with the second pull-down node PD_B, and second pull-down node controls transistor
The source electrode of M7B is connect with the third low-voltage end；
The voltage control circuit is used to provide the third low-voltage LLVGL for the third low-voltage end, so that
In output stage, the gate source voltage of M8A and the gate source voltage of M8B are less than or equal to 0；
The input circuit includes input transistors M1；
The grid of the input transistors M1 and drain electrode are all connect with the input terminal INPUT, the input transistors M1
Source electrode connect with the pull-up node PU；
First pull-down control circuit includes the first control transistor M5A and the second control transistor M6A；
The grid of the first control transistor M5A is connect with the first control voltage end, the first control crystal
The drain electrode of pipe M5A is connect with the first control voltage end, under the second pole and described first of the first control transistor M5A
Draw node PD_A connection；The first control voltage end is for inputting the first control voltage VDD_A；
The grid of the second control transistor M6A is connect with the pull-up node PU, the second control transistor M6A
Drain electrode connect with the first pull-down node PD_A, it is described second control transistor M6A source electrode and the second low-voltage end company
It connects；
Second pull-down control circuit includes the third control of control transistor M5B and the 4th transistor M6B；
The grid of the third control transistor M5B is connect with the second control voltage end, and the third controls crystal
The drain electrode of pipe M5B is connect with the second control voltage end, the source electrode of the third control transistor M5B and second drop-down
Node PD_B connection；The second control voltage end is for inputting the second control voltage VDD_B；
The grid of the 4th control transistor M6B is connect with the pull-up node PU, the 4th control transistor M6B
Drain electrode connect with the second pull-down node PD_B, it is described 4th control transistor M6B the second pole and the second low-voltage end
Connection；
The gate drive signal output circuit include the first output transistor M3, first output pull-down transistor M13A,
Second output pull-down transistor M13B, output reset transistor M4 and storage capacitance Cs；
The grid of the first output transistor M3 is connect with the pull-up node PU, the first output transistor M3's
Drain electrode is connect with the clock signal terminal, and the source electrode and gate drive signal output end OUT1 of the first output transistor M3 connects
It connects；The clock signal terminal is used for input clock signal CLK；
The grid of the first output pull-down transistor M13A is connect with the first pull-down node PD_A, and described first is defeated
The drain electrode of pull-down transistor M13A is connect with the gate drive signal output end OUT1 out, the first output pull-down transistor
The source electrode of M13A is connect with first low-voltage end；
The grid of the second output pull-down transistor M13B is connect with the second pull-down node PD_B, and described second is defeated
The drain electrode of pull-down transistor M13B is connect with the gate drive signal output end OUT1 out, the second output pull-down transistor
The source electrode of M13B is connect with first low-voltage end；
The grid of the output reset transistor M4 is connect with the third reset terminal RST_2, and the output resets crystal
The drain electrode of pipe M4 is connect with the gate drive signal output end OUT1, the source electrode and described the of the output reset transistor M4
The connection of one low-voltage end；
The carry signal output circuit includes the second output transistor M11, third output pull-down transistor M13A and the
Four output pull-down transistor M13B；
The grid of the second output transistor M11 is connect with the pull-up node PU, the second output transistor M11
Drain electrode connect with the clock signal terminal, the source electrode of the second output transistor M11 and carry signal output end OUT_C connect
It connects；
The grid of the third output pull-down transistor M13A is connect with the first pull-down node PD_A, and the third is defeated
The drain electrode of pull-down transistor M13 is connect with the carry signal output end OUT_C out, and the third exports pull-down transistor M13A
Source electrode connect with second low-voltage end；
The grid of the 4th output pull-down transistor M13B is connect with the second pull-down node PD_B, and the described 4th is defeated
The drain electrode of pull-down transistor M13B is connect with the carry signal output end OUT_C out, the 4th output pull-down transistor
The source electrode of M13B is connect with second low-voltage end.
In the second specific embodiment of present invention drive element of the grid as shown in Figure 7, all transistors are all
NMOS tube, but not limited to this.
At work, the voltage provides electricity to second specific embodiment of present invention drive element of the grid as shown in Figure 7
First low-voltage end described in road direction provides the first low-voltage VGL, so that in output stage, the gate source voltage of M2, M15
Gate source voltage is equal to 0, so that M2 and M15 are complete switched off in output stage, reduces the leakage current of M2 and the leakage current of M15.
At work, the voltage control is electric for second specific embodiment of present invention drive element of the grid as shown in Figure 7
Third low-voltage end described in road direction provides the third low-voltage LLVGL, and LLVGL is less than LVGL, so that in output stage,
The current potential of PD_A and the current potential of PD_B are slightly above LLVGL, so that in output stage, the gate source voltage of M8A and the grid source of M8B
Voltage is less than 0, to reduce the leakage current of M8A and the leakage current of M8B.
In the specific implementation, LLVGL can be -15V, and but not limited to this.
Grid drive method described in the embodiment of the present invention, applied to above-mentioned drive element of the grid, the gate driving
Method includes:
In output stage, control circuit controls the grid of the transistor connecting with pull-up node in pull-up node reset circuit
Source voltage controls the transistor connecting with pull-up node in pull-up node pull-down circuit in the first predetermined voltage range
Gate source voltage is in the second predetermined voltage range.
Grid drive method described in the embodiment of the present invention reduces the pull-up node reset circuit in output stage, control
In the transistor being connect with pull-up node leakage current, and control and reduce saving in the pull-up node pull-down circuit with pull-up
The leakage current of the transistor of point connection guarantees the grid so as to keep the current potential of pull-up node well in output stage
The driving capability of pole driving unit.
Specifically, the transistor connecting with pull-up node in the pull-up node reset circuit can be n-type transistor,
First predetermined voltage range is less than or equal to 0；Alternatively,
The transistor connecting with pull-up node in the pull-up node reset circuit can be p-type transistor, described the
One predetermined voltage range is more than or equal to 0.
Specifically, the transistor connecting with pull-up node in the pull-up node pull-down circuit can be n-type transistor,
Second predetermined voltage range is less than or equal to 0；Alternatively,
The transistor connecting with pull-up node in the pull-up node pull-down circuit is p-type transistor, and described second is pre-
Constant voltage range is more than or equal to 0.
Gate driving circuit described in the embodiment of the present invention includes multistage above-mentioned drive element of the grid.
Display device described in the embodiment of the present invention includes above-mentioned gate driving circuit.
Display device provided by the embodiment of the present invention can be mobile phone, tablet computer, television set, display, notebook
Any products or components having a display function such as computer, Digital Frame, navigator.
The above is a preferred embodiment of the present invention, it is noted that for those skilled in the art
For, without departing from the principles of the present invention, it can also make several improvements and retouch, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (11)
1. a kind of drive element of the grid, which is characterized in that including pull-up node reset circuit, pull-up node pull-down circuit and control
Circuit；
The control circuit is used to control the crystalline substance connecting with pull-up node in the pull-up node reset circuit in output stage
The gate source voltage of body pipe controls connecting in the pull-up node pull-down circuit with pull-up node in the first predetermined voltage range
The gate source voltage of the transistor connect is in the second predetermined voltage range.
2. drive element of the grid as described in claim 1, which is characterized in that in the pull-up node reset circuit with pull-up
The transistor of node connection is n-type transistor, and first predetermined voltage range is less than or equal to 0；Alternatively,
The transistor connecting with pull-up node in the pull-up node reset circuit is p-type transistor, the described first predetermined electricity
Pressing range is more than or equal to 0.
3. drive element of the grid as described in claim 1, which is characterized in that in the pull-up node pull-down circuit with pull-up
The transistor of node connection is n-type transistor, and second predetermined voltage range is less than or equal to 0；Alternatively,
The transistor connecting with pull-up node in the pull-up node pull-down circuit is p-type transistor, the described second predetermined electricity
Pressing range is more than or equal to 0.
4. the drive element of the grid as described in any claim in claims 1 to 3, which is characterized in that the pull-up node
Reset circuit includes pull-up node reset transistor；
The control electrode of the pull-up node reset transistor is connect with reset terminal, the first pole of the pull-up node reset transistor
It is connect with the pull-up node, the second pole of the pull-up node reset transistor is connect with first voltage end；
The control circuit includes circuit for providing voltage；
The circuit for providing voltage is used to provide first voltage to the first voltage end, so that in output stage, the pull-up
The gate source voltage of node reset transistor is in the first predetermined voltage range.
5. the drive element of the grid as described in any claim in claims 1 to 3, which is characterized in that the pull-up node
Pull-down circuit includes pull-up node pull-down transistor；
The control electrode of the pull-up node pull-down transistor is connect with pull-down node, and the first of the pull-up node pull-down transistor
Pole is connect with the pull-up node, and the second pole of the pull-up node pull-down transistor is connect with second voltage end；
The control circuit includes circuit for providing voltage；The circuit for providing voltage is used to provide second to the second voltage end
Voltage, so that the gate source voltage of the pull-up node pull-down transistor is in the second predetermined voltage range in output stage；With/
Or,
The control circuit includes voltage control circuit；The voltage control circuit is used in output stage, by described in control
The voltage of pull-down node, so that the gate source voltage of the pull-up node pull-down transistor is in the second predetermined voltage range.
6. drive element of the grid as claimed in claim 5, which is characterized in that the drive element of the grid further includes pull-down node
Control circuit, the pull-down node control circuit are used under the control for the input signal that input terminal inputs, and control the drop-down
It is connected between node and tertiary voltage end；
The control circuit includes voltage control circuit；The voltage control circuit is used to provide third electricity to tertiary voltage end
Pressure, so that the voltage of the pull-down node is the tertiary voltage in the output stage.
7. a kind of grid drive method, applied to the drive element of the grid as described in any claim in claim 1 to 6,
It is characterized in that, the grid drive method includes:
In output stage, control circuit controls the grid source electricity of the transistor connecting with pull-up node in pull-up node reset circuit
It is pressed in the first predetermined voltage range, and controls the grid source of the transistor connecting with pull-up node in pull-up node pull-down circuit
Voltage is in the second predetermined voltage range.
8. grid drive method as claimed in claim 7, which is characterized in that in the pull-up node reset circuit with pull-up
The transistor of node connection is n-type transistor, and first predetermined voltage range is less than or equal to 0；Alternatively,
The transistor connecting with pull-up node in the pull-up node reset circuit is p-type transistor, the described first predetermined electricity
Pressing range is more than or equal to 0.
9. grid drive method as claimed in claim 7, which is characterized in that in the pull-up node pull-down circuit with pull-up
The transistor of node connection is n-type transistor, and second predetermined voltage range is less than or equal to 0；Alternatively,
The transistor connecting with pull-up node in the pull-up node pull-down circuit is p-type transistor, the described second predetermined electricity
Pressing range is more than or equal to 0.
10. a kind of gate driving circuit, which is characterized in that including multistage as described in any claim in claim 1 to 6
Drive element of the grid.
11. a kind of display device, which is characterized in that including gate driving circuit as claimed in claim 10.
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