CN103854587A - Gate driving circuit, gate driving circuit unit and displayer - Google Patents

Gate driving circuit, gate driving circuit unit and displayer Download PDF

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Publication number
CN103854587A
CN103854587A CN201410060595.XA CN201410060595A CN103854587A CN 103854587 A CN103854587 A CN 103854587A CN 201410060595 A CN201410060595 A CN 201410060595A CN 103854587 A CN103854587 A CN 103854587A
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signal
control
transistor
utmost point
level
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CN103854587B (en
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张盛东
廖聪维
胡治晋
李文杰
李君梅
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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Abstract

The invention discloses a gate driving circuit unit which allows an existing gate driving circuit unit to be a circuit structure framework. The gate driving circuit unit comprises a driving module, a low-level maintenance module, a first input module and a second input module. By improving a switching transistor of the first input module and a switching transistor of the second input module, additionally arranging transistors and externally connecting a control signal, multiple scanning modes of the gate driving circuit unit can be switched. In addition, according to circuit logic and requirements for public use, in different working state processes, the gate driving circuit unit multiplexes all circuit modules to the maximum degree, so that module utilization efficiency is enhanced, and hardware overheads are reduced. On the basis of the gate driving circuit unit, the invention further discloses a gate driving circuit and a displayer.

Description

Gate driver circuit and unit thereof and a kind of display
Technical field
The application relates to electronic applications, is specifically related to a kind of display and gate driver circuit thereof and drive element of the grid circuit.
Background technology
Thin film transistor (TFT) (Thin Film Transistor, TFT) Display panel (Flat Panel Display, FPD) is the main flow of current display technique.In recent years, adopt the integrated gate driver circuit design (gate driver in array, GIA) of TFT to start to be widely used in small-medium size display panel, even in large scale display panel.By rational circuit design, even if adopt a-Si TFT also may obtain well behaved GIA circuit, meet the demand of display application at aspects such as Circuit responce speed, stability, power consumptions.The display panel of integrated gate driver circuit has narrow frame, high resolving power, the advantage such as cheap.
Oxide transistor (IGZO TFT) has high mobility, better stability and being more suitable in high resolving power, large-area display application, and therefore, IGZO TFT more likely becomes following main flow TFT technology.The development of the novel high-performance GIA circuit based on IGZO TFT has caused researcher's very big concern.IGZO TFT is because the advantages such as mobility height can improve the performance of circuit significantly.In the occasion such as a-Si or organic tft, because mobility is too low, the application of many circuit engineerings is limited to, and such as feedback circuit unit etc. cannot embody due effectiveness because speed crosses slow.The introducing of IGZO TFT may taking flexibility or transparent display panel as platform allows abundanter circuit engineering implemented, make display panel system (System on Paenl, SoP) more intelligent.
In recent years, the integrated gate drive circuitry design that possesses many scan patterns feature has caused the concern of TFT FPD industrial community.Taking bilateral scanning pattern as example, under peripheral clock signal coordinates, gate driver circuit not only can sequentially scan the gate line of large sequence number number successively from the gate line of little sequence number number, and can scan from the gate line of large sequence number number the gate line of little sequence number number.After having increased bilateral scanning feature, TFT FPD obtains following benefit: (1), in the time that FPD switches between forward, reverse scan pattern, can realize the mirror image that shows image perpendicular to grid line direction.This has strengthened operability, interest and the user's of FPD likability.(2) configuration of display panel is more flexible, meets more easily different designs person's demand.
In prior art, realizing two-way integrated gate drive circuitry generally has two kinds of methods: one for design two cover sweep circuits, is respectively used to realize forward, reverse scan; Two for increasing the electric signal of gated sweep direction.The effect that adopts these two kinds of methods to realize gate driver circuit is all undesirable.This be because, first method need adopt complicated circuit structure, the TFT quantity of using is almost the twice of TFT quantity in simple scanning gate driver circuit.In any working hour, in the first gate driver circuit, almost always there is the device of half in idle state.Above-mentioned second method can reduce the quantity of TFT, but the quantity of control signal has but increased, and these control signals that newly increase can increase the voltage bias time of TFT in gate driver circuit, has shortened the serviceable life of gate driver circuit.
In sum, IGZO TFT is more suitable for designing multimodal GIA circuit.For example, the Leakage Current of IGZO TFT is less, in the time showing still image, the refreshing frequency of TFT panel array can reduce, this not only can reduce TFT panel power consumption, extend the battery life of mobile TFT panel, and there is advantage for the eye fatigue that reduces user.So the GIA of IGZO TFT design has proposed new requirement: one, requires the GIA circuit of IGZO TFT to have multiple scan pattern; Its two, can either export upper frequency scanning impulse show dynamic image, can show still image with less refreshing frequency again.But the function of many scan patterns is not supported in conventional GIA design.Therefore, need to study the GIA scheme of new IGZO TFT, make it there is many scan patterns function, and simpler, the peripheral connecting line negligible amounts of circuit structure.
Summary of the invention
The application provides a kind of gate driver circuit and unit and a kind of display.
According to the application's first aspect, the application provides a kind of gate drive circuit unit, comprising:
First signal input end, for inputting the first pulse signal.
Secondary signal input end, for inputting the second pulse signal.
The first clock signal input terminal, for inputting the first clock signal.
Signal output part, for exporting pulse drive signal.
Driver module, driver module is coupling between the first clock signal input terminal and signal output part, drives control end to obtain after driving voltage at it, and the first clock signal is sent to signal output part, in the time that the first clock signal is high level, driver module is to drawing charging on signal output part; In the time that the first clock signal is low level, driver module is to the drop-down electric discharge of signal output part.
Low level maintains module, and low level maintains module and is coupling between signal output part and low level end; Low level maintains the high level signal of module responds the first clock signal or signal output part is coupled to low level end by the high level signal of the 3rd clock signal, maintains signal output part low level current potential.
The second load module, the second load module comprises at least one second switch transistor of cascade, at least one second switch transistors couple of cascade is between secondary signal input end and driving control end, transistorized first utmost point of chopped-off head second switch is used for inputting second clock signal, transistorized second utmost point of tail level second switch is coupling in driving control end, the transistorized control utmost point of each second switch is coupling in secondary signal input end, for inputting the second pulse signal; Under reverse scan pattern, the second load module responds the overlapping phase signal of high level of the second pulse signal and second clock signal to driving control end charging; Under forward scan pattern, when the second pulse signal and second clock signal are respectively high level and low level, the second load module is to driving control end electric discharge.
The first load module, the first load module comprises at least one first switching transistor of cascade, at least one of cascade the first switching transistor is coupling in first signal input end and drives between control end, first utmost point of chopped-off head the first switching transistor is used for inputting the 4th clock signal, second utmost point of tail level the first switching transistor is coupling in driving control end, the control utmost point of each the first switching transistor is coupling in first signal input end, for inputting the first pulse signal; Under forward scan pattern, the first load module responds the overlapping phase signal of high level of the first pulse signal and the 4th clock signal to driving control end charging; Under reverse scan pattern, when the first pulse signal and the 4th clock signal are respectively high level and low level, the first load module is to driving control end electric discharge.
The first load module also comprises the 15 transistor, and the 15 transistorized control utmost point is for input control signal, and first utmost point is coupled to second utmost point of chopped-off head the first switching transistor, and second utmost point is coupled to low level end; The 15 transistor is coupled to low level end by second utmost point of chopped-off head the first switching transistor under the control of control signal high level signal, and under the control of control signal low level signal, the 15 transistor disconnects.
The first clock signal and the 3rd clock signal complementation.
According to the application's second aspect, the application provides another kind of gate drive circuit unit, comprising:
First signal input end, for inputting the first pulse signal.
Secondary signal input end, for inputting the second pulse signal.
The first clock signal input terminal, for inputting the first clock signal.
Signal output part, for exporting pulse drive signal.
Driver module, driver module is coupling between the first clock signal input terminal and signal output part, drives control end to obtain after driving voltage at it, and the first clock signal is sent to signal output part, in the time that the first clock signal is high level, driver module is to drawing charging on signal output part; In the time that the first clock signal is low level, driver module is to the drop-down electric discharge of signal output part.
Low level maintains module, and low level maintains module and is coupling between signal output part and low level end; Low level maintains the high level signal of module responds the first clock signal or signal output part is coupled to low level end by the high level signal of the 3rd clock signal, maintains signal output part low level current potential.
The first load module, the first load module comprises at least one first switching transistor of cascade, at least one of cascade the first switching transistor is coupling in first signal input end and drives between control end, first utmost point of chopped-off head the first switching transistor is used for inputting the 4th clock signal, second utmost point of tail level the first switching transistor is coupling in driving control end, the control utmost point of each the first switching transistor is coupling in first signal input end, for inputting the first pulse signal; Under forward scan pattern, the first load module responds the overlapping phase signal of high level of the first pulse signal and the 4th clock signal to driving control end charging; Under reverse scan pattern, when the first pulse signal and the 4th clock signal are respectively high level and low level, the first load module is to driving control end electric discharge.
The second load module, the second load module comprises at least one second switch transistor of cascade, at least one second switch transistors couple of cascade is between secondary signal input end and driving control end, transistorized first utmost point of chopped-off head second switch is used for inputting second clock signal, transistorized second utmost point of tail level second switch is coupling in and drives the transistorized control utmost point of the each second switch of control end to be coupling in secondary signal input end, for inputting the second pulse signal; Under reverse scan pattern, the second load module responds the overlapping phase signal of high level of the second pulse signal and second clock signal to driving control end charging; Under forward scan pattern, when the second pulse signal and second clock signal are respectively high level and low level, the second load module is to driving control end electric discharge.
The second load module also comprises the 16 transistor, and the 16 transistorized control utmost point is for input control signal, and first utmost point is coupled to transistorized second utmost point of chopped-off head switch four, and second utmost point is coupled to low level end; The 16 transistor is coupled to low level end by transistorized chopped-off head second switch second utmost point under the control of control signal high level signal, and under the control of control signal low level signal, the 16 transistor disconnects.
The first clock signal and the 3rd clock signal complementation.
According to the application's the third aspect, the application provides a kind of gate driver circuit, comprising:
The gate drive circuit unit of N cascade, wherein, N is greater than 1 integer.Wherein, the gate drive circuit unit that chopped-off head adopts as above-mentioned first aspect provides; The gate drive circuit unit that tail level adopts above-mentioned second aspect to provide.
According to the application's fourth aspect, the application provides a kind of display, comprising:
Display panel, is manufactured with the gate line of first direction and the data line of second direction on display panel;
Above-mentioned gate driver circuit, in gate driver circuit, the signal output part of drive element of the grid is coupled to the gate line corresponding with it;
Timing sequence generating circuit, for generation of the required various control signals of gate driver circuit;
Data drive circuit, for generation of viewdata signal, and is outputed on data line corresponding with it in display panel.
The application's beneficial effect is: in the drive element of the grid circuit that the application provides, by the extra input that increases transistor He Yi road control signal in the first load module and the second load module, thereby realize the control of scan pattern and non-scan pattern, in scan pattern, also can realize the switching of forward scan pattern and reverse scan pattern, and, modules in gate drive circuit unit is that two kinds of scan patterns share, and has improved the utilization ratio of each module.
The application also adopts above-mentioned shift register cell to form gate driver circuit, can be made on display panel together with pixel TFT.Adopt circuit kit to realize the design of many scan patterns integrated gate drive circuitry, component number is few, simple in structure, rationally utilizes each components and parts, has improved integrated degree.
In addition, in the gate driver circuit that the application provides, improved load module can be realized the logical operation of many inputs, and circuit structure is simple, little to transistorized channel width-over-length ratio dependence.
Brief description of the drawings
Fig. 1 is the embodiment of the present application one gate drive circuit unit circuit structure diagram;
Fig. 2 is the embodiment of the present application one gate drive circuit unit forward scan pattern sequential chart;
Fig. 3 (a) is a kind of structural drawing of the embodiment of the present application one first load module 1,
Fig. 3 (b) is the another kind of structural drawing of the embodiment of the present application one first load module 1;
Fig. 4 is the disclosed a kind of gate driver circuit of the embodiment of the present application two;
Fig. 5 is the gated sweep signal graph of the embodiment of the present application two gate driver circuit forward scan pattern outputs;
Fig. 6 is the gated sweep signal graph of the embodiment of the present application two reverse scan pattern outputs;
Fig. 7 is the embodiment of the present application three n level gate drive circuit unit structural drawing;
Fig. 8 is the embodiment of the present application four chopped-off head gate drive circuit unit structural drawing;
Fig. 9 is the embodiment of the present application four tail level gate drive circuit unit structural drawing;
Figure 10 is the disclosed a kind of display device structure figure of the embodiment of the present application five;
Figure 11 is the disclosed a kind of logical transport circuit structure of the embodiment of the present application six;
Figure 12 is the disclosed a kind of logical and transmission circuit structure of the embodiment of the present application six;
Figure 13 is the disclosed a kind of logic XOR transmission circuit structure of the embodiment of the present application six.
Embodiment
Those skilled in the art should understand that, the improvement of the application's gate driver circuit (unit) on circuit structure is the first load module 1 and the second load module 2, other module all can adopt existing proven technique scheme, and in the prior art, other module is difficult to exhaustive in this application.Therefore, other module of following examples all can only be considered as the exemplary illustration of the one or more aspects to present techniques scheme, and can not regard as the full content of present techniques scheme.One or more aspects wherein comprise a key element or multiple key element of present techniques scheme.
First the technical term in the application is made an explanation/defined.
Complementary: in the time that a kind of signal is high level, the another kind of signal of answering is in contrast low level; In the time that a kind of signal is low level, the another kind of signal of answering is in contrast high level.It should be noted that, the complementation of the present embodiment definition is only closed to fasten at level height and is limited, and the amplitude magnitude relationship of low and high level is not done to strict restriction.
Transistor in the application can be bipolar transistor or field effect transistor.In the time that transistor is bipolar transistor, its control utmost point refers to the base stage of bipolar transistor, and first can be extremely collector or the emitter of bipolar transistor, and second of correspondence can be extremely emitter or the collector of bipolar transistor; In the time that transistor is field effect transistor, its control utmost point refers to the grid of field effect transistor, and first can be extremely drain electrode or the source electrode of field effect transistor, and second of correspondence can be extremely source electrode or the drain electrode of field effect transistor.Transistor in display is generally thin film transistor (TFT) (TFT).
Oxide transistor (Indium Gallium Zinc Oxide, IGZO TFT) is because it has high mobility, and better stability and being more suitable in high resolving power, large-area display application, more likely becomes following main flow TFT technology.Adopt IGZO TFT to design GIA circuit, the speed of circuit further may be improved, stability further strengthens, power consumption further reduces.It is than silica-based TFT, and the Leakage Current of IGZO TFT is less, so in the time showing still image, the refreshing frequency of TFT panel can reduce, thereby reduces the power consumption of TFT panel.
Correlative study shows, the Leakage Current of the crystalline state IGZO TFT of amorphous or C axle orientation may be little of 10 -20a/um, this is than the little some orders of magnitude of silicon-based semiconductor devices.And the sub-threshold slope of the IGZO TFT for preparing of advanced technologies can approach the ultimate value of the sub-threshold slope that even breaks through silicon-based semiconductor devices.In other words, one of key property of IGZO TFT is that it can turn-off more up hill and dale.The outstanding turn-off characteristic that utilizes IGZO TFT, the refreshing frequency of TFT panel array may reduce, and this may show that occasion reduces the power consumption of TFT panel, minimizing user's the kopiopia of using at some.For example, for color electric paper or colored electroweting display, in the time showing still image, it is even less that the frame frequency of TFT panel may reduce to 0.1Hz; In the time showing dynamic color image, the frame frequency of TFT panel returns to common 60Hz or higher.
Given this, to be IGZO TFT taking transistor be described in further detail the application as example the embodiment of the present application.It should be noted that, the application's circuit structure is also suitable for adopting other oxide transistor or other mobility is higher, off-state current is less transistor.
Please refer to Fig. 1, the drive element of the grid circuit in the present embodiment comprises: first signal input end, secondary signal input end, the first clock signal input terminal, signal output part, driver module 3, low level maintain module 5, the first load module 1 and the second load module 2.
First signal input end, for inputting the first pulse signal V i1.
Secondary signal input end, for inputting the second pulse signal V i2.
The first clock signal input terminal, for inputting the first clock signal V a.
Signal output part, for exporting pulse drive signal V o.
Driver module 3 is coupling between the first clock signal input terminal and signal output part.Drive control end Q to obtain after driving voltage, by the first clock signal V at it abe sent to signal output part, as the first clock signal V aduring for high level, driver module 3 is to drawing charging on signal output part; As the first clock signal V aduring for low level, driver module 3 is to signal output part V odrop-down electric discharge.
Low level maintains module 5 and is coupling between signal output part and low level end.Low level maintains module 5 and responds the first clock signal V ahigh level signal or the 3rd clock signal V chigh level signal signal output part is coupled to low level end, maintain signal output part low level current potential.
Conventionally, in order to suppress feedthrough effect, in one embodiment, low level maintains module 5 and can also comprise that low level maintains and enable unit 4, low level maintains and enables unit 4 and be coupling in the first clock signal input terminal and low level end, and low level maintains and enables unit 4 and be also coupling in signal output part.Be strobed the stage at gate drive circuit unit at the corresponding levels, low level maintains and enables unit 4 response impulses driving signal V oits low level is maintained to Enable Pin P and be coupled to low level end, output low level signal; In the low level maintenance stage, low level maintains and enables unit 4 at the first clock signal V acontrol lower low level and maintain Enable Pin P output high level signal.Now, low level maintains module 5 and responds low level and maintain high level signal or the 3rd clock signal V of Enable Pin P output chigh level signal signal output part is coupled to low level end, maintain signal output part low level current potential.
The first load module 1 comprises at least one first switching transistor T11 of cascade, at least one of cascade the first switching transistor T11 is coupling in described first signal input end and drives between control end Q, and first utmost point of chopped-off head the first switching transistor T11 (for example drain electrode) is for inputting the 4th clock signal V d, second utmost point (for example source electrode) of tail level the first switching transistor T11 is coupling in and drives control end Q; The control utmost point (for example grid) of each the first switching transistor T11 is coupling in first signal input end, for inputting the first pulse signal V i1.Under forward scan pattern, the first load module 1 responds the first pulse signal V i1with the 4th clock signal V dthe overlapping phase signal of high level to driving control end Q charging; Under reverse scan pattern, the first pulse signal V i1with the 4th clock signal V dwhile being respectively high level and low level, the first load module 1 is to driving control end Q electric discharge;
The second load module 2 comprises at least one second switch transistor T 14 of cascade, at least one second switch transistor T 14 of cascade is coupling in secondary signal input end and drives between control end Q, and first utmost point of chopped-off head second switch transistor T 14 (for example drain electrode) is for inputting second clock signal V b, second utmost point (for example source electrode) of tail level second switch transistor T 14 is coupling in and drives control end Q, and the control utmost point (for example grid) of each second switch transistor T 14 is coupling in secondary signal input end, for inputting the second pulse signal V i2.Under reverse scan pattern, the second load module 2 responds the second pulse signal V i2with second clock signal V bthe overlapping phase signal of high level to driving control end Q charging; Under forward scan pattern, the second pulse signal V i2with second clock signal V bwhile being respectively high level and low level, the second load module 2 is to driving control end Q electric discharge.
In the first gate drive circuit unit circuit structure, the first load module 1 also comprises the 15 transistor T 15.The control utmost point (for example grid) of the 15 transistor T 15 is for input control signal V cTR, first utmost point (for example drain electrode) is coupled to second utmost point (for example source electrode) of chopped-off head the first switching transistor T11, and second utmost point (for example source electrode) is coupled to low level end.The 15 transistor T 15 is at control signal V cTRunder high level signal control, second utmost point of chopped-off head the first switching transistor T11 (for example source electrode) is coupled to low level end, at control signal V cTRunder low level signal control, the 15 transistor T 15 disconnects.
In the second gate drive circuit unit circuit structure, the second load module 2 also comprises the 16 transistor T 16.The control utmost point (for example grid) of the 16 transistor T 16 is for input control signal V cTR, first utmost point (for example drain electrode) is coupled to second utmost point (for example source electrode) of chopped-off head switch four transistor Ts 14, and second utmost point (for example source electrode) is coupled to low level end.The 16 transistor T 16 is at control signal V cTRunder high level signal control, second utmost point of chopped-off head second switch transistor T 14 (for example source electrode) is coupled to low level end, at control signal V cTRunder low level signal control, the 16 transistor T 16 disconnects.
Or, further, in the third gate drive circuit unit structure, also can build above-mentioned two kinds of gate drive circuit unit circuit structures simultaneously, the first load module 1 also comprises that the 15 transistor T 15, the second load modules 2 also comprise the 16 transistor T 16.Now, the control utmost point (for example grid) of the 15 transistor T the 15 and the 16 transistor T 16 can also shared control signals V cTR.
Wherein, the first clock signal V awith the 3rd clock signal V ccomplementary.
Further, in the present embodiment, between each clock signal/pulse signal, should meet following relation:
The first pulse signal V i1with the second pulse signal V i2one, interval clock signal period;
Second clock signal V bwith the 4th clock signal V dcomplementary;
Under forward scan pattern, the 4th clock signal V dlag behind the first pulse signal V i1a phase place, the first clock signal V alag behind the 4th clock signal V da phase place;
Under reverse scan pattern, second clock signal V blag behind the second pulse signal V i2a phase place, the 4th clock signal V dlag behind the first clock signal V aa phase place.
Wherein, a phase place is for being T/4, the cycle that T is clock signal.
To set forth above-mentioned each module by following specific embodiment below.
Embodiment mono-:
Please refer to Fig. 1, in a kind of specific embodiment:
Driver module 3 comprises transistor seconds T2 and the first capacitor C 1.The control utmost point of transistor seconds T2 is coupled to and drives control end Q, and first utmost point is coupled to the first clock signal input terminal, and second utmost point is coupled to signal output part; One end of the first capacitor C 1 is coupled to and is driven control end Q, and the other end is coupled to signal output part.
Low level maintains module 5 and comprises that low level maintains and enable unit 4 and the first low level maintains unit 51.Low level maintains and enables unit 4 and comprise the 6th transistor T 6 and the second capacitor C 2.The control utmost point of the 6th transistor T 6 is coupled to signal output part, and first utmost point is coupled to low level and maintains Enable Pin P, and second utmost point is coupled to low level end; The first clock signal input terminal is coupled in one end of the second capacitor C 2, and the other end is coupled to low level and maintains Enable Pin P.
The first low level maintains unit 51 and comprises: the 4th transistor T 4 and the 7th transistor T 7.The control utmost point of the 4th transistor T 4 is used for inputting the 3rd clock signal V c, first utmost point is coupled to signal output part, and second utmost point is coupled to low level end; The control utmost point of the 7th transistor T 7 is coupled to low level and maintains Enable Pin P, and first utmost point is coupled to signal output part, and second utmost point is coupled to low level end.
Further, in another kind of specific embodiment, low level maintains module 5 can also comprise that the second low level maintains unit 52, the second low levels and maintains unit 52 and comprise the 5th transistor T 5.The control utmost point of the 5th transistor T 5 is coupled to low level and maintains Enable Pin P, and first utmost point is coupled to and drives control end Q, and second utmost point is coupled to low level end.
In other embodiments, above-mentioned each module/unit also can adopt existing other scheme.
In a kind of specific embodiment, in conjunction with the first load module 1 and the second load module 2, as control signal V cTRduring for low level, the 15 transistor T the 15 and the 16 transistor T 16 turn-offs, and gate drive circuit unit has normal forwards/reverse scan pattern function.For example, due to the control utmost point (grid) short circuit of the first switching transistor T11 of cascade, therefore, the first switching transistor T11 of cascade can be equivalent to a switching transistor, and by the first pulse signal V i1control its ON/OFF; Same, the second switch transistor T 14 of cascade also can be equivalent to a switching transistor, and by the second pulse signal V i2control its ON/OFF.
As control signal V cTRfor height at ordinary times, the 15 transistor T 15/ the 16 transistor T 16 conductings, the first switching transistor T11 of cascade and the node that the 15 transistor T 15 interconnects are placed in low level end by pincers, keep electronegative potential; Same, the node that second switch transistor T the 14 and the 16 transistor T 16 of cascade interconnects is also placed in low level end by pincers, keeps electronegative potential.Therefore, no matter be forward or reverse scan pattern, drive the current potential of control end Q all cannot rise to high potential.Gate drive circuit unit is all exported zero level, stops scan function.
Below the course of work of present techniques scheme will be set forth for Fig. 1 as an example of the third gate drive circuit unit example.For the first and the second gate drive circuit unit course of work, those skilled in the art can be easy to the disclosed content analysis according to the present embodiment and draw, therefore repeat no more.The sequential chart that is illustrated in figure 2 shift register cell forward scan pattern in the present embodiment, for reverse scan pattern, principle is identical, no longer separately paints sequential chart at this.The course of work of this shift register cell can be divided into double teacher: (1) pre-charging stage, on (2), draw the stage, (3) drop-down stage, (4) discharge regime, (5) low level maintenance stage.The course of work of this double teacher will be described in detail below.
(1) pre-charging stage t1
In pre-charging stage, the first load module 1 or the second load module 2 are given and are driven control end Q charging that high level voltage is provided, and driver module 3 was opened in advance before bootstrapping action triggers.In this stage, must provide sufficiently high cut-in voltage to driver module 3, avoid the driving force deficiency because of driver module 3, make on follow-up to occur more serious conditions of streaking in draw/downdraw process.
At this stage, control signal V cTRfor low level, the 15 transistor T the 15 and the 16 transistor T 16 is turned off.In forward scan pattern situation, the first pulse signal V i1with the 4th clock signal V dfor high level, so the first switching transistor T11 of cascade is switched on, drive control end Q to be charged to high level state; In reverse scan pattern situation, the second pulse signal V i2with second clock signal V bfor high level, so the 14 transistor T 14 of cascade is switched on, drive control end Q to be charged to high level state.
In a word, no matter be forward or reverse scan, at pre-charging stage t1, drive control end Q to be charged to high level state, transistor seconds T2 is fully opened.This got ready for the stage of drawing on ensuing.The degree that transistor seconds T2 is opened is more abundant, draw on ensuing/in the drop-down stage, the driving force of transistor seconds T2 is stronger.
(2) on, draw stage t2
On being, draw stage t2 after pre-charging stage t1.At the upper stage t2 that draws, the first clock signal V afor high level, at the first clock signal V aeffect under, by bootstrapping principle, driver module 3 will be moved high level to stronger driving force on signal output part.In scanning process, the opening degree of the switching device in flat pannel display array and the amplitude of scanning impulse and effective scanning burst length are closely related.While more than drawing the stage, the response speed of driver module 3 must be enough fast.
At the upper stage t2 that draws, the first pulse signal V i1with the second pulse signal V i2be low level, therefore, the first switching transistor T11 being connected with driving control end Q and T14 are all in off-state.In other words,, at the upper stage t2 that draws, driving control end Q is a kind of state of suspension.
In addition, because transistor seconds T2 is unlocked and in closed conducting state at pre-charging stage t1, and drive control end Q almost to suspend, therefore transistor seconds T2 remained conducting state in the upper stage of drawing.Because transistor seconds T2 is unlocked and in closure state at pre-charging stage t1, the C of transistor seconds T2 gD2(electric capacity between first utmost point and the control utmost point, for example gate-to-drain electric capacity) equals C gS2(controlling the electric capacity between the utmost point and second utmost point, for example gate-to-source electric capacity), and be the half of gate dielectric layer capacitance.And the first clock signal V of first utmost point of transistor seconds T2 (for example drain electrode) coupling abecome high level, this situation has been brought two kinds of variations below: the C of (1) transistor seconds T2 gD2by the first clock signal V ahigh level be coupled to and drive control end Q, drive the current potential on control end Q promptly to raise because of coupling.Therefore, the control utmost point-the second utmost point (for example gate-to-source) voltage difference of transistor seconds T2 increases, and the pulling drive ability of transistor seconds T2 strengthens.(2) stronger electric current is from the first clock signal V in high level state aflow to the signal output part of gate drive circuit unit by the transistor seconds T2 remaining closed.Therefore with the load capacitance C of signal output part coupling lthe upper accumulation because of positive charge, the level on it is elevated.And the current potential on driving control end Q is also along with output pulse drive signal V olevel raise and rise.Finally, output pulse drive signal V omoved to the first high level voltage V on the ground by no-voltage loss h.Said process is voltage bootstrap effect.
(3) drop-down stage t3
Continue on after drawing stage t2 be drop-down stage t3.At drop-down stage t3, signal output part pulled down to low level V l.In the time that the drop-down stage finishes, signal output part also should will keep low level voltage V lconstant.
In the time of the beginning of drop-down stage t3, the first clock signal V abecome low level.The first pulse signal V i1with the second pulse signal V i2still remain low level, therefore the first switching transistor T11 and T14 still remain off-state.Thereby drive control end Q still to remain suspended state in the drop-down stage, so half section of drop-down stage t3, transistor seconds T2 still remains conducting.And the first clock signal V abecome as low level V lthereby the signal output part of gate drive circuit unit pulled down to low level voltage V l.
(4) discharge regime t4
Is discharge regime t4 after drop-down stage t3.At discharge regime t4, drive control end Q electric discharge to pull down to low level state.
At discharge regime t4, the first clock signal V aremain low level, therefore, signal output part also keeps low level voltage V lconstant.The in the situation that of forward scan pattern, the second pulse signal V i2become high level, thus conducting second switch transistor T 14, and second clock signal V bbecome low level, therefore, drive control end Q by second clock signal V bsecond switch transistor T 14 electric discharges by conducting pull down to low level state; The in the situation that of reverse scan pattern, the first pulse signal V i1become high level, thus conducting the first switching transistor T11, and the 4th clock signal V dbecome low level, therefore, drive control end Q by the 4th clock signal V dthe first switching transistor T11 electric discharge by conducting pulls down to low level state.
In a word, no matter be forward or reverse scan pattern, at discharge regime t4, drive control end Q to be discharged and pull down to low level state, transistor seconds T2 is turned off.
(5) low level maintenance stage t5
After discharge regime t4, gate drive circuit unit enters low level maintenance stage t5.At low level maintenance stage t5, signal output part should remain low level voltage V l.Only have the signal output part of working as gate drive circuit unit to remain low level voltage V l, guarantee: in the pixel on the controlling grid scan line of the signal output part coupling of (1) and gate drive circuit unit, switching thin-film transistor remains closed condition, and the pixel electric charge that in corresponding pixel, programming obtains can seriously not revealed.(2) the front and back gate drive circuit units at different levels that are connected with gate drive circuit unit at the corresponding levels can not be affected, and adjacent driving control end Q at different levels can not be subject to the impact of gated sweep signal at the corresponding levels and charge or discharging action with leading to errors.
Therefore, in the present embodiment, use the clock signal of two-way complementation: the first clock signal V awith the 3rd clock signal V ccome alternately to discharge to signal output part, ensure that signal output part always remains low level current potential.
At low level maintenance stage t5, no matter forward or reverse scan pattern, as the 3rd clock signal V cduring for high level, the 4th transistor T 4 is switched on, and signal output part is coupled to low level end by the 4th transistor T 4, and its current potential pulled down to low level voltage V l; At the first clock signal V aduring for high level, low level maintains Enable Pin P and is coupled to high level voltage by the second capacitor C 2, so signal output part is coupled to low level end by the 5th transistor T 5 conductings, its current potential pulled down to low level voltage V l.
In another kind of embodiment, at the first clock signal V aduring for high level, low level maintains Enable Pin P and obtains after high level current potential, also the 5th transistor T 5 is opened, and driving control end Q is coupled to low level end, thereby make at low level maintenance stage t5, can better the current potential that drives control end Q be maintained to low level voltage V l, effectively maintained the low level current potential that drives control end Q.
In the present embodiment, when the acting on signal output part and be high level of the 6th transistor T 6, low level is maintained to Enable Pin P and pull down to low level.Can effectively prevent at signal output part output pulse drive signal V oin process, low level maintains Enable Pin P and is not supposed to draw high pressure on the ground, starts working thereby cause low level to maintain module 5.
It should be noted that, in a kind of specific embodiment, the first switching transistor T11 of cascade can be 1,2 or multiple:
Please refer to Fig. 3 (a), is the structural drawing of the first load module 1 in the time that the first switching transistor T11 of cascade only has.This structure is a kind of partial-pressure structure, at the first pulse signal V i1with control signal V cTRwhile being high level, the first switching transistor T11 and the 15 transistor T 15 are all in conducting state, so drive the current potential of control end Q to be determined by the dividing potential drop of the first switching transistor T11 and the 15 transistor T 15 simultaneously.At control signal V cTRduring for high level, wish to drive control end Q in low level state, just can make driver module 3 in disable state, output signal end remains low level.Therefore for make 15 points of the 15 transistor Ts voltage enough little, must make the ducting capacity of the 15 transistor T 15 much larger than the first switching transistor T11, in other words, the size of the 15 transistor T 15 should obtain enough large.This can increase the area that the 15 transistor T 15 takies on the one hand, increases control signal V cTRcharge capacity; On the other hand, the Leakage Current of the 15 transistor T 15 is by because the increase of the 15 transistor T 15 sizes increases.So the 15 oversize transistor T 15 may reduce the voltage amplitude that drives control end Q, thereby affect the normal work of scan pattern.
Please refer to Fig. 3 (b), is the structural drawing of the first load module 1 in the time that the first switching transistor T11 of cascade is two.This structure is a kind of flow dividing structure, at control signal V cTRduring for high level, the 15 transistor T 15 is in conducting state, so at the first pulse signal V i1during for high level, the input current of chopped-off head the first switching transistor T11 is bypassed shunting by the 15 transistor T 15.Even if tail level the first switching transistor T11 is unlocked, but its first utmost point (for example drain electrode) is because the cause voltage of shunting is lower, so almost there is no charging current process tail level the first switching transistor T11 to driving control end Q charging.Maintain lower level because charging current is not enough so drive control end Q.In this flow dividing structure, the size of the 15 transistor T 15 does not very greatly need responsive control signal V effectively cTR, driving control end Q is maintained to low level.
In sum, the flow dividing structure that Fig. 3 (b) illustrates, than the partial-pressure structure of Fig. 3 (a), may have following several advantages: (1) is responsive control signal V more effectively cTRhigh level, driving control end Q is stable to more electronegative potential, play stop scanning effect.(2) reduced because the 15 transistor T 15 electric leakages wait the spinoff for normal scan function.(3) transmission step by step and the accumulation of the gate drive circuit unit inter-stage noise voltage that may cause due to Leakage Current have been reduced.
In other embodiments, the first switching transistor T11 of cascade can also be multiple, but the number of transistors of connecting on input path is more.The drawback that may bring is like this that on input path, resistance in series is too large, may affect like this charging effect that drives control end Q, causes the inefficacy of gate drive circuit unit normal scan function.In addition, in fact, the structure of Fig. 3 (b) can be suppressed to less value by the leakage current of the first switching transistor T11 by bootstrapping stage or low level maintenance stage, therefore on input path, increase more transistor and can increase on the contrary the complexity of circuit, and affect normal scan function.
Therefore,, in the present embodiment, the first switching transistor T11 number of cascade is 2.Same, be also preferably 2 for the second switch transistor T 14 of cascade.
Embodiment bis-:
Please refer to Fig. 4, the present embodiment discloses a kind of gate driver circuit, comprising: the above-mentioned gate drive circuit unit of N cascade, wherein, N is greater than 1 integer.Gate drive circuit unit is arranged in both sides A-A and the B-B of display panel.In other embodiments, also gate drive circuit unit can be arranged in to a side of display panel.Gate drive circuit unit is arranged in to the both sides of display panel, can make the display effect difference that between the near-end of line direction and far-end, signal delay is brought reduce, in addition, between line due to neighbour, there is the coupling of signal, therefore separately can more conveniently connect up afterwards, thereby minimizing chip area, also can make display panel both sides be evenly distributed, and brings certain aesthetic.Therefore, the present embodiment is preferably arranged in gate drive circuit unit the both sides of display panel, and a kind of preferred mode is: odd level gate drive circuit unit is arranged in to a side of display panel, the opposite side that is arranged in display panel of even level.
Four road clock cables (CLK1, CLK2, CLK3, CLK4), for respectively to gate drive circuit unit transmit clock signal (V a, V b, V cand V d), under forward scan pattern, the clock of the first clock cable CLK1, second clock signal wire CLK2, the 3rd clock cable CLK3 and the 4th clock cable CLK4 is a late phase place successively; Under reverse scan pattern, the clock of the first clock cable CLK1, second clock signal wire CLK2, the 3rd clock cable CLK3 and a 4th clock cable CLK4 phase place early successively, wherein, a phase place is T/4, the cycle that T is clock signal.The first clock signal V of 4k+1 level gate drive circuit unit a, second clock signal V b, the 3rd clock signal V cwith the 4th clock signal V dprovided by the first clock cable CLK1, second clock signal wire CLK2, the 3rd clock cable CLK3 and the 4th clock cable CLK4 respectively; The first clock signal V of 4k+2 level gate drive circuit unit a, second clock signal V b, the 3rd clock signal V cwith the 4th clock signal V dprovided by second clock signal wire CLK2, the 3rd clock cable CLK3, the 4th clock cable CLK4 and the first clock cable CLK1 respectively; The first clock signal V of 4k+3 level gate drive circuit unit a, second clock signal V b, the 3rd clock signal V cwith the 4th clock signal V dprovided by the 3rd clock cable CLK3, the 4th clock cable CLK4, the first clock cable CLK1 and second clock signal wire CLK2 respectively; The first clock signal V of 4k level gate drive circuit unit a, second clock signal V b, the 3rd clock signal V cwith the 4th clock signal V dprovided by the 4th clock cable CLK4, the first clock cable CLK1, second clock signal wire CLK2 and the 3rd clock cable CLK3 respectively, wherein k is natural number.
First signal starts line STV1 and secondary signal starts line STV2, and first signal startup line STV1 is coupled to the first signal input end of first order gate drive circuit unit, for the first pulse signal V is provided to first order gate drive circuit unit i1; Secondary signal startup line STV2 is coupled to the first signal input end of second level gate drive circuit unit, for the first pulse signal V is provided to second level gate drive circuit unit i1; The signal output part of i level gate drive circuit unit is coupled respectively to the secondary signal input end of i-2 level gate drive circuit unit, and the first signal input end of i+2 level gate drive circuit unit, and i is more than or equal to 3 integer; The signal output part of first order gate drive circuit unit is coupled to the first signal input end of third level gate drive circuit unit; The signal output part of second level gate drive circuit unit is coupled to the first signal input end of fourth stage gate drive circuit unit.The signal output part of gate drive circuit units at different levels is also for providing gated sweep signal V g n, wherein, V g nit is the gated sweep signal of n level gate drive circuit unit.
Low level line l-V l, low level line l-V lbe coupled to the low level end of gate drive circuit units at different levels, for providing low level signal V to gate drive circuit units at different levels l.
Control signal wire l-V cTR, control signal wire l-V cTRbe used for to gate driver circuit transmission of control signals V cTR.
Please refer to Fig. 5, for the present embodiment gate driver circuit is under forward scan pattern, the gated sweep signal graph of 1-4 level gate drive circuit unit output.Corresponding with overlapping between two clock signal, the output signal of adjacent gate driver circuit is overlapping between two.When forward scan pattern, the phase place precedence relationship of output signal successively: V g 1, V g 2, V g 3, V g 4; Accordingly, when reverse scan pattern, the phase place precedence relationship of output signal successively: V g 4, V g 3, V g 2, V g 1.No matter forward or reverse scan pattern, is positioned at the odd line signal V of panel one side g 1, V g 3not overlapping; Be positioned at the even line signal V of panel opposite side g 2, V g 4also be not overlapping.The gated sweep signal of all the other gate drive circuit unit outputs also can draw by similar approach analysis.
Please refer to Fig. 6, for the present embodiment gate driver circuit is under reverse scan pattern, the gated sweep signal graph of the 1-4 level gate drive circuit unit output of sweep phase and non-sweep phase.At control signal V cTRduring for low level, gate driver circuit is in sweep phase, and under reverse scan pattern, gated sweep signal is exported V successively g 4, V g 3, V g 2, V g 1; Accordingly, under forward scan pattern, gated sweep signal is exported V successively g 1, V g 2, V g 3, V g 4.At control signal V cTRduring for high level, gate driver circuit is in non-sweep phase, and gate drive circuit unit output signals at different levels are low level.
Embodiment tri-:
The disclosed gate driver circuit of the present embodiment and embodiment bis-differences are, the circuit structure that the gate drive circuit unit employing of intergrade is simplified.
Please refer to Fig. 7, Figure 7 shows that n level gate drive circuit unit circuit structure diagram, wherein n is integer, and 2<n<N-1.The concrete structure of simplifying is the first load module 1 and the second load module 2, wherein:
The first load module 1 comprises a first switching transistor T11, and the control utmost point (for example grid) of the first switching transistor T11 is coupled to first signal input end, for inputting the first pulse signal V i1; First utmost point (for example drain electrode) is for inputting the 4th clock signal V d; Second utmost point is coupling in and drives control end Q.
The second load module 2 comprises a second switch transistor T 14, and the control utmost point (for example grid) of second switch transistor T 14 is coupled to first signal input end, for inputting the second pulse signal V i2; First utmost point (for example drain electrode) is for inputting second clock signal V b; Second utmost point is coupling in and drives control end Q.
With respect to embodiment bis-, the present embodiment n level gate drive circuit unit has reduced the number of cascaded switch transistor (T11, T14), also reduce by the 15 transistor T the 15 and the 16 transistor T 16, and, in the present embodiment, n level gate drive circuit unit does not need input control signal V again cTR.It will be understood by those skilled in the art that the first signal input end of n level gate drive circuit unit is identical with embodiment bis-with the connected mode of secondary signal input end and other signal (end).
The circuit structure that adopts this simplification is based on the following physics fact, the feature scanning step by step according to gate driver circuit, no matter be forward scan pattern or reverse scan pattern, whether gate drive circuit units at different levels work depends on the output of adjacent level gate drive circuit unit signal.What whether decision gate driver circuit started working is chopped-off head gate drive circuit unit or tail level gate drive circuit unit.Therefore, can additionally set up control signal V for n level gate drive circuit unit cTR, n level gate drive circuit unit only need wait for that the excitation of adjacent level gate drive circuit unit gets final product the scan pattern of starting-up response.
Embodiment tetra-:
The physics fact of setting forth according to embodiment tri-, considers and determines that gate driver circuit forwards/reverse scan pattern is chopped-off head/tail level gate drive circuit unit.The present embodiment discloses the gate driver circuit of another kind of simplification.
The disclosed gate driver circuit of the present embodiment and above-described embodiment difference be, chopped-off head (the 1st grade and the 2nd grade) gate drive circuit unit has adopted the circuit structure of simplifying, and is specially, and adopts the first gate drive circuit unit structure.
Please refer to Fig. 8, Figure 8 shows that the 1st grade and the 2nd grade of gate drive circuit unit circuit structure diagram, the concrete structure of simplifying is the second load module 2, the second load module 2 comprises a second switch transistor T 14, the control utmost point (for example grid) of second switch transistor T 14 is coupled to secondary signal input end, for inputting the second pulse signal V i2; First utmost point (for example drain electrode) is for inputting second clock signal V b; Second utmost point is coupling in and drives control end Q.With respect to above-described embodiment, the number that the 1st grade and the 2nd grade gate drive circuit unit of the present embodiment reduced cascade second switch transistor T 14, also reduce by the 16 transistor T 16, and, in the present embodiment, the second load module 2 of the 1st grade and the 2nd grade gate drive circuit unit does not need input control signal V again cTR.It will be understood by those skilled in the art that the 1st grade identical with other embodiment with the connected mode of secondary signal input end and other signal (end) with the first signal input end of the 2nd grade of gate drive circuit unit.
In another kind of embodiment, be with above-described embodiment difference, tail level (N-1 level and N level) gate drive circuit unit has adopted the circuit structure of simplifying, and is specially, and adopts the second gate drive circuit unit structure.
Please refer to Fig. 9, Figure 9 shows that N-1 level and N level gate drive circuit unit circuit structure diagram, the concrete structure of simplifying is the first load module 1, the first load module 1 comprises a first switching transistor T11, the control utmost point (for example grid) of the first switching transistor T11 is coupled to first signal input end, for inputting the first pulse signal V i1; First utmost point (for example drain electrode) is for inputting the 4th clock signal V d; Second utmost point is coupling in and drives control end Q.With respect to above-described embodiment, the present embodiment N-1 level and N level gate drive circuit unit have reduced the number of cascade the first switching transistor T11, also reduce by the 15 transistor T 15, and, in the present embodiment, the first load module 2 of N-1 level and N level gate drive circuit unit does not need input control signal V again cTR.The first signal input end that it will be understood by those skilled in the art that N-1 level and N level gate drive circuit unit is identical with other embodiment with the connected mode of secondary signal input end and other signal (end).
The disclosed two kinds of simplified ways of the present embodiment are based on following foundation:
As long as under forward scan pattern, what play the effect of starting working of driver gate driving circuit is the first load module 1 of chopped-off head gate drive circuit unit, then at different levels response previous stage output pulse drive signal V ocan open the work of gate drive circuit unit at the corresponding levels; What finish gate driver circuit work is the second load module 2 of tail level gate drive circuit unit, along with tail level gate drive circuit unit the second pulse signal V i2input indicate that the forward scan pattern of gate driver circuit finishes.
Under reverse scan pattern, what play the effect of starting working of driver gate driving circuit is the second load module 2 of tail level gate drive circuit unit, then at different levels as long as one-level is exported pulse drive signal V after response ocan open the work of gate drive circuit unit at the corresponding levels; What finish gate driver circuit work is the first load module 1 of first gate drive circuit unit, along with chopped-off head gate drive circuit unit the first pulse signal V i1input indicate that the reverse scan pattern of gate driver circuit finishes.
Therefore, no matter be forward scan pattern, or reverse scan pattern, in actual application, only need be to the first load module 1 of chopped-off head gate drive circuit unit and tail level gate drive circuit unit the second load module 2 input control signal V cTRcontrol.
Embodiment five:
Please refer to Figure 10, is the disclosed a kind of display device structure figure of the present embodiment.
Display panel 100, display panel 100 comprises the two-dimensional array being made up of multiple two-dimensional pixels, and many controlling grid scan lines of the first direction (for example horizontal) being connected with each pixel and many data lines of second direction (for example longitudinal).Same one-row pixels in pel array is all connected to same controlling grid scan line, and the same row pixel in pel array is connected to same data line.Display panel 100 can be display panels, organic electroluminescence display panel, electronic paper display panel etc., and corresponding display device can be liquid crystal display, organic light emitting display, electric paper display etc.
Gate driver circuit 200, in gate driver circuit 200, the signal output part of gate drive circuit unit is coupled to controlling grid scan line corresponding with it in display panel 100, for to the lining by line scan of pel array, gate driver circuit 200 can be connected with display panel 100 or be integrated in display panel 100 by welding.The gate driver circuit that this gate driver circuit 200 adopts above-described embodiment to provide.
Timing sequence generating circuit 300, for generation of the required various control signals of gate driver circuit 200.
Data drive circuit 400, for generation of viewdata signal, and is outputed on data line corresponding with it in display panel 100, is transferred in corresponding pixel cell to realize gradation of image by data line.
Embodiment six:
In above-described embodiment, the improvements that the first load module 1 and/or the second load module 2 are the application, its key point is, has introduced logic control end on the basis of existing load module more, thereby forms logical transport circuit.The present embodiment describes separately this logical transport circuit, please refer to Figure 11, and logical transport circuit structure comprises:
The first logic signal input end, for inputting the first logic control signal V 1.
The second logic signal input end, for inputting the second logic control signal V 2.
Signal transmission input end, for inputting signal transmission V in.
Signal is followed end.
At least one switching transistor T01 of cascade, at least one switching transistor T01 of cascade is coupling in the first logic signal input end and signal is followed between end, first utmost point (for example drain electrode) of chopped-off head switching transistor T01 is for inputting signal transmission, second utmost point (for example source electrode) of tail level switching transistor T01 is coupling in signal and follows end, the control utmost point (for example grid) of each switching transistor T01 is coupling in the first logic signal input end, for inputting the first logic control signal V 1.In a kind of specific embodiment, the number of at least one switching transistor T01 of cascade can be 2.
The first control utmost point (for example grid) of controlling transistor T 21, the first control transistor Ts 21 is coupled to the second logic signal input end, for inputting the second logic control signal V 2, first utmost point (for example drain electrode) is coupled to second utmost point (for example source electrode) of chopped-off head switching transistor T01, and first controls transistorized second utmost point (for example source electrode) for being coupled to low level end, for input low level voltage V l.
First controls transistor T 21 responds the second logic control signal V 2when disconnection: as the first logic control signal V 1during for significant level, the switching transistor T01 conducting of cascade, signal transmission V inbe applied to signal and follow end, signal is followed the current potential V of end qfollow the variation of signal transmission and change.First controls transistor T 21 responds the second logic control signal V 2when conducting, second utmost point of chopped-off head switching transistor T01 (for example source electrode) is coupled to low level end.
In a kind of specific embodiment, in the time that the first control transistor T 21 is N channel type transistor, as the second logic control signal V 2during for high level, first controls transistor T 21 conductings; As the second logic control signal V 2during for low level, first controls transistor T 21 disconnects.In other embodiments, the first control transistor T 21 also can be selected the transistor of other type, corresponding, the second logic control signal V 2logic control relation also can along with occur response change.Further, in another kind of embodiment, can also for example, increase logic inverter at the control utmost point of the first control transistor T 21 (grid), thereby realize logic NOT computing.
In a kind of specific embodiment, in the time that the switching transistor T01 of cascade is N channel type transistor, the first logic control signal V 1significant level be high level, similarly, in other embodiments, the switching transistor T01 of cascade also can select the transistor of other type, corresponding, the first logic control signal V 1significant level also can along with occur response change.
Adopt the logical transport circuit of the present embodiment, can realize logical operation, as many input logics and, many input logics or, logic inverter etc., and, little to transistorized channel width-over-length ratio dependence, output high level or low level amplitude loss are little, and circuit structure is simple.
The present embodiment logical transport circuit, except the application in gate driver circuit, also can be applicable in other circuit, is other application of the present embodiment logical transport circuit as shown in Figure 12,13.
Please refer to Figure 12, logical transport circuit also comprises the second control transistor T 22, be specially: second first utmost point (for example drain electrode) of controlling transistor T 22 is coupled to signal and follows end, second utmost point (for example source electrode), for being coupled to low level end, is controlled the utmost point (for example grid) for inputting the non-signal of the first logic control signal
In the present embodiment, as the first logic control signal V 1significant level be high level; The first control transistor T 21 is the transistor of N channel type, the second logic control signal V 2significant level be high level, at the second logic control signal V 2input to the control utmost point (for example grid) of the first control transistor T 21 before, also make inverse.In other embodiments, the first control transistor T 21 can be also the transistor of P channel type, now, and the second logic control signal V 2the control utmost point (for example grid) that inputs to the first control transistor T 21 does not need to do inverse before.
As the first logic control signal V 1with the second logic control signal V 2while being significant level simultaneously, the switching transistor T01 conducting of cascade, the first control transistor T 21 and second is controlled transistor T 22 and is disconnected, by signal transmission V inbe applied to signal and follow end, signal is followed the current potential V of end qfollow signal transmission V invariation and change, for example, work as V induring for high level, V qfor high level, otherwise, V qfor low level.
As the first logic control signal V 1during for inactive level, the second control transistor T 22 conductings are followed end by signal and are coupled to low level end, and now, signal is followed the current potential V of end qkeep low level V l.
As the second logic control signal V 2during for inactive level, first controls transistor T 21 conductings for example, is coupled to low level end by second utmost point of chopped-off head switching transistor T01 (source electrode).
Adopt the circuit structure of the present embodiment, can realize the first logic control signal V 1with the second logic control signal V 2logic and operation, only have as the first logic control signal V 1with the second logic control signal V 2while being significant level, just by signal transmission V simultaneously inbe applied to signal and follow end.
Please refer to Figure 13, disclose the circuit of the logic XOR of the circuit realization of a kind of Figure 11 of employing, comprise that the first submodule 81 and 82, two submodules of the second submodule all adopt the logical transport circuit shown in Figure 13.
Wherein, the signal transmission input end of two submodules also connects, for inputting signal transmission V in; The signal of two submodules is followed and is held and connect, for following signal transmission; The logic control signal of the first logic signal input end input of the first submodule 81 and the second submodule 82 is contrary, as the first logic signal input end input of the first submodule 81 the first logic signal input end input V of the second submodule 82 1; The logic control signal of the second logic signal input end input of the first submodule 81 and the second submodule 82 is contrary, as the second logic signal input end input of the first submodule 81 the second logic signal input end input V of the second submodule 82 2.
By this circuit, realize the logical transport circuit of logic XOR:
V Q = V in ( V 1 &CirclePlus; V 2 )
Wherein, for XOR,
V Q = V in ( V 1 V 2 &OverBar; + V 1 &OverBar; V 2 )
Above formula shows, works as V 1and V 2level when identical, for example, when being all high level or being all low level, V qfor low level;
Work as V 1and V 2level when different, V qfollow V invariation and change.
The present embodiment adopts simple shunting voltage-controlled circuit structure to realize XOR, has overcome the many shortcomings based on phase inverter logic: for example, output high level large to transistorized channel width-over-length ratio dependence or low level amplitude loss are large etc.
Above content is in conjunction with concrete embodiment further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace.

Claims (10)

1. a gate drive circuit unit, is characterized in that, comprising:
First signal input end, for inputting the first pulse signal (V i1);
Secondary signal input end, for inputting the second pulse signal (V i2);
The first clock signal input terminal, for inputting the first clock signal (V a);
Signal output part, for exporting pulse drive signal (V o);
Driver module (3), described driver module (3) is coupling between described the first clock signal input terminal and described signal output part, drives control end (Q) to obtain after driving voltage, by the first clock signal (V at it a) be sent to signal output part, as described the first clock signal (V a) while being high level, driver module (3) is to drawing charging on signal output part; As the first clock signal (V a) while being low level, driver module (3) is to signal output part (V o) drop-down electric discharge;
Low level maintains module (5), and described low level maintains module (5) and is coupling between signal output part and low level end; Described low level maintains module (5) response the first clock signal (V a) high level signal or the 3rd clock signal (V c) high level signal signal output part is coupled to low level end, maintain signal output part low level current potential;
The second load module (2), described the second load module (2) comprises at least one second switch transistor (T14) of cascade, at least one second switch transistor (T14) of described cascade is coupling between described secondary signal input end and described driving control end (Q), and first utmost point of chopped-off head second switch transistor (T14) is used for inputting second clock signal (V b), second utmost point of tail level second switch transistor (T14) is coupling in and drives control end (Q), and the control utmost point of each second switch transistor (T14) is coupling in secondary signal input end, for inputting the second pulse signal (V i2); Under reverse scan pattern, described the second load module (2) response the second pulse signal (V i2) and second clock signal (V b) the overlapping phase signal of high level described driving control end (Q) is charged; Under forward scan pattern, the second pulse signal (V i2) and second clock signal (V b) while being respectively high level and low level, described the second load module (2) discharges to described driving control end (Q);
The first load module (1), described the first load module (1) comprises at least one first switching transistor (T11) of cascade, at least one of described cascade the first switching transistor (T11) is coupling between described first signal input end and described driving control end (Q), and first utmost point of chopped-off head the first switching transistor (T11) is used for inputting the 4th clock signal (V d), second utmost point of tail level the first switching transistor (T11) is coupling in and drives control end (Q), and the control utmost point of each the first switching transistor (T11) is coupling in first signal input end, for inputting the first pulse signal (V i1); Under forward scan pattern, described the first load module (1) response the first pulse signal (V i1) and the 4th clock signal (V d) the overlapping phase signal of high level described driving control end (Q) is charged; Under reverse scan pattern, the first pulse signal (V i1) and the 4th clock signal (V d) while being respectively high level and low level, described the first load module (1) discharges to described driving control end (Q);
Described the first load module (1) also comprises the 15 transistor (T15), and the control utmost point of described the 15 transistor (T15) is for input control signal (V cTR), first utmost point is coupled to second utmost point of chopped-off head the first switching transistor (T11), and second utmost point is coupled to described low level end; Described the 15 transistor (T15) is at control signal (V cTR) second utmost point of chopped-off head the first switching transistor (T11) is coupled to low level end under high level signal control, at control signal (V cTR) the 15 transistor (T15) disconnects under low level signal control;
The first clock signal (V a) and the 3rd clock signal (V c) complementation.
2. a gate drive circuit unit, is characterized in that, comprising:
First signal input end, for inputting the first pulse signal (V i1);
Secondary signal input end, for inputting the second pulse signal (V i2);
The first clock signal input terminal, for inputting the first clock signal (V a);
Signal output part, for exporting pulse drive signal (V o);
Driver module (3), described driver module (3) is coupling between described the first clock signal input terminal and described signal output part, drives control end (Q) to obtain after driving voltage, by the first clock signal (V at it a) be sent to signal output part, as described the first clock signal (V a) while being high level, driver module (3) is to drawing charging on signal output part; As the first clock signal (V a) while being low level, driver module (3) is to signal output part (V o) drop-down electric discharge;
Low level maintains module (5), and described low level maintains module (5) and is coupling between signal output part and low level end; Described low level maintains module (5) response the first clock signal (V a) high level signal or the 3rd clock signal (V c) high level signal signal output part is coupled to low level end, maintain signal output part low level current potential;
The first load module (1), described the first load module (1) comprises at least one first switching transistor (T11) of cascade, at least one of described cascade the first switching transistor (T11) is coupling between described first signal input end and described driving control end (Q), and first utmost point of chopped-off head the first switching transistor (T11) is used for inputting the 4th clock signal (V d), second utmost point of tail level the first switching transistor (T11) is coupling in and drives control end (Q), and the control utmost point of each the first switching transistor (T11) is coupling in first signal input end, for inputting the first pulse signal (V i1); Under forward scan pattern, described the first load module (1) response the first pulse signal (V i1) and the 4th clock signal (V d) the overlapping phase signal of high level described driving control end (Q) is charged; Under reverse scan pattern, the first pulse signal (V i1) and the 4th clock signal (V d) while being respectively high level and low level, described the first load module (1) discharges to described driving control end (Q);
The second load module (2), described the second load module (2) comprises at least one second switch transistor (T14) of cascade, at least one second switch transistor (T14) of described cascade is coupling between described secondary signal input end and described driving control end (Q), and first utmost point of chopped-off head second switch transistor (T14) is used for inputting second clock signal (V b), second utmost point of tail level second switch transistor (T14) is coupling in and drives the control utmost point of control end (Q) each second switch transistor (T14) to be coupling in secondary signal input end, for inputting the second pulse signal (V i2); Under reverse scan pattern, described the second load module (2) response the second pulse signal (V i2) and second clock signal (V b) the overlapping phase signal of high level described driving control end (Q) is charged; Under forward scan pattern, the second pulse signal (V i2) and second clock signal (V b) while being respectively high level and low level, described the second load module (2) discharges to described driving control end (Q);
Described the second load module (2) also comprises the 16 transistor (T16), and the control utmost point of described the 16 transistor (T16) is for input control signal (V cTR), first utmost point is coupled to second utmost point of chopped-off head switch four transistors (T14), and second utmost point is coupled to described low level end; Described the 16 transistor (T16) is at control signal (V cTR) second utmost point of chopped-off head second switch transistor (T14) is coupled to low level end under high level signal control, at control signal (V cTR) the 16 transistor (T16) disconnects under low level signal control;
The first clock signal (V a) and the 3rd clock signal (V c) complementation.
3. gate drive circuit unit as claimed in claim 1, is characterized in that, described the second load module (2) also comprises the 16 transistor (T16), and the control utmost point of described the 16 transistor (T16) is for input control signal (V cTR), first utmost point is coupled to second utmost point of chopped-off head second switch transistor (T14), and second utmost point is coupled to described low level end; Described the 16 transistor (T16) is at control signal (V cTR) second utmost point of chopped-off head second switch transistor (T14) is coupled to low level end under high level signal control, at control signal (V cTR) the 16 transistor (T16) disconnects under low level signal control.
4. the gate drive circuit unit as described in claims 1 to 3 any one, is characterized in that, the number of first switching transistor (T11) of described the first load module (1) cascade is 2.
5. the gate drive circuit unit as described in claims 1 to 3 any one, is characterized in that, the number of the second switch transistor (T14) of described the second load module (2) cascade is 2.
6. the gate drive circuit unit as described in claims 1 to 3 any one, is characterized in that, described the first pulse signal (V i1) and described the second pulse signal (V i2) one, interval clock signal period; Second clock signal (V b) and the 4th clock signal (V d) complementation;
Under forward scan pattern, the 4th clock signal (V d) lag behind the first pulse signal (V i1) phase place, the first clock signal (V a) lag behind the 4th clock signal (V d) phase place;
Under reverse scan pattern, second clock signal (V b) lag behind the second pulse signal (V i2) phase place, the 4th clock signal (V d) lag behind the first clock signal (V a) phase place;
A described phase place is T/4, the cycle that described T is clock signal.
7. a gate driver circuit, comprising: the gate drive circuit unit of N cascade, and described N is greater than 1 integer; It is characterized in that, chopped-off head adopts the gate drive circuit unit as described in claim 1 or 3; Tail level adopts gate drive circuit unit as claimed in claim 2.
8. a display, is characterized in that, comprising:
Display panel (100), is manufactured with the gate line of first direction and the data line of second direction on described display panel;
Gate driver circuit as claimed in claim 7 (200), in gate driver circuit (200), the signal output part of drive element of the grid is coupled to the gate line corresponding with it;
Timing sequence generating circuit (300), for generation of the required various control signals of gate driver circuit (200);
Data drive circuit (400), for generation of viewdata signal, and is outputed on data line corresponding with it in display panel (100).
9. a logical transport circuit, is characterized in that, comprising:
The first logic signal input end, for inputting the first logic control signal;
The second logic signal input end, for inputting the second logic control signal;
Signal transmission input end, for inputting signal transmission;
Signal is followed end;
At least one switching transistor of cascade, at least one switching transistor of described cascade is coupling in described the first logic signal input end and described signal is followed between end, first utmost point of chopped-off head switching transistor is used for inputting signal transmission, second utmost point of tail level switching transistor is coupling in signal and follows end, the control utmost point of each switching transistor is coupling in the first logic signal input end, for inputting the first logic control signal;
First controls transistor, described first controls the transistorized control utmost point is coupled to the second logic signal input end, be used for inputting the second logic control signal, first utmost point is coupled to second utmost point of chopped-off head switching transistor, first controls transistorized second utmost point is used for being coupled to low level end, in the time that the switching transistor of the second logic control signal disconnection and cascade described in described the first control transient response responds the first logic control signal conducting, signal transmission is applied to signal and follows end, in the time that described first controls described in transient response the second logic control signal conducting, second utmost point of chopped-off head switching transistor is coupled to low level end.
10. logical transport circuit as claimed in claim 9, is characterized in that, also comprises the second control transistor;
Transistorized first utmost point of described the second control is coupled to signal and follows end, and second utmost point is used for being coupled to low level end, controls the utmost point for inputting the non-signal of the first logic control signal;
In the time that the first logic control signal and the second logic control signal are significant level simultaneously, the switching transistor conducting of cascade, first controls transistor and second controls transistor and disconnects, and signal transmission is applied to signal and follows end;
In the time that the first logic control signal is inactive level, the second control transistor turns is followed end by signal and is coupled to low level end;
In the time that the second logic control signal is inactive level, first controls transistor turns is coupled to low level end by second utmost point of chopped-off head switching transistor.
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