KR100940999B1 - Shift register for display device - Google Patents

Abstract

PURPOSE: A shift register for display is provided to perform an individual operation without mutual interwork between registers by comprising a shift register of a decoder type using an amorphous silicon thin film transistor. CONSTITUTION: An input unit(111) outputs a high voltage switched according to a plurality of input signals from the outside. A first bootstrap(112) performs a bootstrapping function by charging the high voltage supplied from the input unit. A buffer(113) buffers a first input signal inputted by being opened or closed according to the charge voltage from the first bootstrap. A second bootstrap(114) performs the bootstrapping function by charging the high voltage supplied through the buffer. An output unit(115) outputs the high voltage supplied by being opened or closed according to the voltage charged in the second bootstrap. A reset circuit(116) discharges the voltage charged in the second bootstrap and pulls down the high voltage of an output terminal to the low potential according to a reset signal inputted from the outside.

Description

Shift register for display {SHIFT REGISTER FOR DISPLAY DEVICE}

The present invention relates to a shift type for display of a decoder type using an amorphous-silicon thin film transistor.

The shift register is used as a driver circuit of a display, and is utilized by being integrated in a liquid crystal display (LCD) or organic light emitting display (OLED) substrate.

For example, in an active matrix liquid crystal display device used for a computer display device and a television, a video signal line (source line) and a scan drive signal line (gate line) are provided in a matrix shape, and are provided at the intersections of these wirings. Switching elements, such as a thin film transistor, which drive the liquid crystal of each pixel are provided.

Then, a plurality of scan drive signal lines are subjected to a main scan drive signal in which these signal lines are sequentially scanned to turn all switching elements on one scan drive signal line into a conducting state (on state) temporarily. Video signals are supplied in synchronization.

The shift register performs an operation of sequentially supplying the plurality of scan drive signal lines.

Such a shift register has a problem that a change in characteristics of a transistor used during use occurs, and an operation deterioration of the shift register occurs due to such a change in characteristics.

1 and 2 are diagrams illustrating a shift register constituting a conventional gate driver, and show a circuit proposed in Japanese Patent Laid-Open No. 2003-95854.

Referring to FIG. 1, a gate driver is cascaded with a plurality of stages (shift registers SR1, SR2,...).

That is, the output terminal OUT of each stage is connected to the input terminal IN of the next stage. For example, when the number of gate lines is 192, the stages may include 192 stages SR1 to SR192 and one dummy stage SR193 corresponding to the gate lines.

Each stage has an input terminal IN, an output terminal OUT, a control terminal CT, clock input terminals CKV and CKVB, a high potential terminal Von, and a low potential terminal Voff.

A start voltage STV, which is a start signal, is input to the input terminal IN of the first stage SR1. The start signal STV is a pulse signal synchronized with the vertical synchronizing signal.

The output signals of each stage, Gout (1), Gout (2), Gout (3), Gout (4), ... are gate line driving signals for driving the respective gate lines, and are connected to the corresponding gate lines. do. The odd clock stages SR1, SR3, ... are provided with the first clock signal CKV, and the even stages SR2, SR4, ... are provided with the second clock signal CKVB. The first clock signal CKV and the second clock signal CKVB have phases opposite to each other.

Each control terminal CT of the stages SR1, SR2, SR3, ... has output signals Gout (2), Gout (3), Gout (4), which are output signals of the next stage SR2, SR3, SR4, ...; Are input as control signals respectively. That is, the control signal input to the control terminal CT becomes a signal delayed by the duty period of its output signal.

Therefore, since output signals of each stage are sequentially generated with an active period (high state), corresponding gate lines (horizontal lines) are selected in the active period of each output signal.

Referring to the circuit diagram of FIG. 2, each stage (shift register) includes pull-up transistors 1, 3, and 5, a pull-down transistor 7, and a gate output driver 9.

In the gate output driver 9, the transistor NT2 is a pull-up NMOS transistor having a drain connected to the clock input terminal CKV, a gate connected to the first node N1, and a source connected to the output terminal OUT.

The transistor NT3 is a pull-down NMOS transistor having a drain connected to the output terminal OUT, a gate connected to the second node N2, and a source connected to the low potential terminal Voff.

The transistor NT2 is driven by the capacitor C1 and the NMOS transistors NT1, NT4, and NT7.

The capacitor C1 is connected between the first node N1 and the output terminal OUT. The transistor NT1 is connected to an input terminal IN of which a drain is connected to the high potential terminal Von, and a gate thereof receives the output signal Gout (N-1) of the front end, and a source is connected to the first node N1. do. The transistor NT4 is connected to a control terminal CT having a drain connected to the first node N1 and a gate thereof receiving the next output signal Gout (N + 1), and a source connected to the low potential terminal Voff. Connected. The transistor NT7 has a drain connected to the first node N1, a gate connected to the second node N2, and a source connected to the low potential terminal Voff.

The pull-down transistor 7 drives the pull-down NMOS transistor NT3 of the gate output driver 9, and preferably has the function of an inverter composed of two NMOS transistors NT5 and NT6. That is, the pull-down transistor 7 controls the pull-down transistor NT3 to be turned off when the pull-up transistor NT2 is turned on, and the pull-down transistor NT3 to control the pull-down transistor NT3 to be turned on when the pull-up transistor NT2 is turned off. Function of. In the transistor NT5, a drain and a gate are commonly coupled to the high potential terminal Von, and a source thereof is connected to the second node N2. The transistor NT6 has a drain connected to the second node N2, a gate connected to the first node N1, and a source connected to the low potential terminal Voff.

The multi-stage shift registers configured as described above are outputted sequentially by the clock signals CKV and CKVB and the start signal STV. It is not possible to produce output by outputting or reordering.

In addition, the multi-stage shift registers are related to each other, so that if a problem occurs in any one of the shift registers, there is a problem that causes a serious problem as a whole.

SUMMARY OF THE INVENTION An object of the present invention is to provide a shift register for a display in which a decoder-type shift register is formed by using an amorphous-silicon thin film transistor, thereby enabling individual operations without interworking between the registers. There is.

Technical means of the present invention for achieving the above object, the input unit for outputting a high voltage is switched and supplied in accordance with a plurality of input signals input from the outside; A first bootstrap that charges the high voltage supplied through the input unit and provides a bootstrapping function; A buffer unit for buffering and outputting the first input signal which is opened and closed according to the charging voltage supplied from the first bootstrap; A second bootstrap for charging the high voltage supplied through the buffer unit to provide a bootstrapping function; An output unit configured to output a high voltage, which is opened and closed according to the voltage charged in the second bootstrap, to an output terminal; And a reset circuit unit for discharging the voltage charged in the second bootstrap or pulling down the high voltage of the output terminal to a low potential according to a reset signal input from the outside.

In detail, the input unit may be a decoder method that selectively operates according to a plurality of input signals.

The input unit may include a plurality of transistors in which current paths are connected in series between the high potential and the first node, and are switched by receiving different input signals.

The input unit includes: a first transistor connected to a current path between a high potential and a drain of the second transistor to output a high voltage that is opened and closed according to a first input signal input from the outside; A second transistor connected with a current path between a source of the first transistor and a drain of the third transistor to output a high voltage that is opened and closed according to a second input signal input from the outside; And a third transistor connected between a source of the second transistor and a first node having a virtual high potential, and outputting a high voltage that is opened and closed according to a third input signal input from the outside. It is done.

The first bootstrap is composed of a capacitor that charges the high voltage supplied between the first node and the second node of the virtual high potential.

The buffer unit may include a current path connected between a gate of the first transistor and a second node to output a first input signal that is opened and closed according to a high voltage supplied to a first node including a charging voltage of a first capacitor. 4 transistors; And a fifth transistor connected between the second node and the third node, which is a virtual low potential, to open and close according to a signal supplied to the second node, and output a first input signal supplied through a fourth transistor. It is characterized by.

The high voltage supplied to the output unit may be a pulse signal corresponding to a next period of the first input signal input to the input unit.

The shift register may further include a leakage current prevention unit configured to switch according to a plurality of input signals input from the outside to pull down the leakage current output through the buffer unit to a low voltage.

As described above, the present invention configures a decoder-type shift register using an amorphous-silicon thin film transistor, so that individual operations can be performed without requiring mutual interworking between registers, thereby selectively turning on only a desired part of the entire screen. In addition, the PIP screen can be easily implemented.

In addition, even if an error occurs in any one of the shift registers because there is no mutual interaction between the shift registers, there is no problem in the overall operation, thereby ensuring the reliability of the driving operation.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a conceptual diagram illustrating a configuration of a liquid crystal display to which the present invention is applied, a liquid crystal pixel array, a gate driver for distributing and sequentially supplying signals input from the outside to each gate line, and an input digital video signal. Source driver for converting the signal into an analog video signal (pixel voltage) and supplying it to the source lines, and a timing controller for controlling the gate driver and the source driver and supplying the digital video signal to the source driver in accordance with a clock signal. It consists of

The liquid crystal pixel array includes a plurality of gate lines and source lines in a matrix form, and includes a switching element (TFT) for controlling a voltage supplied to the liquid crystal at an intersection of the gate line and the source line, and the switching element. It consists of an active matrix circuit in which a liquid crystal element whose liquid crystal array is adjusted in accordance with the voltage supplied through it is arranged.

The gate driver (shift register) turns on the gate line (scan line) by supplying a predetermined voltage in time series, and the source driver changes the optical state of the liquid crystal by supplying the predetermined voltage to the source line in synchronization with this timing. To drive the liquid crystal display.

At this time, it is necessary to operate the gate driver for supplying the voltage to the gate line at high speed and to supply a sufficient amount of current to the gate line.

As shown in Fig. 4, the gate driver includes a multi-stage shift register.

Although FIG. 3 illustrates the LCD panel, the shift register according to the present invention can be applied not only to a liquid crystal display (LCD) type but also to a display such as an organic light emitting display (OLED).

In addition, the shift register may be directly mounted on a substrate of the liquid crystal panel, and the thin film transistor (TFT) constituting the shift register may be of an amorphous-silicon type.

At present, since all TFT LCD processes are of the amorphous-silicon type, panel makers prefer the amorphous-silicon method because there is no investment cost and no additional cost for the process.

The amorphous-silicon type has a simple process and well-processed conditions, and the TFT manufacturing cost is considerably lower than that of the poly-silicon method. TFT-LCDs are made of amorphous silicon, so circuits such as gate drivers must be made of the same amorphous silicon type to reduce process and cost.

4 is a diagram illustrating multiple stage shift registers of a gate driver according to the present invention, and includes a plurality of signal lines I1 to I7 and multiple stage shift registers SR1 to SRn.

The signals supplied to the plurality of signal lines I1 to I7 are signals transmitted from the timing controller of FIG. 3, and are configured of a decoder type in which a specific shift register is selected and operated according to a signal input through the signal line. That is, the shift registers SR1 to SRn are structures that operate independently without being dependent on each other.

For example, the multi-stage shift register of FIG. 1 is cascade-connected so that each shift register in turn supplies a voltage as a driving pulse to the gate line, and supplies a predetermined voltage to the gate of the thin film transistor T of the liquid crystal element. Doing

The shift register circuit is configured to output sequentially by the clock signals CKV and CKVB and the start signal STV. However, in this case, the output can be sequentially processed from the first stage. It is not possible to produce output by outputting or reordering.

However, in the case of the present invention, as shown in FIG. 4, each of the shift registers SR1 to SRn is independently provided regardless of the neighboring shift registers. It is possible to select, and to allow only the selected shift register to drive the gate line. That is, it is possible to turn on only a part of the necessary screens instead of turning on the entire screen in the display panel, and also facilitates the implementation of the PIP (Picture in Picture) and its control.

In addition, the existing shift registers as shown in FIG. 1 are related to each other, and when a problem occurs in any one of the shift registers, a problem occurs in the subsequent registers in succession, causing a serious error. However, since the shift registers SR1 to SRn according to the present invention operate independently of each other, even if a problem occurs in a specific shift register, the shift registers SR1 to SRn operate without any problem.

In the embodiment of FIG. 4, there are seven signal lines, that is, three lines I1, I2 and I3 to which the first input signal IN1 is supplied, and two to which the second input signal IN2 is supplied. It consists of the lines I4 and I5 and the two lines I6 and I7 to which the third input signal IN3 is supplied. That is, the multi-stage shift registers SR1 to SRn have at least one input signal line configured differently from other shift registers.

In this case, 12 shift registers can be configured by 3 * 2 * 2. This is only an embodiment, and it is natural that more shift registers can be configured by increasing the signal lines to which the first to third input signals IN1 to IN3 are supplied. If you need to drive a QVGA pixel, 8 * 8 * 5 = 320, so you can drive 320 gate lines with a total of 21 lines.

As such, the waveform of the signal supplied to each signal line is shown in FIG. 5.

As shown in FIG. 5, pulses I1, I2, and I3 corresponding to the first input signal IN1, pulses I4 and I5 corresponding to the second input signal IN2, and pulse I6 corresponding to the third input signal IN3. It consists of I7.

Input waveforms of the plurality of first input signals I1, I2, and I3 periodically move, a plurality of second input signals I4 and I5 also periodically move, and a plurality of third input signals I6. , I7) also moves periodically. The pulse width of the second input signal I4 or I5 is equal to the sum of the pulse widths of the first input signals I1, I2, and I3, and the pulse width of the third input signal I6 or I7. Is set equal to the sum of the pulse widths of the second input signals I4 and I5.

In this way, the number of shift registers is determined according to the number of input pulses.

6 is a circuit diagram illustrating a unit configuration of a shift register according to an exemplary embodiment of the present invention. The shift register 110 includes an input unit 111, a first bootstrap 112, a buffer unit 113, and a second bootstrap ( 114, an output unit 115, a reset circuit unit 116 and a leakage current prevention unit 117.

The input unit 111 includes a plurality of transistors T1 to T3 connected in series to output high voltages that are switched and supplied according to a plurality of input signals input from the outside.

For example, the input unit 111 includes first, second and third transistors T1 to T3, and the number of shift registers may be increased or decreased according to the number of input lines input to the input unit 111. That is, as the number of shift registers increases, the number of input power sources input to the input unit 111 increases. In addition, the input unit 111 is a decoder type that selectively operates according to a plurality of input signals. For example, the input unit 111 may be selectively operated according to a plurality of input signals input from a timing controller.

The high voltage Vdd of the first transistor T1 is connected to a current path between the high potential Vdd and the drain of the second transistor T2, and is opened and closed according to the first input signal IN1 input from the outside. The second transistor T2 is configured to output a current, and a current path is connected between the source of the first transistor T1 and the drain of the third transistor T3 to input the second input signal IN2 input from the outside. Is configured to output a high voltage Vdd that is opened and closed according to the current, and the third transistor T3 has a current path between the source of the second transistor T2 and the first node Nd1 having a virtual high potential. The high voltage Vdd connected to the third input signal IN3 input from the outside and supplied is output.

The first bootstrap 112 is configured of a first capacitor C1 having a bootstrapping function to more quickly and stably output an input signal by charging a high voltage supplied through the input unit 111. The first capacitor C1 is connected between the first node Nd1 and the second node Nd2 which are virtual high potentials to charge the supplied high voltage Vdd.

The buffer unit 113 includes fourth and fifth transistors T4 and T5 that buffer and output the first input signal IN1 that is opened and closed according to the charging voltage supplied from the first bootstrap 112. have. That is, the fourth transistor T4 is connected to a current path between the gate of the first transistor T1 and the second node Nd2 and supplied to the first node Nd1 including the charging voltage of the first capacitor C1. The first input signal IN1 that is opened and closed according to the high voltage is output, and the fifth transistor T5 has a current path between the second node Nd2 and the third node Nd3 which is a virtual low potential. A drain and a gate which are connected to each other and are opened and closed according to a signal supplied to the second node Nd2 to output the first input signal IN1 supplied through the fourth transistor T4 are connected to each other.

The second bootstrap 114 includes a second capacitor C2 having a bootstrapping function to more quickly and stably output an input signal by charging the high voltage supplied through the buffer unit 113. The second capacitor C2 is connected between the third node Nd3 and the output terminal to charge the first input signal IN1 of the high voltage supplied.

The output unit 115 includes a sixth transistor T6 that opens and closes according to the voltage charged in the second bootstrap 114 and outputs a high voltage pulse V_in supplied to the output terminal to the output terminal. The sixth transistor T6 is connected to a current path between the second input signal IN2 and the output terminal, and is opened and closed according to the high voltage supplied to the third node Nd3 including the charging voltage of the second capacitor C2. It is configured to output the high voltage pulse signal V_in supplied from the circuit.

The reset circuit unit 116 discharges the voltage charged in the second bootstrap 114 or pulls down the high voltage of the output terminal according to a reset signal Reset input from the outside. Consists of That is, the seventh transistor T7 connects a current path between the third node Nd3 and the low potential Vss, opens and closes according to a reset signal input from the outside, and receives the voltage charged in the second bootstrap 114. The eighth transistor T8 is configured to discharge a current path between the output terminal and the low potential, open and close according to a reset signal input from the outside, and pull down the voltage at the output terminal to a low voltage.

The leakage current preventing unit 117 is switched in accordance with a plurality of input signals input from the outside, and pulls down the first input signal IN1 output through the buffer unit 113 to the low potential Vss. (T9, T10, T11).

For example, the leakage current preventing unit 117 is composed of ninth, tenth, and eleventh transistors T9 to T11, and the ninth transistor T9 includes a first input signal terminal IN1 and a fourth node ( A current path is connected between Nd4 and configured to output a first input signal IN1 that is opened and closed according to a first input signal IN1 input from the outside, and the tenth transistor T10 is a third node. The current path is connected between the Nd3 and the low potential Vss, and is configured to pull down the signal of the leaked third node Nd3 to the low potential by opening and closing according to the signal supplied to the fourth node Nd4. The eleventh transistor T11 is connected to a current path between the fourth node Nd4 and the low potential Vss, opened and closed according to the second input signal IN2 input from the outside, and is output through the buffer unit 113. The first input signal IN1 is configured to pull down to the low potential Vss.

The first to eleventh transistors T1 to T11 are amorphous-silicon thin film transistors and have a threshold voltage of about 3V. In addition, since the amorphous-silicon thin film transistor has a bidirectional characteristic in which current flows in either direction depending on the potential, the names of the drain and the source are named for convenience of description and are not significant.

The overall operation of the shift register configured as described above is as follows.

When the first input signal IN1, the second input signal IN2, and the third input signal IN3 of the first to third transistors T1 to T3 are all input with a clock signal having a high voltage, the first to third transistors are input. All of the three transistors T1 to T3 are turned on to turn on the fourth transistor T4 while the high voltage of about 25 V or more supplied from the outside is charged in the first capacitor C1. Here, the fourth transistor T4 is improved in driving ability by bootstrapping by the first capacitor C1. In addition, when the threshold voltage of each transistor is assumed to be 3V, the first capacitor C1 is charged with a voltage of approximately 16V minus the threshold voltage of each of the transistors T1 to T3.

Accordingly, the first input signal IN1 having a high voltage of about 20 V or more passes through the fifth transistor T5 while being turned on to charge the second capacitor C2. Of course, the voltage charged in the second capacitor C2 may be charged by subtracting the threshold voltages of the fourth and fifth transistors T4 and T5 from the voltage of the first input signal IN1.

At this time, the sixth transistor T6 is turned on according to the voltage charged in the second capacitor C2 and the clock signal V_in of the high voltage supplied from the outside is outputted to the output terminal through the sixth transistor T6. do. The high voltage clock signal V_in is a pulse signal corresponding to a next period of a pulse input to the gate of the first transistor T1 among the plurality of first input signals I1, I2, and I3.

After the output, the reset signal is supplied from the outside. The reset signal Reset is reset at the next period of the pulse supplied to the sixth transistor T6 among the plurality of first input signals I1, I2, and I3. Corresponding pulse signal.

That is, the seventh transistor T7 is turned on in response to the input reset signal to discharge the voltage charged in the second capacitor C2 at low potential, and the eighth transistor T8 is also turned on in response to the reset signal to provide the output terminal. The potential is pulled down to a low voltage.

In addition, when the output should not go out, for example, the first input signal IN1 having a high voltage is input to the first transistor T1, and the second input signal IN2 having a low voltage is input to the second transistor T2. When the high voltage third input signal IN3 is input to the third transistor T3, the shift register should not emit an output pulse. However, the fourth transistor T4 connected to the first input signal IN1 emits a leakage current and thus an output may appear.

To prevent this, when the output does not need to go out using the ninth, tenth and eleventh transistors T9, T10, and T11, that is, the first input signal IN1 is a high voltage and the second input signal IN2 is When the voltage is low, the ninth transistor T9 operates to turn on the tenth transistor T10. Accordingly, when the leakage current is input through the fifth transistor T5, the output is prevented as the third node Nd3 is pulled down to the virtual low potential according to the turn-on of the tenth transistor T10.

However, when the first and second input signals IN1 and IN2 are both high voltages, the eleventh transistor T11 is turned on and the tenth transistor T10 is turned off. Then, the high voltage pulse of the first input signal IN1 may operate the sixth transistor T6 to output a desired output.

As a result, only the output is sent at the desired output timing.

Therefore, in the present invention, it is possible to drive a shift register of a multi-stage sequence sequentially or non-sequentially by implementing a decoder type shift register by an amorphous-silicon thin film transistor, so that it is possible to select and drive only any desired shift register. Become.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit of the present invention. Therefore, such modifications, changes and additions should be determined not only by the claims below, but also by equivalents to those claims.

1 is a diagram illustrating a shift register constituting a conventional gate driver.

FIG. 2 is a circuit diagram illustrating a detailed configuration of the shift register of FIG. 1.

3 is a conceptual diagram showing the configuration of a liquid crystal display to which the present invention is applied.

4 is a diagram showing a shift register constituting a gate driver according to the present invention.

FIG. 5 is a diagram illustrating an input waveform supplied to each signal line of FIG. 4.

6 is a circuit diagram showing a detailed configuration of a shift register according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

110: shift register 111: input unit

112: first bootstrap 113: buffer unit

114: second bootstrap 115: output unit

116: reset circuit portion 117: leakage current prevention portion

Claims (7)

An input unit which outputs a high voltage which is switched and supplied according to a plurality of input signals input from the outside; A first bootstrap that charges the high voltage supplied through the input unit and provides a bootstrapping function; A buffer unit for buffering and outputting the first input signal which is opened and closed according to the charging voltage supplied from the first bootstrap; A second bootstrap for charging the high voltage supplied through the buffer unit to provide a bootstrapping function; An output unit configured to output a high voltage, which is opened and closed according to the voltage charged in the second bootstrap, to an output terminal; And And a reset circuit unit configured to discharge a voltage charged in the second bootstrap or pull down a high voltage of an output terminal to a low potential according to a reset signal input from an external device. The method according to claim 1, And the input unit is a decoder system that selectively operates according to a plurality of input signals. The method according to claim 1 or 2, The input unit is a shift register for a display, characterized in that the current path is connected in series between the high potential and the first node, a plurality of transistors are switched to receive different input signals. The method according to claim 1 or 2, A first transistor connected between a high potential and a drain of the second transistor to output a high voltage that is opened and closed according to a first input signal input from the outside; A second transistor connected with a current path between a source of the first transistor and a drain of the third transistor to output a high voltage that is opened and closed according to a second input signal input from the outside; And a third transistor connected between a source of the second transistor and a first node having a virtual high potential, and outputting a high voltage that is opened and closed according to a third input signal input from the outside. Shift register for display. The method according to claim 4, And the first bootstrap comprises a capacitor connected between the first node and the second node having a virtual high potential to charge the supplied high voltage. The method according to claim 5, The buffer unit may include a current path connected between a gate of the first transistor and a second node to output a first input signal that is opened and closed according to a high voltage supplied to a first node including a charging voltage of a first capacitor. 4 transistors; And a fifth transistor connected between the second node and the third node, which is a virtual low potential, to open and close according to a signal supplied to the second node, and output a first input signal supplied through a fourth transistor. A shift register for display, characterized in that. The method according to claim 1, And a leakage current prevention unit which is switched according to a plurality of input signals input from the outside and pulls down the leakage current output through the buffer unit to a low voltage.

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