KR20050065816A - Shift register and shift register with built-in level shifter - Google Patents

Abstract

The present invention relates to a shift register incorporating a shift register and a level shifter capable of preventing deterioration in image quality.

The shift register of the present invention is composed of a plurality of stages for shifting an input signal with first and second supply voltages and phase delayed control signals to supply the respective output signals and the next stage input signals. Each using first to third transistors having conductive paths between an input signal supply line and the first supply voltage input line to selectively supply the input signal and the first supply voltage to a first node therebetween. 1 control unit; Selectively supplying the second and first supply voltages to a second node therebetween using fourth and fifth transistors having conductive paths between the second supply voltage input line and the first supply voltage input line. A second control unit; To the output line of the stage between them using sixth and seventh transistors having a conductive path between the input line of any one of the first to fourth control signals and the first supply voltage input line. An output buffer unit for selectively supplying the specific control signal and the first supply voltage to the output signal; And an eighth transistor configured to delay a specific voltage state of an output signal output from the output line of the stage according to a fifth control signal having a different duty ratio from the first to fourth control signals.

Description

Shift register with built-in shift register and level shifter {SHIFT REGISTER AND SHIFT REGISTER WITH BUILT-IN LEVEL SHIFTER}

The present invention relates to a shift register incorporating a shift register and a level shifter, and more particularly, to a shift register incorporating a shift register and a level shifter capable of preventing image degradation.

A liquid crystal display device used as a display device of a television and a computer displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines.

The driving circuit includes a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially supplies scan signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel. The data driver supplies a video signal to each of the data lines whenever a scan signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the video signal for each liquid crystal cell.

In this driving circuit, the gate driver generates a scan signal for sequentially driving the gate lines using the shift register. The data driver generates a sampling signal for sequentially sampling the video signal input from the outside by a predetermined unit using the shift register. The gate driver and the data driver including the shift register are embedded in the liquid crystal panel together with the liquid crystal matrix when using polysilicon.

1 illustrates a general shift register, and FIG. 2 illustrates input and output waveforms of the shift register illustrated in FIG. 1.

The shift register shown in FIG. 1 has n stages ST1 to STn connected to the start pulse SP input line and supplied with three clock signals among the four clock signals C1 to C4. Referring to FIG. 2, the first to fourth clock signals C1 to C4 are supplied in phase-delayed form by one clock in the order of C4, C1, C2, and C3 through respective supply lines. The start pulse SP, which is supplied in one frame or one horizontal period, is supplied in synchronization with the fourth clock signal C4.

 The first stage ST1 outputs the first output signal SO1 as shown in FIG. 2 using the start pulse SP and three clock signals among the four clock signals C1 to C3. The second to nth stages ST2 to STn are formed as shown in FIG. 2 using the output signals S01 to S0n−1 and three clock signals among the four clock signals C1 to C3. The second to nth output signals SO2 to SOn are output. In other words, the first to nth stages ST1 to STn constituting the shift register output the first to nth output signals SO1 to SOn having a form shifted in phase as shown in FIG. 2. The first to n th output signals SO1 to SOn are supplied as scan signals for sequentially driving the gate lines of the liquid crystal panel or as sampling signals for sequentially sampling the video signals in the data driver.

FIG. 3 illustrates a detailed circuit configuration of the first stage ST1 shown in FIG. 1.

The first stage ST1 illustrated in FIG. 3 includes a first control unit 32 that controls the Q node according to the start pulse SP and the fourth clock signal C4, and the third clock signal C3 and the start pulse. Selecting and outputting one of the first clock signal C1 and the first supply voltage VSS according to the voltage of the Q node and the QB node, and the second control unit 34 that controls the QB node according to (SP). A buffer unit 36 is provided.

The first control unit 32 includes a first PMOS transistor T1 diode-connected to the start pulse SP input line, between the first PMOS transistor T1, the fourth clock signal C4 input line, and the Q node. And a second PMOS transistor T2 connected to it. The first controller 32 is connected between the Q node and the QB node and the first supply voltage VSS input line to control the Q node in dual operation with the seventh PMOS transistor T7. ) Is further provided.

The second control unit 34 may include a fourth PMOS transistor T4 and a fourth PMOS transistor T4 connected between the second supply voltage VDD input line, the third clock signal C3 input line, and the QB node. And a fifth PMOS transistor T5 connected between the start pulse SP input line and the first supply voltage VSS input line.

The buffer unit 36 selects the first clock signal C1 according to the voltage of the Q node and supplies the sixth PMOS transistor T6 to the output line and the first supply voltage VSS according to the voltage of the QB node. And a seventh PMOS transistor T7 that selects and supplies the output line.

The first stage ST1 further includes a first capacitor CB connected between the gate terminal and the source terminal of the sixth PMOS transistor T6, that is, between the Q node and the output line.

C1, C3, and C4 of the first to fourth clock signals C1 to C4 shown in FIG. 2 are supplied to the first stage ST1. In FIG. 2, the first to fourth clock signals C1 to C4 including the start pulse SP are supplied in a negative type having a swing voltage of 10 V or more. For convenience of explanation, a description will be given on the assumption that the potential of 10V is low and the potential of 0V is high. In addition, it is assumed that about 10V supplied to the first supply voltage VSS supplied to the first stage ST1 is low and about 0V supplied to the second supply voltage VDD is high. A detailed operation of the first stage ST1 will be described with reference to the driving waveform as follows.

In the t1 period, when the start pulse SP and the fourth clock signal C4 become high at the same time, the first and second PMOS transistors T1 and T2 are turned on so that the Q node is in the first high state. As a result, the sixth PMOS transistor T6 having the gate terminal connected to the Q node is gradually turned on. At this time, since the fifth PMOS transistor T5 is turned on by the high start pulse SP and the QB node is turned low by the first supply voltage VSS, the gate terminal is connected to the QB node. The third and seventh PMOS transistors T3 and T7 are turned off. As a result, the low state voltage (about 17 V) of the first clock signal C1 is output as the output signal SO1 of the first stage ST1 through the turned-on sixth PMOS transistor T6.

During the t2 period, the start pulse SP and the fourth clock signal C4 go low and the first clock signal C1 goes high to turn off the first and second PMOS transistors T1 and T2. The sixth PMOS transistor T6 is in a certain turn-on state. This is due to the influence of the internal capacitor Cgs and the first capacitor CB formed between the gate and the source of the sixth PMOS transistor T6 in the floating Q node according to the high state voltage of the first clock signal C1. This is because the bootstrapping is a second high state higher than the first high state. Thus, the sixth PMOS transistor T6 is reliably turned on so that the high state voltage (about 0 V) of the first clock signal C1 is rapidly supplied to the output line of the stage ST1. As a result, the first stage ST1 outputs the output signal SO1 in the high state.

In the t3 period, the first clock signal C1 goes low and the second clock signal C2 goes high, whereby the voltage of the Q node in the floating state transitions back to the first high state and the sixth PMOS transistor T6. Remains turned on. Accordingly, the low state voltage (about 17 V) of the first clock signal C1 is output as the output signal SO1 through the turned-on sixth PMOS transistor T6.

In the t4 period, the third clock signal C3 becomes high and the fourth PMOS transistor T4 is turned on so that the QL node is supplied with a high state voltage (about 0 V), which is the second supply voltage VDD. Accordingly, the third and seventh PMOS transistors T3 and T7 are turned on at the same time. The sixth PMOS transistor T6 is turned off because the first supply voltage VSS in a low state is supplied to the Q node through the turned-on third PMOS transistor T3. The first supply voltage VSS in the low state is output as the output signal SO1 of the first stage ST1 via the turned-on seventh PMOS transistor T7.

In the t5 period, only the fourth clock signal C4 becomes high to turn on the second transistor T2, and the first, fourth and fifth PMOS transistors T1, T4, and T5 remain turned off. As a result, the QB node remains at its previous high state. Accordingly, since the third and seventh PMOS transistors T3 and T7 maintain the turn-on state as in the t4 period described above, the output signal SO1 of the first stage ST1 remains low.

The conventional shift register outputs the output signals SO1, SO2, SO3 ... as shown in FIG. However, such output signals SO1, SO2, SO3... Are likely to overlap each other. Accordingly, there is a disadvantage that the image quality is lowered. In other words, when the output signal of the high state is changed to the output signal of the low state in the front stage ST as shown in Figs. 4A to 4C detailing the portion "A" shown in Fig. 2, the next stage ST is low. The output signal of the state changes to the output of the high state. At this point in time, the output signal in the low state is changed to the output signal in the high state before the output signal in the high state is changed to the low state output signal in the front stage ST. Accordingly, the two output signals are overlapped with each other, and thus the image quality is deteriorated.

Accordingly, it is an object of the present invention to provide a shift register incorporating a shift register and a level shifter capable of preventing deterioration in image quality.

In order to achieve the above object, the shift register of the present invention includes a plurality of stages for shifting an input signal by the first and second supply voltages and phase delayed control signals to supply the respective output signals and the next stage input signals. Wherein each of the stages uses the first to third transistors having conductive paths between an input signal supply line and the first supply voltage input line to supply the input signal and first supply to a first node therebetween. A first controller selectively supplying a voltage; Selectively supplying the second and first supply voltages to a second node therebetween using fourth and fifth transistors having conductive paths between the second supply voltage input line and the first supply voltage input line. A second control unit; To the output line of the stage between them using sixth and seventh transistors having a conductive path between the input line of any one of the first to fourth control signals and the first supply voltage input line. An output buffer unit for selectively supplying the specific control signal and the first supply voltage to the output signal; And an eighth transistor configured to delay a specific voltage state of an output signal output from the output line of the stage according to a fifth control signal having a different duty ratio from the first to fourth control signals.

The first and second transistors each have a conductive path between the input signal supply line and the first node, and a control electrode for controlling the conductive path according to the input signal and the first control signal, respectively, and the third The transistor is characterized by having a conductive path between the first node and the first supply voltage input and a control electrode for controlling the conductive path according to the voltage of the second node.

The fourth transistor has a conductive path between the second supply voltage input line and the second node and a control electrode for controlling the conductive path according to a second control signal, wherein the fifth transistor is connected to the second node. And a control electrode for controlling the conductive path between the first supply voltage input line and the conductive path according to the first control signal.

The sixth transistor has a conductive path between a third control signal input line and an output line of the stage, and a control electrode for controlling the conductive path according to the voltage of the first node, and the seventh transistor has an output of the stage. And a control electrode for controlling the conductive path between the line and the first supply voltage input line according to the voltage of the second node.

The sixth transistor further includes a capacitor connected between the gate electrode and the output line of the stage for bootstrapping the gate electrode thereof.

The third transistor may include a dual gate transistor in which a gate electrode is commonly connected to the second node.

The fifth transistor may include a dual gate transistor in which a gate electrode is commonly connected to the first control signal.

In the eighth transistor, a conductive path is formed between the output line of the stage and the first supply voltage input line by the control of the fifth control signal.

The fifth control signal may have a smaller duty width than the first to fourth control signals.

The stage is characterized by consisting of transistors of the same channel type.

The stage is characterized by consisting of a PMOS transistor.

The second supply voltage is greater than the first supply voltage.

The first supply voltage is characterized in that the negative voltage.

Three clock signals of the first to fourth clock signals having a specific voltage state at different phases and at the same period may be supplied to the first to third control signals.

The third control signal may have a phase delayed form by one clock than the first control signal, and the second control signal may have a phase delayed by two clocks than the third control signal.

The input signal may include a portion having an in phase with the first control signal.

The shift register may be applied to at least one of a scan driver driving scan lines of a display device and a data driver driving data lines of a display device.

The shift register with a built-in level shifter according to an embodiment of the present invention is provided with a plurality of stages that are cascade-connected and sequentially output a shift pulse by shifting a start pulse input through an input terminal. A shift register having a level shifter having a plurality of level shifters for level shifting and outputting a voltage level of a shift pulse, wherein the stages each include a first control signal and a first supply according to voltages of the first and second nodes. A buffer unit for outputting the shift pulse using a voltage; A first control unit controlling the voltage of the first node according to the start pulse and the voltage of the second node; And a second controller configured to control the voltage of the second node by using the first and second supply voltages according to the start pulse and the second control signal, wherein each of the level shifters corresponds to a voltage of the first node. A third controller configured to control a voltage of a third node using a third supply voltage and the first supply voltage according to a third control signal; An output buffer which causes the third node voltage to be bootstraped in at least one step and selectively outputs the first and third supply voltages according to a voltage and a fourth control signal of the third node bootstrapped in the at least one step And a fourth controller for delaying a specific voltage state of an output signal output from an output line of the third node and the output buffer unit according to a fifth control signal having a different duty ratio from the first to fourth control signals. do.

The first control unit includes a first transistor having a conductive passage between the start pulse and the first node, a control electrode controlling the conductive passage according to the start pulse, an output terminal of the first transistor, and the first transistor. A second transistor having a conductive passage between nodes and a control electrode for controlling the conductive passage according to a third control signal, a conductive passage between the first node and an input line of the first supply voltage, and a conductive passage thereof And a third transistor having a control electrode controlling the voltage according to the voltage of the second node.

The second control unit includes: a fourth transistor having a conductive passage between the second supply voltage input line and the second node and a control electrode controlling the conductive passage according to the second control signal; And a fifth transistor having a conductive passage between the second node and the first supply voltage input line and a control electrode controlling the conductive passage according to the start pulse.

The buffer unit includes a sixth transistor having a conductive path between the first control signal input line and an output line of the stage, and a control electrode controlling the conductive path according to the voltage of the first node; And a seventh transistor having a conductive passage between the output line of the stage and the first supply voltage input line, and a control electrode for controlling the conductive passage according to the voltage of the second node.

The buffer unit further includes a capacitor connected between the control electrode of the sixth transistor and the output line of the stage to bootstrap the voltage of the control electrode.

The stage further includes a capacitor for preventing voltage distortion of the second node due to leakage current of the fifth transistor.

The third transistor may include a dual gate transistor in which a gate electrode is commonly connected to the second node.

The fifth transistor may include a dual gate transistor in which a gate electrode is commonly connected to the third node.

The third controller includes: an eighth transistor having a conductive path between the input line of the third supply voltage and the third node and a control electrode controlling the conductive path according to an output signal of the stage; And a ninth and tenth transistor having a conductive path between the third node and an input line of the first supply voltage and a control electrode for controlling the conductive path according to the third control signal.

The output buffer unit includes an eleventh transistor having a conductive path between the third supply voltage input line and the third node and a control electrode controlling the conductive path according to the voltage of the third node; And a twelfth transistor having a conductive path between the output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the fourth control signal.

The level shifter may include a conductive path between the third node and an output line of the level shifter, and a thirteenth transistor configured to control the conductive path according to the fourth control signal; A fourteenth transistor configured to control a conductive path between the output line of the level shifter and the first supply voltage input line and the conductive path according to the third control signal; A fifteenth transistor for controlling a conductive path between the output lines of the third and level shifters and the conductive path according to the voltage of the second node; And a sixteenth transistor configured to control the conductive path between the output line of the level shifter and the first supply voltage input line and the conductive path according to the voltage of the second node.

The level shifter further includes a seventeenth transistor diode-connected between the input line of the third supply voltage and the eighth transistor.

The output buffer unit includes a capacitor connected in series between the third node and an output line of the level shifter for the first stage bootstrapping.

The eighth transistor may include a dual gate transistor having a gate electrode commonly connected to the first node.

The fourth controller includes: a seventeenth transistor having a conductive passage between the first supply voltage input line and the third node and a control electrode controlling the conductive passage according to the fifth control signal; And an eighteenth transistor having a conductive passage between the first supply voltage input line and an output line of the level shifter and a control electrode for controlling the conductive passage in accordance with the fifth control signal.

The fifth control signal may have a smaller duty width than the first to fourth control signals.

The stages and level shifters may be constituted only by thin film transistors of the same type channel.

The first to third supply voltages are characterized by having a third <second <first magnitude relationship.

The third supply voltage may be a negative voltage.

The first to fourth control signals may have a specific voltage state which is phase-delayed in order of first, fourth, second, and third, and the third control signal may have an in phase with the start pulse.

The stages and level shifters may be composed of only P-channel thin film transistors.

The level shifter may be configured to lower the lowest voltage level of the shift pulse to the third supply voltage to output the shifted voltage.

The shift register may be applied to at least one of a scan driver driving scan lines of a display device and a data driver driving data lines of a display device.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 10.

FIG. 5 shows a detailed circuit of one stage constituting the shift register according to the first embodiment of the present invention, and FIG. 6 shows input / output waveforms of the stage shown in FIG.

The stage ST shown in FIG. 5 includes a first control unit 142 for controlling the Q node according to the start pulse SP and the fourth clock signal C4, and a third clock signal C3 and the start pulse SP. A second control unit 144 for controlling the QB node and a buffer for selecting and outputting any one of the first clock signal C1 and the first supply voltage VSS according to the voltages of the Q node and the QB node. And a third controller 148 for delaying a specific voltage state of the output signal according to the inter clock Inter_CLK.

The first control unit 142 may include an eleventh PMOS transistor T11 diode-connected to the start pulse SP input line, between the eleventh PMOS transistor T11, the fourth clock signal C4 input line, and the Q node. And a twelfth PMOS transistor T12 connected to it. The first controller 142 is connected between the Q node and the QB node and the first supply voltage VSS input line to control the Q node in dual operation with the seventeenth PMOS transistor T17. The transistors T13A and T13B are further provided. Here, the thirteenth and thirteenth PMOS transistors T13A and T13B have a dual gate structure, thereby increasing the threshold voltage Vth to minimize leakage current.

The second controller 144 may include a fourteenth PMOS transistor T14 connected between a second supply voltage VDD input line, a third clock signal C3 input line, and a QB node, and a fourteenth PMOS transistor T14. 15A and 15B PMOS transistors T15A and T15B connected between the start pulse SP input line and the first supply voltage VSS input line. Here, the 15A and 15B PMOS transistors T15A and T15B have a dual gate structure, thereby increasing the threshold voltage Vth to minimize leakage current.

The buffer unit 146 selects the first clock signal C1 according to the voltage of the Q node and supplies the sixteenth PMOS transistor T16 to the output line and the first supply voltage VSS according to the voltage of the QB node. And a seventeenth PMOS transistor (T17) for selection and supply to an output line.

The third controller 148 includes an eighteenth PMOS transistor T18 for supplying the first supply voltage VSS to the output line according to the inter clock Inter_CLK signal to delay a specific voltage state of the output signal. Here, the inter clock Inter_CLL is set to have a smaller duty ratio than the first to fourth clock signals C1 to C4.

The stage ST includes an eleventh capacitor CB connected between the gate terminal and the source terminal of the sixteenth PMOS transistor T16, that is, between the Q node and the output line, and the Q node and the first supply voltage VSS. A thirteenth capacitor CQ connected between the input lines and a thirteenth capacitor CQ connected between the gate terminal and the source terminal of the seventeenth PMOS transistor T17, that is, between the QB node and the first supply voltage VSS input line CQB) is further provided. Herein, the eleventh capacitor CB causes the voltage of the Q node to be bootstrapping and rises in a specific period, and each of the twelfth and thirteenth capacitors CQ and CQB shares the noise components of the Q node and the QB node. Passed.

As the eleventh to eighteenth transistors T11 to T18 constituting such a stage, a PMOS or NMOS transistor is used. Hereinafter, for convenience of description, only the case where the PMOS transistor is applied will be described as an example.

The stage shown in FIG. 5 controls C1, C3, and C4 of the first to fourth clock signals C1 to C4 having a phase delayed form in order of C4, C1, C2, and C3 as shown in FIG. It is input as a signal. In FIG. 6, the first to fourth clock signals C1 to C4 including the start pulse SP are supplied in a negative polarity type having a swing voltage of 10 V or more. For convenience of explanation, a description will be given on the assumption that the potential of 10V is low and the potential of 0V is high. In addition, it is assumed that about 10V supplied to the first supply voltage VSS supplied to the stage is low and about 0V supplied to the second supply voltage VDD is high. Referring to these driving waveforms, the specific operation of the stage is as follows.

When the start pulse SP and the fourth clock signal C4 become high at the same time in the t1 period, the eleventh and twelfth PMOS transistors T11 and T12 are turned on so that the Q node has the first high state H1. do. As a result, the sixteenth PMOS transistor T16 having the gate terminal connected to the Q node is gradually turned on. At this time, since the start pulse SP is in a high state, the 15A and 15B PMOS transistors T15A and T15B are turned on, and the QB node is turned low by the first supply voltage VSS. The thirteenth and thirteenth PMOS transistors T13A and T13B and the seventeenth PMOS transistor 1T7 to which the gate terminals are connected are turned off. As a result, the low state voltage (about 17 V) of the first clock signal C1 is output as the output signal SO1 of the first stage ST1 through the turned-on sixteenth PMOS transistor T16.

During the t2 period, the start pulse SP and the fourth clock signal C4 go low and the first clock signal C1 goes high, thereby turning the eleventh and twelfth PMOS transistors T11 and T12 off. The sixteenth PMOS transistor T16 is turned on. The Q node in the floating state is influenced by the high state voltage of the first clock signal C1 due to the influence of the internal capacitor Cgs and the first capacitor CB formed between the gate and the source of the sixteenth PMOS transistor T16. This is because the bootstrapping is performed so that the second high state H2 is higher than the first high state H1. Thus, the sixteenth PMOS transistor T16 is reliably turned on so that the high voltage (about 0 V) of the first clock signal C1 is rapidly supplied to the output line of the stage ST1. At this time, the inter clock Inter_CKL signal becomes high for a predetermined period at the same time when the first clock signal C1 becomes high. Accordingly, the eighteenth PMOS transistor T18 is turned on. As a result, the first supply voltage VSS is supplied to the output line of the first stage ST1 while the inter clock Inter_CLK signal is high through the turned-on eighteenth PMOS transistor T18. The first supply voltage VSS is supplied to an output line of the first stage ST1 while the inter clock signal Inter_CLK is in a high state even when the first clock signal C1 is in a high state. Accordingly, the output line of the first stage ST1 maintains the low voltage while the inter clock signal Inter_CLK is high. Subsequently, when the inter clock signal Inter_CLK becomes low, the high voltage (about 0 V) of the first clock signal C1 is rapidly supplied to the output line of the first stage ST1, and thus the first stage ST1. Outputs the first output signal SO1. As a result, the first stage ST1 outputs the output signal SO1 in the high state.

In the t3 period, the first clock signal C1 goes low and the second clock signal C2 goes high, whereby the voltage of the Q node in the floating state transitions back to the first high state and the sixteenth PMOS transistor T16. Remains turned on. Accordingly, the low state voltage (about 17V) of the first clock signal C1 is output as the output signal SO1 through the turned-on sixteenth PMOS transistor T16. On the other hand, in the t3 period, the second stage ST2 operates the first stage ST1 in the t2 period. Accordingly, when the second clock signal C2 is in the high state, the inter clock signal Inter_CLK is also in the high state for a predetermined period of time, thereby turning on the eighteenth PMOS transistor T18. As a result, the first supply voltage VSS is supplied to the output line of the second stage ST2 while the inter clock Inter_CLK signal is high through the turned-on eighteenth PMOS transistor T18. The first supply voltage VSS is supplied to the output line of the second stage ST2 while the inter clock signal Inter_CLK is in a high state even when the second clock signal C2 is in a high state. Accordingly, the output line of the second stage ST2 maintains the low voltage while the inter clock signal Inter_CLK is high. Subsequently, when the inter clock signal Inter_CLK becomes low, the high voltage (about 0 V) of the second clock signal C2 is rapidly supplied to the output line of the second stage ST2, and the second stage ST2 Outputs the second output signal SO2. The second output signal SO2 is output by being spaced apart as long as the inter clock signal Inter_CLK is high after the first output signal SO1 is output.

In the t4 period, the third clock signal C3 is turned high and the fourteenth PMOS transistor T14 is turned on so that the QB node is supplied with a high voltage (about 0 V), which is the second supply voltage VDD. Accordingly, the thirteenth and thirteenth PMOS transistors T13A and T13B and the seventeenth PMOS transistor T17 are simultaneously turned on. The sixteenth PMOS transistor T16 is turned off because the first supply voltage VSS in a low state is supplied to the Q node via the turned-on 13A and 13B PMOS transistors T13A and T13B. The first supply voltage VSS in the low state is output as the output signal SO1 of the first stage ST1 via the turned-on seventeenth PMOS transistor T17. On the other hand, in the t4 period, the third stage ST3 performs the operation of the second stage ST2 performed in the t3 period. Accordingly, when the third clock signal C3 becomes high, the inter clock signal Inter_CLK also becomes high for a predetermined period of time, thereby turning on the eighteenth PMOS transistor T18. As a result, the first supply voltage VSS is supplied to the output line of the third stage ST3 while the inter clock Inter_CLK signal is high through the turned-on eighteenth PMOS transistor T18. The first supply voltage VSS is supplied to the output line of the third stage ST3 while the inter clock signal Inter_CLK is in a high state even when the third clock signal C3 is in a high state. Accordingly, the output line of the third stage ST3 maintains the low voltage while the inter clock signal Inter_CLK is high. Subsequently, when the inter clock signal Inter_CLK becomes low, the high voltage (about 0 V) of the third clock signal C3 is rapidly supplied to the output line of the third stage ST3, and thus the third stage ST3. Outputs a third output signal SO3. The third output signal SO3 is output by being spaced apart as long as the inter clock signal Inter_CLK is high after the second output signal SO2 is output.

In the t5 period, only the fourth clock signal C4 becomes high, thereby turning on the twelfth transistor T12 and turning on the eleventh, fourteenth, fifteenA, and fifteenth PMOS transistors T11, T14, T15A, and T15B. Because it remains off, the QB node floats to maintain the previous high state. Accordingly, since the thirteenth and seventeenth PMOS transistors T13 and T17 maintain the turn-on state as in the t4 period, the output signal SO1 of the first stage ST1 remains low. On the other hand, in the t5 period, the fourth stage ST4 operates the third stage ST3 performed in the t4 period. Accordingly, when the fourth clock signal C4 is in the high state, the inter clock signal Inter_CLK is also in the high state for a predetermined period of time, thereby turning on the eighteenth PMOS transistor T18. As a result, the first supply voltage VSS is supplied to the output line of the fourth stage ST4 while the inter clock Inter_CLK signal is high through the turned-on eighteenth PMOS transistor T18. The first supply voltage VSS is supplied to the output line of the fourth stage ST4 while the inter clock signal Inter_CLK is in a high state even when the fourth clock signal C4 is in a high state. Accordingly, the output line of the fourth stage ST4 maintains the low voltage while the inter clock signal Inter_CLK is high. Subsequently, when the inter clock signal Inter_CLK becomes low, the high voltage (about 0 V) of the fourth clock signal C4 is rapidly supplied to the output line of the fourth stage ST4, and thus the fourth stage ST4. Outputs a fourth output signal SO4. The fourth output signal SO4 is output by being spaced apart as long as the inter clock signal Inter_CLK is high after the third output signal SO3 is output.

As described above, the stages constituting the shift register according to the first embodiment of the present invention simultaneously receive the intern clock signal Inter_CLK when the first to fourth clock signals C1 to C4 change from a low state to a high state. By turning on the eighteenth PMOS transistor T18, the output signals may be spaced apart for a predetermined period of time when the intern clock signal Inter_CLK is supplied. Accordingly, overlapping of output signals may be prevented to prevent deterioration of image quality.

FIG. 7 shows a detailed circuit configuration of a shift register incorporating a level shifter according to a second embodiment of the present invention, and shows one stage ST and level shifter LS of the shift register circuit.

The stage ST shown in FIG. 7 is a diode type in the start pulse SP input line, and the 21st PMOS transistor T21, the 21st PMOS transistor T21, the fourth clock signal C4 input line, and the Q node. First control section including a twenty-second PMOS transistor T22 connected therebetween, and a twenty-third and twenty-third BMOS transistors T23A and T23B connected between a Q node and a QB node and a first supply voltage VSS input line. 242; 24 th PMOS transistor T24, 24 th PMOS transistor T24, and start pulse SP input line connected between the second supply voltage VDD input line, the third clock signal C3 input line, and the QB node. And a second control unit 244 including 25A and 25B PMOS transistors T25A and T25B connected between a first supply voltage VSS input line; The 26th PMOS transistor T26 selects and supplies the first clock signal C1 to the output line according to the voltage of the Q node, and the first supply voltage VSS is selected and supplied to the output line according to the voltage of the QB node. And a buffer unit 246 having a twenty-seventh PMOS transistor T27. The stage ST includes a twenty-first capacitor CB connected between a gate terminal and a source terminal of the twenty-sixth PMOS transistor T26, that is, a Q node and an output line SO of the stage ST, and a Q node. And a twenty-second capacitor CQ connected between the first and second supply voltage VSS input lines, and a gate terminal and a source terminal of the twenty-seventh PMOS transistor T27, that is, a QB node and a first supply voltage VSS input line. A twenty-third capacitor CQB is further provided.

The level shifter LS includes a third control unit 252 for controlling the QL node according to the stage ST node Q and the start pulse SP (or an output signal of the preceding stage), the voltage of the QL node and the second clock signal. And an output buffer unit 256 for selecting and outputting any one of the negative voltage VNEG and the first supply voltage VSS according to (C2) (or the output signal of the next stage).

The third controller 252 charges and discharges the QL node according to the voltage of the stage ST node Q and the start pulse SP (or an output signal of the preceding stage), thereby outputting the output buffer unit 256 to the negative voltage VNEG. Or outputting the first supply voltage VSS. To this end, the third control unit 252 is connected to the 28th and 28B PMOS transistors T28A and T28B connected between the negative voltage VNEG supply line and the Q node and the QL node of the stage ST, and the QL node. The 29th PMOS transistor T29 connected between the start pulse SP (or output signal of the preceding stage) input line, the start pulse SP (or output signal of the preceding stage) input line and the first supply voltage VSS. ) Is provided with a thirtieth PMOS transistor (T30). Here, the 28th and 28B PMOS transistors T28A and T28B have a dual gate structure, thereby increasing the threshold voltage Vth to minimize leakage current.

The output buffer unit 256 uses a bootstrapping according to the voltage of the QL node to supply the negative supply voltage VNEG to the level shifter LS output line, and the second clock signal T31. According to C2) (or the output signal of the next stage), the first supply voltage VSS is provided as the output line of the level shifter LS, and the thirty-second PMOS transistor T32 is provided. In particular, the output buffer unit 256 includes a twenty-fourth capacitor CL connected between the gate terminal and the source terminal of the thirty-first PMOS transistor T31 to use bootstrapping.

The level shifter LS further includes thirty-third to thirty-seventh PMOS transistors T33 to T37 to prevent distortion of the output signal LO.

Specifically, the 33rd PMOS transistor T33 controls the QL node in response to the second clock signal C2 (or an output signal of the next stage). For this purpose, the thirty-third PMOS transistor T33 is connected between the QL node and the second clock signal C2 (or the output signal of the next stage).

The thirty-fourth PMOS transistor T34 is connected between a level shifter LS output line and a start pulse SP and a first supply voltage VSS input line.

The 35 th PMOS transistor T35 controls the QL node in response to the voltage of the QB node. For this purpose, the 35 th PMOS transistor T35 is connected between the QL node and the QB node.

The 36th PMOS transistor T36 is connected between the output line and the QB node and the first supply voltage VSS input line to discharge the level shifter LS output line.

In addition, the 37th PMOS transistor T37 is disposed between the negative voltage VNEG input line and the source terminal of the 28th PMOS transistor T28A to prevent leakage currents of the 28th and 28B transistors T28A and T28B. It is connected in a diode type.

As illustrated in FIG. 8, the stages ST and the level shifters LS having the above configuration are supplied with the first to fourth clock signals C1 to C4 having a phase delayed by one clock. Here, the fourth clock signal C4 has a phase synchronized with the start pulse SP. The first to fourth clock signals C1 to C4 including the start pulse SP are supplied in a negative type having a swing voltage of 10 V or less. In particular, it is assumed here that the potential of 10 V is low and the potential of 0 V is high. The operation of the stage ST and the level shifter LS with reference to the driving waveform is as follows.

When the start pulse SP and the fourth clock signal C4 become high at the same time in the t1 period, the twenty-first and twenty-second PMOS transistors T21 and T22 of the stage ST are turned on, so that the first node has a high first. The voltage of state H1 is charged. Accordingly, the 26th PMOS transistor T26 having the gate terminal connected to the Q node is gradually turned on. Then, the 25A and 25B PMOS transistors T25A and T25B are turned on by the high start pulse SP so that the low state (10V) voltage from the first supply voltage VSS input line is applied to the QB node. Is charged. Accordingly, the 23rd and 23rd PMOS transistors T23A and T23B and the twenty-seventh PMOS transistor T27 having the gate terminal connected to the QB node are turned off. As a result, since the low state voltage 10V of the first clock signal C1 is charged to the output line of the stage ST through the twenty-sixth PMOS transistor T26, the stage ST is output signal of the low state. Will output (SO).

Since the QA node is turned on by the Q node of the stage ST in the first high state 1H, the QL node is turned high and the 31st PMOS transistor T31 is turned on. Even if the negative voltage VNEG in the high state is turned on gradually, the 29th and 30th PMOS transistors T29 and T30 are turned on by the high state start pulse SP (or the output signal of the previous stage). On, the QL node is charged with a low state (10V) voltage from the first supply voltage VSS input line. Accordingly, since the thirty-first PMOS transistor T31 is turned off, the output signal of the level shifter LS maintains the previous state (ie, the low state).

In the t2 period, when the start pulse SP and the fourth clock signal C4 go low and the first clock signal C1 goes high, the twenty-first and twenty-second PMOS transistors T21 and T22 are turned off. The Q node is in a floating state, and the 26th PMOS transistor T26 is maintained in the turned-on state. In this case, the Q node in the floating state is the voltage of the high state of the first clock signal C1 due to the influence of the internal capacitor Cgs and the twenty-second capacitor CB formed between the gate and the source of the 26th PMOS transistor T26. Bootstrapping occurs due to the second high state H2 that is higher than the first high state H1. As a result, the 26th PMOS transistor T26 is reliably turned on so that the high state voltage 0V of the first clock signal C1 is quickly charged to the output line of the stage ST so that the stage ST is in a good high state. The output signal SO of the state is output.

Then, the 28th and 28B PMOS transistors T28A and T28B are turned on by the Q node of the stage ST which is in the second high state H2. Accordingly, the twenty-eighth and the twenty-eighth P-th transistors T37 turned on by the negative voltage VNEG in the high state and the twenty-eighth turned-on by the Q node of the stage ST which became the second high state H2 The 31st PMOS transistor T31 is turned on because the negative voltage VNEG of the high state is charged to the QL node via the 28B PMOS transistors T28A and T28B. In this case, the QL node is in a floating state by the twenty-ninth, thirty, and thirty-fourth PMOS transistors T29, T30, and T34 that are turned off, and are more likely to be caused by bootstrapping by the twenty-fourth capacitor CL. It becomes high high state.

In detail, the bootstrapping phenomenon due to the negative voltage VNEG is affected by the internal capacitor Cgs and the twenty-fourth capacitor CL formed between the gate and the source of the thirty-first PMOS transistor T31. As a result, the 31st PMOS transistor T31 is reliably turned on. Then, the negative voltage VNEG is quickly charged to the output line of the level shifter LS through the 31st PMOS transistor T31 which is certainly turned on. Therefore, the output signal LO of the level shifter LS has a signal waveform in a high state.

In the t3 period, the second clock signal C2 becomes high and the first clock signal C1 becomes low. The voltage of the Q node in the floating state is dropped to the first high state H1 by the first clock signal C1 in the low state and the twenty-six PMOS transistor T26 maintains the turn-on state. Accordingly, since the first clock signal C1 in the low state is charged to the output line of the stage ST via the turned-on 26th PMOS transistor T26, the stage ST is output signal SO in the low state. Will print

Then, the Q-node of the stage ST which is the first high state 1H turns on the 28th and 28th PMOS transistors T28A and T28B so that the QL node is turned high. In this case, the voltage of the QL node is discharged through the thirty-third PMOS transistor T33 turned on by the second clock signal C2 (or the output signal of the next stage) in the high state, and thus, the thirty-first PMOS transistor T31 is discharged. Is turned off. In addition, a first supply in a low state to the output line of the level shifter LS through the 32nd PMOS transistor T32 turned on by the high state second clock signal C2 (or the output signal of the next stage). Since the voltage VSS is charged, the level shifter LS outputs the output signal LO in a low state.

When the third clock signal C3 becomes high in the t4 period, the twenty-fourth PMOS transistor T24 is turned on to charge the QB node with the high voltage 0V, which is the second supply voltage VDD. Accordingly, the twenty-sixth PMOS transistor T26 is turned on by turning on the twenty-third A and twenty-fourth PMOS transistors T23A and T23B, thereby discharging the Q node voltage having the first high state H1 to a low state in the period t3. -Off. Since the first supply voltage VSS is charged to the output line of the stage ST through the twenty-seventh PMOS transistor T27 turned on by the high QB node, the stage ST outputs a low output signal ( SO) will be output. The 28th and 28B PMOS transistors T28A and T28 are turned off by the Q node in the low state. In this case, since the QL node is kept low by the first supply voltage VSS supplied through the 35 th PMOS transistor T35 turned on by the voltage of the QB node in the high state, the 31st PMOS transistor T311 is used. ) Is turned off. In addition, since the output line of the level shifter LS is charged to the low level of the first supply voltage VSS through the 36th PMOS transistor T36 turned on by the voltage of the QB node in the high state, the level shifter LS is charged. Outputs the output signal LO in a low state.

When the fourth clock signal C4 becomes high in the t5 period, the 24 th PMOS transistor T24 is turned off and the QB node maintains the high state in the t4 period. Accordingly, since the Q node remains low by the turned-on 23A and 23B PMOS transistors T23A and T23B, the twenty-sixth PMOS transistor T26 is continuously turned off, and the twenty-seventh PMOS transistor ( Since the first supply voltage VSS is charged to the output line of the stage ST through the T27, the stage ST outputs the output signal SO in a low state. The 28A and 28B PMOS transistors T28A and T28B are turned off by the Q node in the low state. In this case, since the twenty-ninth and thirtieth PMOS transistors T29 and T30 are turned on by the fourth clock signal C4 (or an output signal of the previous stage) in the high state, the QL is applied by the first supply voltage VSS. Since the node remains low, the thirty-first PMOS transistor T311 is turned off. In addition, since the output line of the level shifter LS is charged to the low level of the first supply voltage VSS through the 36th PMOS transistor T36 turned on by the voltage of the QB node in the high state, the level shifter LS is charged. Outputs the output signal LO in a low state.

As described above, in the shift register having the level shifter according to the second embodiment of the present invention, the same problem occurs in the shift register according to the first embodiment of the present invention.

FIG. 9 shows a detailed circuit configuration of a shift register incorporating a level shifter according to a third embodiment of the present invention, and shows one stage ST and level shifter LS of the shift register circuit.

The stage ST shown in FIG. 9 is a diode type to the start pulse SP input line, and the forty-first PMOS transistor T41, the forty-first PMOS transistor T41, the fourth clock signal C4 input line, and the Q node. A first control section including a forty-second PMOS transistor T42 connected between the first and fourth BMOS transistors T43A and 43B connected between the Q node and the QB node and the first supply voltage VSS input line; 342; 44 th PMOS transistor T44, 44 th PMOS transistor T44, and start pulse SP input line connected between the second supply voltage VDD input line, the third clock signal C3 input line, and the QB node. And a second control section 344 including 45A and 45B PMOS transistors T45A and T45B connected between the first supply voltage VSS input line; The 46th PMOS transistor T46 selects and supplies the first clock signal C1 to the output line according to the voltage of the Q node, and the first supply voltage VSS is selected and supplied to the output line according to the voltage of the QB node. And a buffer unit 346 having a forty-seventh PMOS transistor 427. The stage ST includes the forty-first capacitor CB connected between the gate terminal and the source terminal of the 46th PMOS transistor T46, that is, between the Q node and the output line P of the stage ST, and the Q node. And 42 th capacitor CQ connected between the first and second supply voltage VSS input lines and between the gate terminal and the source terminal of the forty-first PMOS transistor T47, that is, the QB node and the first supply voltage VSS input line. And a 43rd capacitor CQB connected therebetween.

The level shifter LS is an output signal according to the third control unit 352 for controlling the QL node according to the stage ST node Q and the start pulse SP (or an output signal of the preceding stage) and the inter clock Inter_CLK. The fourth control unit 354 for delaying a specific voltage state of the negative voltage VNEG and the first supply voltage VSS according to the voltage of the QL node and the second clock signal C2 (or the output signal of the next stage). ) Is provided with an output buffer unit 356 for selecting and outputting any one.

The third control unit 352 charges and discharges the QL node according to the voltage of the stage ST node Q and the start pulse SP (or the output signal of the previous stage), thereby outputting the negative buffer voltage VNEG. Or outputting the first supply voltage VSS. To this end, the third controller 352 is connected to the 48th and 48B PMOS transistors T48A and T48B connected between the negative voltage VNEG supply line and the Q node and the QL node of the stage ST, and the QL node. The 49th PMOS transistor T49 connected between the start pulse SP (or output signal of the preceding stage) input line, the start pulse SP (or output signal of the preceding stage) input line and the first supply voltage VSS. ) Is provided with a fifty PMOS transistor T50. Here, the 48A and 48B PMOS transistors T48A and T48B have a dual gate structure, thereby increasing the threshold voltage Vth to minimize leakage current.

The fourth controller 354 is configured to supply the first supply voltage VSS to the QL node and the output line according to the inter clock signal Inter_CLK to delay the specific voltage state of the output signal. T61). Here, the inter clock Inter_CLL is set to have a smaller duty ratio than the first to fourth clock signals C1 to C4.

The output buffer unit 356 supplies a 51 th PMOS transistor T51 for supplying the negative supply voltage VNEG to the level shifter LS output line using bootstrapping according to the voltage of the QL node, and the second clock signal ( According to C2) (or an output signal of the next stage), the 52nd PMOS transistor T52 is provided as the output line of the level shifter LS. In particular, the output buffer unit 356 includes a 44 th capacitor CL connected between the gate terminal and the source terminal of the 51st PMOS transistor T51 in order to use bootstrapping.

The level shifter LS further includes 53rd to 57th PMOS transistors T53 to T57 to prevent distortion of the output signal LO.

In detail, the 53 th PMOS transistor T53 controls the QL node in response to the second clock signal C2 (or an output signal of a next stage). For this purpose, the 53 th PMOS transistor T53 is connected between the QL node and the second clock signal C2 (or the output signal of the next stage).

The 54th PMOS transistor T54 is connected between the level shifter LS output line and the start pulse SP and the first supply voltage VSS input line.

The 55 th PMOS transistor T55 controls the QL node in response to the voltage of the QB node. For this purpose, the 55th PMOS transistor T55 is connected between the QL node and the QB node.

The 56 th PMOS transistor T56 is connected between the output line, the QB node, and the first supply voltage VSS input line to discharge the level shifter LS output line.

In addition, the 57 th PMOS transistor T57 is disposed between the negative voltage VNEG input line and the source terminal of the 48 th PMOS transistor T48A to prevent leakage currents of the 48 A and 48 B transistors T48A and T48B. It is connected in a diode type.

As shown in FIG. 10, the stages ST and the level shifters LS having such a configuration are supplied with the first to fourth clock signals C1 to C4 having a phase delayed by one clock. Here, the fourth clock signal C4 has a phase synchronized with the start pulse SP. The first to fourth clock signals C1 to C4 including the start pulse SP are supplied in a negative type having a swing voltage of 10 V or less. In particular, it is assumed here that the potential of 10 V is low and the potential of 0 V is high. The operation of the stage ST and the level shifter LS with reference to the driving waveform is as follows.

When the start pulse SP and the fourth clock signal C4 become high at the same time in the t1 period, the forty-first and forty-second PMOS transistors T41 and T42 of the stage ST are turned on so that the first node has a first high state. The voltage of state H1 is charged. As a result, the 46th PMOS transistor T46 having the gate terminal connected to the Q node is gradually turned on. The 45A and 45B PMOS transistors T45A and T45B are turned on by the high start pulse SP, and the low state (10V) voltage from the first supply voltage VSS input line is applied to the QB node. Is charged. Accordingly, the 43rd and 43rd PMOS transistors T43A and T43B and the 47th PMOS transistor T47 having the gate terminal connected to the QB node are turned off. As a result, since the low state voltage 10V of the first clock signal C1 is charged to the output line of the stage ST through the turned-on 46th PMOS transistor T46, the stage ST is output signal of the low state. Will output (SO).

The 48th and 48B PMOS transistors T48A and T48B are turned on by the Q node of the stage ST, which is the first high state 1H, and the QL node is turned to the high state, thereby the 51st PMOS transistor T51. The 49th and 50th PMOS transistors T49 and T50 are turned on by the start pulse SP (or the output signal of the preceding stage) even when the negative voltage VNEG in the high state is slowly turned on. On, the QL node is charged with a low state (10V) voltage from the first supply voltage VSS input line. Accordingly, since the 51st PMOS transistor T51 is turned off, the output signal of the level shifter LS maintains the previous state (ie, the low state).

In the t2 period, when the start pulse SP and the fourth clock signal C4 go low and the first clock signal C1 goes high, the forty-first and forty-second PMOS transistors T41 and T42 are turned off. The Q node is in a floating state, and the forty-fifth PMOS transistor T46 remains turned on. In this case, the Q node in the floating state is the voltage of the high state of the first clock signal C1 due to the influence of the internal capacitor Cgs and the 42nd capacitor CB formed between the gate and the source of the 46th PMOS transistor T46. Bootstrapping occurs due to the second high state H2 that is higher than the first high state H1. As a result, the 46th PMOS transistor T46 is reliably turned on so that the high state voltage 0V of the first clock signal C1 is quickly charged to the output line of the stage ST, so that the stage ST is in a good high state. The output signal SO of the state is output.

Then, the 48th and 48B PMOS transistors T48A and T48B are turned on by the Q node of the stage ST which is in the second high state H2. Accordingly, the 48 th PA transistor T57 turned on by the negative voltage VNEG in the high state and the 48 A and th turn turned on by the Q node of the stage ST which is in the second high state H2. The 51st PMOS transistor T51 is turned on because the negative voltage VNEG of the high state is charged to the QL node via the 48B PMOS transistors T48A and T48B. In this case, the QL node is in a floating state by the turned-off 49th, 50th, and 54th PMOS transistors T49, T50, and T54, and is more likely to be Bootstrapping due to the 44th capacitor CL. It becomes high high state.

In detail, the bootstrapping phenomenon due to the negative voltage VNEG is affected by the internal capacitor Cgs and the 44 th capacitor CL formed between the gate and the source of the 51st PMOS transistor T51. As a result, the 51st PMOS transistor T51 is reliably turned on. The negative voltage VNEG is quickly charged to the output line of the level shifter LS through the 51 th PMOS transistor T51 that is turned on. At this time, the inter clock Inter_CKL signal becomes high for a predetermined period at the same time when the first clock signal C1 becomes high. Accordingly, the 60th and 61st PMOS transistors T60 and T61 are turned on. As a result, the first supply voltage VSS is supplied to the QL node and the output line while the inter clock Inter_CLK signal is high through the turned-on 60th and 61st PMOS transistors T60 and T61. The first supply voltage VSS is supplied to the QL node and the output line while the inter clock signal Inter_CLK is in a high state even when the first clock signal C1 is in a high state. Accordingly, the QL node and the output line remain low while the inter clock signal Inter_CLK is high. Subsequently, when the inter clock signal Inter_CLK goes low, the output signal LO1 of the level shifter LS has a high signal waveform.

In the t3 period, the second clock signal C2 becomes high and the first clock signal C1 becomes low. The voltage of the Q node in the floating state is dropped to the first high state H1 by the first clock signal C1 in the low state, and the forty-six PMOS transistor T46 maintains the turn-on state. Accordingly, since the first clock signal C1 in the low state is charged to the output line of the stage ST via the turned-on 46th PMOS transistor T26, the stage ST is output signal SO in the low state. Will print

The 48th and 48B PMOS transistors T48A and T48B are turned on by the Q node of the stage ST which is the first high state 1H, and the QL node is turned high. In this case, since the voltage of the QL node is discharged through the 53 th PMOS transistor T53 turned on by the second clock signal C2 (or the output signal of the next stage), the 51 th PMOS transistor T51. Is turned off. In addition, a first supply in a low state to the output line of the level shifter LS through the 52nd PMOS transistor T52 turned on by the second clock signal C2 in the high state (or an output signal of the next stage). Since the voltage VSS is charged, the level shifter LS outputs the low level output signal LO1. Meanwhile, in the t3 period, the second stage ST2 and the second level shifter LS2 operate the first stage ST1 and the first level shifter LS1 which are performed in the t2 period. Accordingly, when the second clock signal C2 is in the high state, the inter clock signal Inter_CLK is also in the high state for a predetermined period of time, thereby turning on the 60th and 61st PMOS transistors T60 and T61. As a result, the first supply voltage VSS is supplied to the QL node and the output line while the inter clock Inter_CLK signal is high through the turned-on 60th and 61st PMOS transistors T60 and T61. The first supply voltage VSS is supplied to the QL node and the output line while the inter clock signal Inter_CLK is in a high state even when the second clock signal C2 is in a high state. Accordingly, the QL node and the output line remain low while the inter clock signal Inter_CLK is high. Thereafter, when the inter clock signal Inter_CLK goes low, the output signal LO2 of the level shifter LS has a high signal waveform. The second output signal LO2 is output after being spaced apart as long as the inter clock signal Inter_CLK is high after the first output signal LO1 is output.

When the third clock signal C3 becomes high in the t4 period, the 44 th PMOS transistor T44 is turned on to charge the QB node with the high voltage 0V, which is the second supply voltage VDD. Accordingly, the forty-fifth PMOS transistor T46 is turned on by discharging the Q-node voltage, which is the first high state H1, to the low state during the t3 period. -Off. In addition, since the first supply voltage VSS is charged to the output line of the stage ST through the 47th PMOS transistor T47 turned on by the QB node in the high state, the stage ST outputs a low output signal ( SO) will be output. The 48A and 48B PMOS transistors T48A and T48 are turned off by the Q node in the low state. In this case, since the QL node is kept low by the first supply voltage VSS supplied through the 55th PMOS transistor T55 turned on by the voltage of the QB node in the high state, the 51st PMOS transistor T51 is maintained. ) Is turned off. In addition, since the output line of the level shifter LS is charged to the low level of the first supply voltage VSS through the 56th PMOS transistor T56 turned on by the voltage of the QB node in the high state, the level shifter LS is charged. Outputs a low state output signal LO1. Meanwhile, in the t4 period, the third stage ST3 and the third level shifter LS3 operate the second stage ST2 and the second level shifter LS2 in the t3 period. Accordingly, when the fourth clock signal C4 becomes high, the inter clock signal Inter_CLK also becomes high for a predetermined period of time, thereby turning on the 60th and 61st PMOS transistors T60 and T61. As a result, the first supply voltage VSS is supplied to the QL node and the output line while the inter clock Inter_CLK signal is high through the turned-on 60th and 61st PMOS transistors T60 and T61. The first supply voltage VSS is supplied to the QL node and the output line while the inter clock signal Inter_CLK is in the high state even when the fourth clock signal C4 is in the high state. Accordingly, the QL node and the output line remain low while the inter clock signal Inter_CLK is high. Subsequently, when the inter clock signal Inter_CLK goes low, the output signal LO3 of the level shifter LS has a high signal waveform. The third output signal LO3 is output by being spaced apart as long as the inter clock signal Inter_CLK is high after the second output signal LO2 is output.

When the fourth clock signal C4 becomes high in the t5 period, the forty-fourth PMOS transistor T44 is turned off and the QB node maintains the high state in the t4 period. Accordingly, since the Q node is kept low by the turned-on 43A and 43B PMOS transistors T43A and T43B, the forty-seventh PMOS transistor T46 is continuously turned off, and the forty-seventh PMOS transistor ( Since the first supply voltage VSS is charged to the output line of the stage ST through T47, the stage ST outputs the output signal SO in a low state. The 48th and 48B PMOS transistors T48A and T48B are turned off by the Q node in the low state. In this case, since the 49th and 50th PMOS transistors T49 and T50 are turned on by the fourth clock signal C4 (or an output signal of the previous stage) in the high state, the QL is applied by the first supply voltage VSS. Since the node remains low, the 51st PMOS transistor T51 is turned off. In addition, since the output line of the level shifter LS is charged to the low level of the first supply voltage VSS through the 56th PMOS transistor T56 turned on by the voltage of the QB node in the high state, the level shifter LS is charged. Outputs the output signal LO in a low state. In the t5 period, the fourth stage ST4 and the fourth level shifter LS4 operate the third stage ST3 and the third level shifter LS3 which are performed in the t4 period. Accordingly, when the fifth clock signal C5 is in the high state, the inter clock signal Inter_CLK is also in the high state for a predetermined period of time, thereby turning on the sixty and sixty-first PMOS transistors T60 and T61. As a result, the first supply voltage VSS is supplied to the QL node and the output line while the inter clock Inter_CLK signal is high through the turned-on 60th and 61st PMOS transistors T60 and T61. The first supply voltage VSS is supplied to the QL node and the output line while the inter clock signal Inter_CLK is in the high state even when the fifth clock signal C5 is in the high state. Accordingly, the QL node and the output line remain low while the inter clock signal Inter_CLK is high. Thereafter, when the inter clock signal Inter_CLK becomes low, the output signal LO4 of the level shifter LS has a signal waveform in a high state. The fourth output signal LO4 is output by being spaced apart as long as the inter clock signal Inter_CLK is high after the third output signal LO3 is output.

As described above, the shift registers including the level shifter according to the third embodiment of the present invention simultaneously set the intern clock signal Inter_CLK when the first to fourth clock signals C1 to C4 change from a low state to a high state. By supplying for a period of time to turn on the sixty and sixty-first PMOS transistors (T60, T61) it is possible to space the output signals for a period of time that the intern clock signal Inter_CLK is supplied. Accordingly, overlapping of output signals may be prevented to prevent deterioration of image quality.

As described above, the shift registers incorporating the shift register and the level shifter according to the present invention simultaneously supply the inter-clock signal for a predetermined period of time when the first to fourth clock signals are changed from the low state to the high state to delay the output time. By doing so, the overlap of the output signals can be prevented to prevent deterioration of the image quality.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 schematically illustrates a conventional shift register.

FIG. 2 is an input / output waveform diagram of the shift register shown in FIG. 1. FIG.

3 is a detailed circuit diagram of one stage shown in FIG.

4A to 4C are detailed views of part “A” in the input / output waveform diagram shown in FIG. 2;

5 is a detailed circuit diagram of one stage of the shift register according to the first embodiment of the present invention.

6 is an input / output waveform diagram of the stage shown in FIG. 5;

7 is a detailed circuit diagram of a shift register incorporating a level shifter according to a second embodiment of the present invention.

8 is an input / output waveform diagram of the stage shown in FIG. 7.

9 is a detailed circuit diagram of a shift register incorporating a level shifter according to a third embodiment of the present invention.

10 is an input / output waveform diagram of the stage shown in FIG. 9;

<Description of Main Parts of Drawing>

ST1 to STn: stage 32, 142, 242, 342: first control unit

34,144,244,344: second control unit 36,146,246,346: buffer unit

252,352: third control unit 256,356: output buffer unit

354: fourth controller

Claims (40)

A shift register comprising a plurality of stages for shifting an input signal with first and second supply voltages and phase delayed first through fourth control signals to supply the respective output signals and the next stage input signals. Each of the stages, A first control section for selectively supplying the input signal and the first supply voltage to a first node between them using first to third transistors having conductive paths between an input signal supply line and the first supply voltage input line Wow; Selectively supplying the second and first supply voltages to a second node therebetween using fourth and fifth transistors having conductive paths between the second supply voltage input line and the first supply voltage input line. A second control unit; To the output line of the stage between them using sixth and seventh transistors having a conductive path between the input line of any one of the first to fourth control signals and the first supply voltage input line. An output buffer unit for selectively supplying the specific control signal and the first supply voltage to the output signal; And an eighth transistor configured to delay a specific voltage state of an output signal output from the output line of the stage according to a fifth control signal having a different duty ratio from the first to fourth control signals. The method of claim 1, The first and second transistors each have a conductive path between the input signal supply line and the first node, and a control electrode for controlling the conductive path according to each of the input signal and the first control signal, And the third transistor has a conductive path between the first node and the first supply voltage input and a control electrode for controlling the conductive path according to the voltage of the second node. The method of claim 2, The fourth transistor has a conductive path between the second supply voltage input line and the second node and a control electrode controlling the conductive path according to a second control signal, And the fifth transistor has a conductive path between the second node and the first supply voltage input line and a control electrode for controlling the conductive path according to a first control signal. The method of claim 3, wherein The sixth transistor has a conductive path between a third control signal input line and an output line of the stage, and a control electrode for controlling the conductive path according to the voltage of the first node, And the seventh transistor has a conductive path between an output line of the stage and the first supply voltage input line, and a control electrode for controlling the conductive path according to the voltage of the second node. The method of claim 4, wherein And the sixth transistor further comprises a capacitor connected between the gate electrode and an output line of the stage for bootstrapping the gate electrode thereof. The method of claim 2, And the third transistor includes a dual gate transistor having a gate electrode connected to the second node in common. The method of claim 3, wherein And the fifth transistor includes a dual gate transistor having a gate electrode connected to the first control signal in common. The method of claim 1, And the eighth transistor is configured to form a conductive path between an output line of the stage and the first supply voltage input line under control of the fifth control signal. The method of claim 8, And the fifth control signal has a smaller duty width than the first to fourth control signals. The method of claim 1, And the stage comprises a transistor of the same channel type. The method of claim 1, And said stage comprises a PMOS transistor. The method of claim 1, And the second supply voltage is greater than the first supply voltage. The method of claim 12, And the first supply voltage is a negative voltage. The method of claim 6, 3. The shift register of claim 1, wherein the first to third control signals are supplied with three clock signals among the first to fourth clock signals having different voltages and having a specific voltage state at the same period. The method of claim 14, And the third control signal has a phase delayed form by one clock than the first control signal, and the second control signal has a phase delayed form by two clocks than the third control signal. The method of claim 14, And the input signal comprises a portion in phase with the first control signal. The method according to any one of claims 1 to 16, And the shift register is applied to at least one of a scan driver for driving scan lines of a display device and a data driver for driving data lines of a display device. A plurality of stages that are cascade-connected and shift the start pulses input through the input terminal to sequentially output the shift pulses, and a plurality of level shifters that level shift the voltage levels of the shift pulses supplied from each of the stages. In the shift register with a built-in level shifter, Each of the stages, A buffer unit configured to output the shift pulse using a first control signal and a first supply voltage according to voltages of first and second nodes; A first control unit controlling the voltage of the first node according to the start pulse and the voltage of the second node; And a second controller configured to control the voltage of the second node using the first and second supply voltages according to the start pulse and the second control signal. Each of the level shifters A third controller configured to control a voltage of a third node using a third supply voltage and the first supply voltage according to the voltage of the first node and a third control signal; An output buffer which causes the third node voltage to be bootstraped in at least one step and selectively outputs the first and third supply voltages according to a voltage and a fourth control signal of the third node bootstrapped in the at least one step Wealth, And a fourth controller for delaying a specific voltage state of an output signal output from an output line of the third node and the output buffer unit according to a fifth control signal having a different duty ratio from the first to fourth control signals. Shift register with built-in level shifter. The method of claim 18, The first control unit A first transistor having a conductive passage between the start pulse and the first node, and a control electrode controlling the conductive passage according to the start pulse; A second transistor having a conductive passage between an output terminal of the first transistor and the first node, and a control electrode controlling the conductive passage according to a third control signal; And a third transistor having a conductive passage between the first node and the input line of the first supply voltage and a control electrode for controlling the conductive passage according to the voltage of the second node. Built-in shift register. The method of claim 19, The second control unit A fourth transistor having a conductive passage between the second supply voltage input line and the second node and a control electrode controlling the conductive passage according to the second control signal; And a fifth transistor having a conductive passage between the second node and the first supply voltage input line and a control electrode for controlling the conductive passage according to the start pulse. . The method of claim 20, The buffer unit A sixth transistor having a conductive path between the first control signal input line and an output line of the stage, and a control electrode controlling the conductive path according to the voltage of the first node; And a seventh transistor having a conductive passage between the output line of the stage and the first supply voltage input line and a control electrode for controlling the conductive passage according to the voltage of the second node. Built-in shift register. The method of claim 21, The buffer unit And a capacitor connected between the control electrode of the sixth transistor and the output line of the stage, for further bootstrapping the voltage of the control electrode. The method of claim 21, The stage is And a capacitor for preventing a voltage distortion of the second node due to the leakage current of the fifth transistor. The method of claim 19, And the third transistor includes a dual gate transistor having a gate electrode connected to the second node in common. The method of claim 20, And the fifth transistor comprises a dual gate transistor having a gate electrode connected to the third node in common. The method of claim 21, The third control unit An eighth transistor having a conductive path between the input line of the third supply voltage and the third node and a control electrode controlling the conductive path according to an output signal of the stage; And a ninth and tenth transistor having a conductive path between the third node and an input line of the first supply voltage and a control electrode for controlling the conductive path according to the third control signal. Shift register with built-in. The method of claim 18, The output buffer unit An eleventh transistor having a conductive path between the third supply voltage input line and the third node and a control electrode controlling the conductive path according to the voltage of the third node; And a twelfth transistor having a conductive path between the output line of the level shifter and the first supply voltage input line and a control electrode for controlling the conductive path according to the fourth control signal. Shift register with built-in level shifter. The method of claim 27, The level shifter A thirteenth transistor configured to control a conductive path between the third node and an output line of the level shifter and the conductive path according to the fourth control signal; A fourteenth transistor configured to control a conductive path between the output line of the level shifter and the first supply voltage input line and the conductive path according to the third control signal; A fifteenth transistor for controlling a conductive path between the output lines of the third and level shifters and the conductive path according to the voltage of the second node; And a sixteenth transistor configured to control a conductive path between the output line of the level shifter and the first supply voltage input line and the conductive path according to the voltage of the second node. One shift register. The method of claim 28, The level shifter And a seventeenth transistor diode-connected between the input line of the third supply voltage and the eighth transistor, wherein the shift register has a level shifter. The method of claim 27, The output buffer unit And a capacitor connected in series between the third node and the output line of the level shifter for the first stage bootstrapping. The method of claim 26, And the eighth transistor includes a dual gate transistor having a gate electrode connected to the first node in common. The method of claim 21, The fourth control unit, A seventeenth transistor having a conductive passage between the first supply voltage input line and the third node and a control electrode controlling the conductive passage according to the fifth control signal; And an eighteenth transistor having a conductive passage between the first supply voltage input line and an output line of the level shifter and a control electrode for controlling the conductive passage according to the fifth control signal. Built-in shift register. The method of claim 32, And the fifth control signal has a smaller duty width than the first to fourth control signals. The method of claim 18, And said stages and level shifters comprise only thin film transistors of the same type channel. The method of claim 11, And the first to third supply voltages have a third < second < first magnitude relationship. 36. The method of claim 35 wherein And the third supply voltage is a negative voltage. The method of claim 18, The first to fourth control signals have specific voltage states that are phase delayed in the order of first, fourth, second, and third, And the third control signal has a phase in phase with the start pulse. The method of claim 18, And said stages and level shifters comprise only a thin film transistor of a P channel. The method of claim 18, The level shifter And shifting the lowest voltage level of the shift pulse to the third supply voltage to output the shifted voltage. The method of claim 18, And the shift register is applied to at least one of a scan driver for driving the scan lines of the display device and a data driver for driving the data lines of the display device.