KR20190031026A - Shift Resister and Display Device having the Same - Google Patents

Abstract

According to the present invention, a display device includes a pixel array on which pixels connected to a gate line are disposed and first and second shift resisters. The first resister synchronized with timing of an L clock signal outputs a 2n^th scan signal in a data writing period of the pixels arranged in an even-numbered pixel line, wherein n is a natural number. The second shift resister synchronized with timing of an R clock signal outputs a (2n-1)^th scan signal in the data writing period of the pixels arranged in an odd-numbered pixel line. The voltage difference between turn-on voltages and turn-off voltages of the L clock signal and the R clock signal is set larger than the voltage difference between the turn-on voltage of the L clock signal and the R clock signal and turn-off voltages of the 2n^th scan signal and the (2n-1)^th scan signal.

Description

Technical Field [0001] The present invention relates to a shift register and a display device including the shift register,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register capable of reducing a bezel and a display device including the shift register.

Flat panel displays (FPDs) are widely used not only for monitors of desktop computers but also for portable computers such as notebook computers and tablets, as well as mobile phone terminals, due to their advantages of miniaturization and light weight. Currently, various types of display devices such as a curved display, a flexible display, a rollable display, and a wearable display have been developed not only in the flat panel display, have. Such display devices include a liquid crystal display (LCD) LCD, Field Emission Display, An organic light emitting diode (OLED), and a quantum dot display (QD).

Among these, the organic light emitting display device has advantages of high response speed, high luminance efficiency, and large viewing angle. In general, an organic light emitting display uses a transistor turned on by a scan signal to apply a data voltage to a gate electrode of a driving transistor, and charges a data voltage supplied to the driving transistor to a storage capacitor. The organic light emitting element emits light by outputting the data voltage charged to the storage capacitor using the emission control signal.

The OLED display device is driven using an emission signal and one or more scan signals. The gate driving circuit for generating the emission signal and the scan signals, which are gate signals, generally includes a shift register for sequentially outputting the gate signals. The gate driving circuit may be implemented as a gate-in-panel (GIP) type in which a bezel region in a display panel is a non-display region and a combination of thin film transistors.

The gate driving circuit can be implemented in various forms, and a method for optimizing the circuit configuration for increasing the reliability of the driving is being sought.

A shift register capable of reducing the bezel of the present invention and a display device including the shift register.

A display device according to the present invention includes a pixel array in which pixels connected to a gate line are arranged, first and second shift registers. The first shift register outputs a second (n is a natural number) scan signal in the data writing period of the pixels arranged in the odd-numbered pixel line in synchronism with the timing of the L clock signal. The second shift register outputs the (2n-1) th scan signal in the data writing period of the pixels arranged in the odd-numbered pixel line in synchronism with the timing of the R clock signal. The voltage difference between the turn-on voltage and the turn-off voltage of the L clock signal and the R clock signal is the difference between the turn-on voltage of the L clock signal and the R clock signal, the turn of the (2n-1) - < / RTI > off voltage.

The present invention can improve the delay of the scan signal by increasing the voltage level of the clock signals applied to the shift register. As a result, it is possible to improve the scan signal delay phenomenon by driving the display panel by a single feeding method in which a scan signal is applied in one direction of the scan line. Since the delay phenomenon does not occur even with the single feeding method, the size of the gate driving circuit can be reduced to half the size of the double feeding type gate driving circuit for improving the scanning signal delay.

1 is a view showing a configuration of a display device according to the present invention.
2 is a schematic diagram showing a pixel circuit according to an embodiment of the present invention.
3 is a timing chart of scan signals for driving the pixel circuit shown in FIG.
4 is a block diagram showing a gate drive circuit according to the present invention.
5 is a circuit diagram showing a detailed configuration of the stage shown in Fig.
6 is a timing chart of clock signals driving the stage shown in FIG.
Fig. 7 is a diagram showing the drive timing of the first stage of the second shift register shown in Fig. 4;

Brief Description of the Drawings The advantages and features of the present disclosure, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that the description is not limited to the embodiments disclosed herein but is to be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and this specification is only defined by the scope of the claims.

In the gate driving circuit of the present specification, the switching elements may be implemented as n-type or p-type metal oxide semiconductor field effect transistor (MOSFET) transistors. Although p-type transistors are exemplified in the following embodiments, the present specification is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, the current flows from the source to the drain because the holes flow from the source to the drain. The source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. In the following embodiments, the invention is not limited by the source and the drain of the transistor.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a diagram showing a configuration of a display device according to the present invention; FIG.

1, a display device according to the present invention includes a display panel 100 in which pixels P are arranged in a matrix, a data driving circuit 120, gate driving circuits 130 and 140, and a timing controller 110 do.

The display panel 100 includes a pixel array 100A in which pixels P are arranged to display an image and a non-display portion 100B in which gate drive circuits 130 and 140 are disposed and an image is not displayed.

The pixel array 100A includes a plurality of pixels P, and displays an image based on the gradation displayed by each of the pixels P. [ The pixels P are arranged along the first to n-th pixel lines HL1 to HLn. Each pixel P is connected to a data line DL arranged along the column line and connected to a gate line GL arranged along the pixel line HL. That is, the pixels arranged in the same pixel line share the same gate line GL and are simultaneously driven. When the pixels arranged in the first pixel line HL1 are defined as the first pixels P1 and the pixels arranged in the nth pixel line HLn are defined as the nth pixels Pn, (P1) to the n-th pixel (Pn) are sequentially driven. A sampling period for writing data into one scan line can be defined as one horizontal period (1H).

The timing controller 110 is for controlling the driving timings of the data driving circuit 120 and the gate driving circuits 130 and 140. To this end, the timing controller 110 rearranges image data (RGB) input from the outside according to the resolution of the display panel 100 and supplies the same to the data driving circuit 120. The timing controller 110 generates a data control signal DDC for controlling the operation timing of the data driving circuit 120 and a gate control signal GDC for controlling the operation timing of the gate driving circuit.

The data driving circuit 120 drives the data line section DL. The data driving circuit 120 converts the image data RGB input from the timing controller 110 into an analog data voltage based on the data control signal DDC and supplies the analog data voltage to the data lines DL.

The gate drive circuits 130 and 140 include a level shifter 130 and a shift register 140. The level shifter 130 may be formed on a printed circuit board connected to the display panel 100 in the form of an IC and the shift register 140 may be formed of a GIP circuit in the non-display area 100B of the display panel 100 .

The level shifter 130 level-shifts the clock signals and the start signal under the control of the timing controller 110, and supplies the level shift signal to the shift register 140. The shift register 140 is formed by a combination of a plurality of thin film transistors (hereinafter referred to as transistors) in the non-display area 100B of the display panel 100 by the GIP method.

The shift register 140 may include a scan signal generator for outputting a scan signal and an emission signal generator for outputting an emission signal. In Fig. 1, the shift registers 140 are shown on one side of the pixel array for the sake of simplification of the drawings, but the shift registers can be distributed on both sides of the pixel array.

FIG. 2 is a schematic diagram showing a pixel structure according to an embodiment of the present invention, and FIG. 3 is a timing diagram of a scan signal.

2 and 3, the pixel includes first and second switching transistors SW1 and SW2, a driving transistor DT, a compensation circuit C_com, and an organic light emitting diode OLED. The organic light emitting diode OLED operates to emit light in accordance with the driving current formed by the driving transistor DT. The first switching transistor SW1 is connected to the (n-1) th scan signal SCAN (n-1) applied through the (n-1) th scan line SL (n-1) In response to this, the initializing voltage Vini is applied to the gate voltage of the driving transistor DT. The second switching transistor SW2 applies a data voltage Vdata to the source electrode of the driving transistor DT in response to the nth scan signal SCAN (N) applied through the nth scan line SL (n) . Therefore, the nth scan signal SCAN (N) may be defined as a scan signal for controlling data writing of the nth pixel P (n). The compensation circuit C_com controls the voltage of the main nodes N1, N2, N3 and N4 of the pixel P. [

4 is a diagram illustrating a scan signal generator according to the present invention.

4, the shift register 140 includes a first shift register 141 and a second shift register 142 disposed on both sides of the pixel array 100A, respectively.

The first shift register 141 consists of a dummy stage STG (D) and a second k (k is a natural number) stages. That is, the first shift register 141 includes the dummy stage STG (D), the second stage STG2, and the fourth stage STG4. The dummy stage STG (D), the second stage STG2, and the fourth stage STG4 are connected to each other.

Each of the stages STG (D), STG2 and STG4 of the first shift register 141 uses the low potential voltage VGL, the first high potential voltage VGH1 and the second high potential voltage VGH2, And outputs the scan signals SCAN (D), SCAN2, and SCAN4 according to the timings of the first L clock signal LCLK1 and the second L clock signal LCLK2.

And the 2 < n > n stages output the 2 < n > scan signal. The second scan signal is applied to the nth scan line SL (n) of the second 2n pixels and is applied to the (n-1) th scan line SL (n-1) of the (2n + . For example, the second stage STG2 outputs the second scan signal SCAN2, and the fourth stage STG4 outputs the fourth scan signal SCAN4. The second scan signal SCAN2 is applied to the nth scan line SL (n) of the second pixel P2 and the (n-1) th scan line SL (n-1) of the third pixel P3 ). The fourth scan signal SCAN4 is applied to the nth scan line SL (n) of the fourth pixel P4 and the (n-1) th scan line SL (n-1) of the fifth pixel P ). The dummy scan signal SCAN (D) output from the dummy stage STG (D) is applied to the (n-1) th scan line SL (n-1) of the first pixel P1.

The respective stages STG1, STG3 and STG5 of the second shift register 142 use the low potential voltage VGL, the first high potential voltage VGH1 and the second high potential voltage VGH2, And outputs a scan signal according to the timing of the R clock signal RCLK1 and the second R clock signal RCLK2.

The second shift register 142 consists of (2n-1) stages. That is, the second shift register 142 includes a first stage STG1, a third stage STG3, and a fifth stage STG5. The first stage STG1, the third stage STG3, and the fifth stage STG5 are connected to each other in a dependent manner.

The (2n-1) th stages output the (2n-1) th scan signal. The (n-1) th scan line SL (n-1) scan signal is applied to the nth scan line SL (n) of the (2n- . For example, the first stage STG1 outputs the first scan signal SCAN1, the third stage STG3 outputs the third scan signal SCAN3, the fifth stage STG5 outputs the fifth scan signal SCAN5). The first scan signal SCAN1 is applied to the nth scan line SL (n) of the first pixel P1 and the (n-1) th scan line SL (n-1) of the second pixel P2 ). The third scan signal SCAN3 is applied to the nth scan line SL (n) of the third pixel P3 and the (n-1) th scan line SL (n-1) of the fourth pixel P4 ). The fifth scan signal SCAN5 is applied to the nth scan line SL (n) of the fifth pixel P5 and the (n-1) th scan line SL (n-1) .

5 is a diagram showing a stage of a gate drive circuit according to the present invention. Although FIG. 5 shows the stage of the second shift register shown in FIG. 4, the first stage may also be implemented with the same circuit configuration.

Referring to FIG. 5, the n-th stage according to the present invention includes start control units T1 and T2, node control units T3, T4, T5 and T8, a scan pull-up transistor T6, a carry pull-up transistor T6C, A transistor T7 and a carry pull-down transistor T7C.

The start control units T1 and T2 precharge the Q node in response to the start signal. The start control units T1 and T2 include a first transistor T1 and a second transistor T2. The first transistor T1 includes a gate electrode connected between the input terminal of the low potential voltage VGL and the QA node and connected to the start input terminal GVST. The first transistor (T1), in response to the start signal, precharges the QA node to the low potential voltage (VGL). The second transistor T2 includes a gate electrode connected between the QA node and the Q node and connected to the input terminal of the low potential voltage VGL. The second transistor T2 is always kept in the turn-on state and prevents the voltage change of the QA node when the Q node is bootstrapped. The stabilization transistor prevents the voltage change of the QA node from suddenly changing during the bootstrapping process of the Q node, thereby preventing the electrical stress on the first transistor T1 and the third transistor T3 from becoming excessive.

The node controllers T3, T4, T5 and T8 control the voltage of the Q node or the QB node. The node controllers T3, T4, T5 and T8 include a third transistor T3, a fourth transistor T4, a fifth transistor T5 and an eighth transistor T8.

The third transistor T3 includes a gate electrode connected between the QA node and the input of the second high potential voltage VGH2 and connected to the QB node. The third transistor T3, in response to the QB node voltage, applies a second high potential voltage VGH2 to the QA node.

The fourth transistor T4 is connected between the input terminal of the low potential voltage VGL and the QB node and includes a gate electrode connected to the CB node. The fourth transistor T4, in response to the voltage of the CB node, applies a low potential voltage to the QB node. The first capacitor Cb1 is connected between the input node of the second R clock signal RCLK2 and the CB node to charge the voltage of the second R clock signal RCLK2.

 The fifth transistor T5 is connected between the CB node and the input terminal of the second high voltage VGH2 and includes a gate electrode connected to the start input terminal GVST. The fifth transistor T5, in response to the start signal, applies the second high potential voltage VGH2 to the CB node. That is, the fifth transistor T5 initializes the CB node to a turn-off voltage, and turns off the fourth transistor T4.

The eighth transistor T8 includes a gate electrode connected between the QB node and the input terminal of the second high-potential voltage VGH2 and connected to the start input terminal GVST. The eighth transistor T8, in response to the start signal VST_R, applies the second high potential voltage VGH2 to the QB node.

The second capacitor Cb2 connects between the QB node and the second high potential voltage VGH2 and maintains the voltage level of the QB node.

The scan pull-up transistor T6 is connected between the input terminal of the first R clock signal RCLK1 and the scan output terminal SRO_N and includes a gate electrode connected to the Q node. The scan pull-up transistor T6 applies a turn-on voltage to the scan output terminal SRO_N in response to the Q node voltage.

The carry pull-up transistor T6C is connected between the input terminal of the first R clock signal RCLK1 and the carry output terminal CRO_N and includes a gate electrode connected to the Q node. The carry pull-up transistor T6C, in response to the Q node voltage, applies a turn-on voltage to the carry output CRO_N.

The scan pull-down transistor T7 is connected between the scan output terminal SRO_N and the input terminal of the first high potential voltage VGH1, and includes a gate electrode connected to the QB node. The scan pull-down transistor T7 applies a turn-off voltage to the scan output terminal SRO_N in response to the voltage of the QB node.

The carry pull-down transistor T7C is connected between the carry output CRO_N and the input terminal of the second high voltage VGH2, and includes a gate electrode connected to the QB node. The carry pull-down transistor T7C, in response to the voltage of the QB node, applies a turn-off voltage to the carry output CRO_N.

6 is a timing chart of clock signals for the operation of the scan driver shown in FIG.

6, clock signals for driving the first shift register 141 include a first start signal VST_L and L clock signals, and L clock signals include a first L clock signal LCLK1 and a second L clock signal LCLK1. L clock signal LCLK2. The clock signals for driving the second shift register 142 include a second start signal VST_R and R clock signals and the R clock signals include a first R clock signal RCLK1 and a second R clock signal RCLK2, . The high-potential voltage level of the clock signals is the second high-potential voltage (VGH2). Although not shown in the figure, all clock signals can utilize a low potential voltage (VGL) for the turn-on voltage.

 The period in which each of the L clock signals LCLK1 and LCLK2 and the R clock signals RCLK1 and RCLK2 are maintained at the turn-on voltage is one horizontal period (1H), and the L clock signals LCLK1 and LCLK2 and the R clock The period of each of the signals RCLK1 and RCLK2 is four horizontal periods. Each of the L clock signals LCLK1 and LCLK2 and R clock signals RCLK1 and RCLK2 has two phases.

7 is a diagram showing voltage changes of main nodes according to the clock signals and the driving timing applied to the first stage. 5 and 7, the operation of the first stage will be described below.

At the first timing t1, the start signal VST_R is inverted to the low potential voltage VGL which is the turn-on voltage.

The first transistor (T1) precharges the QA node by applying a low potential voltage (VGL) to the QA node in response to the start signal (VST_R). The voltage of the Q node becomes the low potential voltage VGL which is the same level as the voltage of the QA node at the first timing t1 since the second transistor T2 always maintains the turn-on state.

The fifth transistor T5, in response to the start signal VST_R, applies a second high-potential voltage VGH2, which is a turn-off voltage, to the CB node. The fourth transistor T4 is turned off so that the current path through which the turn-on voltage is applied to the QB node through the fourth transistor T4 is cut off.

The eighth transistor T8, in response to the start signal VST_R, applies a second high potential voltage VGH2, which is a turn-off voltage, to the QB node. As a result, the carry pull-down transistor T7C and the scan pull-down transistor T7 are turned off. The carry signal CARRY (n) and the scan signal SCAN (n) are supplied to the second capacitor Cb2 since the second capacitor Cb2 keeps the voltage of the QB node stably at the turn-off voltage while the Q node is at the turn- Is maintained stably.

At the second timing t2, the first R clock signal RCLK1 is inverted to the low potential voltage VGL, and the Q node is bootstrapped. The Q node is bootstrapped according to the amount of voltage change when the first R clock signal RCLK1 is inverted from the second high potential voltage VGH2 to the low potential voltage VGL. As a result, the scan pull-up transistor T6 applies a low potential voltage VGL which is a turn-on voltage to the scan output terminal SRO_N, and the carry pull-up transistor T6C applies a turn- And applies the potential voltage VGL.

The second transistor T2 prevents an instantaneous large change in the drain voltage of the first transistor T1 when the Q node is bootstrapped. Without the second transistor T2, the voltage of the drain electrode of the first transistor T1 and the voltage of the source electrode of the third transistor T3 are significantly lowered when the Q node is bootstrapped. As a result, the first transistor T1 and the third transistor T3 are instantaneously subjected to a large electrical stress.

However, since the gate voltage of the second transistor T2 is always the low potential VGL, the voltage of the QA node corresponding to the source electrode of the second transistor T2 is lower than the low potential VGL It does not. This is because the second transistor T2 is turned off when the voltage of the QA node becomes lower than the low voltage VGL. Therefore, even if the Q node is bootstrapped, the QA node can maintain the low potential voltage VGL, and the voltage level between the drain and the source of the first transistor T1 can be prevented from changing instantaneously.

At the third timing t3, the first R clock signal RCLK1 is inverted to the second high potential voltage VGH2 so that the scan output stage SRO_N and the carry output stage CRO_N become the second high potential voltage VGH2 do. The second high-potential voltage VGH2 is higher than the first high-potential voltage VGH1 used for driving the pixel array 100A. When driving a typical shift register, the high-potential voltage of the clock signals utilizes the same voltage as the high-potential voltage applied to the pixel array. Since the high potential voltage of the R clock signals RCLK1 and RCLK2 and the L clock signals LCLK1 and LCLK2 applied to the shift register 140 is used as the second high potential voltage VGH2, The voltage variation amount of the scan output stage SRO_N and the carry output stage CRO_N becomes large at the timing t3. The increase in the voltage variation of the scan output stage SRO_N and the carry output stage CRO_N for a constant time means that the voltage change rate is large. That is, in the present invention, the delay in which the scan output terminal SRO_N and the carry output terminal CRO_N are inverted to the turn-off voltage is reduced. The delay effect of the scan signal output from the scan output stage SRO_N is improved, so that even if a scan signal is applied in one direction of the scan lines, the problem caused by the delay of the scan signal is improved.

At the fourth timing (t4), the second R clock signal RCLK2 becomes the turn-on voltage.

When the low potential voltage VGL is applied to the second capacitor Cb2, the CB node is bootstrapped and becomes the low potential voltage VGL. The CB node becomes the turn-on voltage, and the fourth transistor T4 applies the low potential voltage VGL to the QB node. The carry pull-down transistor T7C, in response to the QB node voltage, applies the second high potential voltage VGH2 to the carry output CRO_N. The scan pull-down transistor T7, in response to the QB node voltage, applies the first high potential voltage VGH1 to the scan output terminal SRO_N. The scan output terminal SRO_N rises to the second high potential voltage VGH2 of the first R clock signal RCLK1 at the third timing t3 and the scan output terminal SRO_N rises to the first high potential voltage VGH2 at the fourth timing t4, It is somewhat lowered to the high potential voltage (VGH1). That is, at the fourth timing t4, the scan output terminal SRO_N outputs a scan signal having the same voltage level as the first high-potential voltage VGH1 corresponding to the turn-on voltage for driving the pixels of the pixel array 100A .

The third transistor T3, in response to the QB node, applies a second high potential voltage VGH2 to the Q node. As a result, the scan pull-up transistor T6 and the carry pull-up transistor T6C are stably turned off.

As described above, the shift register according to the present invention controls the high-potential voltage of the clock signals LCLK1, LCKL2, RCLK1 and RCLK2 applied to the pull-up transistors T6 and T6C to the first classical And uses the second high-potential voltage VGH2 higher than the upper voltage VGH1. Therefore, the delay time at which the scan signal is turned off can be reduced, and the delay of the scan signal can be improved even if the scan line is driven by the single feeding method. Therefore, the size of the shift register of the present invention is half the size of the double-feeding type shift register, and as a result, the area in which the shift register is disposed can be reduced. That is, the bezel of the display panel can be greatly reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Accordingly, the technical scope of the present specification should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: timing controller
120: Data driving circuit 130: Level shifter
140: shift register STG: stage

Claims (10)

A pixel array in which pixels connected to a gate line are arranged; And
A first shift register for outputting a second (n is a natural number) scan signal in a data writing period of pixels arranged in the odd-numbered pixel line in synchronization with the timing of the L clock signal; And
And a second shift register for outputting a (2n-1) th scan signal in a data writing period of pixels arranged in an odd-numbered pixel line in synchronization with the timing of the R clock signal,
The voltage difference between the turn-on voltage and the turn-off voltage of the L clock signal and the R clock signal is a difference between the turn-on voltage of the L clock signal and the R clock signal, the second n scan signal and the (2n-1) The voltage difference between the turn-off voltage of the signal. The method according to claim 1,
Wherein the first shift register comprises a second n stage arranged on one side of the pixel array and connected to each other in a dependent manner,
The second shift register includes a (2 < n-1) > stage arranged on the other side of the pixel array and connected to each other in a dependent manner,
Wherein the (2n-1) th stage outputs the (2n-1) th scan signal. 3. The method of claim 2,
The second n stage outputs a carry signal used as a start signal of the second (n + 1) stage,
And the (2n-1) th stage outputs a carry signal used as a start signal of the second n-th stage. 3. The method of claim 2,
Wherein each of the pixels includes an organic light emitting diode and a driving transistor for driving the organic light emitting diode,
The second scan signal controls the timing of initializing the gate electrodes of the driving transistors of the second (n + 1) -th pixel line,
And the (2n-1) th scan signal controls the timing for initializing the gate electrode of the driving transistors of the second n-pixel line. The method according to claim 1,
Wherein the L clock signal and the R clock signal each maintain a turn-on voltage for one horizontal period, the period is four horizontal periods,
And the turn-on voltage sections of the L clock signal and the R clock signal do not overlap. A shift register comprising a stage for supplying a scan signal to pixels and being connected to each other in a dependent manner,
The stage
A start control unit for precharging a Q node in response to a start signal;
A scan pull-up transistor responsive to the Q node voltage for applying a voltage of a first clock signal to a scan output terminal;
A scan pull-up transistor responsive to the Q node voltage for applying a voltage of a first clock signal to a carry output;
A scan pull-down transistor for applying a first turn-off voltage to the scan output terminal in response to a QB node voltage having an opposite potential to the Q node; And
And a carry pull-down transistor responsive to the QB node voltage for applying a second turn-off voltage to the carry output,
And a voltage difference between the turn-on voltage of the clock signal and the second turn-off voltage is greater than a voltage difference between the turn-on voltage of the clock signal and the first turn-off voltage. The method according to claim 6,
Wherein the first turn-off voltage has the same voltage level as the turn-off voltage of the transistors disposed in the pixels. The method according to claim 6,
The start control unit
A first transistor connected between an input terminal of a low potential voltage and a QA node, and having a gate electrode receiving the start signal; And
And a second transistor connected between the QA node and the Q node and having a gate electrode connected to an input terminal of the low potential voltage. The method according to claim 6,
And a gate electrode connected between the input terminal of the low potential voltage and the QB node and connected to the CB node charged by the second clock signal,
Wherein the first clock signal and the second clock signal have two phases. 10. The method of claim 9,
Wherein the first clock signal and the second clock signal each have a period of four horizontal periods and have a pulse width of one horizontal period.

Images