KR20170141036A - Display Device - Google Patents

Abstract

The present invention relates to a display device which comprises a pixel array, a shift register, and a gate low voltage control unit. Data lines and gate lines are defined in the pixel array, and pixels are arranged in a matrix form. The shift register includes a stage connected to be subordinate thereto, and sequentially supplies a gate pulse swung between a gate high voltage and a gate low voltage to the gate lines. The gate low voltage control unit decreases the gate low voltage when a leakage current of the stages is greater than or equal to a predetermined level. An n^th stage includes a pull-up transistor, a pull-down transistor, a start control unit, and a QB node discharge control unit. The pull-up transistor charges an output terminal in response to a voltage of a Q node to output an n^th gate pulse. The pull-down transistor discharges the output terminal with the gate low voltage in response to the voltage of the QB node. The start control unit pre-charges the Q node in response to a start pulse or the gate pulse other than the n^th gate pulse.

Description

[0001]

The present invention relates to a display device.

The display device is arranged such that the data lines and the gate lines are orthogonal and the pixels are arranged in a matrix form. Video data voltages to be displayed are supplied to the data lines and gate pulses are sequentially supplied to the gate lines. The video data voltage is supplied to the pixels of the display line to which the gate pulse is supplied and all of the display lines are sequentially scanned by the gate pulse to display the video data.

The gate driver for supplying the gate pulse to the gate lines of the display device usually includes a plurality of gate integrated circuits (hereinafter referred to as "IC"). Since each of the gate drive ICs must sequentially output gate pulses, it basically includes a shift register and may include circuits and output buffers for adjusting the output voltage of the shift register depending on the driving characteristics of the display panel.

A gate driver for generating a gate pulse, which is a scan signal in a display device, may be implemented as a gate-in-panel (GIP) type in which a combination of thin film transistors is formed in a bezel region which is a non-display region in a display panel. The GIP type gate driver includes a stage corresponding to the number of gate lines, and each stage outputs a gate pulse to the corresponding gate line on a one-to-one basis.

The transistor characteristics curve of the thin film transistor included in the shift register is negatively shifted over time and the leakage current is increased. When the leakage current of a specific thin film transistor is increased, the transistors operate during an undesired period, causing a stress of the transistor to be worsened and heat generation to be increased.

In order to solve the above-mentioned problems, the present invention provides a display device capable of solving the problem caused by a leakage current of a transistor belonging to a shift register.

The display device of the present invention includes a pixel array, a shift register, and a gate low voltage control unit. Data lines and gate lines are defined in the pixel array, and pixels are arranged in a matrix form. The shift register includes a stage connected in a dependent manner, and sequentially supplies gate pulses to gate lines swinging between a gate high voltage and a gate low voltage. The gate low voltage control part lowers the gate low voltage when the leakage current of the stage is higher than a certain level. The n-th stage includes a pull-up transistor, a pull-down transistor, a start control section, and a QB node discharge control section. The pull-up transistor charges the output terminal in response to the voltage of the Q-node, and outputs the n-th gate pulse. The pull-down transistor discharges the output terminal to the gate-low voltage in response to the voltage of the QB node. The start control unit precharges the Q node in response to a start pulse or a gate pulse other than the nth gate pulse.

The present invention lowers the voltage level of the gate low voltage of the gate pulse according to the amount of leakage current of the stage. As a result, the voltage level of the gate electrode of the start control unit receiving the gate pulse as the carry signal is lowered, and the leakage current of the start control unit can be reduced. It is possible to prevent the Q node from being precharged in an undesired period if the amount of leakage current of the start control unit is reduced. As a result, it is possible to prevent the generation of the heat generation problem by operating the transistors for a long time due to the precharging of the Q node.

1 is a view showing a display device according to the present invention.
2 is a view showing a shift register according to the first embodiment.
3 is a view showing a stage according to the first embodiment.
4 is a timing chart showing the input and output of the shift register.
5 is a flowchart showing the operation of the gate low voltage control unit according to the present invention.
6 is a block diagram showing a configuration of a gate low voltage control unit according to the present invention.
7 is a diagram for explaining an increase in the amount of leakage current due to the shift of the transistor characteristic curve.
8 is a diagram showing a shift register according to the second embodiment.
9 is a view showing a stage according to the second embodiment.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

1 is a block diagram showing a display device according to an embodiment of the present invention. Referring to FIG. 1, the display apparatus of the present invention includes a display panel 100, a timing controller 110, a data driver 120, and scan drivers 130 and 150.

The display panel 100 includes a pixel array 100A in which data lines DL and gate lines GL are defined and pixels are arranged, a non-display region 100A in which various signal lines, pads, etc. are formed outside the pixel array 100A, (100B). The display panel 100 may be a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electrophoretic display (EPD), or the like.

The timing controller 110 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock DLCK through an LVDS or TMDS interface receiving circuit connected to an image board, . The timing controller 110 includes a data timing control signal DDC for controlling the operation timing of the data driver 120 and a gate timing control signal DDC for controlling the operation timing of the scan drivers 130 and 140 based on the input timing signal GDC).

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the shift start timing of the source drive ICs 120. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 120 based on the rising or falling edge.

The scan timing control signal includes a start pulse VST, a gate clock CLK, and the like. The start pulse VST is input to the shift register 130 to control the shift start timing. The gate clock CLK is level-shifted through the level shifter 150 and then input to the shift register 130.

The data driver 120 includes a plurality of source drive ICs (Integrated Circuits). The source drive ICs are supplied with digital video data (RGB) and source timing control signal (DDC) from the timing controller 110. The source driver ICs convert the digital video data RGB to a gamma voltage in response to the source timing control signal DDC to generate a data voltage and apply the data voltage to the data lines DL of the display panel 100 Supply.

The scan drivers 130 and 150 include a level shifter 150 and a shift register unit 130. The shift register unit 130 is formed in a gate-in-panel (GIP) manner in the non-display area 100B of the display panel 100. [

The level shifter 150 is formed on a printed circuit board (not shown) connected to the display panel 100 in the form of an IC. The level shifter 150 level-shifts the clock signals (CLK) and the start signal (VST) under the control of the timing controller 110, and supplies the level shift signals to the shift register unit 130.

The shift register unit 130 is formed by a combination of a plurality of thin film transistors (hereinafter referred to as TFT) in the non-display area 100B of the display panel 100 by the GIP method. The shift register unit 130 outputs gate pulses corresponding to the clock signals CLK and the start pulse VST.

The gate-low voltage controller 200 adjusts the gate-low voltage VGL_M according to the leakage current. As a result, the deterioration of the transistors included in the shift register 130 due to the leakage current can be improved.

2 is a diagram showing a stage of a shift register according to the first embodiment.

Referring to FIGS. 1 and 2, a shift register 130 according to the present invention includes first through n-th stages ST1 through STn, where n is a natural number of 2 or more. 2 shows the [n-3] stage STG [n-3] and the n-th stage STGn.

In the following description, the term "front stage" means that the stage is located at the upper portion of the reference stage. For example, with respect to the stage STk in which the k-th stage k is a natural number with 1 <k <n, the front stage may be any one of the first stage ST1 to the (k-1) th stage ST Indicate. Quot; rear stage "refers to a stage located at the bottom of the reference stage. For example, on the basis of the kth (1 &lt; k < n) stage STk, the last stage indicates either the k + 1 stage ST (k + 1) to the nth stage.

Each stage STG of the shift register 130 sequentially outputs the gate pulses Gout [1] to Gout [n]. For example, the [n-3] stage STG [n-3] outputs the [n-3] gate pulse Gout [n- 3], the nth stage STGn outputs the n- Gout [n]). To this end, each stage STG receives one gate clock among sequentially sequentially delayed gate clocks CLK. Gate clocks can be implemented in more than 6 phases to ensure sufficient charge time when driving at high speeds of 240Hz or more. The [n-3] gate pulse Gout [n-3] is applied to the [n-3] gate line and also serves as a carry signal transmitted to the nth stage. 2 shows that the carry signal input to the n-th stage STGn is the [n-3] gate pulse Gout [n-3], but the carry signal is not limited thereto.

FIG. 3 is a diagram showing the configuration of the stage shown in FIG. 2, and FIG. 4 is a diagram showing the timing and output signal of a driving signal input to the stage shown in FIG.

1 to 4, the stage STG of the shift register 130 includes a pull-up transistor Tpu, a pull-down transistor Tpd, and a node control circuit NCON .

The pull-up transistor Tpu includes a gate electrode connected to the Q node, a drain electrode connected to the gate clock (CLK) input terminal, and a source electrode connected to the output terminal Nout.

The pull-down transistor Tpd includes a gate electrode connected to the QB node, a drain electrode connected to the output node Nout, and a source electrode connected to the gate low voltage VGL_M input.

The node control circuit NCON controls the voltages of the Q node and the QB node and includes a start control part T1, a Q node discharge control part T6, a QB node discharge control part T5 and QB node charge control parts T2 and T3 , T4).

The start control unit T1 includes a gate electrode connected to the input terminal of the start pulse VST or the input terminal of the [n-3] th gate pulse Gout [n-3], a drain electrode connected to the input terminal of the high potential voltage And a source electrode connected to the node.

The QB node discharge control unit T5 includes a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode connected to a low potential voltage (VGL) input terminal.

The Q node discharge control unit T6 includes a gate electrode connected to the NEXT input terminal, a drain electrode connected to the Q node, and a source electrode connected to the low potential voltage (VGL) input terminal.

The QB node charge control sections T2, T3 and T4 include second to fourth transistors T2, T3 and T4. The gate electrode and the drain electrode of the second transistor T2 are connected to a high potential input terminal. The third transistor T3 includes a gate electrode connected to the Q node, a drain electrode connected to the source electrode of the second transistor T2, and a source electrode connected to the low potential voltage (VGL) input terminal. The fourth transistor T4 includes a gate electrode connected to the drain electrode of the third transistor T3, a drain electrode connected to the drain electrode of the second transistor T2, and a source electrode connected to the QB node.

The start control unit T1 pre-charges the Q node to the Q node in response to the start pulse VST or the [n-3] th gate pulse Gout [n-3].

When the gate clock CLK is input to the drain electrode of the pull-up transistor Tpu in the state where the Q node is precharged, the Q node is bootstrapped according to the voltage rise of the drain electrode of the pull-up transistor Tpu. As the Q node is bootstrapped, the potential difference between the gate and the source of the pull-up transistor Tpu increases, and the pull-up transistor Tpu is turned on. As a result, the pull-up transistor Tpu charges the output node Nout using the gate clock CLK. The output terminal Nout is connected to the gate line GL and the gate pulse Gout is applied to the gate line GL from the output terminal Nout.

After the gate clock CLK is inverted to the low level, the gate electrode of the Q node discharge control unit T6 receives the subsequent signal NEXT. The Q node discharge control section T6 is turned on in response to the downstream signal NEXT, and as a result, discharges the voltage of the Q node to the low potential voltage VGL.

4, since the Q node is kept at a high level during the period from &quot; t0 to t2 &quot;, the QB node discharge control section T5 is turned on, so that the gate electrode of the pulldown transistor Tpd is connected to the gate low voltage VGL_M, &Lt; / RTI &gt; That is, the QB node discharge control section T5 suppresses the operation of the pull-down transistor Tpd when the Q node is at the high level.

4, the voltage of the Q node is maintained at the low potential voltage in the period from &quot; t0 to t1 &quot; during which the start pulse VST is input and during the &quot; t1_t2 &quot; period during which the gate clock is input, The QB node discharge control section T5 does not operate.

The source electrode of the QB node discharge control unit T5 according to the first embodiment is connected to the gate low voltage VGL_M and the gate low voltage VGL_M is varied in accordance with the leakage current amount of the stage STG. The gate low voltage VGL_M is controlled by the gate low voltage control unit 200 to prevent malfunction of the QB node discharge control unit T5.

Hereinafter, the operation of the gate-low voltage control unit 200 will be described with reference to FIGS. 5 and 6. FIG.

FIG. 5 is a flowchart showing the operation of the gate low voltage control unit according to the present invention, and FIG. 6 is a block diagram showing the configuration of the gate low voltage control unit.

Referring to FIGS. 1 to 6, the gate low voltage control unit 200 senses the leakage current of the stage STG. In particular, the current measuring unit 210 of the gate low voltage control unit 200 can measure the leakage current of the start control unit T1. The leakage current of the start control section T1 can be measured based on the input line current amount of the low potential voltage VGL (S501)

The comparator 220 of the gate low voltage controller 200 determines whether the input line current amount of the low potential voltage VGL has reached a preset reference value or more. The amount of leakage current of the start control section T1 can be estimated based on the amount of current of the low potential voltage VGL since the amount of the low potential voltage VGL is proportional to the amount of leakage current of the start control section T1.

The gate-low voltage control unit 200 holds the gate-low voltage VGL_M and outputs it to the stage STG when the amount of current is equal to or smaller than the reference value (S505, S507)

On the other hand, the voltage regulator 230 of the gate low voltage controller 200 regulates the gate low voltage VGL_M when the amount of current is equal to or greater than the reference value. The voltage level of the initial gate low voltage VGL_M may be set equal to the low potential voltage VGL.

The start characteristic of the transistor T1 may be negatively shifted by degradation or stress. As shown in FIG. 7, when the characteristic curve of the transistor is negatively shifted from the second graph (2) to the first graph (1), the leakage current amount at the low potential voltage VGL is increased from "I1" to "I2".

When the amount of leakage current of the start control section T1 increases, the QB node discharge control section T5 may be turned on in a period other than the period from "t0 to t2". Thus, a current path from the fourth transistor T4 and the QB node discharge control section T5 to the input terminal of the low potential voltage VGL is formed. Since this current path is formed during most of the one frame except for the period of &quot; t0 to t3 &quot;, the fourth transistor T4 and the QB node discharge control unit T5 generate a heating problem for a long time.

The gate low voltage control unit 200 lowers the voltage level of the gate low voltage VGL_M when the input line current amount of the low potential voltage VGL is equal to or higher than the reference value. The gate low voltage VGL_M is a low level voltage value of the gate pulse Gout and the gate pulse Gout also serves as a carry signal inputted to the subsequent stage STG. That is, when the voltage level of the gate low voltage VGL_M is lowered, the low level voltage of the carry signal input to the start control section T1 of the subsequent stage STG is also lowered. Since the start control unit T1 receives a lower voltage except the period for precharging the Q node, the voltage level of Vgs of the start control unit T1 becomes lower. As a result, the leak current of the start control section T1 decreases during the period excluding the precharging interval, and the phenomenon that the Q node is undesirably charged is improved.

The gate low voltage control unit 200 can lower the voltage level of the gate low voltage VGL_M in proportion to the amount of change of the current value measured at the input line of the low potential voltage VGL. The input line current amount of the low potential voltage VGL is proportional to the negative shifted degree of the transistor characteristic curve of the start control section T1. The input line current amount of the low potential voltage () and the adjustment amount of the gate low voltage () can be stored in the look-up table based on the pre-calculated result (S509, S011)

FIG. 8 shows a shift register according to the second embodiment, and FIG. 9 shows a stage of the shift register shown in FIG. Hereinafter, the same components as those in the above-described embodiment in the description of the second embodiment will not be described in detail.

Referring to FIGS. 8 and 9, the shift register 130 according to the present invention includes first through n-th stages ST1 through STn, where n is a natural number of 2 or more. 2 shows the [n-3] stage STG [n-3] and the n-th stage STGn.

Each stage STG of the shift register 130 sequentially outputs the gate pulses Gout [1] to Gout [n]. For example, the [n-3] stage STG [n-3] outputs the [n-3] gate pulse Gout [n- 3], the nth stage STGn outputs the n- Gout [n]).

The stage STG of the shift register 130 includes first and second pull-up transistors Tpu1 and Tpu2, first and second pull-down transistors Tpd1 and Tpd2 and a node control circuit NCON.

The first pull-up transistor Tpu1 includes a gate electrode connected to the Q node, a drain electrode connected to the gate clock (CLK) input terminal, and a source electrode connected to the first output terminal Nout. The first pull-up transistor Tpu1 includes a gate electrode connected to the Q node, a drain electrode connected to the gate clock (CLK) input terminal, and a source electrode connected to the second output terminal Nout2.

The first pull-down transistor Tpd1 includes a gate electrode connected to the QB node, a drain electrode connected to the first output terminal Nout1, and a source electrode connected to a low potential voltage (VGL) input terminal. The second pull-down transistor Tpd2 includes a gate electrode connected to the QB node, a drain electrode connected to the second output terminal Nout2, and a source electrode connected to the gate low voltage VGL_M input terminal.

The node control circuit NCON controls the voltages of the Q node and the QB node and includes a start control part T1, a QB node discharge control part T5, a Q node discharge control part T6 and QB node charge control parts T2 and T3 , T4).

The start control unit T1 includes a gate electrode connected to the input terminal of the start pulse VST or the input terminal of the [n-3] th gate pulse Gout [n-3], a drain electrode connected to the input terminal of the high potential voltage And a source electrode connected to the node.

The QB node discharge control unit T5 includes a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode connected to a low potential voltage (VGL) input terminal.

The Q node discharge control unit T6 includes a gate electrode connected to the NEXT input terminal, a drain electrode connected to the Q node, and a source electrode connected to the low potential voltage (VGL) input terminal.

The QB node charge control sections T2, T3, and T4 include second to fourth transistors. The gate electrode and the drain electrode of the second transistor T2 are connected to a high potential input terminal. The third transistor T3 includes a gate electrode connected to the Q node, a drain electrode connected to the source electrode of the second transistor T2, and a source electrode connected to the low potential voltage (VGL) input terminal. The fourth transistor T4 includes a gate electrode connected to the drain electrode of the third transistor T3, a drain electrode connected to the drain electrode of the second transistor T2, and a source electrode connected to the QB node.

The driving signal input to the stage of the second embodiment shown in Figs. 8 and 9 may be the same as the driving signal shown in Fig. 4 as in the first embodiment.

The first output terminal Nout1 of the stage of the second embodiment is connected to the gate line GL and the second output terminal Nout2 is inputted to the start control section T1 of the subsequent stage as a carry signal. 8 shows an embodiment in which the carry signal of the [n-3] stage STG [n-3] is input to the n-th stage. However, the stage to which the carry signal is input is not limited thereto.

The shift register according to the second embodiment separates the carry signal from the output terminal for outputting the gate pulse. The gate low voltage (VGL_M) of the second output terminal, which is input to the carry signal of the subsequent stage, is adjusted according to the leakage current amount of the shift register. As a result, the shift register according to the second embodiment can also improve degradation of transistors due to leakage current.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

100: display panel 110: timing controller
120: Data driver 130, 150: Gate driver
200: gate low voltage control unit

Claims (8)

A pixel array in which data lines and gate lines are defined, and pixels are arranged in a matrix form;
A shift register for sequentially supplying a gate pulse swinging between a gate high voltage and a gate low voltage to the gate lines, the shift register including a stage connected in a dependent manner; And
And a gate low voltage controller for lowering the gate low voltage when the leakage current of the stage is higher than a predetermined level,
The nth (n is a natural number) stage
A pull-up transistor that charges the output terminal in response to the voltage of the Q node and outputs an n-th gate pulse;
A pull-down transistor responsive to the voltage of the QB node for discharging said output to said gate low voltage;
And a start control unit for precharging the Q node in response to a start pulse or a gate pulse other than the n-th gate pulse. The method according to claim 1,
The n-th stage
And a QB node discharge control unit comprising a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode connected to the low potential voltage input line,
The gate-low voltage control unit
And lowers the gate-low voltage when the current value of the low-potential-voltage input line is equal to or greater than a preset reference value. 3. The method of claim 2,
The n-th stage
And a Q node discharge control unit comprising a gate electrode connected to a rear stage signal input terminal, a drain electrode connected to the Q node, and a source electrode connected to a low potential voltage input terminal. The method of claim 3,
The n-th stage
A second transistor having a gate electrode and a drain electrode connected to a high potential input terminal;
A transistor having a gate electrode connected to the Q node, a drain electrode connected to a source electrode of the second transistor, and a source electrode connected to the low potential voltage input terminal; And
A QB charge control unit comprising a fourth transistor including a gate electrode connected to a drain electrode of the third transistor, a drain electrode connected to a drain electrode of the second transistor, and a source electrode connected to the QB node,
And the QB charge control unit charges the QB node during a period in which the Q node is not charged. The method according to claim 1,
Wherein the pull-up transistor is connected to the gate clock input and the output,
The pull-down transistor being coupled to the output and gate low voltage inputs,
And the gate pulse output from the output stage is input to the gate electrode of the start control unit of any stage in the subsequent stage. 3. The method of claim 2,
Wherein an initial voltage of the gate low voltage is set equal to the low potential voltage. A pixel array in which data lines and gate lines are defined, and pixels are arranged in a matrix form;
A shift register for sequentially supplying a gate pulse swinging between a gate high voltage and a gate low voltage to the gate lines, the shift register including a stage connected in a dependent manner; And
And a gate low voltage controller for lowering the gate low voltage when the leakage current of the stage is higher than a predetermined level,
The nth (n is a natural number) stage
A first pull-up transistor that charges the first output terminal in response to the voltage of the Q node and outputs an nth gate pulse;
A first pull-down transistor responsive to a voltage of a QB node for discharging the first output terminal to a low potential voltage;
A second pull-up transistor that charges the second output terminal in response to the voltage of the Q node and outputs an n-th carry signal;
A second pull-down transistor responsive to a voltage of the QB node for discharging the second output terminal to the gate low voltage;
And a start control unit for precharging the Q node in response to a start pulse or a carry signal other than the n-th carry signal. 8. The method of claim 7,
The gate-low voltage control unit
And lowers the gate-low voltage when the current value at the input line of the low-potential voltage is equal to or greater than a preset reference value.

Images