KR20170005239A - Organic light emitting display device and driving method thereof - Google Patents

Abstract

The present invention relates to an organic light emitting display device. The present invention provides an organic light emitting display device for initializing the gate-source voltage of a driving transistor by using a scan transistor, which does not flow initialization current, of a plurality of scan transistors. The present invention includes: a panel having a plurality of data lines and a plurality of gate lines arranged thereon; a data driving unit which drives the data line; and a gate driving unit which drives the gate line.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting display and a driving method thereof.

Conventionally, a pixel of an OLED display has a structure in which an organic light emitting diode, a driving transistor for driving the organic light emitting diode, a scan transistor for inputting a scan signal, and a sensing transistor for inputting a reference voltage are connected to various signal lines.

In this pixel structure, when the scan transistor and the sensing transistor are turned on, the data voltage is supplied to the gate of the driving transistor and the reference voltage is supplied to the source of the driving transistor. At this time, the initializing current flows through the driving transistor and the sensing transistor.

However, when the initializing current flows through the sensing transistor, a voltage drop occurs in the sensing transistor due to the turn-on resistance in the sensing transistor. This voltage drop causes the reference voltage to not be transmitted to the source of the driving transistor.

When a data voltage corresponding to a high gradation is supplied to the driving transistor, the magnitude of the initialization current becomes larger, thereby causing the above-described voltage drop to be larger.

On the other hand, when the source voltage of the driving transistor increases according to the voltage drop described above, there arises a problem that the data voltage becomes larger to represent the same gradation.

The turn-on resistance of the sensing transistor may be different for each pixel. The difference in the turn-on resistance of each pixel may be caused by process variation or may be caused by the degree of deterioration.

When the difference in the turn-on resistance occurs, the voltage drop is different for each pixel. Thus, the two pixels supplied with the same data voltage may exhibit different brightnesses. When such a difference in turn-on resistance occurs between adjacent pixels, the pattern of the stain may be observed in the image according to the brightness difference of the pixel.

In view of the foregoing, it is an object of the present invention to provide a technique for forming a gate-source voltage of a driving transistor without being affected by an initialization current.

In another aspect, an object of the present invention is to provide a technique for transferring a voltage substantially equal to a reference voltage to a source of a driving transistor.

In order to achieve the above object, in one aspect, the present invention provides an organic light emitting display device including a plurality of scan transistors and using a scan transistor having no initialization current among a plurality of scan transistors to initialize a gate- A display device is provided.

According to another aspect of the present invention, there is provided an organic light emitting display including a panel in which a plurality of pixel regions are defined and in which a plurality of data lines and a plurality of gate lines are arranged, a data driver driving a data line and a gate driver driving a gate line Device. The organic light emitting display device of the present invention includes an organic light emitting diode in which an anode is connected to a first node, a driving transistor in which a second node and a driving voltage line are connected and a data voltage is supplied to the gate, An emitter transistor disposed between the first node and the second node and supplied with a gate emission signal, a first scan transistor for connecting the gate of the driving transistor and the data line according to a scan signal, A second scan transistor for connecting the reference voltage line, a third scan transistor for connecting the second node and the reference voltage line according to the scan signal, and a storage capacitor between the gate and the first node of the drive transistor.

As described above, according to the present invention, by forming the gate-source voltage of the driving transistor without being influenced by the initialization current, the pixel can be driven uniformly regardless of the characteristic difference of the transistors disposed in each pixel .

1 is a schematic system configuration diagram of an organic light emitting display according to embodiments.
2 is an equivalent circuit diagram illustrating a pixel structure of an organic light emitting diode display according to an exemplary embodiment.
3 is a diagram showing a main signal and a main node waveform in an initialization step and an emission step of the organic light emitting diode display.
4 is a diagram showing a transistor driving state and a voltage / current flow in the initialization step of the OLED display device.
5 is a view for explaining a voltage waveform of the storage capacitor in the initialization step of the organic light emitting diode display.
6 is a view showing a transistor driving state and a voltage / current flow in the emissive step of the organic light emitting display device.
7 is a diagram showing a main signal, a storage capacitor voltage, and a gate-source voltage waveform of a driving transistor in an initialization step and an emission step of an organic light emitting display device.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference symbols as possible even if they are shown in different drawings. In the following description of the embodiments of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected to or connected to the other component, It should be understood that an element may be "connected," "coupled," or "connected." In the same context, when an element is described as being formed on an "upper" or "lower" side of another element, the element may be formed either directly or indirectly through another element As will be understood by those skilled in the art.

1 is a schematic system configuration diagram of an organic light emitting display according to embodiments.

1, an OLED display 100 may include a panel 110, a data driver 120, a gate driver 130, and a timing controller 140. Referring to FIG.

A plurality of data lines DL are arranged in the panel 110 and a plurality of gate lines GL are arranged in the panel 110. The data lines DL correspond to the intersections of the data lines DL and the gate lines GL. A plurality of pixel regions (P) may be defined.

The panel 110 may include a display panel and a touch panel (TSP), wherein the display panel and the touch panel may be separate from each other, .

The data driver 120 drives the data line DL to display the digital image on each pixel area P of the panel 110. [

The data driver 120 may include at least one data driver integrated circuit such as a Tape Automated Bonding (TAB) or a Chip On Glass (COG) On glass may be connected to the bonding pad of the panel 110 or may be directly formed on the panel 110 or integrated on the panel 110 as the case may be. In addition, the data driver 120 may be implemented by a chip on film (COF) method.

The gate driver 130 drives the gate line GL to turn on or off the transistor located in each pixel region P. [

1, the gate driving unit 130 may be located on one side of the panel 110, or on both sides of the panel 110 divided into two, as shown in FIG.

In addition, the gate driver 130 may include at least one gate driver integrated circuit, such as a tape automated bonding (TAB) or a chip on glass (COG) (Gate In Panel) type and may be directly formed on the panel 110, or may be integrated on the panel 110 as the case may be. In addition, the gate driver 130 may be implemented by a chip on film (COF) method.

The timing controller 140 supplies various control signals to the data driver 120 and the gate driver 130 and supplies image data corresponding to the digital image signals to the data driver 120. The data driver 120 supplies data voltages to the data lines 116 according to the image data.

At least one organic light emitting diode (OLED) including an anode, a cathode, and an organic light emitting layer may be disposed in each pixel region P of the panel 110. The organic light emitting layer included in each organic light emitting diode (OLED) may include at least one organic light emitting layer or a white organic light emitting layer among organic light emitting layers for red, green, blue, and white.

A plurality of transistors and capacitors may be disposed in each pixel region P of the panel 110.

2 is an equivalent circuit diagram illustrating a pixel structure of an organic light emitting diode display according to an exemplary embodiment.

2, the pixel region P includes an organic light emitting diode OLED, a driving transistor DT, an emission transistor ET, a first scan transistor ST1, a second scan transistor ST2, A scan transistor ST3 and a storage capacitor Cst may be arranged.

The anode of the organic light emitting diode (OLED) may be connected to the first node (N1), and the cathode may be connected to the low potential voltage (EVSS).

The driving transistor DT may be disposed between the second node N2 and the driving voltage line DVL. At this time, the drain (or source) of the driving transistor DT is connected to the driving voltage EVDD through the driving voltage line DVL, the source (or drain) is connected to the second node N2, 3 node N3.

The emission transistor ET may be connected in series with the driving transistor DT. The emission transistor ET may be disposed between the first node N1 and the second node N2. At this time, the drain (or source) of the emission transistor ET may be connected to the second node N2, and the source (or drain) may be connected to the organic light emitting diode OLED through the first node N1. The gate of the emission transistor ET may be connected to an emission line (not shown), and an emission signal may be supplied to the emission line (not shown).

In the pixel region P, three scan transistors receiving the scan signal SCAN as a gate may be disposed.

The first scan transistor ST1 connects the gate of the driving transistor DT and the data line DL in accordance with the scan signal SCAN. To this end, the drain (or source) of the first scan transistor ST1 may be connected to the gate of the driving transistor DT through the third node N3, and the source (or drain) may be connected to the data line DL have. The gate of the first scan transistor ST1 may be supplied with a scan signal SCAN through a gate line (see GL in FIG. 1) while being connected to a gate line (see GL in FIG. 1).

The second scan transistor ST2 connects the first node N1 and the reference voltage line RVL according to the scan signal SCAN. To this end, the drain (or source) of the second scan transistor ST2 may be connected to the first node N1, and the source (or drain) may be connected to the reference voltage line RVL. In addition, the gate of the second scan transistor ST2 may receive the scan signal SCAN through the gate line (see GL in FIG. 1) while being connected to the gate line (see GL in FIG. 1).

The third scan transistor ST3 connects the second node N2 and the reference voltage line RVL according to the scan signal SCAN. To this end, the drain (or source) of the third scan transistor ST3 may be connected to the second node N2, and the source (or drain) may be connected to the reference voltage line RVL. The gate of the third scan transistor ST3 may be supplied with a scan signal SCAN through a gate line (see GL in FIG. 1) while being connected to a gate line (see GL in FIG. 1).

A storage capacitor Cst may be disposed between the third node N3, which is the gate node of the driving transistor DT, and the first node N1. One electrode of the storage capacitor Cst may be connected to the third node N3 and the other electrode may be connected to the first node N1.

Electrode capacitance may exist in the transistors DT, ET, ST1, ST2, and ST3 disposed in the pixel region P. For example, in the transistors DT, ET, ST1, ST2, and ST3, gate-source capacitors formed between the gate electrode and the source electrode, gate-drain capacitors formed between the gate electrode and the drain electrode, A drain-source capacitor formed between the electrodes, and the like. In FIG. 2, not all of these electrode capacitances are shown. For convenience of explanation, a gate-source capacitor formed between the gate electrode of the driving transistor DT and the second node N2 (the drain electrode of the driving transistor DT, Only the gate-drain capacitor is connected to the second node N2.

The reference voltage line RVL may be supplied with a reference voltage VREF from a reference voltage source (not shown) while being connected to a reference voltage source (not shown). The data line DL may be connected to a DAC (Digital to Analog Converter) disposed in a data driver (see 120 in FIG. 1), and may receive a data voltage from the DAC. The second scan transistor ST2 and the third scan transistor ST3 may be connected to an analog-to-digital converter (ADC) through a switch SAM. The organic light emitting diode display 100 may be driven The threshold voltage of the transistor DT or the emission transistor ET can be compensated.

Meanwhile, the organic light emitting diode OLED disposed in the pixel region P may be driven according to a driving method including an initialization step and an emission step.

FIG. 3 is a view showing a main signal and a main node waveform in the initialization step and the emission step of the OLED display device, and FIG. 4 is a view showing a transistor driving state and a voltage / FIG.

3 and 4, in the initialization step, the scan signal SCAN has a high level period and the first scan transistor ST1, the second scan transistor ST2, and the third scan transistor ST2 are turned on according to the scan signal SCAN. The scan transistor ST3 is turned on.

The data line DL and the gate of the driving transistor DT are connected to each other and the data voltage Vdata is transferred to the gate of the driving transistor DT in accordance with the turn-on of the first scan transistor ST1.

When the second scan transistor ST2 is turned on, the reference voltage line RVL and the first node N1 are connected and the reference voltage VREF is transmitted to the first node N1.

The drain and source of the emission transistor ET are not connected because the emission signal EM supplied to the gate of the emission transistor ET maintains a low level. In another aspect, in the initialization step, the first node N1 and the second node N2 are kept disconnected without being connected.

At this time, since the storage capacitor Cst is arranged between the third node N3 and the first node N1, the data voltage Vdata is supplied to one side N3 of the storage capacitor Cst and the data voltage Vdata is supplied to the other side N1 The reference voltage VREF is supplied. The storage capacitor Cst is charged by the data voltage Vdata and the reference voltage VREF.

5 is a view for explaining a voltage waveform of the storage capacitor in the initialization step of the organic light emitting diode display.

5, data voltages Vdata and Vdata are applied to both sides of the storage capacitor Cst during a period in which the scan signal SCAN maintains a high level and on the other side in the turn-on period T1 of the second scan transistor ST2. The reference voltage VREF is supplied to charge the storage capacitor Cst.

The storage capacitor Cst is charged with the data voltage Vdata-reference voltage VREF in the turn-on period T1 of the second scan transistor ST2.

The time T2 at which the storage capacitor Cst is charged with the data voltage Vdata-the reference voltage VREF is shorter than the turn-on period T1 of the second scan transistor ST2. In another aspect, charging of the storage capacitor Cst is completed before the second scan transistor ST2 is turned off.

Referring to FIG. 5, the charge current Iref flowing through the second scan transistor ST2 does not flow after the charge time T2 has elapsed. There may be a slight leakage current in the second scan transistor ST2 but the magnitude of the current flowing to the second scan transistor ST2 at a point in time immediately before the turn-off of the second scan transistor ST2 is less than a predetermined value or does not substantially flow Can be the same.

When the turn-on period T1 of the second scan transistor ST2 is set longer than the charge period T2 of the storage capacitor, the second scan transistor ST2 is turned off, (ST2) is turned off. In this case, the second scan transistor ST2 is turned off in a state where there is no voltage drop due to the turn-on resistance of the second scan transistor ST2. Accordingly, the voltage of the first node N1 is substantially equal to the reference voltage Becomes substantially equal to the voltage of the line RVL or the reference voltage VREF.

Since the first scan transistor ST1 is driven by the same scan signal SCAN as the second scan transistor ST2, the turn-on period T1 of the first scan transistor ST1 is also connected to the charge period of the storage capacitor Cst The gate voltage of the third node N3, that is, the driving transistor DT becomes substantially equal to the data line DL voltage or the data voltage Vdata.

As a result, since the storage capacitor Cst is turned off and the first and second scan transistors ST1 and ST2 are turned off in a state where the charging is completed and no current flows, the voltage Vst formed in the storage capacitor Cst, Becomes substantially equal to the voltage (data voltage (Vdata) - reference voltage (VREF)).

Referring again to FIGS. 3 and 4, the reference voltage line RVL and the second node N2 are connected in accordance with the turn-on of the third scan transistor ST3 in a period in which the scan signal SCAN is at a high level And the reference voltage is transmitted to the second node N2.

The voltage is transferred to the third node N3 which is the gate of the driving transistor DT and the second node N2 which is the source of the driving transistor DT so that the gate-source capacitor Cgs of the driving transistor DT A voltage is formed. At this time, the gate-source capacitor Cgs of the driving transistor DT may be the parasitic capacitance between the gate node and the source node of the driving transistor DT.

As the gate-source voltage Vgs becomes larger than the threshold voltage of the driving transistor DT, the initializing current Iprog flows to the driving transistor DT. Since the emission transistor ET is turned off in the initialization step, the initialization current does not flow to the second scan transistor ST2 but flows to the third scan transistor ST3.

At this time, the magnitude of the initialization current Iprog may be determined according to the magnitude of the data voltage Vdata. For example, if the data voltage Vdata corresponding to a high gradation is supplied to the driving transistor DT, the magnitude of the initialization current Iprog can be larger and the data voltage Vdata corresponding to the low gradation can be supplied to the driving transistor DT, the magnitude of the initialization current Iprog may be smaller.

The third scan transistor ST3 has a turn-on resistance. The turn-on resistance and the initialization current Iprog cause a voltage drop dV across the third scan transistor ST3. Since the initialization current Iprog is continuously maintained in the turn-on period of the third scan transistor ST3, the voltage drop dV is continuously maintained in the turn-on period of the third scan transistor ST3.

The voltage of the second node N2 is formed higher than the reference voltage VREF according to the voltage drop dV. For reference, the direction of the initialization current Iprog may be reversed. In this embodiment, the voltage of the second node N2 may be lower than the reference voltage VREF.

Referring to the voltage waveforms of the first node N1 and the second node N2 shown in Fig. 3, in the initialization step, the voltage of the first node N1 has a value substantially equal to the reference voltage VREF The voltage of the second node N2 has a voltage higher than the reference voltage VREF by the voltage drop dV of the second scan transistor ST2.

The second scan transistor ST2 and the third scan transistor ST3 are disposed for each pixel region P and the turn-on of at least two third scan transistors ST3 disposed in different pixel regions P The resistor size may be different. The difference in the magnitude of the turn-on resistance may be caused by a process deviation or a difference in degree of deterioration. Accordingly, the voltage drop (dV) of the third scan transistor ST3 may be different from each other.

Likewise, the magnitude of the turn-on resistance of the second scan transistor ST2 may also be different for each pixel. However, in spite of this variation, the voltage of the first node N1 does not vary by pixel. The second scan transistor ST2 is completed in a state in which no current flows, so that the voltage of the first node N1 does not differ from pixel to pixel.

Accordingly, the voltage Vst of the storage capacitor Cst also does not differ from pixel to pixel. Since the organic light emitting diode display 100 according to the embodiment uses the voltage Vst formed in the storage capacitor Cst, the OLED display 100 can drive the driving transistor DT without being affected by the initialization current Iprog do.

The organic light emitting diode display 100 thus forms the voltage Vst of the storage capacitor Cst irrespective of the initialization current Iprog in the initialization step and then the voltage Vst of the storage capacitor Cst in the emissive step And is injected into the gate-source voltage Vgs of the driving transistor DT.

6 is a view showing a transistor driving state and a voltage / current flow in the emissive step of the organic light emitting display device.

3 and 6, in the emissive step, the scan signal SCAN is at the low level and the emission signal EM is at the high level. The transistors DT, ET, ST1, ST2 and ST3 are turned on when the high level signal is input to the gate and turned off when the low level signal is inputted for convenience of explanation. However, When the low level signal is input, and when the high level signal is input, it may be turned off.

The timing at which the scan signal SCAN switches from the high level to the low level and the timing at which the emission signal EM changes from the low level to the high level can be the same. The time point at which the scan signal SCAN is switched from the high level to the low level may be faster than the time at which the emission signal EM is switched from the low level to the high level. However, the timing at which the scan signal SCAN is switched from the high level to the low level is not slower than the timing at which the emission signal EM is switched from the low level to the high level.

When the scan signal SCAN is switched to the low level, the first scan transistor ST1, the second scan transistor ST2, and the third scan transistor ST3 are all turned off.

Then, the emission transistor ET is turned on in accordance with the emission signal EM. At this time, the emission transistor ET is turned on after the second scan transistor ST2 and the third scan transistor ST3 are turned off according to the following relationship between the scan signal SCAN and the emission signal EM . In this case, the initialization current Iprog can be prevented from flowing to the second scan transistor ST2.

When the emission transistor ET is turned on, the drive transistor DT and the emission transistor ET are both connected, so that the drive current Iem due to the drive voltage EVDD can be transmitted to the organic light emitting diode OLED have.

At this time, the magnitude of the driving current Iem can be determined by the gate-source voltage Vgs of the driving transistor DT.

The gate-source voltage Vgs of the driving transistor DT is determined by the second node N2 and the third node N3 in the initialization step. In the emission step, the first node N1 and the third node N3 N3).

When the emission transistor ET is turned on in the emissive step, the charge stored in the storage capacitor Cst and the charge stored in the gate-source capacitor Cgs of the driving transistor DT are shared.

At this time, the capacitance of the storage capacitor Cst may be larger than the capacitance of the gate-source capacitor Cgs. According to an embodiment, the capacitance of the storage capacitor Cst may be greater than five times the capacitance of the gate-source capacitor Cgs. Also, according to the embodiment, the storage capacitor Cst may have a capacitance according to the design and the capacitance of the gate-source capacitor Cgs may be parasitic capacitance.

The charge stored in the storage capacitor Cst becomes much larger than the charge stored in the gate-source capacitor Cgs since the capacitance of the storage capacitor Cst is larger than the capacitance of the gate-source capacitor Cgs. Accordingly, the charge stored in the storage capacitor Cst plays a dominant role in the charge sharing period, and the voltage (Vdata-VREF) charged in the storage capacitor Cst is substantially maintained. Since the voltage Vst of the storage capacitor Cst becomes equal to the gate-source voltage Vgs of the driving transistor DT due to charge sharing, the gate-source voltage Vgs of the driving transistor DT also becomes Vdata RTI ID = 0.0 > VREF < / RTI >

7 is a diagram showing a main signal, a storage capacitor voltage, and a gate-source voltage waveform of a driving transistor in an initialization step and an emission step of an organic light emitting display device.

Referring to FIGS. 3 and 7, the storage capacitor voltage Vst and the driving transistor DT are turned on during a period in which the scan signal SCAN is at a high level and the scan transistors ST1, ST2, The gate-source voltage Vgs of the transistor Q1 increases. At this time, the gate-source voltage Vst of the driving transistor DT rises more rapidly because the capacitance of the gate-source capacitor Cgs of the driving transistor DT is larger than the capacitance of the storage capacitor Cst It is because it is small.

The storage capacitor voltage Vst and the gate-source voltage Vst of the driving transistor DT are saturated to a constant value. When the final value of the storage capacitor voltage Vst is equal to the gate-source voltage Vst of the driving transistor DT, Lt; / RTI > The storage capacitor voltage Vst is saturated at the final size of Vdata-VREF in the initialization step, and the gate-source voltage Vst of the driving transistor DT is saturated to Vdata-VREF-dV.

In the emissive step, the storage capacitor Cst and the gate-source capacitor Cgs of the driving transistor DT are charge-shared. At this time, since the capacitance of the storage capacitor Cst is much larger than the capacitance of the gate-source capacitor Cgs of the driving transistor DT, the storage capacitor voltage Vst does not substantially change, The gate-source voltage Vgs of the storage capacitor DT is changed to the same voltage as the storage capacitor voltage Vst.

Through this process, the gate-source voltage Vgs of the driving transistor DT becomes substantially equal to the voltage of Vdata-VREF. The driving current (Iem in Fig. 6) of the driving transistor DT is determined by the gate-source voltage Vgs of the driving transistor DT. Since the magnitude of the gate-source voltage Vgs of this driving transistor DT is determined to be a voltage substantially equal to Vdata-VREF, the driving current Iem is supplied to the data voltage Vdata and the reference voltage VREF ). ≪ / RTI >

The panel 110 is further provided with an emission line (not shown) through which the emission signal EM is transmitted, and an emission line (not shown) may be driven by the gate driver 130. The OLED display 100 further includes a reference voltage supply unit (not shown). The reference voltage supply unit (not shown) may supply a reference voltage to the reference voltage line RVL.

As described above, according to the present invention, the gate-source voltage of the driving transistor can be formed without being affected by the initialization current. Further, according to the present invention, a voltage substantially equal to the reference voltage can be transmitted to the source of the driving transistor.

Thus, when the gate-source voltage of the driving transistor can be formed without being influenced by the initializing current or a voltage substantially equal to the reference voltage can be transferred to the source of the driving transistor, the characteristic difference of the transistors (for example, ) Can be solved.

Since the initialization current flows through the third scan transistor and does not flow to the second scan transistor in the initialization step, a voltage which is not affected by the initialization current may be formed in the storage capacitor connected to the second scan transistor. Further, since the voltage formed in such a storage capacitor is fully used as the gate-source voltage of the driving transistor in the emission step, the organic light emitting display can form the gate-source voltage of the driving transistor without being affected by the initialization current .

It is to be understood that the terms "comprises", "comprising", or "having" as used in the foregoing description mean that the constituent element can be implanted unless specifically stated to the contrary, But should be construed as further including other elements. All terms, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Commonly used terms, such as predefined terms, should be interpreted to be consistent with the contextual meanings of the related art, and are not to be construed as ideal or overly formal, unless expressly defined to the contrary.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

Claims (10)

A panel in which a plurality of pixel regions are defined and a plurality of data lines and a plurality of gate lines are arranged;
A data driver driving the data lines; And
And a gate driver for driving the gate line,
In the pixel region,
An organic light emitting diode in which the anode is connected to the first node,
A driving transistor arranged between the second node and the driving voltage line and supplied with a data voltage to the gate,
An emitter transistor disposed between the first node and the second node and supplied with a gate emission signal,
A first scan transistor for connecting a gate of the driving transistor and a data line according to a scan signal,
A second scan transistor for connecting the first node and the reference voltage line according to the scan signal,
A third scan transistor for connecting the second node and the reference voltage line according to the scan signal,
And a storage capacitor is disposed between a gate of the driving transistor and the first node. The method according to claim 1,
Wherein the panel is further provided with an emission line through which the emission signal is transmitted,
Wherein the emission line is driven by the gate driver. The method according to claim 1,
An initializing current is formed in the driving transistor in the turn-on period of the second scan transistor and the third scan transistor, and the initializing current flows to the third scan transistor. The method of claim 3,
And the emit transistor is turned on after the second scan transistor and the third scan transistor are turned off. The method of claim 3,
And the storage capacitor (data voltage-reference voltage) is charged in the turn-on period of the second scan transistor. 6. The method of claim 5,
Wherein a capacitance of the storage capacitor is larger than a capacitance of a gate-source capacitor formed in the driving transistor. The method according to claim 6,
Wherein the emission transistor is turned on and the charge of the storage capacitor and the charge of the gate-source capacitor of the driving transistor are shared. The method of claim 3,
Wherein the third scan transistor has a turn-on resistance and a voltage higher or lower than the reference voltage is formed at the second node by the initialization current. 9. The method of claim 8,
Wherein at least two third scan transistors disposed in different pixel regions have different turn-on resistance magnitudes. The method of claim 3,
Wherein a current does not flow to the second scan transistor immediately before the second scan transistor is turned off or a current flowing to the second scan transistor is less than a predetermined value.

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