KR102295351B1 - Organic light emitting display device and driving method thereof - Google Patents

Abstract

The present invention provides an organic light emitting display device that includes a plurality of scan transistors and initializes a gate-source voltage of a driving transistor by using a scan transistor through which an initialization current does not flow among the plurality of scan transistors.

Description

Organic light emitting display device and driving method thereof

The present invention relates to an organic light emitting display device and a driving method thereof.

A pixel of a conventional organic light emitting display device has a structure in which an organic light emitting diode, a driving transistor for driving the organic light emitting diode, a scan transistor for inputting a scan signal, and a sensing transistor for inputting a reference voltage are connected to various signal lines.

In this pixel structure, when the scan transistor and the sensing transistor are turned on, the data voltage is supplied to the gate of the driving transistor and the reference voltage is supplied to the source of the driving transistor. And, at this time, the initialization current flows through the driving transistor and the sensing transistor.

However, when this initialization current flows through the sensing transistor, a voltage drop occurs in the sensing transistor due to the turn-on resistance in the sensing transistor. And, this voltage drop causes the reference voltage to not be completely transmitted to the source of the driving transistor.

When the data voltage corresponding to the high gray level is supplied to the driving transistor, the magnitude of the initialization current becomes larger, and accordingly, the above-described voltage drop occurs larger.

On the other hand, when the source voltage of the driving transistor increases according to the above-described voltage drop, a problem occurs in that the data voltage increases by that amount in order to express the same grayscale.

The turn-on resistance of the sensing transistor may be different for each pixel. Such a difference in turn-on resistance for each pixel may be due to a deviation in the process or may be due to a difference in the degree of deterioration.

When a difference occurs in the turn-on resistance as described above, the magnitude of the voltage drop is different for each pixel. Accordingly, two pixels receiving the same data voltage may exhibit different brightnesses. If such a difference in turn-on resistance occurs between adjacent pixels, a speckle pattern may be observed in the video image according to the difference in brightness of the pixels.

Against this background, it is an object of the present invention to provide a technique for forming a gate-source voltage of a driving transistor without being affected by an initialization current.

In another aspect, an object of the present invention is to provide a technique for transferring a voltage substantially equal to a reference voltage to a source of a driving transistor.

In order to achieve the above object, in one aspect, the present invention provides an organic light-emitting device that includes a plurality of scan transistors and initializes the gate-source voltage of the driving transistor using a scan transistor in which an initialization current does not flow among the plurality of scan transistors. display is provided.

In another aspect, the present invention provides an organic light emitting display including a panel in which a plurality of pixel regions are defined and a plurality of data lines and a plurality of gate lines are disposed, a data driver driving the data lines and a gate driver driving the gate lines provide the device. In addition, in the pixel region of the organic light emitting diode display provided by the present invention, an organic light emitting diode having an anode connected to the first node, a driving transistor disposed between the second node and a driving voltage line and supplied with a data voltage to the gate, An emission transistor disposed between the first node and the second node and supplied with an emission signal to the gate, a first scan transistor connecting the gate and data line of the driving transistor according to a scan signal, and the first node and the first node according to a scan signal A storage capacitor is disposed between the gate and the first node of the second scan transistor connecting the reference voltage line, the third scan transistor connecting the second node and the reference voltage line according to the scan signal, and the driving transistor.

As described above, according to the present invention, by forming the gate-source voltage of the driving transistor without being affected by the initialization current, it is possible to drive the pixels uniformly regardless of the difference in characteristics of the transistors disposed in each pixel. .

1 is a schematic system configuration diagram of an organic light emitting diode display according to example embodiments.
2 is an equivalent circuit diagram illustrating a pixel structure of an organic light emitting diode display according to an exemplary embodiment.
3 is a diagram illustrating main signals and main node waveforms in an initialization stage and an emission stage of an organic light emitting diode display.
4 is a diagram illustrating a transistor driving state and a flow of voltage/current in an initialization stage of an organic light emitting diode display.
5 is a diagram for explaining a voltage waveform of a storage capacitor in an initialization step of an organic light emitting diode display.
6 is a diagram illustrating a transistor driving state and a flow of voltage/current in an emission stage of an organic light emitting diode display.
7 is a diagram illustrating main signals, a storage capacitor voltage, and a gate-source voltage waveform of a driving transistor in an initialization step and an emission step of the organic light emitting diode display.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to the components of each drawing, it should be noted that the same components are given the same reference numerals as much as possible even though they are indicated on different drawings. In addition, in describing the embodiments of the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

In addition, in describing the components of the invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the components from other components, and the essence, order, or order of the components are not limited by the terms. When a component is described as being “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but another component is between each component. It should be understood that elements may be “connected,” “coupled,” or “connected.” In the same vein, when it is described that a component is formed "on" or "below" another component, the component is both formed directly on the other component or indirectly through another component. should be understood as including

1 is a schematic system configuration diagram of an organic light emitting diode display according to example embodiments.

Referring to FIG. 1 , the organic light emitting diode display 100 may include a panel 110 , a data driver 120 , a gate driver 130 , and a timing controller 140 .

In the panel 110 , a plurality of data lines (DL) are disposed, and a plurality of gate lines (GL) are disposed, corresponding to the intersections of the data lines (DL) and the gate lines (GL). A plurality of pixel areas (P: Pixels) may be defined at a position where

The panel 110 may include a display panel and a touch screen panel (TSP), where the display panel and the touch panel may be separated from each other, or an integrated panel may be formed while sharing some components. It can also be configured.

The data driver 120 drives the data line DL to display a digital image in each pixel region P of the panel 110 .

The data driver 120 may include at least one data driver integrated circuit. The at least one data driver integrated circuit may include a Tape Automated Bonding (TAB) method or a Chip on Glass (COG) method. It may be connected to a bonding pad of the panel 110 in an on-glass method, or may be directly formed on the panel 110 , or may be integrated and disposed on the panel 110 in some cases. In addition, the data driver 120 may be implemented in a chip on film (COF) method.

The gate driver 130 drives the gate line GL to turn on or off the transistor located in each pixel region P.

The gate driver 130 may be positioned on only one side of the panel 110 as shown in FIG. 1 or may be divided into two and positioned on both sides of the panel 110 according to a driving method.

In addition, the gate driver 130 may include at least one gate driver integrated circuit, and the at least one gate driver integrated circuit may be formed using a tape automatic bonding (TAB) method or a chip-on-glass (COG) method. It may be connected to the bonding pad of 110 , or may be implemented as a GIP (Gate In Panel) type and directly formed on the panel 110 , or may be integrated and disposed on the panel 110 in some cases. In addition, the gate driver 130 may be implemented in a chip on film (COF) method.

The timing controller 140 supplies various control signals to the data driver 120 and the gate driver 130 , and supplies image data corresponding to a digital image signal to the data driver 120 . The data driver 120 supplies a data voltage to each data line 116 according to the image data.

At least one organic light emitting diode (OLED) including an anode, a cathode, and an organic light emitting layer may be disposed in each pixel area P of the panel 110 . The organic light emitting layer included in each organic light emitting diode (OLED) may include at least one organic light emitting layer or a white organic light emitting layer among red, green, blue, and white organic light emitting layers.

A plurality of transistors and capacitors may be disposed in each pixel region P of the panel 110 .

2 is an equivalent circuit diagram illustrating a pixel structure of an organic light emitting diode display according to an exemplary embodiment.

Referring to FIG. 2 , in the pixel region P, an organic light emitting diode (OLED), a driving transistor (DT), an emission transistor (ET), a first scan transistor (ST1), a second scan transistor (ST2), and a third A scan transistor ST3 and a storage capacitor Cst may be disposed.

The anode of the organic light emitting diode OLED may be connected to the first node N1 , and the cathode may be connected to the low potential voltage EVSS.

The driving transistor DT may be disposed between the second node N2 and the driving voltage line DVL. At this time, the drain (or source) of the driving transistor DT is connected to the driving voltage EVDD through the driving voltage line DVL, the source (or drain) is connected to the second node N2, and the gate is connected to the first It may be connected to the 3 node N3.

The emission transistor ET may be connected in series with the driving transistor DT. The emission transistor ET may be disposed between the first node N1 and the second node N2 . In this case, the drain (or source) of the emission transistor ET may be connected to the second node N2 , and the source (or drain) may be connected to the organic light emitting diode OLED through the first node N1 . In addition, the gate of the emission transistor ET may be connected to an emission line (not shown), and an emission signal may be supplied to the emission line (not shown).

In the pixel region P, three scan transistors receiving the scan signal SCAN to the gate may be disposed.

The first scan transistor ST1 connects the gate of the driving transistor DT and the data line DL according to the scan signal SCAN. To this end, the drain (or source) of the first scan transistor ST1 may be connected to the gate of the driving transistor DT through the third node N3 , and the source (or drain) may be connected to the data line DL. have. Also, the gate of the first scan transistor ST1 may receive the scan signal SCAN through the gate line (refer to GL of FIG. 1 ) while being connected to the gate line (see GL of FIG. 1 ).

The second scan transistor ST2 connects the first node N1 and the reference voltage line RVL according to the scan signal SCAN. To this end, the drain (or source) of the second scan transistor ST2 may be connected to the first node N1 , and the source (or drain) may be connected to the reference voltage line RVL. Also, the gate of the second scan transistor ST2 may be connected to the gate line (see GL of FIG. 1 ) and receive the scan signal SCAN through the gate line (see GL of FIG. 1 ).

The third scan transistor ST3 connects the second node N2 and the reference voltage line RVL according to the scan signal SCAN. To this end, the drain (or source) of the third scan transistor ST3 may be connected to the second node N2 , and the source (or drain) may be connected to the reference voltage line RVL. Also, the gate of the third scan transistor ST3 may be connected to the gate line (see GL of FIG. 1 ) and receive the scan signal SCAN through the gate line (see GL of FIG. 1 ).

A storage capacitor Cst may be disposed between the third node N3 and the first node N1, which are gate nodes of the driving transistor DT. One electrode of the storage capacitor Cst may be connected to the third node N3 , and the other electrode may be connected to the first node N1 .

An electrode capacitance may exist in the transistors DT, ET, ST1, ST2, and ST3 disposed in the pixel region P. For example, in the transistors DT, ET, ST1, ST2, and ST3, a gate-source capacitor formed between the gate electrode and the source electrode, a gate-drain capacitor formed between the gate electrode and the drain electrode, a drain electrode, and a source There may be a drain-source capacitor formed between the electrodes, and the like. Not all of these electrode capacitances are shown in FIG. 2 , and for convenience of explanation, a gate-source capacitor (drain electrode of the driving transistor DT) formed between the gate electrode of the driving transistor DT and the second node N2 is When connected to the second node N2, only the gate-drain capacitor) is shown.

The reference voltage line RVL may receive the reference voltage VREF from the reference voltage source (not shown) while being connected to the reference voltage source (not shown). The data line DL may receive a data voltage from the DAC while being connected to a digital to analog converter (DAC) disposed in the data driver (see 120 of FIG. 1 ). In addition, the second scan transistor ST2 and the third scan transistor ST3 may be connected to an analog to digital converter (ADC) through a switch SAM, and the organic light emitting diode display 100 is driven using the ADC. The threshold voltage of the transistor DT or the emission transistor ET may be compensated.

Meanwhile, the organic light emitting diode OLED disposed in the pixel region P may be driven according to a driving method including an initialization step and an emission step.

3 is a diagram illustrating main signals and main node waveforms in an initialization step and an emission step of an organic light emitting diode display, and FIG. 4 is a diagram illustrating a transistor driving state and voltage/current flows in an initialization step of the organic light emitting diode display. It is a drawing.

3 and 4 , in the initialization step, the scan signal SCAN has a high level section, and according to the scan signal SCAN, the first scan transistor ST1, the second scan transistor ST2, and the third The scan transistor ST3 is turned on.

When the first scan transistor ST1 is turned on, the data line DL and the gate of the driving transistor DT are connected, and the data voltage Vdata is transferred to the gate of the driving transistor DT.

Then, according to the turn-on of the second scan transistor ST2 , the reference voltage line RVL and the first node N1 are connected, and the reference voltage VREF is transmitted to the first node N1 .

Since the emission signal EM supplied to the gate of the emission transistor ET maintains a low level, the drain and the source of the emission transistor ET are not connected. From another aspect, in the initialization step, the first node N1 and the second node N2 are not connected and remain separated.

At this time, since the storage capacitor Cst is disposed between the third node N3 and the first node N1, the data voltage Vdata is supplied to one side N3 of the storage capacitor Cst and the other side N1 ), the reference voltage VREF is supplied. The storage capacitor Cst is charged by the data voltage Vdata and the reference voltage VREF.

5 is a diagram for explaining a voltage waveform of a storage capacitor in an initialization step of an organic light emitting diode display.

Referring to FIG. 5 , in the period in which the scan signal SCAN maintains the high level, and in the turn-on period T1 of the second scan transistor ST2 from the other side, the data voltage Vdata and When the reference voltage VREF is supplied, the storage capacitor Cst is charged.

In the turn-on period T1 of the second scan transistor ST2, the storage capacitor Cst (data voltage Vdata-reference voltage VREF) is charged.

The time T2 during which the storage capacitor Cst is charged to the (data voltage Vdata-reference voltage VREF) is shorter than the turn-on period T1 of the second scan transistor ST2. In another aspect, the charging of the storage capacitor Cst is finished before the second scan transistor ST2 is turned off.

Referring to FIG. 5 , the charging current Iref flowing through the second scan transistor ST2 does not flow after the charging time T2 has elapsed. Although there may be a minute leakage current in the second scan transistor ST2, the magnitude of the current flowing into the second scan transistor ST2 immediately before the turn-off of the second scan transistor ST2 is less than a predetermined value or does not flow substantially. may be the same.

As described above, when the turn-on period T1 of the second scan transistor ST2 is set longer than the charging period T2 of the storage capacitor, in a state in which no current substantially flows in the second scan transistor ST2, the second scan transistor (ST2) is turned off. In this case, the second scan transistor ST2 is turned off in a state where there is no voltage drop due to the turn-on resistance of the second scan transistor ST2. Accordingly, the voltage of the first node N1 is substantially the reference voltage. It becomes substantially equal to the voltage of the line RVL or the reference voltage VREF.

Since the first scan transistor ST1 is driven by the same scan signal SCAN as the second scan transistor ST2, the turn-on period T1 of the first scan transistor ST1 is also the charging period of the storage capacitor Cst ( T2), and accordingly, the gate voltage of the third node N3, that is, the driving transistor DT, is also substantially equal to the data line DL voltage or the data voltage Vdata.

As a result, the storage capacitor (Cst) is the voltage (Vst) formed in the storage capacitor (Cst) because the first scan transistor (ST1) and the second scan transistor (ST2) are turned off in a state where charging is completed and no current flows is substantially equal to (data voltage Vdata-reference voltage VREF).

Referring back to FIGS. 3 and 4 , in a section in which the scan signal SCAN becomes high level, the reference voltage line RVL and the second node N2 are connected according to the turn-on of the third scan transistor ST3, and The reference voltage is transmitted to the second node N2.

As the voltage is transferred to the third node N3 that is the gate of the driving transistor DT and the second node N2 that is the source of the driving transistor DT, the voltage is applied to the gate-source capacitor Cgs of the driving transistor DT. voltage is formed. In this case, the gate-source capacitor Cgs of the driving transistor DT may be a parasitic capacitance between the gate node and the source node of the driving transistor DT.

As the gate-source voltage Vgs becomes greater than the threshold voltage of the driving transistor DT, the initialization current Iprog flows through the driving transistor DT. Since the emission transistor ET is turned off in the initialization step, the initialization current does not flow to the second scan transistor ST2 but to the third scan transistor ST3.

In this case, the magnitude of the initialization current Iprog may be determined according to the magnitude of the data voltage Vdata. For example, when the data voltage Vdata corresponding to the high gray level is supplied to the driving transistor DT, the size of the initialization current Iprog may be increased, and the data voltage Vdata corresponding to the low gray level is supplied to the driving transistor ( DT), the magnitude of the initialization current Iprog may be smaller.

The third scan transistor ST3 has a turn-on resistance, and a voltage drop dV occurs across the third scan transistor ST3 by the turn-on resistance and the initialization current Iprog. Since the initialization current Iprog is continuously maintained during the turn-on period of the third scan transistor ST3, this voltage drop dV is continuously maintained during the turn-on period of the third scan transistor ST3.

According to the voltage drop dV, the voltage of the second node N2 is higher than the reference voltage VREF. For reference, the direction of the initialization current Iprog may be reversed. In this embodiment, the voltage of the second node N2 may be lower than the reference voltage VREF.

Referring to the voltage waveforms of the first node N1 and the second node N2 shown in FIG. 3 , in the initialization step, the voltage of the first node N1 has substantially the same value as the reference voltage VREF. However, the voltage of the second node N2 has a voltage greater than the reference voltage VREF by the voltage drop dV of the second scan transistor ST2.

Meanwhile, a second scan transistor ST2 and a third scan transistor ST3 are disposed in each pixel area P, and at least two third scan transistors ST3 disposed in different pixel areas P are turned on. The resistor sizes may be different. Such a difference in the magnitude of the turn-on resistance may be due to a process deviation or a difference in the degree of deterioration. Accordingly, the magnitude of the voltage drop dV of the third scan transistor ST3 may also be different from each other.

Similarly, the size of the turn-on resistance of the second scan transistor ST2 may be different for each pixel. However, despite the deviation, the voltage of the first node N1 does not differ for each pixel. Since the second scan transistor ST2 is finished in a state in which no current flows, the voltage of the first node N1 does not differ for each pixel.

Accordingly, the voltage Vst of the storage capacitor Cst also does not differ for each pixel. Since the organic light emitting diode display 100 according to an embodiment uses the voltage Vst formed on the storage capacitor Cst, the driving transistor DT can be driven without being affected by the initialization current Iprog. do.

In this way, the organic light emitting display device 100 forms the voltage Vst of the storage capacitor Cst irrespective of the initialization current Iprog in the initialization step, and then increases the voltage Vst of the storage capacitor Cst in the emission step. It is injected into the gate-source voltage Vgs of the driving transistor DT.

6 is a diagram illustrating a transistor driving state and a flow of voltage/current in an emission stage of an organic light emitting diode display.

3 and 6 , in the emission stage, the scan signal SCAN becomes a low level, and the emission signal EM becomes a high level. For convenience of description, it is described that the transistors DT, ET, ST1, ST2, and ST3 are turned on when a high-level signal is input to the gate and are turned off when a low-level signal is inputted to the gate. It may be turned on when a low-level signal is input and turned off when a high-level signal is input.

A time when the scan signal SCAN is converted from a high level to a low level and a time when the emission signal EM is converted from a low level to a high level may be the same. Also, a time at which the scan signal SCAN switches from a high level to a low level may be earlier than a time at which the emission signal EM transitions from the low level to the high level. However, the time at which the scan signal SCAN switches from the high level to the low level is not slower than the time at which the emission signal EM changes from the low level to the high level.

When the scan signal SCAN is switched to the low level, the first scan transistor ST1 , the second scan transistor ST2 , and the third scan transistor ST3 are all turned off.

Then, the emission transistor ET is turned on according to the emission signal EM. At this time, after the second scan transistor ST2 and the third scan transistor ST3 are turned off according to the precedence relationship between the scan signal SCAN and the emission signal EM, the emission transistor ET is to be turned on. can In this case, it is possible to prevent the initialization current Iprog from flowing into the second scan transistor ST2.

When the emission transistor ET is turned on, since both the driving transistor DT and the emission transistor ET are connected, the driving current Iem by the driving voltage EVDD can be transferred to the organic light emitting diode OLED. have.

In this case, the magnitude of the driving current Iem may be determined by the gate-source voltage Vgs of the driving transistor DT.

The gate-source voltage Vgs of the driving transistor DT was determined by the second node N2 and the third node N3 in the initialization step, and in the emission step, the first node N1 and the third node (N1) N3).

When the emission transistor ET is turned on in the emission stage, the charge stored in the storage capacitor Cst and the charge stored in the gate-source capacitor Cgs of the driving transistor DT are shared.

In this case, the capacitance of the storage capacitor Cst may be greater than the capacitance of the gate-source capacitor Cgs. In some embodiments, the capacitance of the storage capacitor Cst may be 5 times or more greater than the capacitance of the gate-source capacitor Cgs. Also, according to an embodiment, the storage capacitor Cst may have a capacitance according to a design, and the capacitance of the gate-source capacitor Cgs may be a parasitic capacitance.

Since the capacitance of the storage capacitor Cst is greater than the capacitance of the gate-source capacitor Cgs, the charge stored in the storage capacitor Cst becomes much larger than the charge stored in the gate-source capacitor Cgs. Accordingly, in the charge sharing period, the charge stored in the storage capacitor Cst plays a dominant role, and the voltage Vdata-VREF charged in the storage capacitor Cst is substantially maintained. Also, since the voltage Vst of the storage capacitor Cst and the gate-source voltage Vgs of the driving transistor DT are equal to each other due to charge sharing, the gate-source voltage Vgs of the driving transistor DT is also Vdata It will be substantially equal to the -VREF voltage.

7 is a diagram illustrating main signals, a storage capacitor voltage, and a gate-source voltage waveform of a driving transistor in an initialization step and an emission step of an organic light emitting diode display.

Referring to FIGS. 3 and 7 , the storage capacitor voltage Vst and the driving transistor DT are turned on in a section in which the scan signal SCAN becomes high level, and in a section in which the scan transistors ST1, ST2, and ST3 are turned on from the other side. ) of the gate-source voltage (Vgs) rises. At this time, the gate-source voltage Vst of the driving transistor DT rises faster, which is because the capacitance of the gate-source capacitor Cgs of the driving transistor DT is much greater than the capacitance of the storage capacitor Cst. because it is small

The storage capacitor voltage Vst and the gate-source voltage Vst of the driving transistor DT are saturated to a predetermined value, and the final value of the storage capacitor voltage Vst is the gate-source voltage Vst of the driving transistor DT. greater than the final value of The storage capacitor voltage Vst is finally saturated to the level of Vdata-VREF in the initialization step, and the gate-source voltage Vst of the driving transistor DT is saturated to Vdata-VREF-dV.

In the emission stage, the storage capacitor Cst and the gate-source capacitor Cgs of the driving transistor DT share charge. At this time, since the capacitance of the storage capacitor Cst is much larger than the capacitance of the gate-source capacitor Cgs of the driving transistor DT, substantially no change occurs in the storage capacitor voltage Vst. The gate-source voltage Vgs of DT) is changed to the same voltage as the storage capacitor voltage Vst.

Through this process, the gate-source voltage Vgs of the driving transistor DT becomes substantially the same as the voltage Vdata-VREF. The driving current of the driving transistor DT (refer to Iem of FIG. 6 ) is determined by the gate-source voltage Vgs of the driving transistor DT. However, since the gate-source voltage Vgs of the driving transistor DT is determined to be substantially the same as Vdata-VREF, the driving current Iem is the data voltage Vdata and the reference voltage VREF. ) is precisely controlled by

Meanwhile, an emission line (not shown) to which the emission signal EM is transmitted is further disposed on the panel 110 , and the emission line (not shown) may be driven by the gate driver 130 . Also, the organic light emitting diode display 100 further includes a reference voltage supply unit (not shown), and the reference voltage supply unit (not shown) may supply a reference voltage to the reference voltage line RVL.

As described above, according to the present invention, the gate-source voltage of the driving transistor can be formed without being affected by the initialization current. Also, according to the present invention, a voltage substantially equal to the reference voltage may be transmitted to the source of the driving transistor.

In this way, when the gate-source voltage of the driving transistor is formed without being affected by the initialization current or a voltage substantially equal to the reference voltage can be transmitted to the source of the driving transistor, the difference in characteristics of the transistors (eg, the difference in turn-on resistance) ) can solve the problem of pixel brightness difference.

In the initialization step, since the initialization current flows only through the third scan transistor and does not flow through the second scan transistor, a voltage unaffected by the initialization current may be formed in the storage capacitor connected to the second scan transistor. In addition, since the voltage formed on the storage capacitor is fully used as the gate-source voltage of the driving transistor in the emission step, the organic light emitting diode display can form the gate-source voltage of the driving transistor without being affected by the initialization current. .

Terms such as "include", "compose" or "have" described above mean that the corresponding component may be embedded unless otherwise stated, so it does not exclude other components. It should be construed as being able to further include other components. All terms, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs, unless otherwise defined. Terms commonly used, such as those defined in the dictionary, should be interpreted as being consistent with the meaning of the context of the related art, and are not interpreted in an ideal or excessively formal meaning unless explicitly defined in the present invention.

The above description is merely illustrative of the technical spirit of the present invention, and various modifications and variations will be possible without departing from the essential characteristics of the present invention by those skilled in the art to which the present invention pertains. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

Claims (10)

a panel in which a plurality of pixel regions are defined and a plurality of data lines and a plurality of gate lines are disposed;
a data driver for driving the data line; and
and a gate driver for driving the gate line;
In the pixel area,
An organic light emitting diode having an anode connected to the first node,
a driving transistor disposed between the second node and the driving voltage line and supplied with a data voltage to a gate;
an emission transistor disposed between the first node and the second node and supplied with an emission signal to a gate;
a first scan transistor connecting a gate of the driving transistor and a data line according to a scan signal;
a second scan transistor connecting the first node and a reference voltage line according to the scan signal;
a third scan transistor connecting the second node and the reference voltage line according to the scan signal; and
and a storage capacitor disposed between a gate of the driving transistor and the first node. According to claim 1,
An emission line through which the emission signal is transmitted is further disposed on the panel,
and the emission line is driven by the gate driver. According to claim 1,
An initialization current is formed in the driving transistor in a turn-on period of the second scan transistor and the third scan transistor, and the initialization current flows into the third scan transistor. 4. The method of claim 3,
An organic light emitting display device in which the emission transistor is turned on after the second scan transistor and the third scan transistor are turned off. 4. The method of claim 3,
An organic light emitting display device in which (data voltage-reference voltage) is charged in the storage capacitor during a turn-on period of the second scan transistor. 6. The method of claim 5,
A gate-source capacitor is formed between the gate node and the source node of the driving transistor,
An organic light emitting diode display having a capacitance of the storage capacitor greater than a capacitance of the gate-source capacitor. 7. The method of claim 6,
The emission transistor is turned on, and the charge of the storage capacitor and the charge of the gate-source capacitor of the driving transistor are shared. 4. The method of claim 3,
A turn-on resistance exists in the third scan transistor, and a voltage higher or lower than a reference voltage is formed at the second node by the initialization current. 9. The method of claim 8,
An organic light emitting display device having different turn-on resistances of at least two third scan transistors disposed in different pixel areas. 4. The method of claim 3,
An organic light emitting display device in which no current flows through the second scan transistor or the magnitude of the current flowing through the second scan transistor is equal to or less than a predetermined value immediately before the second scan transistor is turned off.

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