KR20190024465A - Gate driving circuit and organic light emitting display using the same - Google Patents

Abstract

An organic light emitting display device according to the present invention comprises: pixels connected to a gate line; and a gate driving circuit made of a plurality of stages supplying a gate signal applied to at least one of the gate lines and dependently connected to each other. The n^th stage of the gate driving circuit includes a Q1 node charging unit charging a Q1 node with a turn-on voltage and a full-up transistor applying the turn-on voltage to an output terminal in response to a Q1 node voltage using first and second clock signals having antiphase, wherein n is a natural number. The Q1 node charging unit includes a first charging unit charging the Q1 node voltage with the turn-on voltage and a second charging unit charging a Q2 node coupled to the Q1 node using a first clock signal in a section where the Q1 node is charged with the turn-on voltage using a second clock signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate driving circuit and an organic light emitting diode (OLED)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driving circuit having improved driving capability and an OLED display using the same.

Flat panel displays (FPDs) are widely used not only for monitors of desktop computers but also for portable computers such as notebook computers and tablets, as well as mobile phone terminals, due to their advantages of miniaturization and light weight. Currently, various types of display devices such as a curved display, a flexible display, a rollable display, and a wearable display have been developed not only in the flat panel display, have. Such display devices include a liquid crystal display (LCD) (LCD), a plasma display panel (PDP), a field emission display An organic light emitting diode (OLED), and a quantum dot display (QD).

Among these, the organic light emitting display device has advantages of high response speed, high luminance efficiency, and large viewing angle. In general, an organic light emitting display uses a transistor turned on by a scan signal to apply a data voltage to a gate electrode of a driving transistor, and charges a data voltage supplied to the driving transistor to a storage capacitor. The organic light emitting element emits light by outputting the data voltage charged to the storage capacitor using the emission control signal.

The OLED display device is driven using an emission signal and one or more scan signals. The gate driving circuit for generating the emission signal and the scan signals, which are gate signals, generally includes a shift register for sequentially outputting the gate signals. The gate driving circuit may be implemented as a gate-in-panel (GIP) type in which a bezel region in a display panel is a non-display region and a combination of thin film transistors. The gate driving circuit of the GIP type has a stage corresponding to the number of gate lines, and each stage outputs a gate pulse supplied to the corresponding gate line on a one-to-one basis.

The shift register can be implemented in various forms, and a method for optimizing the circuit configuration for improving the driving capability of the gate driving circuit and for increasing the reliability of the driving is being sought.

As mentioned above, the gate driver circuit can be implemented in the form of a gate driver in panel (GIP), which is a technique embedded in a display panel together with a pixel array. Such a gate drive circuit may be referred to as a GIP circuit. The GIP circuit includes a shift register, and the stages constituting the shift register generate an output in response to a start pulse, and can shift the output according to the clock signal. That is, the gate driving circuit has stages including a plurality of transistors, and the stages may be connected in a cascading manner to sequentially generate outputs. In this case, the transistor may include a thin film transistor (TFT) as a kind of transistor.

The stages may each include a Q node for controlling a pull-up transistor, and a QB (Q bar) node for controlling a pull-up transistor. For example, each of the stages may include transistors for charging and discharging the Q node and the QB node voltage in opposition to each other in response to a start voltage signal and a clock signal input from the front stage.

The QB node is charged and discharged as opposed to the Q node. When the Q node is a high potential voltage, the QB node becomes a low potential voltage, and when the Q node is a low potential voltage, the QB node becomes a high potential voltage. When a low potential voltage is applied to the Q node or the QB node, the pull-up transistor or the pull-down transistor is turned on. When a high potential voltage is applied to the Q node or the QB node, the pull- ), Thereby turning on / off the transistor connected to the gate line. One electrode of each of the pull-up transistor and the pull-down transistor is connected to the output terminal, and the output terminal is connected to the gate line for providing the gate signal to the pixel array.

As mentioned above, the output signal is applied to the output terminal by the Q node and the QB node. Therefore, if the Q node or the QB node is floated, the voltage of the Q node or the QB node may fluctuate without being fixed, so that an erroneous output signal may be output.

Accordingly, the inventors of the present invention recognized the above-mentioned problems and devised a gate driving circuit for improving driving capability and driving reliability of a gate driving circuit, and invented a display using the same.

The present invention provides a gate driving circuit in which a Q node is not floated and a high potential voltage or a low potential voltage is applied so that a wrong output is not generated at an output node so that driving capability and reliability are improved, And a display device using the same.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

An organic light emitting display according to the present invention includes a gate driving circuit including a plurality of stages connected to each other and supplying gate signals to at least one of pixels connected to a gate line and gate lines. The n-th (n is a natural number) stage of the gate drive circuit uses a first and a second clock signal having opposite phases to each other to supply a Q1 node charging unit for charging the Q1 node to a turn- On-state voltage to the output terminal. The Q1 node charging unit uses a second clock signal to couple a first charging unit charging the Q1 node voltage to the turn-on voltage and a Q1 node coupled to the Q1 node using the first clock signal in the period where the Q1 node is the turn-on voltage And a second charging unit charging the node Q2.

The gate drive circuit according to the present specification is composed of a plurality of stages which are connected in a dependent manner, and outputs a gate signal. Each of the plurality of stages outputs the gate signal using the first and second clock signals. The nth (n is a natural number) stage of the plurality of stages includes a pull-up transistor responsive to the Q1 node voltage for applying a turn-on voltage to the output stage, a first capacitor connected between nodes Q1 and Q2, A first transistor including a gate electrode connected to the input terminal, a source electrode connected to the input terminal of the start signal, and a drain electrode connected to the node Q1, a gate electrode connected to the node Q1, a source electrode connected to the input terminal of the first clock signal, And a second transistor including a connected drain electrode.

The display device according to the present specification can stably maintain the voltage of the node controlling the pull-up transistor of the gate drive circuit, thereby improving the driving ability and reliability of the gate drive circuit and enabling the display device to display an image accurately.

The scope of the claims is not limited to the matters described in the description of the specification, as the contents of the description in the problems, the solutions to the problems, and the effects described above do not specify the essential features of the claims.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a diagram showing the configuration of an organic light emitting diode display according to the present invention; FIG.
2 is a diagram showing a configuration of a gate drive circuit according to the present specification.
3 is a view showing a stage of the gate drive circuit shown in Fig.
4 is a view showing a detailed configuration of a stage according to the first embodiment.
5 is a timing chart of clock signals driving the stage shown in FIG.
Fig. 6 is a view showing a detailed configuration of a stage according to the second embodiment.
7 is a timing chart showing the timing of the clock signals driving the stage shown in Fig.

Brief Description of the Drawings The advantages and features of the present disclosure, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that the description is not limited to the embodiments disclosed herein but is to be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and this specification is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description of the present invention, a detailed description of known related arts will be omitted when it is determined that the gist of the present specification may be unnecessarily obscured. In the case where the word 'includes', 'having', 'done', etc. are used in this specification, other parts can be added unless '~ only' is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical concept of the present specification.

It is to be understood that each of the features of the various embodiments herein may be combined or combined with each other, partially or wholly, and technically various interlocking and driving are possible, and that the embodiments may be practiced independently of each other, It is possible.

In the gate driving circuit of the present specification, the switching elements may be implemented as n-type or p-type metal oxide semiconductor field effect transistor (MOSFET) transistors. Although p-type transistors are exemplified in the following embodiments, the present specification is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, the current flows from the source to the drain because the holes flow from the source to the drain. The source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. In the following embodiments, the invention is not limited to the source and the drain of the transistor.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a diagram showing a configuration of a display device according to the present invention; FIG.

1, the organic light emitting display according to the present invention includes a display panel 10, a data driver 120, gate drivers 130 and 140, and a timing controller 110 in which pixels P are arranged in a matrix form. Respectively.

The display panel 10 includes a display portion 10A in which pixels P are disposed and an image is displayed and a non-display portion 10B in which a gate driving circuit 140 is disposed and an image is not displayed.

The display unit 10A includes a plurality of pixels P, and displays an image based on the gradation displayed by each of the pixels P. [ The pixels P are arranged along the first to n-th pixel lines HL1 to HLn. Each pixel P is connected to a data line DL arranged along a column line and connected to a gate line GL arranged along a pixel line HL. That is, the pixels arranged in the same pixel line share the same gate line GL and are simultaneously driven. When the pixels arranged in the first pixel line HL1 are defined as the first pixels P1 and the pixels arranged in the nth pixel line HLn are defined as the nth pixels Pn, (P1) to the n-th pixel (Pn) are sequentially driven. A sampling period for writing data into one scan line can be defined as one horizontal period (1H).

The gate line GL may include an emission line and a plurality of scan lines depending on the pixel structure. The gate line GL according to an embodiment of the present invention includes a first scan line SL1, a second scan line SL2, and an emission line EML, as shown in FIG.

The timing controller 110 is for controlling the driving timing of the data driver 120 and the gate driver. To this end, the timing controller 110 rearranges the digital video data RGB input from the outside according to the resolution of the display panel 10 and supplies the rearranged digital video data RGB to the data driver 120. The timing controller 110 is also connected to the data driver 120 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. A data control signal DDC for controlling the operation timing and a gate control signal GDC for controlling the operation timing of the gate driver.

The data driver 120 drives the data line unit DL. To this end, the data driver 120 converts the digital video data RGB input from the timing controller 110 into analog data voltages based on the data control signal DDC and supplies the analog data voltages to the data lines DL.

The gate driver includes a level shifter 130 and a gate driver circuit 140. The level shifter 130 is formed on a printed circuit board connected to the display panel 10 in the form of an IC and the gate drive circuit 140 is formed by a GIP circuit formed in the non-display area 10B of the display panel 10 do.

The level shifter 130 level-shifts the clock signals and the start signal VST under the control of the timing controller 110, and supplies the level-shifted signals to the gate driving circuit 140. The gate driving circuit 140 is formed by a combination of a plurality of thin film transistors (hereinafter referred to as transistors) in the non-display area 10B of the display panel 10 by the GIP method.

The gate driving circuit 140 may include a scan signal generating unit for outputting a scan signal and an emission signal generating unit for outputting an emission signal. The scan signal generating unit and the emission signal generating unit may include a plurality of stages that are connected to each other. The gate drive circuit will be described in detail below.

2 is a diagram showing a gate drive circuit according to the present specification. 2 shows the emission signal generator of the gate driver circuit, the scan signal generator may also have the configuration shown in FIG. The gate drive circuit may be formed with a shift register configuration. Each of the stages connected in a shift register in a dependent manner corresponds to an emission driver or a scan driver.

Referring to Figs. 1 and 2, an emission signal generator according to the present invention includes first to nth emission drivers EMD1 to EMD (n). The first emission driver EMD1 generates an emission signal EM1 and applies the emission signal EM1 to the emission line disposed in the first pixel line HL1. The second emission driver EMD2 generates the emission signal EM2 and applies the emission signal EM2 to the emission line disposed in the second pixel line HL2. Similarly, the nth emission driver EMD (n) generates the emission signal EM (n) and supplies the emission signal EM (n) to the emission line .

The first and second eighth and eighth emission drivers EMD2 to EMDn receive the output signal of the previous emission driver EMD1, That is, by receiving an emission signal at the start signal input terminal VP.

That is, the first to nth emission drivers EMD1 to EMD (n) of the emission signal generating unit are connected to each other.

3 is a diagram illustrating the configuration of an nth emission driver in the emission signal generator shown in FIG.

3, the nth emission driver EMD (n) includes Q1 node charging units 100 and 200, a node control unit 300, a pull-up unit 400, and a pull-down unit 500. FIG.

The Q1 node charging units 100 and 200 apply the turn-on voltage to the Q1 node Q1 using the first and second clock signals ECLK1 and ECLK2 which are alternately applied to each other. The Q1 node charging units 100 and 200 are connected to the Q1 node Q1 by using the first charging unit 100 and the first clock signal ECLK1 that apply the turn-on voltage to the Q1 node Q1 using the second clock signal ECLK2, And a second charging unit 200 for applying a turn-on voltage to the first switching unit Q1.

The node controller 300 controls the voltages of the Q1 node Q1, the QB1 node QB1, and the QB2 node QB2.

The pull-up unit 400 outputs an emission signal in response to the Q1 node (Q1) voltage.

The pull-down unit 500 controls the voltage of the output node Nout to a turn-off voltage in response to at least one of the voltages of the QB1 node QB1 and the QB2 node QB2.

Hereinafter, a specific embodiment of the emission driver shown in FIG. 3 will be described.

4 is a view showing an nth emission driver according to the first embodiment of the present invention.

4, the nth emission driver EMD (n) includes Q1 node charging units 100 and 200, a node control unit 300, a pull-up unit 400, and a pull-down unit 500. FIG.

The Q1 node charging units 100 and 200 include a first charging unit 100 and a second charging unit 100. [ The first charging unit 100 includes a gate electrode connected to a second clock signal input terminal ECLK2 and a source connected to a start signal input terminal VP for providing an emission start signal EVST. And a drain electrode connected to the electrode Q1 and the node Q1. The second clock signal input terminal CP2 receives the second clock signal ECLK2 and the start signal input terminal VP receives the emission start signal EVST or the carry signal. The carry signal may be the output signal of the (n-1) -th emission driver EM (n-1). The first transistor T1 is charged to the low potential voltage VEL which is the turn-on voltage in the Q1 node Q1 in the period in which both of the emission start signal EVST and the second clock signal ECLK2 are the turn- .

The second charging unit 200 includes a second transistor T2 and a first capacitor C1. The second transistor T2 includes a gate electrode connected to the Q1 node Q1, a source electrode connected to the first clock signal input CP1, and a drain electrode connected to the Q2 node Q2. The second transistor T2 charges the Q2 node Q2 to the low potential voltage VEL which is the turn-on voltage in the period in which the Q1 node Q1 and the first clock signal ECLK1 are the turn-on voltage.

The first capacitor C1 is connected between the Q1 node Q1 and the Q2 node Q2. The first capacitor C1 bootstrap the voltage of the Q2 node Q2 corresponding to the voltage of the Q1 node Q1. Alternatively, the first capacitor C1 bootstrap the voltage of the Q1 node Q1 corresponding to the voltage of the Q2 node Q2.

The node controller 300 includes a Q1 holding unit (hereinafter referred to as a third transistor) T3, a QP node controller (hereinafter referred to as a fourth transistor) T4, a QB2 node controller (hereinafter referred to as an eighth transistor) T8, (Hereinafter referred to as a ninth transistor) T9, a QB1 holding unit (hereinafter referred to as a fifth transistor) T5, a QB2 holding unit (hereinafter referred to as a tenth transistor) T10, a second and a third capacitors C2 and C3, . The node control unit 300 may be referred to as a Q1 node control unit.

The third transistor T3 includes a gate electrode connected to the QB2 node QB2, a source electrode connected to the Q1 node Q1, and a drain electrode connected to the input terminal of the high potential voltage VEH. The Q1 node controller 300 charges the Q1 node Q1 to the high potential voltage VEH which is the turn-off voltage when the QB2 node QB2 is at the turn-on voltage.

The QB node charging units T4, T8 and T9 include a fourth transistor T4, an eighth transistor T8 and a ninth transistor T9.

The fourth transistor T4 is connected to the gate electrode connected to the second clock signal input CP2, the source electrode connected to the (n-1) th QB2 node QB2 (n-1) and the QP node QP And a drain electrode. The fourth transistor T4 turns on and off the QP node QP in a period in which the voltage of the (n-1) th QB2 node QB2 (n-1) and the second clock signal ECLK2 are both the turn- (VEL) which is a turn-on voltage. The (n-1) th QB2 node QB2 (n-1) refers to the QB2 node QB2 of the (n-1) th emission driver EM (n-1).

The eighth transistor T8 includes a gate electrode connected to the QP node QP, a source electrode connected to the first clock signal input CP1, and a drain electrode connected to the QB2 node QB2. The eighth transistor T8 applies the voltage of the first clock signal ECLK1 to the QB2 node QB2 when the voltage of the QP node QP is the turn-on voltage.

Both electrodes of the second capacitor C2 are connected to the QP node QP and the QB2 node QB2, respectively. As a result, the QP node QP is bootstrapped according to the voltage change of the QB2 node QB2.

The ninth transistor T9 includes a gate electrode connected to the first clock signal input CP1, a source electrode connected to the QB2 node QB2, and a drain electrode connected to the QB1 node QB1. The ninth transistor T9 switches the current path between the QB2 node QB2 and the QB1 node QB1 according to the voltage level of the first clock signal ECLK1.

The QB node controllers T5 and T10 include a fifth transistor T5 and a tenth transistor T10.

The fifth transistor T5 includes a gate electrode connected to the Q1 node Q1, a source electrode connected to the QB1 node QB1, and a drain electrode connected to the input terminal of the high potential voltage VEH. The fifth transistor T5 charges the voltage of the QB1 node QB1 to the high-potential voltage VEH which is the turn-off voltage when the voltage of the node Q1 is the turn-on voltage.

The tenth transistor T10 includes a gate electrode connected to the Q1 node Q1, a source electrode connected to the QB2 node QB2, and a drain electrode connected to the input terminal of the high potential voltage VEH. The tenth transistor T10 charges the voltage of the QB2 node QB2 to the high-potential voltage VEH which is the turn-off voltage when the voltage of the node Q1 is the turn-on voltage.

Both electrodes of the third capacitor C3 are connected to the input terminal of the QB1 node QB1 and the high potential voltage VEH, respectively. The third capacitor C3 can stably maintain the voltage of the QB1 node QB1, thereby increasing the operational reliability of the pull-down transistor T7.

Up section 400 applies a low potential voltage VEL, which is a turn-on voltage, to the output terminal Nout in response to the voltage of the Q1 node Q1. Up portion 400 may be implemented as a pull-up transistor T6 connected between the input terminal of the low potential voltage VEL and the output terminal Nout and the gate electrode connected to the node Q1.

The pull down section 500 includes a pulldown transistor T7 which applies a high potential voltage VEH which is a turn-off voltage to the output node Nout in response to the voltage of the QB1 node QB1.

FIG. 5 is a timing diagram showing clock signals applied to the nth emission driver shown in FIG. 4 and a voltage change of a main node.

4 and 5, the pull-up transistor T6 charges the output node Nout to the low potential voltage VEL when the Q1 node voltage is a turn-on voltage lower than or equal to the low potential voltage VEL. An emission signal EM (n) of a turn-on voltage is applied to the emission line of the n-th pixel line HLn connected to the output terminal Nout. The Q1 node Q1 is maintained at the low potential voltage VEL by the first clock signal ECLK1 and the second clock signal ECLK2 that alternately maintain the turn-on voltage. The first clock signal ECLK1 and the second clock signal ECLK2 have opposite phases and have a period of two horizontal periods 2H. However, the first clock signal ECLK1 and the second clock signal ECLK2 may be designed so that the pulse width is somewhat overlapped in a section where the voltage level is inverted for the operation margin.

The first transistor T1 is turned on during the period in which the second clock signal ECLK2 and the emission start signal EVST are synchronized to charge the Q1 node Q1 to the low potential VEL.

The second transistor T2 charges the Q2 node Q2 to the low potential voltage VEL in a period in which the first clock signal ECLK1 is at the low potential voltage VEL. The Q1 node Q1 is bootstrapped to the bootstrapping voltage Vboot, corresponding to the voltage of the Q2 node Q2 being changed by the first clock signal ECLK1. As a result, the pull-up transistor T6 charges the low potential voltage VEL of the turn-on voltage to the output terminal Nout and the output terminal Nout outputs the emission signal EM (n) of the turn- do.

The fifth transistor T5 charges the QB1 node QB1 with the high-potential voltage VEH which is the turn-off voltage, and the tenth transistor T10 charges the node QB1 with the high- Charges QB2 node QB2 with a high-potential voltage VEH which is a turn-off voltage. As a result, the pull-down transistor T7 stably maintains the turn-off state in the period where the Q1 node Q1 is the turn-on voltage.

At the first timing t1, the fourth transistor T4 applies a low potential voltage VEL applied from the (n-1) th QB2 node QB2 (n-1) to the QP node QP. At the first timing t1, the second clock signal ECLK2 is inverted to the turn-on voltage so that the first transistor T1 is turned on and the emission start signal EVST is switched to the high potential voltage VEH It is reversed. As a result, at the first timing t1, the Q1 node Q1 is inverted to the high potential voltage VEH. At the first timing t1, the Q1 node Q1 rises to the turn-off voltage and the second transistor T2 is turned off. The second transistor T2 turned off at the first timing t1 maintains the turn-off state until the fourth timing t4 when the emission start signal EVST and the second clock signal ECLK2 are synchronized . While the second transistor T2 is in the turn-off state, the Q2 node Q2 can maintain a constant voltage without being affected by the voltage change of the first clock signal ECLK1. As a result, the voltage of the Q1 node (Q1) coupled to the Q2 node (Q2) through the first capacitor (C1) can stably maintain the turn-off voltage.

At the second timing t2, the eighth transistor T8 applies the low potential voltage VEL of the first clock signal ECLK1 to the QB2 node QB2. At this time, the QP node QP is bootstrapped to a lower voltage level corresponding to the voltage change amount of the QB2 node QB2. The ninth transistor T9 applies the voltage of the QB2 node QB2 to the QB1 node QB1 in response to the first clock signal ECLK1 of the low potential voltage VEL.

The pull-down transistor T7 charges the output node Nout to the turn-off voltage in response to the voltage of the QB1 node QB1.

At the second timing t2, the third transistor T3 applies the high potential voltage VEH to the Q1 node Q1 in response to the voltage of the QB2 node QB2, so that the Q1 node Q1 stably turns - Keep the off voltage.

At the third timing t3, the first clock signal ECLK1 is inverted to the high potential voltage VEH. The voltage of the QB2 node QB2 becomes the high potential voltage VEH by the high potential voltage VEH of the first clock signal ECLK1 applied through the eighth transistor T8. At the fourth timing t4, , The emission start signal EVST and the second clock signal ECLK2 are synchronized again with the turn-on voltage, and as a result, the low potential voltage VEL is applied to the Q1 node Q1.

As described above, the emission driver of the gate driving circuit according to the present invention controls the Q1 node Q1, which is the gate voltage of the pull-up transistor, using the first and second clock signals ECLK1 and ECLK2. The second transistor T2 applies the turn-on voltage to the Q2 node Q2 coupled to the Q1 node Q1, instead of directly applying the turn-on voltage to the Q1 node Q1, ) Voltage. In particular, the gate electrode of the second transistor T2 is connected to the node Q1. Therefore, the second transistor T2 is turned off during the period in which the pull-up transistor is turned off, so that the coupling voltage does not directly occur due to the first clock signal ECLK1 in the gate voltage of the pull-up transistor.

A general gate driving circuit directly applies a clock signal to a Q node when the Q node is charged by using alternately applied first and second clock signals. As a result, even when the pull-up transistor is in the turn-off state and the turn-on voltage is not applied to the Q node, the Q node is bootstrapped according to the voltage change amount of the clock signal, and an undesired gate signal is also output.

On the other hand, the gate drive circuit according to the present invention applies a turn-on voltage through the Q2 node Q2 without directly applying a turn-on voltage to the Q1 node Q1 which is the gate electrode of the pull-up transistor, Off state of the second transistor T2 that connects the Q2 node Q2 and the Q1 node Q1 when the transistor Tpu is turned off. Therefore, the voltage of the Q2 node (Q2) is maintained at a stable turn-off voltage when the pull-up transistor is in the turn-off state, thereby preventing the pull-up transistor from malfunctioning.

6 is a view showing an nth emission driver according to the second embodiment of the present invention. 6, the same reference numerals are used for the same components as those in the above-described embodiment, and a detailed description thereof will be omitted or briefly explained.

6, the nth emission driver EMD (n) includes Q1 node charging units 100, 200 and 210, a node control unit 300, a pull-up unit 400 and a pull-down unit 500. FIG.

The Q1 node charging units 100, 200 and 210 include first and second charging units 100 and 200 and a Q2 node control unit 210. [

The first charging unit 100 includes a gate electrode for receiving the second clock signal ECLK2, a source electrode connected to a start signal input VP for providing an emissive start signal EVST, And a drain electrode connected to the node Q1.

The second charging unit 200 includes a second transistor T2 and a first capacitor C1. The second transistor T2 includes a gate electrode connected to the Q1 node Q1, a source electrode connected to the first clock signal input CP1, and a drain electrode connected to the Q2 node Q2. The first capacitor C1 is connected between the Q1 node Q1 and the Q2 node Q2.

The first capacitor C1 bootstrapping the voltage of the Q2 node Q2 corresponding to the voltage of the Q1 node Q1. Alternatively, the first capacitor C1 bootstrap the voltage of the Q1 node Q1 corresponding to the voltage of the Q2 node Q2.

The Q2 node controller 210 applies the constant potential voltage to the Q2 node Q2 in the period in which the Q1 node Q1 is the turn-off voltage. The constant-potential voltage can utilize a high-potential voltage (VEH). The Q2 node control unit 210 may include a gate electrode connected to the second clock signal input CP2, a drain electrode connected to the Q2 node Q2, and a source electrode connected to the input terminal of the high voltage VEH. have. In this case, the Q2 node controller 210 is the 2a transistor T2a.

FIG. 7 is a timing diagram showing clock signals for driving the emission driver shown in FIG. 6 and a voltage change of a main node. Since the timings of the first and second clock signals shown in Fig. 7 are the same as the timings of the first and second clock signals shown in Fig. 5, the driving timings of the emission driver according to the second embodiment are similar to those of the first embodiment It is the same as the example.

6 and 7, the emission driver according to the second embodiment uses the Q2 node controller 210 to control the Q2 node Q2 (Q2) in a period in which the Q1 node Q1 maintains the high potential voltage VEH Can be maintained at the high-potential voltage (VEH).

The characteristics of the Q2 node control unit 210 of the second embodiment are compared with those of the first embodiment as follows.

In the first embodiment shown in Fig. 4, the Q2 node Q2 is coupled through the Q1 node Q1 and the first capacitor C1. Therefore, as shown in FIG. 5, the voltage of the Q2 node Q2 rises to a voltage level higher than the high-potential voltage VEH by the coupling phenomenon in a period in which the voltage of the Q1 node Q1 rises. The difference (Vds) between the drain voltage and the source voltage of the second transistor T2 corresponds to the difference between the voltage of the node Q2 and the voltage of the first clock signal ECLK1. When the voltage of the Q2 node Q2 becomes higher than the high potential voltage VEH, the Vds of the second transistor T2 becomes larger in the section where the first clock signal ECLK1 is the low potential voltage VGL. As a result, deterioration of the second transistor T2 can be accelerated.

The Q2 node controller 210 of the second embodiment applies a constant potential voltage, e.g., a high potential voltage VEH, to the Q2 node Q2 in a period in which the voltage of the Q1 node Q1 rises. Therefore, even if the voltage of the Q1 node (Q1) rises, the Q2 node (Q2) can maintain the high potential voltage (VEH) without any coupling phenomenon. Thus, the second embodiment can prevent the deterioration of the second transistor T2 from being accelerated.

Embodiments of the present invention can be described as follows.

An organic light emitting display according to the present invention includes a gate driving circuit including a plurality of stages connected to each other and supplying gate signals to at least one of pixels connected to a gate line and gate lines. The n-th (n is a natural number) stage of the gate drive circuit uses a first and a second clock signal having opposite phases to each other to supply a Q1 node charging unit for charging the Q1 node to a turn- On-state voltage to the output terminal. The Q1 node charging unit uses a second clock signal to couple a first charging unit charging the Q1 node voltage to the turn-on voltage and a Q1 node coupled to the Q1 node using the first clock signal in the period where the Q1 node is the turn-on voltage And a second charging unit charging the node Q2.

The first charging unit may include a first transistor connected between a start signal input terminal and a node Q1, and a gate electrode connected to an input terminal of the second clock signal.

The second charging unit may include a second transistor connected between the input terminal of the first clock signal and a node Q2, a gate electrode connected to the node Q1, and a first capacitor connected between the node Q1 and the node Q2.

The Q1 node charging unit may further include a Q2 node control unit for applying a constant potential voltage to the Q2 node in a period in which the Q1 node is in a turn-off voltage.

The Q2 node control unit may include a gate electrode connected to the second clock signal input terminal, a drain electrode connected to the Q2 node, and a source electrode connected to the high potential input terminal.

The gate driving circuit may further include a pull-down section for controlling the voltage of the output terminal to a turn-off voltage in response to the voltage of the QB1 node, and a node control section for controlling the voltage of the QB1 node at the opposite voltage level of the Q1 node.

The node controller may further include a second capacitor connected between the QP node and the QB2 node, a QB2 node of the (n-1) th stage, and a QP node controller coupled to the upper QP node.

The node control unit may further include a QB2 node control unit responsive to the voltage of the QP node for applying a turn-on voltage of the first clock signal to the QB2 node.

The node control unit may further include a QB1 node controller connected to the first clock signal input terminal to which the gate electrode receives the first clock signal and to apply the voltage of the QB2 node to the QB1 node.

The gate drive circuit according to the present specification comprises a plurality of stages to which a drive circuit is connected in a dependent manner, and outputs a gate signal. Each of the plurality of stages outputs the gate signal using the first and second clock signals. The nth (n is a natural number) stage of the plurality of stages includes a pull-up transistor responsive to the Q1 node voltage for applying a turn-on voltage to the output stage, a first capacitor connected between nodes Q1 and Q2, A first transistor including a gate electrode connected to the input terminal, a source electrode connected to the input terminal of the start signal, and a drain electrode connected to the node Q1, a gate electrode connected to the node Q1, a source electrode connected to the input terminal of the first clock signal, And a second transistor including a connected drain electrode.

The first clock signal and the second clock signal may be in opposite phases to each other.

The first clock signal and the second clock signal may be one horizontal period and two horizontal periods.

The start signal may be a gate signal output from the (n-1) th stage.

A transistor including a drain electrode connected to the Q2 node, a source electrode connected to the input terminal of the high potential voltage, and a gate electrode connected to the second clock signal.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Accordingly, the technical scope of the present specification should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 110: Timing controller
120: Data driver 130, 140: Gate driver

Claims (14)

Pixels connected to the gate line; And
And a gate driving circuit which supplies a gate signal applied to at least one of the gate lines and has a plurality of stages which are connected to each other in a dependent manner,
The nth (n is a natural number) stage of the gate drive circuit
A Q1 node charging unit charging the Q1 node with a turn-on voltage using first and second clock signals having opposite phases to each other; And
A pull-up transistor responsive to a Q1 node voltage for applying a turn-on voltage to an output terminal,
The Q1 node charging unit
A first charging unit charging the Q1 node voltage to a turn-on voltage using the second clock signal; And
And a second charging unit charging the node Q2 coupled with the node Q1 using the first clock signal in a period in which the node Q1 is a turn-on voltage.
The method according to claim 1,
The first charging unit
And a first transistor connected between a start signal input terminal and the Q1 node and having a gate electrode connected to an input terminal of the second clock signal.
The method according to claim 1,
The second charging unit
A second transistor connected between the input terminal of the first clock signal and the Q2 node, and having a gate electrode connected to the Q1 node; And
And a first capacitor connected between the Q1 node and the Q2 node.
The method according to claim 1,
The Q1 node charging unit
And a Q2 node controller for applying a constant potential voltage to the node Q2 in a period where the node Q1 is a turn-off voltage.
5. The method of claim 4,
The Q2 node control unit
A gate electrode connected to the second clock signal input terminal, a drain electrode connected to the node Q2, and a source electrode connected to the high potential input terminal.
The method according to claim 1,
The gate drive circuit
A pull-down unit responsive to the voltage of the node QB1 for controlling the voltage of the output terminal to a turn-off voltage; And
And a node controller for controlling the voltage of the QB1 node to a voltage level opposite to that of the Q1 node.
The method according to claim 6,
The node control unit
A second capacitor connected between the QP node and the QB2 node;
Further comprising a QB2 node of the (n-1) th stage and a QP node controller connected to the QP node.
8. The method of claim 7,
The node control unit
And a QB2 node controller for applying a turn-on voltage of the first clock signal to the QB2 node in response to the voltage of the QP node.
9. The method of claim 8,
The node control unit
And a QB1 node controller connected to a first clock signal input terminal to which a gate electrode of the first clock signal is applied and to apply a voltage of the QB2 node to the QB1 node.
A gate drive circuit comprising a plurality of stages connected in a dependent manner and outputting a gate signal,
Each of the plurality of stages outputting the gate signal using first and second clock signals,
The nth (n is a natural number) stage among the plurality of stages is
A pull-up transistor responsive to the Q1 node voltage for applying a turn-on voltage to an output terminal;
A first capacitor connected between the node Q1 and the node Q2;
A first transistor including a gate electrode connected to an input terminal of the second clock signal, a source electrode connected to an input terminal of the start signal, and a drain electrode connected to the node Q1;
And a second transistor including a gate electrode connected to the node Q1, a source electrode connected to the input terminal of the first clock signal, and a drain electrode connected to the node Q2.
11. The method of claim 10,
Wherein the first clock signal and the second clock signal are in opposite phase to each other.
12. The method of claim 11,
Wherein the first clock signal and the second clock signal have one period of two horizontal periods.
13. The method of claim 12,
And the start signal is a gate signal output from the (n-1) th stage.
11. The method of claim 10,
A transistor including a drain electrode coupled to the node Q2, a source electrode coupled to an input terminal of the high potential voltage, and a gate electrode coupled to the second clock signal.

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