KR102418573B1 - Gate driver and display device including the same - Google Patents

Abstract

A gate driver according to an embodiment of the present invention has a plurality of stages. Each of the stages may include a pull-up device configured to output a scan signal of a gate-on voltage of the first clock signal while the potential of the node Q is boosted; a transistor T2 configured to activate a node QA connected to the node Q to the gate-on voltage according to a second clock signal having a phase ahead of the first clock signal; a transistor T4 activating the node QB to the gate-on voltage according to a third clock signal out of phase with the first clock signal; and a pull-down device outputting a scan signal of a gate-off voltage while the node QB is activated, wherein the first to third clock signals swing between the gate-on voltage and the gate-off voltage, and Gate-on voltage sections of the first clock signal and the second clock signal partially overlap each other, and the gate-on voltage sections of the first clock signal and the third clock signal do not overlap.

Description

GATE DRIVER AND DISPLAY DEVICE INCLUDING THE SAME

The present invention relates to a gate driver and a display device including the same.

The electroluminescent display device is roughly classified into an inorganic light emitting display device and an organic light emitting display device according to the material of the light emitting layer. Among them, the active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has a fast response speed, luminous efficiency, luminance and The viewing angle is a big plus.

An organic light emitting display device arranges pixels including OLEDs in a matrix form and adjusts the luminance of the pixels according to the gray level of image data. Each of the pixels includes a driving TFT (Thin Film Transistor) that controls a driving current flowing through the OLED according to a gate-source voltage, and switch TFTs that program a gate-sort voltage of the driving TFT according to a scan signal, The display gradation (luminance) is controlled by the amount of light emitted by the OLED in proportion to the current.

The organic light emitting diode display includes a gate driver that generates a scan signal. The gate driver sequentially supplies scan signals to the gate lines. A scan signal is supplied to the switch TFT of each pixel through gate lines.

The gate driver may be implemented as a gate shift register composed of a plurality of stages. Each stage outputs a scan signal as a gate-off voltage or a gate-on voltage according to the potentials of the nodes Q and QB. The scan signal of the gate-off voltage is a voltage capable of turning off the switch TFTs, and the scan signal of the gate-on voltage is a voltage capable of turning on the switch TFTs. In each stage, a scan signal of a gate-on voltage is output while node Q is activated, and a scan signal of a gate-off voltage is output while node QB is activated.

The potentials of the nodes Q and QB are controlled by a start signal (or carry signal) and clock signals. The clock signals swing between a gate-on voltage and a gate-off voltage, and may be applied to the stages through a plurality of clock lines. Clock signals applied through different clock lines may have different phases. While the node Q is activated in each stage, the clock signal of the gate-on voltage is output as the scan signal of the gate-on voltage.

When the scan signal of the gate-on voltage is output, an initialization operation of the pixels may be performed. In the case of the high-resolution model, since the gate-on voltage period of the scan signal is short, a sufficient time for the initialization operation is secured by overlapping the gate-on voltage periods of the neighboring scan signals using clock signals.

In order to ensure the operation stability of the gate driver, the potential of the node Q and the potential of the node QB should be controlled opposite to each other in each stage. In other words, while node Q is activated with a gate-on voltage, node QB must be deactivated with a gate-off voltage, and conversely, node QB must be activated with a gate-on voltage while node Q is deactivated with a gate-off voltage.

However, in the case of overlap driving in which neighboring clock signals overlap by a predetermined phase, a current path interval in which the potential of the node Q and the potential of the node QB cannot be controlled in opposite directions may occur in each stage. In the current pass section, since the input terminal of the gate-off voltage and the input terminal of the gate-on voltage are shorted to each other and both the node Q and the node QB are activated with the gate-on voltage, the voltage of the scan signal may become unstable and power consumption may increase.

Accordingly, the present invention has been devised to solve the problems of the prior art, and provides a gate driver capable of securing operational stability and reliability and reducing power consumption by eliminating a current path section during clock overlap driving, and a display device including the same.

A gate driver according to an embodiment of the present invention has a plurality of stages. Each of the stages may include a pull-up device configured to output a scan signal of a gate-on voltage of the first clock signal while the potential of the node Q is boosted; a transistor T2 configured to activate a node QA connected to the node Q to the gate-on voltage according to a second clock signal having a phase ahead of the first clock signal; a transistor T4 activating the node QB to the gate-on voltage according to a third clock signal out of phase with the first clock signal; and a pull-down device outputting a scan signal of a gate-off voltage while the node QB is activated, wherein the first to third clock signals swing between the gate-on voltage and the gate-off voltage, and Gate-on voltage sections of the first clock signal and the second clock signal partially overlap each other, and the gate-on voltage sections of the first clock signal and the third clock signal do not overlap.

A gate-on voltage period of each of the first to third clock signals is shorter than a gate-off voltage period so that the potential of the node QA and the potential of the node QB are opposite to each other.

The turn-on period of the transistor T4 does not overlap the turn-on period of the transistor T2 so that the potential of the node QA and the potential of the node QB are opposite to each other.

Each of the stages further includes a transistor TBv connecting the node Q and the node QA to each other for a period other than a period in which the potential of the node Q is boosted.

The transistor TBv is turned off in a period in which the potential of the node Q is boosted, and is turned on in the remaining period.

The transistor TBv includes a gate electrode connected to the input terminal of the gate-on voltage, a first electrode connected to the node Q, and a second electrode connected to the node QA.

Each of the stages may include a transistor T1 configured to activate the node QA to the gate-on voltage according to a start signal synchronized with the second clock signal; a transistor T3 that deactivates the node QA to the gate-off voltage while the node QB is activated; a transistor T5 that deactivates the node QB to the gate-off voltage according to the start signal; and a transistor T6 that deactivates the node QB to the gate-off voltage while the node QA is activated.

Each of the stages further includes a transistor TRST that deactivates the node QA to the gate-off voltage according to a global reset signal.

In addition, the gate driver according to the embodiment of the present invention has a plurality of stages. Each of the plurality of stages may include a first clock terminal to which a first clock signal is input to be synchronized with a scan signal; a second clock terminal to which a second clock signal is input so as to be synchronized with a start signal having a phase ahead of the scan signal; and a third clock terminal to which a third clock signal that is out of phase with the first clock signal is input, wherein the first to third clock signals swing between a gate-on voltage and a gate-off voltage, and the first clock signal The gate-on voltage sections of the signal and the second clock signal partially overlap each other, and the gate-on voltage sections of the first clock signal and the third clock signal do not overlap each other.

A gate driver according to an embodiment of the present invention includes a signal line C5 to which a clock signal CLK5 is applied; a signal line C1 to which a clock signal CLK1 that is out of phase with the clock signal CLK5 and partially overlaps a gate-on voltage section with the clock signal CLK5 is applied; a signal line C2 to which a clock signal CLK2, which is out of phase with the clock signal CLK1, partially overlaps with the gate-on voltage section and does not overlap with the clock signal CLK5 and the gate-on voltage section, is applied; a signal line C3 to which a clock signal CLK3, which is out of phase with the clock signal CLK2, partially overlaps with the gate-on voltage period and does not overlap with the clock signal CLK1 and the gate-on voltage period, is applied; and a signal line C4 to which a clock signal CLK4, which is out of phase with the clock signal CLK3, partially overlaps with the gate-on voltage section, and does not overlap with the clock signal CLK2 and the gate-on voltage section, is applied. and the first to third clock signals are determined from among the clock signals CLK1, CLK2, CLK3, CLK4, and CLK5.

The first to third clock signals are different from each other in the five adjacent stages.

A gate-on voltage period of each of the first to third clock signals is shorter than a gate-off voltage period so that the potential of the node QA and the potential of the node QB are opposite to each other.

According to the present invention, it is possible to secure operational stability and reliability and reduce power consumption by eliminating a current path section during clock overlap driving.

1 shows a display device according to an embodiment of the present invention.
FIG. 2 shows a pixel array formed on the display panel of FIG. 1 .
FIG. 3 schematically shows one pixel circuit included in the pixel array of FIG. 2 .
FIG. 4 shows a gate signal applied to the pixel circuit of FIG. 3 .
FIG. 5 shows a scan driver and an emission driver included in the gate driver of FIG. 1 .
FIG. 6 shows the configuration of a gate shift register included in the scan driver of FIG. 5 .
FIG. 7 shows a configuration of one stage included in the gate shift register of FIG. 6 .
8A to 8E show operation states of the stage of FIG. 7 respectively corresponding to sections ① to ⑤.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be embodied in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'next to', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

The first, second, etc. may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to substantially identical elements throughout.

In the present invention, the pixel circuit and the gate driver formed on the substrate of the display panel may be implemented as a TFT having a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, but is not limited thereto. A TFT is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers start flowing from the source. The drain is an electrode through which carriers exit the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of a p-type TFT (PMOS), since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed according to the applied voltage. Therefore, in the description of the embodiment of the present invention, any one of the source and the drain is described as the first electrode, and the other one of the source and the drain is described as the second electrode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be mainly described with respect to the organic light emitting display device including the organic light emitting material. However, it should be noted that the technical spirit of the present invention is not limited to an organic light emitting display device, and may be applied to an inorganic light emitting display device including an inorganic light emitting material.

1 shows a display device according to an embodiment of the present invention. FIG. 2 shows a pixel array formed on the display panel of FIG. 1 . FIG. 3 schematically shows one pixel circuit included in the pixel array of FIG. 2 . FIG. 4 shows a gate signal applied to the pixel circuit of FIG. 3 . FIG. 5 shows a scan driver and an emission driver included in the gate driver of FIG. 1 .

Referring to FIG. 1 , the display device of the present invention includes a display panel 100 , a timing controller 110 , a data driver 120 , a gate driver 130 , and a level shifter 150 .

In the display panel 100 , a plurality of data lines 14 and a plurality of gate lines 15a and 15b cross each other, and pixels PXL are arranged in a matrix form at each intersection area to form a pixel array. can be configured.

The pixel array of the display panel 100 includes a plurality of horizontal pixel lines L1 to L4 as shown in FIG. 2 , and horizontally adjacent gate lines 15a and 15b on each horizontal pixel line L1 to L4 . A plurality of pixels PXL commonly connected to . Here, each of the horizontal pixel lines L1 to L4 does not mean a physical signal line, but a pixel block equivalent to one line implemented by horizontally adjacent pixels PXL. The pixel array includes a first power line 17 for supplying the high potential power voltage EVDD to the pixels PXL and a second power line 16 for supplying the reference voltage Vref to the pixels PXL. can Also, the pixels PXL may be connected to the low potential power voltage EVSS.

As shown in FIG. 2 , each of the gate lines includes a first gate line 15a to which a scan signal SCAN is supplied, and a second gate line 15b to which an emission signal EM is supplied.

Each of the pixels PXL may be any one of a red pixel, a green pixel, a blue pixel, and a white pixel. A red pixel, a green pixel, a blue pixel, and a white pixel constitute one unit pixel to implement various colors. A color implemented in a unit pixel may be determined according to emission ratios of a red pixel, a green pixel, a blue pixel, and a white pixel. A data line 14 , a first gate line 15a , a second gate line 15b , a first power line 17 , a second power line 16 , etc. may be connected to each of the pixels PXL.

3 , each of the pixels PXL controls the driving current flowing through the OLED according to the OLED, the switch circuit SWC for programming the gate-source voltage of the driving TFT DT, and the gate-source voltage. It may include a driving TFT (DT) for controlling the light, and in some cases, may further include an emission TFT (ET) that is turned on/off according to the emission signal EM to determine the emission timing of the OLED. The switch circuit SWC may include a plurality of switch TFTs and at least one capacitor, and various modifications may be made according to product models and specifications. The TFTs included in each of the pixels PXL may be implemented as PMOS-type LTPS TFTs, and through this, desired response characteristics may be secured. However, the technical spirit of the present invention is not limited thereto. For example, at least one TFT among the TFTs may be implemented as an NMOS-type oxide TFT having good off-current characteristics, and the remaining TFTs may be implemented as a PMOS-type LTPS TFT having a good response characteristic.

Each of the pixels PXL may be driven according to, for example, a gate signal as shown in FIG. 4 . In this case, each of the pixels PXL may perform an initialization operation, a programming operation, and a light emission operation according to the scan signal SCAN and the emission signal EM. For safety of operation during the initialization period A, the switch circuit SWC may initialize specific nodes in the pixel circuit to the reference voltage Vref. During the programming period B, the switch circuit SWC may program the gate-source voltage of the driving TFT DT based on the data voltage Vdata. During the programming period B, the threshold voltage of the driving TFT DT may be sampled and compensated. During the emission period C, a driving current corresponding to the gate-source voltage flows between the source and the drain of the driving TFT DT, and the OLED emits light by the driving current.

While the emission TFT ET is turned on during the initialization period A and the emission period C according to the emission signal EM, it may be turned off during the programming period B.

In FIG. 4 , the gate on voltage is the voltage of the gate signal at which the TFT can be turned on. The gate off voltage is the voltage of the gate signal at which the TFT can be turned off. For example, in the PMOS, the gate-on voltage is the gate low voltage VGL, and the gate-off voltage is the gate high voltage VGH higher than the gate low voltage VGL.

Referring to FIG. 1 , the data driver 120 receives image data DATA and a source timing control signal DDC from the timing controller 110 . The data driver 120 converts the image data DATA into a gamma compensation voltage in response to a source timing control signal DDC from the timing controller 110 to generate a data voltage Vdata, and the data voltage Vdata. is supplied to the data lines 14 of the display panel 100 in synchronization with the scan signal SCAN. The data driver 120 may be connected to the data lines of the display panel 100 through a chip on glass (COG) process or a tape automated bonding (TAB) process.

Referring to FIG. 1 , the level shifter 150 applies a transistor-transistor-logic (TTL) level voltage of the gate timing control signal GDC input from the timing controller 110 to drive the TFT formed in the display panel 100 . The gate high voltage VGH and gate low voltage VGL are boosted and supplied to the gate driver 130 . The gate timing control signal GDC may include an external start signal, a clock signal, and the like.

Referring to FIG. 1 , the gate driver 130 is operated according to a gate timing control signal GDC input from the level shifter 150 to generate a gate signal. Then, the gate signal is sequentially supplied to the gate lines. The gate driver 130 may be directly formed on the lower substrate of the display panel 100 using a gate driver in panel (GIP) method. The gate driver 130 is formed in the non-display area (ie, the bezel area BZ) outside the screen of the display panel 100 . In the GIP method, the level shifter 150 may be mounted on the printed circuit board 140 together with the timing controller 110 .

As shown in FIG. 5 , the gate driver 130 is provided in a double bank method on opposite sides of the display panel 100 to minimize signal distortion due to a load deviation of each gate line. The gate driver 130 includes a scan driver 131 generating a scan signal SCAN and an emission driver 132 generating an emission signal EM.

The scan driver 131 may supply the scan signal SCAN to the first gate lines 15a(1) to 15a(n) in a line-sequential manner. The emission driver 132 may supply the emission signal EM to the second gate lines 15b(1) to 15b(n) in a line-sequential manner. The scan driver 131 may be implemented as a gate shift register including a plurality of stages. Each stage of the scan driver 131 may be implemented as shown in FIGS. 6 to 8E to ensure operation stability and reliability.

Referring to FIG. 1 , the timing controller 110 may be connected to an external host system (not shown) through various well-known interface methods. The timing controller 110 receives the image data DATA from the host system, corrects the image data DATA to compensate for a luminance deviation due to a difference in electrical characteristics of the pixels PXL, and then sends the image data DATA to the data drivers 120 . can be transmitted

The timing controller 110 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK from the host system, and the timing signal A gate timing control signal GDC and a source timing control signal DDC may be generated based on .

FIG. 6 shows the configuration of a gate shift register included in the scan driver 131 of FIG. 5 .

Referring to FIG. 6 , the scan driver 131 according to the embodiment of the present invention may be implemented as a gate shift register including a plurality of stages ST1 to ST5, .... The stages ST1 to ST5, ... may be GIP devices formed in a GIP method.

The stages ST1 to ST5, ... are sequentially activated according to a start signal to output scan signals SCAN(1) to SCAN(5), ...). The operation of the uppermost stage ST1 is activated according to the external start signal VST, and the operation of the second upper stage ST2 to the lowest stage is activated according to the scan signal of the previous stage. The scan signal of the previous stage is an internal start signal and becomes a carry signal CRY. Here, the “front stage” refers to a stage that is positioned above a reference stage and generates a scan signal having a phase ahead of a scan signal output from the reference stage.

The stages ST1 to ST5, ... are an external start signal VST and a plurality of clock signals CLK1 from the level shifter 150 to output scan signals SCAN(1) to SCAN(5), ...). ~CLK5) can be input. Both the external start signal VST and the clock signals CLK1 to CLK5 swing between the gate high voltage VGH (ie, the gate-off voltage) and the gate low voltage VGL (ie, the gate-on voltage).

The stages ST1 to ST5, ... may be connected to the signal lines C1 to C7 and the power lines W1 and W2 through the plurality of connection terminals 1 to 7 . The stages ST1 to ST5, ... are commonly connected to the signal line C6 and the power lines W1 and W2, and may be selectively connected to the signal lines C1 to C5. In addition, the signal line C7 may be connected only to the uppermost stage ST1 . Accordingly, the external start signal VST may be input to the uppermost stage ST1, and the clock signals CLK1 to CLK5 may be sequentially input to all stages ST1 to ST5, ... by three.

To this end, each of the stages ST1 to ST5, ... is a first clock terminal 3 to which a first clock signal is input so as to be synchronized with the scan signals SCAN(1) to (5), and a scan signal SCAN(1). ) to (5)) a second clock terminal 5 to which a second clock signal is input so as to be synchronized with a start signal VST or CRY, which has a phase ahead of that, and a third clock signal that is out of phase with the first clock signal and a third clock terminal 4 to which is input.

The first to third clock signals may swing between the gate-on voltage VGL and the gate-off voltage VGH and may be determined from among the clock signals CLK1 to CLK5 . Here, the gate-on voltage sections of the first and second clock signals partially overlap each other and are designed to not overlap the gate-on voltage sections of the third clock signal. In addition, each of the first to third clock signals is designed so that the gate-on voltage period is shorter than the gate-off voltage period. The reason for designing the clock signals in this way is to secure operational stability and reliability and reduce power consumption by eliminating the current path section during overlap driving.

For example, the clock signal CLK5 is applied to the signal wiring C5. A clock signal CLK1 that is out of phase with the clock signal CLK5 and partially overlaps with the clock signal CLK5 and a gate-on voltage section is applied to the signal line C1. A clock signal CLK2, which is out of phase with the clock signal CLK1, partially overlaps the clock signal CLK1 and the gate-on voltage period, and does not overlap the clock signal CLK5 and the gate-on voltage period, is applied to the signal line C2. A clock signal CLK3 is applied to the signal line C3 that is out of phase with the clock signal CLK2, partially overlaps the clock signal CLK2 with the gate-on voltage section, and does not overlap the clock signal CLK1 and the gate-on voltage section. Then, the clock signal CLK4 is applied to the signal line C4, which is out of phase with the clock signal CLK3, partially overlaps the clock signal CLK3 with the gate-on voltage section, and does not overlap the clock signal CLK2 and the gate-on voltage section.

In this case, the first to third clock signals are different from each other in five adjacent stages ST1 to ST5. The first to third clock signals are the clock signals CLK1, CLK5, and CLK3 in the first stage ST1, the clock signals CLK2, CLK1, CLK4 in the second stage ST2, and the clock signals CLK1, CLK4 in the third stage ST3 clock signals CLK3, CLK2, and CLK5; clock signals CLK4, CLK3, and CLK1 in the fourth stage ST4; and clock signals CLK5, CLK4, and CLK2 in the fifth stage ST5.

FIG. 7 shows the configuration of the first stage included in the gate shift register of FIG. 6 . The configuration of the uppermost stage to the lowermost stage of FIG. 6 is substantially the same as that of the first stage except that only the input clock signal is different.

Referring to FIG. 7 , the first stage ST1 includes a reset unit 10 , a QA control unit 20 , a QB control unit 30 , a reliability unit 40 , a first output unit 50 , and a second output unit ( 60), including a boosting capacitor CB1.

The reset unit 10 may be implemented as a transistor TRST that is switched according to the global reset signal QRST. The gate electrode of the transistor TRST is connected to the reset terminal 6 . The global reset signal QRST may be simultaneously input to all stages as a gate-on voltage VGL for a predetermined time (eg, a frame start time). When the transistor TRST is turned on by the global reset signal QRST of the gate-on voltage VGL, the node Q and the node QA may be reset to the gate-off voltage VGH.

The first output unit 50 is a pull-up device that outputs the scan signal SCAN( 1 ) of the gate-on voltage VGL to the node Na when the potential of the node Q is boosted according to the first clock signal CLK1 . (Tu) is implemented. The gate electrode of the pull-up element Tu is connected to the node Q, the first electrode is connected to the first clock terminal 3, and the second electrode is connected to the node Na.

Boosting capacitor CB1 is connected between node Q and node Na. When the first clock signal CLK1 drops to the gate-on voltage VGL, the potential of the node Q drops from the gate-on voltage VGL to a lower boosting level due to the coupling effect of the boosting capacitor CB1. By this bootstrapping, the potential of the node Na rapidly drops to the gate-on voltage VGL. By using the bootstrapping effect, the scan signal SCAN(1) of the gate-on voltage VGL can be quickly output without distortion and delay.

The QA control unit 20 includes a transistor T1 switched according to the external start signal VST, a transistor T2 switched according to a second clock signal CLK5, and a transistor T3 switched according to the potential of the node QB, Enables or disables node QA connected to Q.

When both of the transistors T1 and T2 are turned on, the node QA is activated with the gate-on voltage VGL. The transistor T2 is turned on according to the second clock signal CLK5 having a phase ahead of the first clock signal CLK1 to activate the node QA with the gate-on voltage VGL. The gate electrode of the transistor T2 is connected to the second clock terminal 5, the first electrode is connected to the second electrode of the transistor T1, and the second electrode is connected to the node QA. In addition, the transistor T1 is turned on according to the external start signal VST synchronized with the second clock signal CLK5 to activate the node QA to the gate-on voltage VGL. The gate electrode of the transistor T1 is connected to the start terminal 7 , the first electrode is connected to the VGL power supply terminal 2 , and the second electrode is connected to the first electrode of the transistor T2 .

The gate electrode of the transistor T3 is connected to the node QB, the first node is connected to the node QA, and the second electrode is connected to the VGH input terminal (1).

The QB control unit 30 includes a transistor T4 switched according to a third clock signal CLK3 that is out of phase with the first clock signal CLK1 , a transistor T5 switched according to an external start signal VST, and a potential of a node QA and a transistor T6 switched according to , and a stabilizing capacitor CB2 connected between the node QB and the VGH input terminal 1 .

The transistor T4 is turned on according to the third clock signal CLK3 to activate the node QB to the gate-on voltage VGL. Since the turn-on period of the transistor T4 does not overlap the turn-on period of the transistor T2, the VGH input terminal 1 and the VGL input terminal 2 are shorted to each other, or both the nodes QA and QB are connected to the gate-on voltage (VGL). There are no activation issues. To this end, the gate-on voltage period of each of the first to third clock signals CLK1 , CLK5 , and CLK3 is designed to be shorter than the gate-off voltage period.

The gate electrode of the transistor T4 is connected to the third clock terminal 4 , the first electrode is connected to the VGL power supply terminal 2 , and the second electrode is connected to the node QB. The transistor T5 is turned on according to the external start signal VST to deactivate the node QB to the gate-off voltage VGH. The gate electrode of the transistor T5 is connected to the start terminal 7 , the first electrode is connected to the node QB, and the second electrode is connected to the VGH input terminal 1 . The transistor T6 controls the potential of the node QA and the potential of the node QB inversely. When the node QA is activated with the gate-on voltage VGL, the node QB is deactivated with the gate-off voltage VGH. When the transistor T6 is turned off, the node QB is activated with the gate-on voltage VGL. Since the node QB needs to remain active for a relatively long time in one frame, a stabilizing capacitor CB2 may be required.

The reliability unit 40 may be implemented as a transistor TBv connected between the node Q and the node QA. The transistor TBv includes a gate electrode connected to an input terminal of the gate-on voltage VGL, a first electrode connected to a node Q, and a second electrode connected to a node QA. The transistor TBv is turned off during the period in which the potential of the node Q is boosted, and is turned on during the remaining period excluding the boosting period to connect the node Q and the node QA to each other. In other words, the transistor TBv is turned off in the period in which the potential of the node Q is boosted, and is turned on in the remaining period.

Transistor TBv is turned off in the period in which the potential of node Q is boosted, thereby suppressing increase in drain-source voltage (Vds) applied to each of transistors TRST and T3 at the moment of boosting, thereby extending the lifespan of transistors TRST and T3 and improving reliability. can

The second output unit 60 is implemented as a pull-down device Td that outputs the scan signal SCAN( 1 ) of the gate-off voltage VGH to the node Na when the node QB is activated. The gate electrode of the pull-down element Td is connected to the node QB, the first electrode is connected to the node Na, and the second electrode is connected to the VGH input terminal 1 .

Meanwhile, the transistors TRST, T3-T6 may be designed in a dual gate structure to suppress leakage current when turned off. In the dual gate structure, two gate electrodes are connected to each other to have the same potential, and the channel length becomes longer than that of the single gate structure. When the channel length is increased, resistance is increased, so that leakage current is reduced during turn-off, so that operation stability can be secured.

8A to 8E show an operation state and driving waveform diagrams of the stage of FIG. 7 respectively corresponding to sections ① to ⑤.

Referring to FIG. 8A , in section 1, the external start signal VST and the clock signal CLK5 are input as the gate-on voltage VGL, and the clock signal CLK1 and the clock signal CLK3 are input as the gate-off voltage VGH. Here, the clock signals CLK1, CLK5, and CLK3 are the first, second, and third clock signals of the claims, respectively.

In section ①, the transistors T1 and T2 are turned on in response to the external start signal VST of the gate-on voltage VGL and the second clock signal CLK5, and the node QA is activated with the gate-on voltage VGL. .

In section ①, the transistor T4 is turned off in response to the third clock signal CLK3 of the gate-off voltage VGH, the transistor T5 is turned on in response to the external start signal VST, and according to the potential of the node QA The transistor T6 is turned on, and the node QB is deactivated by the gate-off voltage VGH.

In section ①, the transistor TBv maintains a turned-on state, and the node Q is activated with the gate-on voltage VGL. As a result, the pull-up element Tu is turned on according to the active potential of the node Q, and the first clock signal CLK1 of the gate-off voltage VGH is output from the node Na as the scan signal SCAN(1). .

In section ①, the pull-down element Td is turned off according to the inactive potential of the node QB.

Referring to FIG. 8B , in section ②, the external start signal VST and the second clock signal CLK5 are maintained at the gate-on voltage VGL, and the third clock signal CLK3 is maintained at the gate-off voltage VGH. do. On the other hand, the first clock signal CLK1 is inverted from the gate-off voltage VGH to the gate-on voltage VGL.

In section ②, the transistors T1 and T2 maintain an on state in response to the external start signal VST of the gate-on voltage VGL and the second clock signal CLK5, and the node QA maintains an active potential.

In section ②, the transistor T4 maintains the off state in response to the third clock signal CLK3 of the gate-off voltage VGH, the transistor T5 maintains the on state in response to the external start signal VST, and the node QA Transistor T6 remains on according to the potential of , and node QB maintains an inactive potential.

In section ②, when the first clock signal CLK1 is lowered from the gate-off voltage VGH to the gate-on voltage VGL, a parasitic capacitor (not shown) formed between the node Q and the first clock terminal 3 is coupled Due to the ring effect, the potential of the node Q is also lowered from the gate-on voltage VGL to a lower boosting voltage BL. As a result, the first clock signal CLK1 of the gate-on voltage VGL is output as the scan signal SCAN( 1 ) at the node Na through the pull-up device Tu. In section ②, the pull-down element Td maintains a turned-off state according to the non-active potential of the node QB.

In section ②, the transistor TBv is turned off because the node Q is lowered to the boosting voltage BL. At the moment when node Q is boosted, the gate-source voltage of the transistor TBv becomes lower than the threshold voltage and is turned off. As the transistor TBv is turned off, it has the effect of suppressing in advance an increase in the load applied to the transistors T3 and TRST connected between the node QA and the VGH input terminal at the boosting moment.

Referring to FIG. 8C , in section ③, the external start signal VST and the second clock signal CLK2 are inverted to the gate-off voltage VGH, and the first clock signal CLK1 is maintained at the gate-on voltage VGL. and the third clock signal CLK3 is maintained at the gate-off voltage VGH.

In section ③, the transistors T1 and T2 are turned off in response to the external start signal VST of the gate-off voltage VGH and the second clock signal CLK5, and the node QA maintains an active potential.

In section ③, the transistor T4 maintains the off state in response to the third clock signal CLK3 of the gate-off voltage VGH, the transistor T5 is turned off in response to the external start signal VST, and the potential of the node QA Transistor T6 remains on, and node QB maintains an inactive potential.

In section ③, the first clock signal CLK1 is maintained as the gate-on voltage VGL and the potential of the node Q is also maintained as the boosting voltage BL. As a result, the first clock signal CLK1 of the gate-on voltage VGL is continuously output as the scan signal SCAN( 1 ) at the node Na through the pull-up device Tu. In section ③, the pull-down element Td maintains a turned-off state according to the inactive potential of the node QB.

Referring to FIG. 8D , in section ④, the external start signal VST and the second clock signal CLK2 are maintained at the gate-off voltage VGH, and the first clock signal CLK1 is inverted to the gate-off voltage VGH. and the third clock signal CLK3 is inverted to the gate-on voltage VGL.

In section ④, the transistors T1 and T2 maintain an off state in response to the external start signal VST of the gate-off voltage VGH and the second clock signal CLK5. In section ④, the transistor T4 is turned off in response to the third clock signal CLK3 of the gate-on voltage VGL, and the transistor T5 is kept off in response to the external start signal VST, so that the node QB is gated on. It is activated by voltage (VGL). Then, the transistor T3 is turned on according to the activation potential of the node QB and the node QA is deactivated with the gate-off voltage VGH. Also, the transistor T6 is turned off according to the potential of the node QA.

In section ④, when the first clock signal CLK1 is inverted to the gate-off voltage VGH, the potential of the node Q also rises from the boosting voltage BL due to the coupling effect, and accordingly, the transistor TBv is also turned on. At this time, the node QA is deactivated to the gate-off voltage VGH by the turn-on of the transistor T3, and eventually the node Q is also deactivated to the gate-off voltage VGH. The pull-up element Tu is turned off by the non-active potential of the node Q.

In section ④, the pull-down device Td is turned on according to the active potential of the node QB, and the gate-off voltage VGH is a scan signal (SCAN(1)) at the node Na through the pull-down device Td. is output as

Referring to FIG. 8E , since the input potentials of the first to third clock signals CLK1 , CLK5 and CLK3 and the potentials of the nodes Q, QA, and QB in the period ⑤ are the same as in the period ④, the gate The off voltage VGH is output as the scan signal SCAN(1) at the node Na through the pull-down element Td.

As described above, according to the present invention, it is possible to secure operational stability and reliability and reduce power consumption by eliminating a current path section during clock overlap driving.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: timing controller
120: data driver 130: gate driver
131: scan driver

Claims (19)

A gate driver having a plurality of stages, comprising:
Each of the plurality of stages,
a pull-up device for outputting a scan signal of a gate-on voltage of the first clock signal while the potential of the node Q is boosted;
a transistor T2 configured to activate a node QA connected to the node Q to the gate-on voltage according to a second clock signal having a phase ahead of the first clock signal;
a transistor T4 activating the node QB to the gate-on voltage according to a third clock signal out of phase with the first clock signal; and
a pull-down device that outputs a scan signal of a gate-off voltage while the node QB is activated;
The first to third clock signals swing between the gate-on voltage and the gate-off voltage, and gate-on voltage sections of the first clock signal and the second clock signal partially overlap each other, and the first clock signal The gate-on voltage sections of the signal and the third clock signal do not overlap. The method of claim 1,
so that the potential of the node QA and the potential of the node QB are opposite to each other,
Each of the first to third clock signals has a gate-on voltage period shorter than a gate-off voltage period. The method of claim 1,
so that the potential of the node QA and the potential of the node QB are opposite to each other,
A turn-on period of the transistor T4 does not overlap with a turn-on period of the transistor T2. The method of claim 1,
Each of the stages further includes a transistor TBv connecting the node Q and the node QA to each other for a period other than a period in which the potential of the node Q is boosted. 5. The method of claim 4,
The transistor TBv is turned off in a period in which the potential of the node Q is boosted and turned on in the remaining period. 5. The method of claim 4,
The transistor TBv is
A gate driver comprising: a gate electrode connected to an input terminal of the gate-on voltage; a first electrode connected to the node Q; and a second electrode connected to the node QA. The method of claim 1,
Each of the stages is
a transistor T1 activating the node QA to the gate-on voltage according to a start signal synchronized with the second clock signal;
a transistor T3 that deactivates the node QA to the gate-off voltage while the node QB is activated;
a transistor T5 that deactivates the node QB to the gate-off voltage according to the start signal; and
and a transistor T6 that deactivates the node QB to the gate-off voltage while the node QA is activated. The method of claim 1,
Each of the stages further includes a transistor TRST for inactivating the node QA to the gate-off voltage according to a global reset signal. A gate driver having a plurality of stages, comprising:
Each of the plurality of stages,
a first clock terminal to which a first clock signal is input to be synchronized with the scan signal;
a second clock terminal to which a second clock signal is input so as to be synchronized with a start signal having a phase ahead of the scan signal; and
a third clock terminal to which a third clock signal that is out of phase with the first clock signal is input;
a pull-up device outputting a scan signal of a gate-on voltage of a first clock signal while the potential of the node Q is boosted;
a transistor T2 configured to activate the node Q to the gate-on voltage according to a second clock signal having a phase ahead of the first clock signal;
a transistor T4 activating the node QB to the gate-on voltage according to a third clock signal out of phase with the first clock signal; and
a pull-down device that outputs a scan signal of a gate-off voltage while the node QB is activated;
The first to third clock signals swing between a gate-on voltage and a gate-off voltage, and gate-on voltage sections of the first clock signal and the second clock signal partially overlap each other, and the first clock signal and The gate-on voltage sections of the third clock signal do not overlap. 10. The method of claim 9,
a signal wiring C5 to which the clock signal CLK5 is applied;
a signal line C1 to which a clock signal CLK1 that is out of phase with the clock signal CLK5 and partially overlaps a gate-on voltage section with the clock signal CLK5 is applied;
a signal line C2 to which a clock signal CLK2, which is out of phase with the clock signal CLK1, partially overlaps with the gate-on voltage section and does not overlap with the clock signal CLK5 and the gate-on voltage section;
a signal line C3 to which a clock signal CLK3, which is out of phase with the clock signal CLK2, partially overlaps with the gate-on voltage period and does not overlap with the clock signal CLK1, is applied; and
and a signal line C4 to which a clock signal CLK4, which is out of phase with the clock signal CLK3, partially overlaps with the gate-on voltage section, and does not overlap with the clock signal CLK2 and the gate-on voltage section, is applied; ,
The first to third clock signals are determined from among the clock signals CLK1, CLK2, CLK3, CLK4, and CLK5. 11. The method of claim 10,
The first to third clock signals input to the five adjacent stages are different from each other. 10. The method of claim 9,
so that the potential of the node QA electrically connected to the node Q and the potential of the node QB are opposite to each other,
Each of the first to third clock signals has a gate-on voltage period shorter than a gate-off voltage period. a display panel provided with gate lines connected to pixels; and
A display device comprising a gate driver supplying outputs of the plurality of stages according to any one of claims 1 to 12 to the gate lines. A gate driver including a plurality of stages, the gate driver comprising:
Each of the plurality of stages,
a pull-up element controlled by the node Q to output a first clock signal;
a transistor T2 configured to transmit a gate-on voltage to the node Q according to a second clock signal having a phase ahead of the first clock signal;
a transistor T4 transferring the gate-on voltage to the node QB according to a third clock signal out of phase with the first clock signal; and
and a pull-down device controlled by the node QB to output a gate-off voltage,
The first to third clock signals swing between the gate-on voltage and the gate-off voltage, a gate-on voltage period of the first clock signal and a gate-on voltage period of the second clock signal overlap, and the second clock signal swings between the gate-on voltage and the gate-off voltage. A gate driver in which a period of the gate-on voltage of the first clock signal and the gate-on voltage of the third clock signal does not overlap. 15. The method of claim 14,
Each of the first to third clock signals has a gate-on voltage period shorter than a gate-off voltage period. 15. The method of claim 14,
A turn-on period of the transistor T2 and a turn-on period of the transistor T4 are different from each other. 15. The method of claim 14,
Five clock signals overlapping each other and sequentially having a gate-on voltage pulse are provided to the gate driver,
The first to third clock signals are three clock signals among the five clock signals. 15. The method of claim 14,
Further comprising a transistor T1 and a transistor T5 which are synchronized with the second clock signal and controlled by a start signal having a gate-on voltage or an output signal of a previous stage,
The transistor T1 transfers the gate-on voltage to the transistor T2, and the transistor T5 transfers the gate-off voltage to the node QB. 15. The method of claim 14,
and a transistor T6 for controlling the potential of the node QB to be opposite to that of the node Q.

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