KR102514174B1 - Organic Light Emitting Display and Device for driving the same - Google Patents

Abstract

The present invention relates to an organic light emitting display device and a driving device thereof, and includes a duty driver generating an emission control signal (EM) for controlling turning on and off of the pixels. Since this duty driver operates as a shift register, it does not need to be connected to a separate shift register or an inverter to realize a duty driving method of pixels. A period, pulse width, and duty ratio of the emission control signal are controlled by the start pulse.

Description

Organic Light Emitting Display and Device for Driving the Same}

The present invention relates to an organic light emitting display capable of duty-driving pixels and a driving device therefor.

An active matrix type organic light emitting display device includes organic light emitting diodes (hereinafter referred to as “OLEDs”) that emit light by itself, and has advantages such as fast response speed, high luminous efficiency, luminance, and viewing angle. An OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer, EIL), etc. When a driving voltage is applied to the anode and cathode of the OLED, holes that have passed through the hole transport layer (HTL) and electrons that have passed through the electron transport layer (ETL) move to the light emitting layer (EML) to form excitons, and as a result, the light emitting layer (EML) visible light is generated.

The OLED display device may be driven by a duty driving method. In order to implement this duty driving method, an emission control signal (hereinafter referred to as “EM signal”) must be applied to the pixels. The EM signal is generated as an AC signal that swings between an ON level defining turn-on time of pixels and an OFF level defining turn-off time of pixels. In the case of a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the on level is a low logic level and the off level is a high logic level. The duty ratio of the EM signal defines turn-on and turn-off times of pixels. The pixel includes a switch element that supplies current to the OLED at an on level of the EM signal and cuts off the current from the OLED at an off level of the EM signal.

In order to implement the duty driving method, an EM driver capable of switching an EM signal to an on level and an off level at a desired time is required. The EM driver may be formed in a bezel area of the display panel. The bezel area is a non-display area disposed at an edge of the display panel. The EM driver includes shift registers that sequentially generate scan signals and inverters that invert outputs of the shift registers. Since the circuit area of the EM driver is relatively large, the bezel area of the display panel is enlarged, making it difficult to implement a narrow bezel.

The present invention provides an organic light emitting display device capable of reducing a circuit area and a driving device therefor.

An organic light emitting display device of the present invention includes a display panel in which pixels are arranged in a matrix form, a data driver supplying data voltages to the display panel, a scan driver supplying scan pulses synchronized with the data voltages, and lighting and and a duty driving unit that generates a light emission control signal for controlling lights off.

The duty driver includes a shift register independent of the scan driver.

The shift register receives a start pulse of an off-level voltage and a shift clock of an on-level voltage, outputs the emission control signal, and inverts the voltage of the emission control signal to an off-level voltage whenever the start pulse is input.
One frame period includes a scanning period and a duty driving period after the scanning period. During the duty driving period, the start pulse and the off-level voltage pulse of the emission control signal are generated twice or more.
A period, pulse width, and duty ratio of the emission control signal are controlled by the start pulse.

In the organic light emitting display, the shift register includes a plurality of stages connected in cascade. The shift clock includes clocks whose phases are sequentially shifted.

Each of the stages has a gate connected to the CLK1 terminal to which the first clock is input, a drain connected to the VST terminal to which the start pulse is input, and a source connected to the Q node, and a first TFT connected to the CLK2 terminal to which the second clock is input. A second TFT having a gate, a drain connected to a first input voltage terminal into which an on-level voltage is input, and a source connected to the A node, a gate connected to the Q node, a source connected to the A node, and a drain connected to the CLK1 terminal. A fourth TFT including a third TFT, a gate connected to the CLK3 terminal to which the third clock is input, a drain connected to the VST terminal, and a source connected to the Q node, a gate connected to the Q node, a drain connected to the QB node, and the A fifth TFT having a source connected to a second input voltage terminal to which an off-level voltage is supplied, a gate connected to the Q node, a drain connected to the second input terminal, and a source connected to an output node from which the emission control signal is output. A sixth TFT and a seventh TFT having a gate connected to the QB node, a drain connected to the output node, and a source connected to the second input voltage terminal.

Each of the stages further includes an eighth TFT having a gate connected to the A node, a source connected to the B node, and a drain connected to the CLK2 terminal.

Each of the stages further includes a first capacitor connected between the A node and the B node.

Each of the stages further includes a second capacitor connected between the gate and the source of the sixth TFT, and a third capacitor connected between the QB node and the second input voltage terminal.

Each of the stages further includes a ninth TFT having a gate and a drain connected to the B node and a source connected to the QB node.

Since the duty driver of the present invention operates as a shift register, it is not necessary to be connected to a separate shift register or an inverter to realize a method of driving the duty of pixels. In the present invention, the duty ratio of the emission control signal EM may be adjusted by adjusting the start pulse input to the duty driver. The period, pulse width, and duty ratio of the emission control signal EM may be adjusted with a start pulse.

1 is a block diagram showing an organic light emitting display device according to an exemplary embodiment of the present invention.
2 is a circuit diagram showing a pixel.
3 is a waveform diagram illustrating a pixel driving method.
4 is a block diagram briefly showing an EM driving unit.
FIG. 5 is a circuit diagram showing in detail the circuit of the EM driver shown in FIG. 4 .
6 and 7 are waveform diagrams showing input/output waveforms of the circuit shown in FIG. 5 .
8 to 17 are diagrams showing the operation of the circuit shown in FIG. 5 step by step.
18 and 19 are diagrams showing simulation results obtained by changing the period, pulse width, and duty ratio of the emission control signal EM by adjusting the start pulse.
20 and 21 are diagrams showing simulation results of changing the voltages of the A node, the B node, and the QB node according to the presence or absence of the first capacitor shown in FIG. 5 .
FIG. 22 is diagrams showing simulation results in which the voltage of the QB node varies when the ninth TFT shown in FIG. 5 is omitted.
FIG. 23 is a circuit diagram showing an example in which the first capacitor is deleted from the circuit of FIG. 5 .
FIG. 24 is a circuit diagram showing an example in which a ninth TFT is deleted from the circuit of FIG. 5 .

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

1 is a block diagram showing an organic light emitting display device according to an exemplary embodiment of the present invention. 2 is a circuit diagram showing a pixel. 3 is a waveform diagram illustrating a pixel driving method.

1 to 3 , an organic light emitting display device according to an exemplary embodiment of the present invention includes a display panel 100, a data driver 102, a scan driver 104, an EM driver 106, and a timing controller 110. ) is provided.

The display panel 100 includes a pixel array (AA) on which an input image is displayed and a bezel area (BZ) outside the pixel array (AA). The pixel array AA includes a plurality of data lines 12 , a plurality of scan lines 14 , and a plurality of EM lines 16 . Scan lines 14 and EM lines 16 are orthogonal to data lines 12 . The pixels 10 of the pixel array AA are arranged in a matrix form.

The display panel 100 further includes a VDD line supplying a high potential driving voltage VDD to the pixels 10 and a VSS electrode supplying a ground voltage VSS. In addition, the display panel may further include an electromotive voltage line supplying a reference voltage (or initialization voltage) to the pixels.

Each of the pixels is divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. The pixels may further include white sub-pixels. As shown in FIG. 2 , the subpixels include an OLED, a thin film transistor (TFT) M1 , a first switch TFT M2 , a second switch TFT M3 , and a storage capacitor Cst. The TFTs M1, M2, and M3 are illustrated as p-type MOSFETs in FIG. 2, but are not limited thereto. For example, the TFTs M1, M2, and M3 may be implemented with n-type MOSFETs. In this case, the phases of the scan signal SCAN and the emission control signal (hereinafter referred to as “EM signal”) EM are inverted. The TFTs M1, M2, and M3 may be implemented with any one of an amorphous silicon (a-Si) TFT, a poly-silicon TFT, and an oxide semiconductor TFT, or a combination thereof.

The anode of the OLED is connected to the driving TFT (M1) through the second switch TFT (M2). The cathode of the OLED is connected to the VSS electrode to receive the base voltage (VSS). The base voltage may be a low potential DC voltage of negative polarity.

The driving TFT (M1) is a driving element that adjusts the current (Ioled) flowing through the OLED according to the gate-source voltage. The driving TFT (M1) has a gate supplied with a data voltage through the first switch TFT (M2), a source supplied to the VDD line to receive the high potential driving voltage (VDD), and a drain connected to the second switch TFT (M2). includes The storage capacitor Cst is connected between the gate and the source of the driving TFT MT1.

The first switch TFT (M2) is turned on in response to the scan pulse (SCAN) from the scan line 14 during the scan period to supply the data voltage (DATA) to the gate of the driving TFT (M1). It is a switch element that maintains an off state during the duty driving period. The first switch TFT (M2) includes a gate connected to the scan line 14, a source connected to the data line 12, and a source connected to the gate of the driving TFT (M1). The scan pulse SCAN is supplied to the pixels through the scan line 14 for approximately one horizontal period.

The second switch TFT (M3) is a switch element that switches the current Ioled flowing through the OLED in response to the EM signal EM from the EM line 16. The second switch TFT (M3) maintains an off state during the scan period and is turned on/off in response to the EM signal (EM) turned on/off during the duty driving period to switch the current (Ioled) of the OLED. The duty driving method is implemented by adjusting the turn-on time and turn-off time of the OLED according to the duty ratio of the EM signal (EM). The second switch TFT (M2) includes a gate connected to the EM line, a source connected to the driving TFT (M1), and a drain connected to the anode of the OLED. The EM signal EM is generated at an off level during the scan period to block the current Ioled of the OLED.

It should be noted that the pixel circuit is not limited to FIG. 2 . For example, a switch element and a capacitor may be further added to the pixel circuit for internal compensation, and a sensing path may be further added for external compensation. The sensing path includes one or more switch elements, sample & holder, ADC (Analog-Digital Converter), etc. to sense the threshold voltage of the driving TFT or OLED of the pixel, convert the sensed value into digital data, to the timing controller 110

One frame period of the organic light emitting display device is divided into a scan period and a duty driving period in which pixels are repeatedly turned on and off according to an EM signal (EM) after the scanning period. Since the scan period is only approximately one horizontal period, most of one frame period is a duty driving period. During the scan period, the present invention may sample the threshold voltage of the driving TFT (Thin Film Transistor) to compensate for the current deviation of the OLED by a known internal compensation method, and compensate the data voltage DATA by the gate turn voltage.

The duty driving method displays gray levels by emitting pixels with high luminance full white luminance and adjusting the EM emission ratio controlled by the EM duty ratio. For example, when the full white luminance of a pixel is 500 nits and the pixel is driven with a duty ratio of 20%, the user can perceive the luminance of the pixel as luminance of 100 nits. On the other hand, if a pixel is driven with a duty ratio of 80%, the user can perceive the luminance of the pixel as 400 nit.

The duty driving method can improve the stain (or mura) of the display panel 100 . The stain of the display panel 100 is a phenomenon in which pixels emit light with non-uniform luminance due to a process deviation and thus look like stains. A general method of driving a display panel expresses a gray level by varying the luminance of pixels according to the gray level of input data. Blobs appear darker or weaker depending on the luminance of the pixels. Therefore, in order to compensate for such a stain, a general driving method requires different compensation values for the stain according to the gradation values of the pixels. In contrast, the duty driving method displays gray levels by emitting pixels with the same high luminance and varying the duty ratio of the pixels according to the duty ratio of the EM signal EM. Therefore, if the pixels are driven by the duty driving method, since the stain appears at the same level in all grayscales, the stain is not easily seen and the algorithm for compensating for the stain is simplified.

The duty driving method is advantageous for optical compensation of the display panel 100 . Optical compensation includes color coordinate compensation, white balance compensation, and the like. In general, optical compensation is compensated with different compensation values according to the luminance of pixels. Therefore, since the general driving method needs to set compensation values for optical compensation according to the luminance of pixels, the compensation values increase and the compensation algorithm becomes complicated. In contrast, the duty driving method displays gray levels by emitting pixels with the same high luminance and varying the duty ratio of the pixels according to the duty ratio of the EM signal EM. Therefore, since the duty driving method drives pixels with the same luminance and expresses gray levels with the duty ratio of the pixels, only one optical compensation value for full white luminance is required and the optical compensation algorithm can be simplified.

The duty driving method can improve flicker and motion blur caused by periodic flickering of the screen. Flicker is more visible when the driving frequency of the pixels is low. The duty driving method can reduce flicker because the driving frequency of the pixels is increased by increasing the duty ratio of the pixels. When the driving frequency of the pixels increases, the response speed of the pixels increases, thereby improving the motion blur phenomenon in the video.

The data driver 102 converts the data DATA of the input image received from the timing controller 110 into a gamma compensation voltage under the control of the timing controller 110 to generate a data voltage DATA, and converts the data voltage into the data voltage. output on lines 12. The data voltage DATA is supplied to the pixels 10 through the data lines 12 .

The scan driver 104 sequentially supplies scan pulses SCAN to the scan lines 12 using a shift register under the control of the timing controller 110 . The scan pulse (SCAN) is synchronized with the data voltage. The shift register of the scan driver 104 may be directly formed on the substrate of the display panel 100 together with the pixel array AA through a gate-driver in panel (GIP) process.

The EM driver 106 sequentially supplies the EM signal EM to the EM lines 12c using a shift register under the control of the timing controller 110 to realize the duty driving method. The shift register of the EM driver 106 may be directly formed on the substrate of the display panel 100 together with the pixel array AA through a GIP process. The shift register of the EM driver 106 is separated from the scan driver 104. Therefore, the EM driver 106 is implemented as a separate shift register independent from the shift register of the scan driver 104 .

The shift register of the EM driver 106 receives the start pulse VST of the off-level voltage and the shift clock of the on-level voltage, outputs the EM signal EM, and shifts the EM signal EM at the shift clock timing. The shift clock includes clocks CLK1 to CLK4 whose phases are sequentially shifted. This shift register inverts the voltage of the EM signal to an off-level voltage whenever a start pulse is input.

The shift register of the EM driver 106 includes cascadingly connected stages. Each of the stages receives a start pulse and a shift clock. The start pulse is toggled one or more times within the duty driving period in every frame period to invert the EM signal EM.

The timing controller 110 controls operation timings of the data driver 102 , scan driver 104 , and EM driver 106 to synchronize the operations of the drivers 102 , 104 , and 106 . The timing controller 110 receives digital video data (DATA) of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a clock signal CLK, and a data enable signal DE. The host system is a TV (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, a phone system, or a virtual reality (VR) device. can be one

The timing controller 110 includes a data timing control signal for controlling the operation timing of the data driver 102 based on the timing signal received from the host system, a scan timing control signal for controlling the operation timing of the scan driver 104, Then, an EM timing control signal for controlling the operation timing of the EM driver 106 is generated.

Each of the scan timing control signal and the EM timing control signal includes a start pulse and a shift clock. The start pulse defines a start timing at which the first output is generated from shift registers of the scan driver 104 and the EM driver 106, respectively. The shift register starts driving when the start pulse is input and generates the first output signal at the first clock timing. The shift clock defines the shift timing of the output signal output from the shift register.

4 is a block diagram briefly showing an EM driving unit. 5 is a circuit diagram showing the shift register shown in FIG. 4 in detail. 6 and 7 are waveform diagrams showing input/output waveforms of the circuit shown in FIG. 5 .

4 to 7, the EM driver 106 includes a shift register. The shift register includes cascadingly connected stages ST1 to STn. This shift register receives a start pulse (VST) and shift clocks (CLK1 to CLK4), outputs an EM signal (EM), and shifts the EM signal (EM) according to the timing of the shift clock (CLK). 4, EM(1) Out to EM(n) Out represent shifted EM signals.

Figure 5 shows an arbitrary stage circuit in the shift register shown in Figure 4; Other stages have the same circuit configuration as the circuit shown in FIG. 4 .

The stages ST1 to STn of the shift register have a circuit configuration as shown in FIG. 5 . Each of the stages ST1 to STn includes first to ninth transistors T1 to T9 and first to third capacitors C1 to C3. The ninth TFT (T9) and the first capacitor (C1) can be omitted as shown in FIGS. 23 and 24, but are preferably added for operational stability of the shift register. The TFTs T1 to T9 constituting the stages ST1 to STn are illustrated as p-type MOSFETs in FIG. 5, but are not limited thereto. For example, the TFTs T1 to T9 may be implemented with n-type MOSFETs. In this case, the phases of the start pulse VST and the shift clocks CLK1 to CLK4 are inverted. The TFTs T1 to T9 may be implemented with any one of an amorphous silicon (a-Si) TFT, a polysilicon TFT, and an oxide semiconductor TFT, or a combination thereof. The TFTs T1 to T9 constituting the stages ST1 to STn and the TFTs M1 to M3 of the pixel circuit may be implemented with the same type of MOSFET to simplify the manufacturing process.

Hereinafter, the on-level voltage is the gate low voltage (VGL), and the off-level voltage is the gate high voltage (VGH) higher than the gate low voltage (VGL).

The start pulse VST is generated with an off-level voltage. The first to fourth clocks CLK1 to CLK4 are generated as on-level voltages. The first clock CLK1 is synchronized with the start pulse VST and generated in the opposite phase of the start pulse VST. The second clock CLK2 is generated subsequent to the first clock CLK1, and the third clock CLK3 is generated subsequent to the second clock CLK2.

The first and second TFTs T1 and T2 are turned on in response to the first clock CLK1. The first TFT (T1) supplies the off-level voltage (VGH) of the start pulse (VST) to the gate of the third TFT (T1) and the Q node (Q) in response to the first clock (CLK1) to supply the third TFT ( T1) is turned off, and the gate and Q node (Q) are charged. A gate of the first TFT (T1) is connected to the first clock terminal. The drain of the first TFT (T1) is connected to the VST terminal, and the source of the first TFT (T1) is connected to the Q node (Q). The VST terminal of the first stage ST1 receives the start pulse VST, and the VST terminals of the stages ST2 to STn other than the first stage ST1 receive the carry signal output from the previous stage. The carry signal may be an EM signal (EM out) output from the stage.

The second TFT T2 lowers the A node voltage by supplying the on-level voltage VGL to the A node A in response to the first clock CLK1. A gate of the second TFT (T2) is connected to the second clock terminal. The drain of the second TFT (T2) is connected to the VGL terminal, and the source of the second TFT (T2) is connected to the A node (A).

The third TFT T3 is turned off when the off level voltage of the start pulse VST is input, and turned on when the Q node is lowered to the on level. The gate of the third TFT (T3) is connected to the Q node (Q). The source of the third TFT (T3) is connected to the A node (A), and the drain of the third TFT (T3) is connected to the first clock terminal.

The fourth TFT T4 is turned on in response to the third clock CLK3 and supplies the on-level voltage of the start pulse VST to the Q node to charge the voltage at the Q node Q to the on-level voltage. A gate of the fourth TFT (T4) is connected to the third clock terminal. The drain of the fourth TFT (T4) is connected to the VST terminal, and the source of the fourth TFT (T4) is connected to the Q node (Q).

The fifth TFT (T5) is turned on when the voltage of the Q node (Q) is at the on level and supplies the off level voltage (VGH) to the QB node (QB) to raise the voltage at the QB node (QB) to the off level. let it A gate of the fifth TFT (T5) is connected to the Q node (Q). The drain of the fifth TFT (T5) is connected to the QB node (QB), and the source of the fifth TFT (T5) is connected to the VGH terminal.

The sixth TFT (T6) is turned on when the voltage of the Q node (Q) is at the on level, and supplies the on level voltage (VGL) to the output node to lower the EM signal (EM) to the on level voltage. The gate of the sixth TFT (T6) is connected to the Q node (Q). The drain of the sixth TFT (T6) is connected to the VGL terminal, and the source of the sixth TFT (T6) is connected to the output node from which the EM signal (EM) is output.

The seventh TFT (T7) is turned on when the voltage of the QB node (QB) is at the on level, and supplies the off level voltage (VGH) to the output node to increase the EM signal (EM) to the off level voltage (VGH). A gate of the seventh TFT (T7) is connected to the QB node (QB). The drain of the seventh TFT (T7) is connected to the output node, and the source of the seventh TFT (T7) is connected to the VGH terminal.

The eighth TFT (T8) is turned on when the voltage of node A (A) is at an on-level, and supplies the on-level voltage of the second clock (CLK2) to node B (B) to reduce the voltage of node B (B). Reduce to the on-level voltage. The gate of the eighth TFT (T8) is connected to the A node (A). The source of the eighth TFT (T8) is connected to the B node (B), and the drain of the eighth TFT (T8) is connected to the second clock terminal.

The ninth TFT (T9) operates as a diode that is turned on when the voltage of the QB node (QB) is higher than the voltage of the B node (B), and sets the on-level voltage of the second clock (CLK2) to the QB node ( QB) to reduce the voltage at the QB node to the on-level voltage. The gate and drain of the ninth TFT (T9) are connected to the B node (B). A source of the ninth TFT (T9) is connected to the QB node (QB).

The first capacitor (C1) is connected between the A node (A) and the B node (B) to further lower the voltage of the A node (A) when the on-level voltage of the second clock (CLK2) is input to the eighth TFT ( Increase the On current of T8). The second capacitor (C2) is connected between the gate and the source of the sixth TFT (T6) to lower the voltage of the Q node when the on-level voltage (VGL) is supplied to the output node, thereby reducing the on-current of the sixth TFT (T6). raise A third capacitor (C3) is connected between the QB node (QB) and the VGH terminal to suppress the variation of the voltage of the QB node (QB).

Since the EM driver 106 of the present invention operates as a shift register, it does not need to be connected to a separate shift register or an inverter to realize a duty driving method of pixels. As shown in FIG. 7 , the EM driver 106 may adjust the duty ratio of the EM signal EM by adjusting the start pulse VST. The period, pulse width, and duty ratio of the EM signal EM are controlled identically to those of the start pulse VST.

8 to 17 are diagrams showing the operation of the circuit shown in FIG. 5 step by step.

Referring to FIGS. 8 and 9 , in step (1), the start pulse VST is generated with an off-level voltage, and at the same time, the first clock signal CLK1 is generated with an on-level voltage. The second to fourth clocks CLK2 to CLK4 are maintained at off-level voltages in step (1). In step (1), the first and second TFTs T1 and T2 are turned on. Accordingly, the voltage of the Q node Q rises to the off-level voltage of the start pulse VST, and the third and sixth TFTs T3 and T6 are turned off. At the same time, the on-level voltage VGL is supplied to node A through the turned-on second TFT T2 so that the voltage at node A is charged to the on-level voltage.

Referring to FIGS. 10 and 11 , in step (2), the start pulse VST is inverted to an on level voltage and the first clock CLK1 is inverted to an off level. The third and fourth clocks CLK3 and CLK4 are maintained at off-level voltages in step (2). At the same time, the second clock CLK2 is generated with an on-level voltage. In step (2), the first and second TFTs T1 and T2 are turned off according to the off-level voltage applied to their gates. In step (2), the eighth TFT (T8) is turned on according to the on-level voltage of the A node (A) and supplies the on-level voltage of the second clock (CLK2) to the QB node (QB) to the QB node ( The voltage of QB) is charged to the on-level voltage. When the voltage at the B node (B) is lowered due to the on-level voltage of the second clock (CLK2) due to the first capacitor (C1) connected between the A node (A) and the B node (B), the capacitor (C1) Through this, the voltage of the A node (A) coupled with the B node (B) is further lowered. In step (2), when the voltage of the QB node QB is lowered to an on level, the seventh TFT T7 is turned on. As a result, the off-level voltage VGH is supplied to the output node and the EM signal EM rises to the off-level voltage. In step (2), the pixel's OLED current is cut off so that the pixel does not emit light.

When the second clock CLK2 is supplied as an on-level voltage to the QB node QB, the first capacitor C1 floats, causing the A node (A) to float due to parasitic capacitance. ) is increased to prevent the on-current of the eighth TFT (T8) from being reduced. When the on-current of the eighth TFT (T8) is reduced, the voltage of the QB node (QB) rises and the on-current of the seventh TFT (T7) is reduced so that the voltage of the EM signal (EM) is not sufficiently lowered. The operational effect of the first capacitor C1 can be clearly understood by looking at the simulation results of FIGS. 20 and 21 .

Referring to FIGS. 12 and 13 , in step (3), the start pulse VST is maintained at an on-level voltage and the second clock CLK2 is inverted to an off-level. The first and fourth clocks CLK1 and CLK4 are maintained at off-level voltages in step (3). At the same time, the third clock CLK3 is generated with an on-level voltage. In step (3), the fourth TFT T4 is turned on according to the on-level voltage of the third clock CLK3 and supplies the on-level voltage to the Q node Q. The third, fifth, and sixth TFTs T3, T5, and T6 are turned on in response to the on-level voltage of the Q node Q in step (3). The voltage of the A node (A) is charged with the off-level voltage of the first clock (CLK1) supplied through the turned-on third TFT (T3). Accordingly, the on-level voltage VGL is supplied to the output node through the sixth TFT T6 to lower the voltage of the EM signal EM to the on-level voltage. In step (3), the EM signal EM is lowered to an on-level voltage so that a current flows through the OLED and the pixel emits light.

In step (3), the off-level voltage VGH is supplied to the QB node QB through the turned-on fifth TFT T5 so that the QB node QB is charged with the off-level voltage. At the same time, the seventh TFT T7 is turned off according to the off-level voltage of the QB node QB. When the on-level voltage VGL is supplied to the output node of the second capacitor C2, the Q node Q floats and the voltage at the Q node Q rises due to the parasitic capacitance to turn on the sixth TFT T6. This prevents the phenomenon of reducing the current.

Referring to FIGS. 14 and 15 , in step (3), the start pulse VST is maintained at an on level voltage, and the third clock signal CLK3 is inverted to an off level. The first and second clocks CLK1 and CLK2 are maintained at off-level voltages in step (4). At the same time, the fourth clock CLK4 is generated with an on-level voltage. In step (4), the voltage of the Q node Q is maintained at the on level voltage so that the third, fifth and sixth TFTs T3, T5 and T6 remain on. The voltage of the QB node QB is charged with the off-level voltage VGH supplied through the turned-on fifth TFT T5 to control the seventh TFT T7 to be turned off. The voltage of the EM signal EM is maintained at the on-level voltage VGL supplied through the sixth TFT T6. In step (4), the EM signal (EM) maintains an on-level voltage so that a current flows through the OLED and the pixel emits light.

16 and 17, step (5) is the same as step (1). Steps (1) to (4) are repeated so that the EM signal (EM) swings between an on-level voltage and an off-level voltage during the duty driving period.

As shown in the simulation results of FIGS. 18 and 19 , the period T, pulse width, and duty ratio of the EM signal EM may be adjusted by the start pulse VST. In the example of FIG. 18, whenever a pulse of the start pulse VST occurs, the voltage of the Q node Q rises to the off-level voltage, and then the EM signal EM rises to the off-level voltage at the next clock CLK. do. In the example of FIG. 19 , when the pulse width W of the start pulse VST is increased, the pulse width of the EM signal EM is also increased to change the duty cycle of the pixel.

Whenever a start pulse is input, the EM signal EM is inverted to an off-level voltage to turn off pixels. The lower the gradation of the input image, the longer the number of turns off and the longer the turn off time of pixels. Accordingly, the number of start pulses VST generated during the duty driving period increases as the grayscale of the input image data decreases. In addition, the pulse width (W) of the start pulse (VST) generated during the duty driving period may be controlled to be longer as the grayscale of the input image data is lower.

20 and 21 are diagrams showing simulation results of changing the voltages of the A node, the B node, and the QB node according to the presence or absence of the first capacitor shown in FIG. 5 . The first capacitor C1 prevents unwanted increase in voltages of the QB node, the A node, and the B node when the second clock CLK2 is supplied to the QB node QB. When the first capacitor C1 is connected between the A node (A) and the B node (B), when the second clock CLK2 is generated, the voltage of the QB node QB is -4V and the A node as shown in FIG. The voltage of (A) is -20V and the voltage of B node (B) is reduced to -7.5V. On the other hand, if the first capacitor C1 is deleted as shown in FIG. 23, the voltage of the QB node QB is 0.5V, the voltage of the A node is -5V, and the voltage of the B node is 0.5V, as shown in FIG. 21. It rose to -4V and didn't drop enough to the on-level voltage. If the voltage of node A is not boosted to a lower voltage by the first capacitor C1, the voltage of node B is not maintained at VGL (-7.5V) and the threshold of the eighth TFT T8 As the voltage (Vth = 3.5V) rises, the voltage of the B node (B) rises to 4V. This causes the voltage of the QB node (QB) to rise, thereby reducing the on-state current of the seventh TFT (T7), resulting in the inability to sufficiently increase the off-level voltage of the EM signal.

FIG. 22 is diagrams showing simulation results in which the voltage of the QB node is varied when the ninth TFT T9 shown in FIG. 5 is omitted. The ninth TFT T9 operates as a diode so that the voltage of the QB node QB does not fluctuate according to the second clock CLK2 when the voltage of the second clock CLK2 swings. 24, when the ninth TFT (T9) is deleted and the pulse width (W) of the start pulse (VST) is longer than the clock cycle, the off-level voltage period of the start pulse (VST), that is, the high-level voltage period A period in which the TFT (T5) is turned off occurs. When the fifth TFT (T5) is turned off, the voltage of the QB node (QB) does not maintain VGH (= 9.6V), and whenever the second clock (CLK2) is input to the circuit of FIG. 5, the QB node ( The voltage of QB) fluctuates. This results in a voltage fluctuation of the EM signal (EM).

Therefore, even if the ninth TFT (T9) and the first capacitor (C1) are omitted from the EM driver circuit, there is no problem with the basic operation of the EM driver 106, but for stability of operation, as shown in FIG. 5, the ninth TFT (T9) and a first capacitor C1 to the EM driver circuit.

Through the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

100: display panel 110: timing controller
102: data driver 104: gate driver
106: EM driving unit (duty driving unit) T1 to T9: transistor (TFT)
C1, C2, C3: capacitor

Claims (13)

a display panel in which pixels are arranged in a matrix form;
a data driver supplying a data voltage to the display panel;
a scan driver supplying a scan pulse synchronized with the data voltage; and
a duty driver for generating a light emission control signal for controlling turning on and off of the pixels;
The duty driver includes a shift register independent of the scan driver,
The shift register receives a start pulse of an off-level voltage and a shift clock of an on-level voltage, outputs the emission control signal, and inverts the voltage of the emission control signal to an off-level voltage whenever the start pulse is input;
One frame period includes a scanning period and a duty driving period after the scanning period, and during the duty driving period, the start pulse and the off-level voltage pulse of the emission control signal are generated twice or more;
The period, pulse width and duty ratio of the emission control signal are controlled by the start pulse,
The organic light emitting display device of claim 1 , wherein the number of start pulses generated during the duty driving period increases and the pulse width of the start pulses increases as the grayscale of the input image data decreases. According to claim 1,
the shift register includes a number of cascadingly connected stages;
The shift clock includes clocks whose phases are sequentially shifted,
Each of the above stages
a first TFT having a gate connected to a CLK1 terminal to which a first clock is input, a drain connected to a VST terminal to which the start pulse is input, and a source connected to a Q node;
a second TFT having a gate connected to the CLK2 terminal to which the second clock is input, a drain connected to the first input voltage terminal to which the on-level voltage is input, and a source connected to the A node;
a third TFT having a gate connected to the Q node, a source connected to the A node, and a drain connected to the CLK1 terminal;
a fourth TFT including a gate connected to the CLK3 terminal to which a third clock is input, a drain connected to the VST terminal, and a source connected to the Q node;
a fifth TFT having a gate connected to the Q node, a drain connected to the QB node, and a source connected to a second input voltage terminal to which the off-level voltage is supplied;
a sixth TFT having a gate connected to the Q node, a drain connected to the first input voltage terminal, and a source connected to an output node from which the emission control signal is output; and
and a seventh TFT having a gate connected to the QB node, a drain connected to the output node, and a source connected to the second input voltage terminal. According to claim 2,
Each of the stages,
and an eighth TFT having a gate connected to the A node, a source connected to the B node, and a drain connected to the CLK2 terminal. According to claim 3,
Each of the stages,
and a first capacitor connected between the A node and the B node. According to claim 4,
Each of the stages,
a second capacitor connected between the gate and the source of the sixth TFT; and
and a third capacitor connected between the QB node and the second input voltage terminal. According to claim 5,
Each of the stages,
and a ninth TFT having a gate and a drain connected to the B node and a source connected to the QB node. A driving device for an organic light emitting display device having pixels turned on/off during a duty driving period according to a light emitting control signal,
The driving device includes a shift register for generating the emission control signal;
The shift register receives a start pulse of an off-level voltage and a shift clock of an on-level voltage, outputs the emission control signal, and inverts the voltage of the emission control signal to an off-level voltage whenever the start pulse is input;
One frame period includes a scanning period and a duty driving period after the scanning period, and during the duty driving period, the start pulse and the off-level voltage pulse of the emission control signal are generated twice or more;
The period, pulse width and duty ratio of the emission control signal are controlled by the start pulse,
The driving device of the organic light emitting display device, wherein the number of start pulses generated during the duty driving period increases and the pulse width of the start pulse increases as the gray level of the input image data decreases. According to claim 7,
the shift register includes a number of cascadingly connected stages;
The shift clock includes clocks whose phases are sequentially shifted,
Each of the above stages
a first TFT having a gate connected to a CLK1 terminal to which a first clock is input, a drain connected to a VST terminal to which the start pulse is input, and a source connected to a Q node;
a second TFT having a gate connected to the CLK2 terminal to which the second clock is input, a drain connected to the first input voltage terminal to which the on-level voltage is input, and a source connected to the A node;
a third TFT having a gate connected to the Q node, a source connected to the A node, and a drain connected to the CLK1 terminal;
a fourth TFT including a gate connected to the CLK3 terminal to which a third clock is input, a drain connected to the VST terminal, and a source connected to the Q node;
a fifth TFT having a gate connected to the Q node, a drain connected to the QB node, and a source connected to a second input voltage terminal to which the off-level voltage is supplied;
a sixth TFT having a gate connected to the Q node, a drain connected to the first input voltage terminal, and a source connected to an output node from which the emission control signal is output; and
and a seventh TFT having a gate connected to the QB node, a drain connected to the output node, and a source connected to the second input voltage terminal. According to claim 8,
Each of the stages,
and an eighth TFT having a gate connected to the A node, a source connected to the B node, and a drain connected to the CLK2 terminal. According to claim 9,
Each of the stages,
and a first capacitor connected between the A node and the B node. According to claim 10,
Each of the stages,
a second capacitor connected between the gate and the source of the sixth TFT; and
and a third capacitor connected between the QB node and the second input voltage terminal. According to claim 11,
Each of the stages,
and a ninth TFT having a gate and a drain connected to the B node and a source connected to the QB node. delete

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