KR20190067435A - Gate driving circuit and display device comprising the same - Google Patents

Abstract

The present invention relates to a display device and, more specifically, to a gate driving circuit mounted in a gate in panel (GIP) type and a display device comprising the same. According to one embodiment of the present invention, the gate driving circuit comprises a plurality of stages dependently connected to each other. Each of the plurality of stages comprises: an output unit configured to output a first clock signal as a gate output voltage by a voltage of a Q node and a voltage of a QB node; a first node control unit configured to charge the voltage of the Q node corresponding to an output voltage of the previous stage; and a second node control unit configured to charge the voltage of the QB node corresponding to second and third clock signals, a phase of which is different from that of the first clock signal. The second node control unit comprises: a fourth transistor configured to output high level power voltage to the QB node corresponding to the third clock signal; a fifth transistor configured to output the second clock signal to the QB node corresponding to the output voltage of the previous stage; and a sixth transistor configured to output the second clock signal to the QB node corresponding to the voltage of the Q node. Accordingly, it is possible to prevent a decrease in a discharge rate of the QB node of the gate driving circuit.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate driving circuit and a display device including the gate driving circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a gate driving circuit mounted in a gate in panel (GIP) form and a display device including the same.

In the information age, the display field for visually expressing electrical information signals has been rapidly developed. In response to this, various display devices having excellent performance such as thinning, light weight, and low power consumption have been developed Is being developed. Examples of such a display device include a liquid crystal display device (LCD), an organic light emitting display device (OLED), and the like.

Such a display device includes a display panel on which pixel arrays for displaying an image are arranged, a data driving circuit for supplying data signals to data lines arranged on the display panel, a gate driving circuit for sequentially supplying gate pulses to the gate lines arranged in the display area And a timing controller for controlling the data driving circuit and the gate driving circuit.

Among such driving circuits, a gate driving circuit is recently applied to a display device in the form of a gate-in-panel (GIP) embedded in a display panel together with pixel arrays.

The GIP includes a shift register for sequentially outputting a gate voltage, and the shift register includes a plurality of stages connected in a dependent manner.

In order to reduce power consumption, the switching circuit includes an LTPS transistor, which is a transistor having a low temperature poly-silicon (hereinafter referred to as LTPS) as an active layer.

However, when the LTPS transistor included in the switching circuit is continuously supplied with a fixed level voltage, the mobility of the LTPS transistor active layer is lowered due to a high junction stress (HJS) of 99% or more.

As a result, the QB node discharge speed of the switching circuit is lowered, and the GIP can not output the gate voltage sequentially.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gate driver circuit having improved device reliability and a display device including the same.

Another object of the present invention is to provide a gate driving circuit and a display device including the gate driving circuit in which the discharge speed of the QB node is reduced.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a gate driving circuit including a plurality of stages connected in a dependent manner, each of the plurality of stages including a first node and a second node, A first node controller for charging the voltage of the Q node corresponding to the output voltage of the previous stage, a second node controller for charging the voltage of the Q node corresponding to the output voltage of the previous stage, a second clock signal different in phase from the first clock signal, And the second node control unit includes a fourth transistor for outputting a high level power supply voltage to the QB node corresponding to the third clock signal, A sixth transistor for outputting a second clock signal to the QB node corresponding to the voltage of the Q node; It is possible to improve the discharge rate QB node, degradation of a gate driving circuit, including.

A display device according to an embodiment of the present invention includes a display panel including a plurality of pixels, a gate driving circuit configured to sequentially output a gate output voltage to a plurality of pixels, And each of the plurality of stages includes an output section for outputting the first clock signal as a gate output voltage by the voltage of the Q node and the voltage of the QB node and the output section for outputting the voltage of the Q node corresponding to the output voltage of the previous stage And a second node controller for charging the QB node with a voltage corresponding to a second clock signal and a third clock signal having different phases from the first clock signal, The phase of the second clock signal and the phase of the third clock signal are delayed to improve the QB node discharge speed drop phenomenon of the gate drive circuit.

The details of other embodiments are included in the detailed description and drawings.

By applying a clock signal to the transistor that controls the QB node, the present invention can prevent the switching characteristics of the transistor from deteriorating.

According to the present invention, the QB node discharge rate is prevented from being lowered, and the gate voltage can be outputted sequentially in accordance with the normal timing, thereby improving the reliability of the display device.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a block diagram for explaining a display device according to an embodiment of the present invention.
2 is a block diagram illustrating a configuration of a gate driving circuit according to an embodiment of the present invention.
3A to 3C are diagrams showing equivalent circuits of stages of a gate driving circuit of a display device according to an embodiment of the present invention.
4A and 4B are circuit diagrams of a fifth transistor and a sixth transistor included in a gate driving circuit of a display device according to an embodiment of the present invention.
5 is a timing diagram illustrating an internal signal applied to a gate driving circuit of a display device according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. However, it is to be understood that the present invention is not limited to the embodiments disclosed herein but may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In the context of the present invention, the term 'includes', 'having', 'done', or the like is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

An element or layer is referred to as being another element or layer "on ", including both intervening layers or other elements directly on or in between.

Also, the first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The sizes and thicknesses of the individual components shown in the figures are shown for convenience of explanation and the present invention is not necessarily limited to the size and thickness of the components shown.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Although the embodiments of the present invention have been described on the basis of a liquid crystal display device, the present invention is not limited to a liquid crystal display device, but can be applied to all display devices having a gate drive circuit such as an organic light emitting display device.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a block diagram for explaining a display device according to an embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display panel 100, a gate driving circuit 200, a data driving circuit 300, and a timing controller 400.

The display panel 100 includes a display area A / A for displaying an image and a non-display area N / A where various signal lines or drive circuits are arranged outside the display area A / A.

A plurality of pixels P are arranged in the display area A / A, and an image is displayed based on the gradation displayed by each of the pixels P. In the display area A / A, n gate lines GL1 through GLn arranged in a first direction and m data lines DL1 through DLm arranged in a direction different from the first direction are arranged. The plurality of pixels P are electrically connected to n gate lines GL1 through GLm and m data lines DL1 through DLm and are electrically connected to gate lines GL1 through GLn and data lines DL1 through DLm The image is displayed by the driving signal or the driving voltage applied through the driving circuit.

For example, a gate drive circuit 200 is arranged in the non-display area N / A such as various signal wirings for transmitting signals for controlling the operation of the pixels P arranged in the display area A / A .

The timing controller 400 transmits the input video signal RGB received from the host system to the data driving circuit 300. The timing controller 400 uses a timing signal such as a clock signal DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE received together with an input video signal RGB A timing control signal for controlling the operation timings of the gate driving circuit 200 and the data driving circuit 300 is generated. The horizontal synchronization signal Hsync is a signal indicating the time taken to display one horizontal line of the screen. The vertical synchronization signal Vsync is a signal indicating the time taken to display a frame of one frame. The data enable signal DE Is a signal indicating a period of supplying the data voltage to the pixel P defined in the display panel 100. [ The timing controller 400 generates the control signal GCS of the gate driving circuit 200 and the control signal DCS of the data driving circuit 300 in synchronization with the timing signal.

The data driving circuit 300 generates a sampling signal by the data driving control signal DCS transmitted from the timing controller 400 and latches the video data inputted from the timing controller 400 according to the sampling signal to generate a data signal And supplies a data signal to the data lines DL1, ... DLm in response to a source output enable (SOE) signal. The data driving circuit 300 may be connected to the bonding pad of the display panel 100 by a chip on glass (COG) method or may be disposed directly on the display panel 100, As shown in FIG. In addition, the data driving circuit 300 may be arranged in a chip on film (COF) manner.

The gate driving circuit 200 sequentially supplies gate signals to the gate lines GL1, ..., GLn in accordance with the gate driving control signal GCS transmitted from the timing controller 400. [ The gate drive circuit 200 may include a shift register, a level shifter, and the like.

The gate drive circuit 200 of the display device according to an exemplary embodiment of the present invention may include a display panel (not shown) (GIP) method on the non-display area N / A in the form of a thin film pattern during the fabrication of the substrate of the display panel 100 (FIG. 1, only one gate driving circuit 200 is shown in the non-display area N / A of the display panel 100. However, the present invention is not limited to this, and two gate driving circuits 200 may be disposed .

The gate drive circuit 200 includes a plurality of stages including shift registers. 2, a detailed configuration of a gate driving circuit according to an embodiment of the present invention will be described.

2 is a block diagram illustrating a configuration of a gate driving circuit according to an embodiment of the present invention.

2, a gate driving circuit 200 according to an embodiment of the present invention receives a power supply voltage VDD and a ground voltage VSS and receives gate lines GL1 through GLn (N-1), Sn (n-1), and S (n-1) that output gate output voltages Vout1, Vout2, Vout3, And a shift register (not shown).

At this time, the clock signal CLK includes the first clock signal CLK (n), the second clock signal CLK (n + 1) and the third clock signal CLK (n + 2) can do. Here, the clock signal CLK may be a four-phase clock signal CLK having a high-to-low duty ratio of 1: 3. The second clock signal CLK (n + 1) has a phase delayed from the first clock signal CLK (n + 1) and the third clock signal CLK (n + 1) +2) have a delayed phase. Specifically, the first clock signal CLK (n) is a clock signal for outputting the gate output voltages Vout1, Vout2, Vout3, ... Vout (n-1), Vout The clock signal CLK (n + 1) may be a clock signal for discharging the voltage of the QB node and the third clock signal CLK (n + 2) may be a clock signal for charging the voltage of the QB node.

The first stage S1 receives the gate start signal VST and outputs the first gate output voltage Vout1 using the clock signal CLK and the second stage S2 to the nth stage Sn And sequentially outputs the second to n-th gate output voltages Vout2 to Vout (n) using a plurality of clock signals CLKs according to the previous stage output voltage or the next stage output voltage.

3A to 3C are diagrams showing equivalent circuits of stages of a gate driving circuit of a display device according to an embodiment of the present invention.

The operation of outputting the gate output voltages Vout1, Vout2, Vout3, ... Vout (n-1), Vout (n) is described below with reference to the operation of each stage S1, S2, S3, The n-th stage Sn will be described as an example. The switching elements constituting the gate driving circuit may be implemented by transistors of an n-type or p-type MOSFET structure. Although n-type transistors are exemplified in the following embodiments, the present invention is not limited thereto.

 A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, the current flows from the source to the drain because the holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. In the following embodiments, the invention should not be limited to the source and the drain of the transistor.

Specifically, in the gate drive circuit 200 of the present invention, an LTPS transistor using a low temperature poly-silicon (hereinafter referred to as LTPS) transistor, which is a transistor having a polycrystalline semiconductor material as an active layer, can be used. The polysilicon material has high mobility (100 cm < 2 > / Vs or more), low energy consumption power, and excellent reliability, so that it can be applied to a driving device transistor for driving display device transistors.

3A, the n-th stage of the gate driving circuit includes a first node controller T1, a third node controller T3, and a third node controller T3, a second node controller T4, T5, and T5Q, a first auxiliary transistor TA1, CQ, a second capacitor CQB and an output unit T6, T7.

The first capacitor CQ may be connected to a Q-node and a ground voltage VSS which are one electrode of the first auxiliary transistor TA1 and the second capacitor CQB may be connected to a QB node QB- And the ground voltage VSS.

The first node controllers T1, T3R, and T3 determine the charging timing of the P-node and the Q-node connected thereto. The first node controllers T1, T3R and T3 include a first transistor T1, a second transistor T3R and a third transistor T3.

Here, the P-node and the Q-node are connected to each other by the first auxiliary transistor TA1 turned on at the high potential source power supply voltage VDD, and therefore they are at the same potential.

In the first transistor T1, the gate electrode and the first electrode are connected to the output terminal Vout (n-1) of the (n-1) -th stage, and the second electrode is connected to the P-node . The first transistor T1 charges the P node and the Q node in response to the gate output voltage Vout (n-1) of the (n-1) th stage.

The second transistor T3R has a gate electrode connected to the gate start pulse terminal VST and a first electrode connected to a ground voltage VSS which is a low potential power source and a second electrode connected to a P- . The second transistor T3R discharges the P-node and the Q-node to the ground voltage VSS in response to the gate-start pulse signal supplied through the gate-start pulse terminal VST.

The third transistor T3 has a gate electrode connected to a QB node, a first electrode connected to a ground voltage VSS, and a second electrode connected to a P-node. The third transistor T3 discharges the P-node and the Q-node to the ground voltage VSS when the QB node is at a high level.

The second node controllers T4, T5 and T5Q determine the charging timing of the QB node (QB-node). The second node controllers T4, T5 and T5Q include a fourth transistor T4, a fifth transistor T5 and a sixth transistor T5Q.

The fourth transistor T4 has a gate electrode connected to the third clock signal terminal CLK (n + 2), a first electrode connected to the power supply voltage VDD and a second electrode connected to the QB node QB- Electrodes are connected. The fourth transistor T4 supplies the QB voltage corresponding to the period of the second clock signal CLK (n + 2) to the QB node (QB-node) when the high level supply voltage VDD is input Charge.

The fifth transistor T5 has a gate electrode connected to the output terminal Vout (n-1) of the (n-1) th stage and a first electrode connected to the second clock signal terminal CLK (n + And the second electrode is connected to the QB node (QB-node). The fifth transistor T5 outputs the second clock signal CLK (n + 1) to the QB node (QB-node) in response to the output of the (n-1) th stage.

The sixth transistor T5Q has a gate electrode connected to a P-node, a first electrode connected to a second clock signal terminal CLK (n + 1), a QB node QB-node And the second electrode is connected. The sixth transistor T5Q outputs the second clock signal CLK (n + 1) to the QB node (QB-node) in response to the voltage of the P-node.

The specific operation of the fifth transistor T5 and the sixth transistor T5Q will be described later with reference to FIGS. 4A to 5B.

The first auxiliary transistor TA1 protects the first transistor T1, the second transistor T3R and the third transistor T3, which are transistors connected to the P-node, for example, can do. Specifically, the first auxiliary transistor TA1 is connected to the gate of the power supply voltage VDD, the first electrode of the first auxiliary transistor TA1 is connected to the P-node, and the second electrode of the first auxiliary transistor TA1 is connected to the Q- do.

In the general first auxiliary transistor TA1, the same voltage, that is, the power supply voltage VDD, is applied except when the gate voltage is output. However, when the Q-node bootstrapping is performed, the first auxiliary transistor TA1 is turned off to turn off the transistors T1 of the first node controller connected to the P-node , T3R, T3).

The output sections T7 and T8 pull down the nth gate output voltage Vout (n) and the seventh transistor T7, which is a transistor for pulling up the nth gate output voltage Vout (n) and an eighth transistor T8 which is a pull-down transistor.

The seventh transistor T7 has a gate connected to the Q-node, a first clock signal CLK (n) connected to the first electrode, and an output terminal Vout (n) The second electrode is connected. The seventh transistor T7 outputs the first clock signal CLK (n) to the output terminal Vout (n) of the n-th stage when the Q-node is in a charged state.

The eighth transistor T8 has a gate connected to the QB node QB, a first electrode connected to the output terminal Vout (n) of the n-th stage, a second electrode connected to the ground voltage VSS . The eighth transistor T8 discharges the potential of the output terminal Vout (n) of the n-th stage to the ground voltage VSS when the QB node (QB-node) is in a charged state.

The first capacitor CQ is connected between the ground power supply VSS and the Q-node to stabilize the Q-node and the second capacitor CQB is connected to the ground power supply VSS. And a QB node (QB-node) to stabilize the QB node (QB-node).

In some embodiments, as shown in FIG. 3B, the first capacitor CQ is connected between the ground power supply VSS and the P-node to stabilize the P-node, 3C, the first capacitor CQ is connected between the output terminal Vout (n) and the Q-node to stabilize the Q-node.

In the driving of the n-th stage of the gate driving circuit according to an embodiment of the present invention, during the first time period, the first transistor T1 is turned on by the output voltage of the (n-1) The Q-node is charged, the Q-node is charged by the first transistor T5 being turned on and the sixth transistor T5Q is turned on by the voltage charged in the Q- The QB node QB is discharged and the seventh transistor T7 is turned on in response to bootstrapping by the first clock signal CLK (n) of high level to output the output terminal Vout (n ), A high-level scan pulse can be output.

On the other hand, the n-th stage is turned on by the third clock signal CLK (n + 2) at the high level during the second time period following the first time period to turn on the QB node The third transistor T3 is turned on by the voltage charged in the QB node and the Q node is discharged. Thus, the seventh transistor T7 is turned on so that the output terminal Vout (n) of the n-th stage can be discharged by the ground voltage VSS.

Hereinafter, the driving of the fifth transistor and the sixth transistor of the display device according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4A through 5. FIG.

4A and 4B are circuit diagrams of a fifth transistor and a sixth transistor included in a gate driving circuit of a display device according to an embodiment of the present invention.

5 is a timing chart showing an internal signal applied to a gate driving circuit of a display apparatus according to an embodiment of the present invention.

Specifically, a circuit diagram of the fifth transistor T5 is shown in FIG. 4A, and a circuit diagram of the sixth transistor T5Q is shown in FIG. 4B.

4A, the fifth transistor T5 has the gate electrode connected to the output terminal Vout (n-1) of the (n-1) th stage and the second clock signal terminal CLK (n + And the second electrode is connected to the QB node (QB-node). The fifth transistor T5 outputs the second clock signal CLK (n + 1) to the QB node (QB-node) in response to the output of the (n-1) th stage.

Referring to FIG. 4B, the sixth transistor T5Q has a gate electrode connected to a Q-node, a first electrode connected to a second clock signal terminal CLK (n + 1) And the second electrode is connected to the QB node (QB-node). The sixth transistor T5Q outputs the second clock signal CLK (n + 1) to the QB node (QB-node) in response to the voltage of the P-node.

5, the output voltage Vout (n-1) of the (n-1) -th stage is raised to the high level at the first time point t1 of the GIP outputting period, 5 transistor T5 is turned on. Thus, the output voltage Vout (n-1) of the (n-1) -th stage of the high level applied to the first transistor T1 is applied to the P-node and the Q- And the second clock signal CLK (n + 1) of low level applied to the fifth transistor T5 is outputted to the QB node (QB-node). Then, the sixth transistor is also turned on due to the output voltage Vout (n-1) of the (n-1) -th stage at the high level applied to the Q-node. Thus, the low-level second clock signal CLK (n + 1) applied to the fifth transistor T5 is output to the QB node (QB-node).

The output voltage Vout (n-1) of the (n-1) -th stage is polled to a low level at the second time point t2 so that the first transistor T1 and the fifth transistor T5 are turned off do. Then, the first clock signal CLK (n) is raised to a high level, and the voltage of the Q-node is bootstrapped. The seventh transistor T7 is turned on to output the high level first clock signal CLK (n) as the output voltage Vout (n) of the (n) th stage.

At the third time point t3, the QB node QB node is driven to the high level through the fifth transistor T5 and the sixth transistor T5Q which are turned on due to the high level P node voltage The third transistor T3 and the eighth transistor T8 are turned on and the ground voltage VSS (n + 1) is applied through the third transistor T3, Is discharged to the P-node and the Q-node and discharged through the eighth transistor T8 to the ground voltage VSS to the output voltage Vout (n) of the (n) -th stage, The second clock signal CLK (n + 1) having the high-level and low-level duty ratio of 1: 3 can be input to the fifth transistor T5 and the sixth transistor T5Q. have. However, the duty ratio of the second clock signal CLK (n + 1) is not limited to this, and may be variously set.

In a general gate drive circuit, the transistor discharging the QB node is supplied with a fixed potential ground voltage and the mobility of the active layer of the LTPS transistor is lowered due to a high junction stress (HJS) of 99% or more.

Accordingly, in the present invention, the fifth transistor T5 and the sixth transistor T5Q, which are LTPS transistors for discharging the QB node, discharge a second clock signal CLK (n + 1)), it is possible to reduce the high junction stress (HJS).

Specifically, as shown in Figs. 4A and 4B, when the duty ratio of the high level and the low level of the second clock signal CLK (n + 1) is 1: 3, the high junction stress (HJS) Lt; / RTI > Thus, the phenomenon that the mobility of the active layer of the fifth transistor T5 and the sixth transistor T5Q is lowered is prevented, and the deterioration of the switching characteristics of the fifth transistor T5 and the sixth transistor T5Q is prevented .

Accordingly, the gate driving circuit 200 of the display device 100 according to an embodiment of the present invention can reduce the discharge speed of the QB node (QB node) so that the gate voltage can be sequentially output to the normal timing So that the reliability of the display device can be improved.

A gate driving circuit and a display device including the same according to various embodiments of the present invention can be described as follows.

According to an aspect of the present invention, there is provided a gate driving circuit including a plurality of stages connected in a dependent manner, each of the plurality of stages including a first node and a second node, A first node controller for charging the voltage of the Q node corresponding to the output voltage of the previous stage, a second node controller for charging the voltage of the Q node corresponding to the output voltage of the previous stage, a second clock signal different in phase from the first clock signal, And the second node control unit includes a fourth transistor for outputting a high level power supply voltage to the QB node corresponding to the third clock signal, A sixth transistor for outputting a second clock signal to the QB node corresponding to the voltage of the Q node; It is possible to improve the discharge rate QB node, degradation of a gate driving circuit, including.

According to another aspect of the present invention, the fifth transistor and the sixth transistor are LTPS (Low Temperature Poly Silicon) transistors.

According to another aspect of the present invention, the duty ratio of the high level and the low level of the second clock signal is 1: 3.

According to another aspect of the present invention, there is further provided a first auxiliary transistor connected to a gate electrode of the high level power supply voltage to stabilize the Q node.

According to another aspect of the present invention, there is further provided a first capacitor connected to one electrode of the first auxiliary transistor.

According to another aspect of the present invention, the first capacitor is coupled to a ground voltage.

According to another aspect of the present invention, the first capacitor is connected to the output terminal.

A display device according to an embodiment of the present invention includes a display panel including a plurality of pixels, a gate driving circuit configured to sequentially output a gate output voltage to a plurality of pixels, And each of the plurality of stages includes an output section for outputting the first clock signal as a gate output voltage by the voltage of the Q node and the voltage of the QB node and the output section for outputting the voltage of the Q node corresponding to the output voltage of the previous stage And a second node controller for charging the QB node with a voltage corresponding to a second clock signal and a third clock signal having different phases from the first clock signal, The phase of the second clock signal and the phase of the third clock signal are delayed to improve the QB node discharge speed drop phenomenon of the gate drive circuit.

According to another aspect of the present invention,

A fourth transistor for outputting a high level power supply voltage to the QB node in response to the third clock signal,

A fifth transistor for outputting a second clock signal to the QB node corresponding to the output voltage of the previous stage and

And a sixth transistor for outputting a second clock signal to the QB node corresponding to the voltage of the Q node.

According to another aspect of the present invention, the phase of the third clock signal is delayed relative to the phase of the second clock signal.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display panel
200: Gate drive circuit
300: Data driving circuit
400: timing controller
P: pixel
T1: first transistor
T3R: the second transistor
T3: Third transistor
T4: fourth transistor
T5: fifth transistor
T5Q: sixth transistor
T7: seventh transistor
T8: the eighth transistor

Claims (12)

Comprising a plurality of stages connected in a dependent manner,
Wherein each of the plurality of stages includes:
An output unit for outputting the first clock signal as a gate output voltage by the voltage of the Q node and the voltage of the QB node;
A first node controller for charging a voltage of the Q node corresponding to an output voltage of a previous stage;
And a second node controller for charging a voltage to the QB node corresponding to a second clock signal and a third clock signal having different phases from the first clock signal,
The second node control unit,
A fourth transistor for outputting a high level power supply voltage to the QB node in response to the third clock signal,
A fifth transistor for outputting the second clock signal to the QB node corresponding to an output voltage of the previous stage,
And a sixth transistor for outputting the second clock signal to the QB node corresponding to the voltage of the Q node. The method according to claim 1,
And the fifth transistor and the sixth transistor are LTPS (Low Temperature Poly Silicon) transistors. The method according to claim 1,
And the duty ratio of the high level and the low level of the second clock signal is 1: 3. The method according to claim 1,
And a gate electrode connected to the high level power supply voltage to stabilize the Q node. 5. The method of claim 4,
Further comprising a first capacitor coupled to one electrode of the first auxiliary transistor. 6. The method of claim 5,
And the first capacitor is coupled to a ground voltage. 6. The method of claim 5,
And the first capacitor is connected to the output terminal. A display panel including a plurality of pixels;
A gate driving circuit which is composed of a plurality of stages and sequentially outputs a gate output voltage to the plurality of pixels;
And a timing controller for controlling driving of the gate driving circuit,
Wherein each of the plurality of stages includes:
An output unit for outputting the first clock signal as a gate output voltage by the voltage of the Q node and the voltage of the QB node;
A first node controller for charging a voltage of the Q node corresponding to an output voltage of a previous stage;
And a second node controller for charging a voltage to the QB node corresponding to a second clock signal and a third clock signal having different phases from the first clock signal,
Wherein the phase of the second clock signal and the phase of the third clock signal are delayed relative to the phase of the first clock signal. 9. The method of claim 8,
The second node control unit,
A fourth transistor for outputting a high level power supply voltage to the QB node in response to the third clock signal,
A fifth transistor for outputting the second clock signal to the QB node corresponding to an output voltage of the previous stage,
And a sixth transistor for outputting the second clock signal to the QB node corresponding to the voltage of the Q node. 10. The method of claim 9,
And the phase of the third clock signal is delayed relative to the phase of the second clock signal. 10. The method of claim 9,
And the fifth transistor and the sixth transistor are LTPS (Low Temperature Poly Silicon) transistors. 9. The method of claim 8,
And the duty ratio of the high level and the low level of the second clock signal is 1: 3.

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