KR102565082B1 - Organic Light Emitting Display and Degradation Sensing Method of Organic Light Emitting Display - Google Patents

Abstract

According to the present invention, a display panel having a plurality of pixels each including a driving element and an organic element is connected to the pixels through a sensing line to sense an electrical characteristic value of at least one of the driving element and the organic element to obtain an analog sensing value. A sensing unit, an analog-to-digital converter that converts an analog sensing value into a digital sensing value, a gate driving circuit that generates a scan pulse by receiving a high-potential driving voltage and supplies the scan pulse to a gate line connected to pixels, and a digital sensing value. An organic light emitting display device including a timing controller that generates a power control signal and a power regulator that adjusts a high-potential driving voltage according to the power control signal.

Description

Organic Light Emitting Display and Degradation Sensing Method of Organic Light Emitting Display

The present invention relates to an organic light emitting display device and a method for sensing degradation thereof.

Various flat panel displays (FPDs) capable of reducing the weight and volume, which are disadvantages of cathode ray tubes, are being developed and marketed. A scan driving circuit of such a flat panel display generally includes a gate shift register to sequentially supply scan pulses to scan lines.

The gate shift register of the scan driving circuit includes thin film transistors (hereinafter referred to as “TFT”) and includes a plurality of stages connected in a cascading manner. The stages are connected to each other in a cascade manner to sequentially generate scan pulses. 1 shows an example of an n-th stage for generating an n-th scan pulse Vg(n) to be supplied to an n-th scan line. And, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1 . A transistor to be described below may be implemented as a TFT.

1 and 2, the nth stage controls the Q node for controlling the switching operation of a pull-up transistor (Tpu) and the switching operation of a pull-down transistor (Tpd). It includes a QB node for The pull-up transistor Tpu is turned on during the first output period X1 in which the potential VQ of the Q node is maintained at the bootstrapping level BH, and outputs the shift clock signal CLKn to a gate high voltage ( It is output as the nth scan pulse (Vg(n)) of VGH. The pull-up transistor Tpu is turned off during the second output period X2 when the potential VQ of the Q node is maintained at the discharge level L. The potential (VQB) of the QB node is maintained at the discharge level (L) during the first output period (X1) and maintained at the charge level (H) during the second output period (X2). Due to the potential VQB of the QB node, the pull-down transistor Tpd is turned on during the second output period X2 to generate the low potential driving voltage VSS at the nth scan pulse Vg( output as n)). The pull-down transistor Tpd is turned off during the first output period X1. In the third output period (X3) prior to the first output period (X1), the potential (VQ) of the Q node is maintained at the charge level (H), and the potential (VQB) of the QB node is maintained at the discharge level (L). .

The first, fifth, and sixth transistors T1, T5, and T6 connected to the Q node control the potential VQ of the Q node through a switching action. The first transistor T1 charges the Q node according to the set signal SET during the third output period X3. The set signal SET may be selected as the n−1 th scan pulse Vg(n−1). The fifth transistor T5 discharges the Q node according to the reset signal RESET during the second output period X2. The reset signal RESET may be selected as the n+1th scan pulse Vg(n+1). The sixth transistor T6 maintains the Q node at the discharge level (L) when the QB node is maintained at the charge level (H) during the second output period (X2). The sixth transistor T6 prevents ripple from occurring at the Q node during the second output period X2 and functions to stabilize the output.

The second to fourth transistors T2 , T3 , and T4 connected to the QB node control the potential VQB of the QB node through a switching action. The second transistor T2 discharges the QB node according to the set signal SET during the third output period X3. The third transistor T3 discharges the QB node according to the potential VQ of the Q node in the third output period X3 and the first output period X1. The fourth transistor T4 supplies a high potential driving voltage VDD to the QB node. The high potential driving voltage VDD charges the QB node in the second output period X2 when the second and third transistors T2 and T3 are turned off.

As such, within each stage, the Q node and QB node are charged and discharged opposite to each other. That is, when the Q node is charged (including bootstrapping), the QB node is discharged, and conversely, when the Q node is discharged, the QB node is charged. The scan pulse is generated as a gate high voltage (VGH) only for a very short time (X1) so that the data voltage is charged in one horizontal pixel line, and must be maintained as a gate low voltage (VGL) for the remaining period. Therefore, the period in which the potential (VQB) of the QB node is maintained at the charge level (H) within one frame (ie, the second output period (X2)) is, as shown in FIG. 3, the potential (VQB) of the QB node It is much longer than the period maintained at the discharge level (ie, the first and third output periods X1 and X3).

In this way, as the width of the pull-up transistor Tpu increases, the parasitic capacitance between the shift clock signal CLKn and the Q node increases. As the parasitic capacitance between Q nodes increases, the Q node is affected by the shift clock signal CLKn. As the Q node is affected by the shift clock signal CLKn, the sixth transistor T6 stabilizing the Q node deteriorates and loses its function. Ripple is generated at the Q node because the sixth transistor T6 loses its function and cannot maintain the Q node at the discharge level (L) during the second output period X2.

When the sixth transistor T6 deteriorates and loses its function, the pull-up transistor Tpu is operated by the ripple, and the shift clock signal CLKn is output to the first node Vg(n) as it is. Multi-pulse scan pulses are output for each gate line of . During sensing, if a multi-pulse scan pulse is output through one gate line, the analog signal (sensing data) input to the ADC through the reference voltage line (Ref Line) in a gate line unit is outside the input range of the ADC. overflow occurs.

An object of the present invention is to provide an organic light emitting display device capable of delaying the deterioration rate by minimizing the bias of a driving element, monitoring the deterioration rate, and extending the driving lifespan by varying the bias accordingly, and a deterioration sensing method thereof. .

In order to achieve the above object, an organic light emitting display device according to an embodiment of the present invention is a display panel having a plurality of pixels including a driving element and an organic element, respectively, and a driving element and an organic element connected to the pixels through a sensing line. A sensing unit that obtains an analog sensing value by sensing at least one of the electrical characteristic values, an analog-to-digital converter that converts the analog sensing value into a digital sensing value, generates a scan pulse by receiving a high-potential driving voltage, and converts the scan pulse into a pixel It includes a gate driving circuit supplying gate lines connected to the gate lines, a timing controller generating a power control signal based on a digitally sensed value, and a power regulator adjusting a high-potential driving voltage according to the power control signal.

The gate driving circuit includes a shift register and stages dependently connected to the shift register, and each stage outputs one of the shift clock signals as a scan pulse of a gate high voltage according to the potential of the Q node, a pull-up transistor, an output It is connected to the pull-up transistor through a node and outputs a low potential driving voltage as a gate low voltage scan pulse according to the potential of the QB node. and a node controller including a stabilization transistor connected to the QB node for controlling.

The timing controller calculates compensation data for compensating for deterioration of an organic element of each pixel or compensating for threshold voltage deviation and mobility deviation of a driving element from a digital sensing value, and stores the compensation data in a memory.

The timing controller generates a power control signal based on compensation data stored in a memory and supplies the generated power control signal to a power regulator.

In the case of the analog-to-digital converter, when the scan pulse is output to the gate line in the form of a multi-pulse, the analog sensing value input through the sensing line increases in each gate line, and the output value of the analog-to-digital converter overflows to the upper limit of the input voltage range. do.

In order to achieve the above object, in a method for sensing deterioration of an organic light emitting display device including a display panel having a plurality of pixels each including a driving element and an organic element, the driving element and the organic element are connected to the pixels through a sensing line. Obtaining an analog sensing value by sensing at least one electrical characteristic value among, converting the analog sensing value into a digital sensing value, generating a scan pulse by receiving a high potential driving voltage, and connecting the scan pulse to pixels. Supplying it to the gate line, generating a power control signal based on the digitally sensed value, and adjusting the high-potential driving voltage according to the power control signal.

According to the present invention, the lifetime of the gate driving circuit can be greatly increased by suppressing deterioration of the threshold voltage of the transistors connected to the Qb node as much as possible to stabilize the output of the scan pulse.

According to the present invention, the gate-bias stress of the transistor can be reduced by lowering the initial high-potential driving voltage supplied to the gate terminal of the transistor connected to the Qb node. As a result, the shift of the threshold voltage can be alleviated.

1 is a diagram showing the configuration of an nth stage of a conventional gate shift register;
Figure 2 is a waveform diagram for explaining the operation of Figure 1;
Fig. 3 is a waveform diagram showing the potential of the QB node over a number of frames;
4 is a diagram showing a threshold voltage shift of a TFT according to the lapse of driving time.
5 is a schematic diagram of an organic light emitting display device according to an exemplary embodiment of the present invention;
6 is a diagram showing an example of a configuration of a pixel, data driving circuit, and gate driving circuit according to the present invention;
7 is a diagram showing an example of a configuration of pixels, stages, and sensing units to which the sensing method of the present invention is applied;
8 is a diagram showing that sensing is performed when the sensing drive of the present invention is powered on;
9 is a diagram showing that sensing is performed when the sensing drive of the present invention is powered off.
10 is a diagram showing a change in threshold voltage when GVDD is lowered.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 5 to 10 .

5 to 10 , an organic light emitting display device according to an embodiment of the present invention includes a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and power generation. A part 17 may be provided.

A plurality of data lines and sensing lines 14A and 14B and a plurality of gate lines 15 intersect on the display panel 10, and pixels P are arranged in a matrix form at each intersection.

The pixels P may be connected to any one of the data lines 14A, any one of the sensing lines 14B, and any one of the gate lines. The pixel P is electrically connected to the data line 14A in response to the scan pulse SCAN input through the gate lines 15 and receives the sensing data voltage Vdata_SEN from the data line 14A. , a sensing signal may be output through the sensing line 14B.

Each of the pixels P receives a high potential driving voltage EVDD and a low potential driving voltage EVSS from the power generator 17 . The pixel P of the present invention includes an organic element, a driving TFT, first and second switch TFTs, and a storage capacitor for external compensation, and in particular, the first switch TFT and the second switch TFT are the same to reduce the signal line. It has a feature of simultaneous switching according to the scan pulse. TFTs, which are driving elements constituting the pixel P, may be implemented as p-type or n-type. In addition, the semiconductor layer of the TFTs constituting the pixel P may include amorphous silicon, polysilicon, or oxide.

Each of the pixels P may operate differently during normal driving to implement a display image and sensing driving to obtain a sensing value. The sensing driving may be performed during a predetermined time during power-on or during vertical blank periods during normal driving. Also, sensing driving may be performed for a predetermined time during a power-off process.

The sensing drive may be performed by one operation of the data driving circuit 12 and the gate driving circuit 13 under the control of the timing controller 11 . An operation of deriving compensation data for compensating the threshold voltage deviation and mobility deviation of the driving TFT based on the sensing result, an operation of deriving compensation data for deterioration compensation, and digital video for normal driving using the compensation data An operation of modulating data is performed in the timing controller 11 .

The data driving circuit 12 includes at least one data driver Integrated Circuit (IC) (SDIC). In this data driver IC (SDIC), a plurality of digital-to-analog converters (hereinafter referred to as DACs) 121 connected to each data line 14A and a plurality of Sensing units 122, a multiplexer 123 (hereinafter referred to as a mux unit) selectively connecting the sensing units 122 to an analog-to-digital converter (Analog Digital converter: hereinafter described as an ADC), and a selection control signal A shift register 124 may be included to sequentially turn on the switches SS1 to SSk of the mux unit 123 by generating .

The DAC of the data driver IC (SDIC) converts digital video data (RGB) into data voltages for image display according to the data timing control signal (DDC) applied from the timing controller 11 during normal operation, and converts the data lines 14A supply to On the other hand, the DAC of the data driver IC (SDIC) can generate the sensing data voltage (Vdata_SEN) according to the data timing control signal (DDC) applied from the timing controller 11 during sensing driving and supply it to the data lines 14A. there is.

Each of the sensing units SU#1 to #k of the data driver IC (SDIC) may be connected to the sensing line 14B one-to-one. It is not limited thereto, and the sensing unit may have an independent structure independently connected to a sensing line or a shared structure connected together with a plurality of sensing lines.

The ADC of the data driver IC (SDIC) converts the sensing voltage input through the mux unit 123 into a digital sensing value SD and transmits it to the timing controller 11 . ADC is a special encoder that converts analog signals into data in the form of digital signals. The ADC has a preset input voltage range, that is, a sensing range. The input voltage range of the ADC may vary depending on the resolution of the AD conversion, but may be set to Evref (ADC reference voltage) to Evref + kV (k is a real number). Here, the resolution of AD conversion indicates a bit value capable of converting an analog input voltage into a digital value. At this time, when the analog signal input to the ADC is out of the input range of the ADC, the output value of the ADC may overflow to the upper limit of the input voltage range.

The gate driving circuit 13 receives a high potential driving voltage and generates a scan pulse. The scan pulse includes a scan pulse for threshold voltage sensing, a scan pulse for mobility sensing, and a scan pulse for image display, which are generated with different pulse widths. A scan pulse for mobility sensing may be generated with a much smaller pulse width than a scan pulse for threshold voltage sensing. The gate driving circuit 13 may supply scan pulses for threshold voltage sensing to the gate lines 16 in a line sequential manner during threshold voltage sensing driving, and may supply scan pulses for mobility sensing to the gate lines 16 in line sequential manner during mobility sensing driving. can be supplied to the gate lines 15 in this manner, and during image display driving, scan pulses for image display can be supplied to the gate lines 15 in a line-sequential manner. The gate driving circuit 13 may be directly formed on the display panel 10 according to a gate-driver in panel (GIP) method. GIP includes a shift register. The shift register includes sequentially connected stages 131 (STG(i) to STG(i+3)). Each stage is connected to the pull-up transistor through a pull-up transistor (Tpu) outputting one of the shift clock signals as an n-th scan pulse of a gate high voltage according to the potential of the Q node, and an output node. A pull-down transistor (Tpd) outputs a low potential driving voltage as an n-th scan pulse of the gate low voltage according to the potential of the QB node, and a Q node for controlling the switching operation of the pull-up transistor (Tpu) A node controller 132 connected to the QB node for controlling the switching operation of the pull-down transistor Tpd is included.

The timing controller 11 operates the data driving circuit 12 based on timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK, and the data enable signal DE. A data control signal DDC for controlling the timing and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13 are generated. The timing controller 11 separates normal driving and sensing driving based on predetermined reference signals (driving power enable signal, vertical synchronization signal, data enable signal, etc.), and generates a data control signal (DDC) and gate for each drive. A control signal GDC may be generated. In addition, the timing controller 11 further sends related switching control signals (including PRE and SAM of FIG. 7 ) to operate internal switches of each sensing unit SU#1 to #k according to normal driving and sensing driving. can create

The timing controller 11 may transmit digital data corresponding to the sensing data voltage Vdata_SEN to the data driving circuit 12 during sensing driving. Here, the sensing data voltage Vdata_SEN applied to each pixel may be set differently according to the threshold voltage deviation and the mobility deviation of the driving TFT included in the corresponding pixel.

The timing controller 11 provides compensation data capable of compensating deterioration of organic elements of each pixel P or threshold voltage deviation of a driving TFT based on the digital sensing value SD transmitted from the data driving circuit 12 during sensing driving. And compensation data for compensating for the mobility deviation may be calculated, and the compensation data may be stored in the memory 16 . The timing controller 11 generates a power control signal capable of adjusting the high-potential driving voltage supplied to the node controller 132 based on the digital sensing value SD during sensing operation. The timing controller 11 may modulate the digital video data RGB for image display with reference to the compensation data stored in the memory 16 during normal driving and transmit the modulated digital video data RGB to the data driving circuit 12 .

The power generation unit 17 generates a high potential driving voltage (EVDD) and a low potential driving voltage (EVSS). The power generator 17 includes a power regulator 171 that adjusts the high potential driving voltage EVDD according to the power control signal generated by the timing controller 11 .

7 shows an example of a configuration of a pixel, a stage, and a sensing unit to which the degradation sensing method of the present invention is applied. Since FIG. 7 is only an example, it should be noted that the technical spirit of the present invention is not limited to the exemplified structures of pixels, stages, and sensing units.

Referring to FIG. 7 , the pixel P may include an OLED, a driving TFT (DT), a storage capacitor (Cst), a first switch TFT (ST), and a second switch TFT (ST2).

The organic element OLED includes an anode electrode connected to the source node Ns, a cathode electrode connected to an input terminal of the low potential driving voltage EVSS, and an organic compound layer positioned between the anode electrode and the cathode electrode. The driving TFT (DT) controls the driving current (Ioled) flowing through the organic element (OLED) according to the gate-source voltage (Vgs). The driving TFT (DT) has a gate electrode connected to the gate node Ng, a drain electrode connected to the input terminal of the high potential driving voltage EVDD, and a source electrode connected to the source node Ns. The storage capacitor Cst is connected between the gate node Ng and the source node Ns. The first switch TFT (ST1) applies the data voltage (Vdata) on the data line (14A) to the gate node (Ng) in response to the scan pulse (GP). The first switch TFT (ST1) has a gate electrode connected to the gate line 15, a drain electrode connected to the data line 14A, and a source electrode connected to the gate node Ng. The second switch TFT (ST2) switches the current flow between the source node (Ns) and the sensing line (14B) in response to the scan pulse (SP), and follows the gate voltage of the gate node (Ng) in a source-following method. The changing source voltage of the source node Ns is stored in the sensing capacitor Cx on the sensing line 14B. The gate electrode of the second switch TFT (ST2) is commonly connected to the gate line 15 together with the gate electrode of the first switch TFT (ST1), and the drain electrode of the second switch TFT (ST2) is connected to the source node (Ns). and the source electrode of the second switch TFT (ST2) is connected to the sensing line 14B.

The stage 131 may include a node controller 132 , a pull-up transistor Tpu and a pull-down transistor Tpd. Although not shown, a sixth transistor T6 (see FIG. 1 ) for preventing ripple from occurring and stabilizing the Q node is disposed in the node controller 132 . This sixth transistor T6 is defined as a stabilization transistor.

The node controller 132 includes a stabilization transistor T6 connected to a Q node for controlling the switching operation of the pull-up transistor Tpu and a QB node for controlling the switching operation of the pull-down transistor Tpd. The node controller 132 includes a plurality of driving elements, and is directly or indirectly connected to the Q node and the QB node by the plurality of driving elements. The node controller 132 controls the pull-up transistor Tpu and the pull-down transistor Tpd to output a scan pulse by supplying a high potential driving voltage and shift clock signals to the Q node or the QB node. The pull-up transistor Tpu outputs one of the shift clock signals CLKn as an n-th scan pulse of a gate high voltage according to the potential of the Q node. The pull-up transistor Tpu has a gate electrode connected to the Q node, a drain electrode connected to a clock terminal, and a source electrode connected to an output node. The pull-down transistor Tpd is connected to the pull-up transistor Tpu through an output node, and outputs a low potential driving voltage as an nth scan pulse of the gate low voltage according to the potential of the QB node. The pull-down transistor Tpd has a gate electrode connected to the QB node, a source electrode connected to a low potential driving voltage terminal, and a drain electrode connected to the output node No. The pull-up transistor Tpu and the pull-down transistor Tpd are connected in series to each other through an output node No through which the nth scan pulse Vg(n) is output.

Also, the sensing unit SU may include an initialization switch SW1, a sampling switch SW2, and a sample and hold unit S/H.

The initialization switch SW1 is switched according to the initialization control signal PRE to switch the flow of current between the input terminal of the initialization voltage Vpre and the sensing line 14B. The sampling switch SW2 is switched according to the sampling control signal SAM to connect the sensing line 14B and the sample and hold unit S/H. The sample and hold unit S/H samples and holds the voltage stored in the line capacitor LCa of the sensing line 14B as a sensing voltage when the sampling switch SW2 is turned on, and then transfers the sampled voltage to the ADC. Here, the line capacitor LCa may be replaced with a parasitic capacitor present in the sensing line 14B.

Based on the exemplary configuration of the organic light emitting display device described above, a sensing method of the organic light emitting display device according to an exemplary embodiment of the present invention will be described in detail below.

8 shows that sensing is performed when the sensing drive of the present invention is powered on, and FIG. 9 shows that sensing is performed when the sensing drive is powered off.

As shown in FIG. 8 , the sensing driving may be performed during a predetermined time during a power-on process or may be performed during vertical blank periods during normal driving. The sensing drive may be performed by one operation of the data driving circuit 12 and the gate driving circuit 13 under the control of the timing controller 11 . The operation of deriving compensation data for compensating the deviation of the threshold voltage and the deviation of mobility of the driving TFT based on the sensing result and the operation of modulating digital video data for normal driving using the compensation data are performed by the timing controller 11. is carried out

Power is supplied to the organic light emitting display device of the present invention (S101).

When power is supplied, the timing controller 11 sets the high potential driving voltage supplied to the QB node low (S102). The timing controller 11 generates a power control signal based on compensation data stored in the memory 16 and supplies the generated power control signal to the power regulator 171 . The power regulator 171 receives a power control signal and adjusts the high potential driving voltage. At this time, the power regulator 171 may adjust the high potential driving voltage by removing a voltage margin from the high potential driving voltage. The voltage margin is defined as a voltage difference between a minimum voltage at which the stabilization transistor T6 can be driven at a high potential driving voltage. The adjusted high-potential driving voltage is supplied to the QB node electrically connected to the gate terminal of the stabilization transistor T6. At this time, the adjusted high potential driving voltage is a voltage between the high potential driving voltage and the threshold voltage of the stabilization transistor T6. The adjusted high potential driving voltage is a threshold voltage capable of driving the stabilization transistor T6 and is higher than the threshold voltage.

Driving elements disposed in the gate driving circuit 13 are sensed and driven by supplying an adjusted high-potential driving voltage (S103). That is, the stabilization transistor T6, which is one of the driving elements, is sensed and driven with a high-potential driving voltage lower than the high-potential driving voltage.

The stabilization transistor T6 is driven by receiving the adjusted high-potential driving voltage through the QB node. When the stabilization transistor T6 is normally driven, the Q node is stably maintained at the discharge level (L) while the pull-down transistor Tpd operates. Accordingly, the adjusted high potential driving voltage is continuously applied to the QB node. Accordingly, one scan pulse is sequentially supplied to each of the plurality of gate lines (S104 and S106).

In contrast, if the stabilization transistor T6 is not normally driven, the Q node cannot be maintained at the discharge level (L) and ripple is generated. As the stabilization transistor T6 shakes instead of maintaining the Q node at the discharge level (L) due to the ripple, the shift clock signals supplied to the pull-up transistor Tpu are affected between the floated Q node and the N0 node. received and the scan pulse can be output in the form of multi-pulse through the N0 node. When the multi-pulse scan pulse is output to one gate line, an analog signal input to the ADC through the sensing line 14B in units of gate lines may be out of the input range of the ADC. When the scan pulse is output to the sensing line 14B in the form of a multi-pulse, the analog sensing value may increase because the sensing unit can sense a plurality of multi-scan pulses in units of one horizontal pixel line. Also, the sensing unit may sense a plurality of multi-scan pulses in units of one horizontal pixel line, or may sense a plurality of multi-scan pulses in units of a plurality of horizontal pixel lines regularly arranged at equal intervals.

As shown in the pixel structure of FIG. 6, this is due to the fact that a plurality of pixels share one sensing line 14B connected to the sensing unit. If the analog sensing value increases, the output value of the ADC may overflow to the upper limit of the input voltage range.

Stages including the node controller 132, the pull-up transistor Tpu, and the pull-down transistor Tpd are connected to each other in a cascade manner, so that when a scan pulse is generated in the form of a multi-pulse, adjacent sensing lines 14B Alternatively, it may overlap scan pulses supplied to the sensing lines 14B connected at regular intervals. When the analog sensing value increases for each sensing line 14B by the multi-pulse scan pulse, the output value of the ADC may overflow to the upper limit of the input voltage range. The ADC converts the overflowed analog sensed value into a digital sensed value.

As such, when the stabilization transistor T6 is not normally driven, a high potential driving voltage higher than the adjusted high potential driving voltage is applied to the QB node. A high potential driving voltage obtained by adding a predetermined voltage to the adjusted high potential driving voltage may be applied to the QB node (S104 and S105). By applying a high potential driving voltage in which a predetermined voltage is added to the stabilization transistor T6, the stabilization transistor T6 can stably maintain the Q node at the discharge level (L). Accordingly, a high potential driving voltage in which a predetermined voltage is added is continuously applied to the QB node. Accordingly, one scan pulse is sequentially supplied to each of the plurality of sensing lines 14B.

The timing controller 11 calculates compensation data for compensating for deterioration of organic elements of each pixel P or compensation data for compensating for threshold voltage deviation and mobility deviation of the driving TFT based on the digital sensed value, Compensation data may be stored in memory 16 . The timing controller 11 generates a power control signal capable of adjusting a high-potential driving voltage supplied to the node controller 132 based on compensation data stored in the memory 16 during sensing operation.

The power regulator 171 adjusts the high potential driving voltage according to the power control signal. The power regulator 171 may adjust the high potential driving voltage to rise by a predetermined voltage when the digital sensing value includes the analog sensing value that overflows.

In the present invention, the stabilization transistor T6 operates normally by adjusting the high-potential driving voltage with a threshold voltage, which is the minimum voltage capable of driving the stabilization transistor T6 during sensing operation, and applying the adjusted high-potential driving voltage to the QB node. Then, even during normal driving, the stabilization transistor T6 can be driven with the high potential driving voltage adjusted to the threshold voltage. Alternatively, the stabilization transistor T6 may be driven with the high potential driving voltage in which the voltage margin is restored during normal driving (S107).

In addition, if the stabilization transistor T6 operates abnormally, it can be driven by supplying a high potential driving voltage higher than the threshold voltage to the stabilization transistor T6 during normal driving. Alternatively, during normal driving, the voltage margin is restored to the high potential driving voltage adjusted to the threshold voltage, and the stabilization transistor T6 is driven with the high potential driving voltage obtained by adding a predetermined voltage to the high potential driving voltage in which the voltage margin is restored. can

When normal driving is completed, power is cut off (S108).

In the present invention, when the stabilization transistor T6 is driven with a threshold voltage during sensing driving and normal driving, the gate-bias stress of the stabilization transistor T6 is reduced, thereby mitigating the shift in the threshold voltage. On the other hand, when the present invention drives the stabilization transistor T6 with a high potential driving voltage including a voltage margin during sensing driving and normal driving, the deterioration state of the stabilization transistor T6 can be checked using the size of the voltage margin. there is. Accordingly, it is possible to prevent the occurrence of malfunction due to deterioration of the stabilization transistor T6 and at the same time alleviate the shift of the threshold voltage.

Also, as shown in FIG. 9 , sensing driving may be performed for a predetermined time during a power-off process. The sensing drive may be performed by one operation of the data driving circuit 12 and the gate driving circuit 13 under the control of the timing controller 11 . An operation of deriving compensation data for deterioration compensation based on a sensing result and an operation of modulating digital video data for normal driving using the compensation data are performed by the timing controller 11 .

Power to the organic light emitting display device of the present invention is cut off (S201).

Before power is cut off, the timing controller 11 sets the high potential driving voltage supplied to the QB node low (S202). The timing controller 11 generates a power control signal based on compensation data stored in the memory 16 and supplies the generated power control signal to the power regulator 171 . The power regulator 171 receives a power control signal and adjusts the high potential driving voltage. At this time, the power regulator 171 may adjust the high potential driving voltage by removing a voltage margin from the high potential driving voltage.

Subsequent processes (S203 to S208) can be sufficiently inferred through FIG. 8, so a detailed description thereof will be omitted.

Referring to FIG. 10, the threshold voltage is shown as a vertical line and the driving time is shown as a horizontal line, showing that the threshold changes according to the driving time. As the driving time progresses, the rate of change of the threshold voltage decreases.

The graph shown as a dotted line is when the high potential driving voltage is 24V, and the graph shown as a solid line is when the high potential driving voltage is 12V.

As shown in FIG. 10, unlike the prior art, the present invention can generate a scan pulse by supplying an initial high potential driving voltage lower than the conventional high potential driving potential. The node controller of the present invention controls the stabilization transistor T6 by receiving a high potential driving voltage lower than the conventional high potential driving voltage and applying it to the Qb node.

A relatively low high-potential driving voltage is applied to the gate electrode of the stabilization transistor T6, thereby reducing gate-bias stress. Accordingly, the change rate at which the threshold voltage of the stabilization transistor T6 increases is reduced. For example, when the initial high potential driving voltage supplied to the gate terminal of the stabilization transistor T6 is 24V, it takes about 600 hours of driving time to reach the threshold voltage of 6V. However, when the initial high potential driving voltage supplied to the gate terminal of the stabilization transistor T6 is 12V, it takes about 800 hours of driving time to reach the threshold voltage of 6V. Accordingly, according to the present invention, the threshold voltage of the stabilization transistor T6 may be less deteriorated by a driving time of 200 hours than in the prior art.

As described above, in the present invention, gate-bias stress of the stabilization transistor T6 is reduced by lowering the initial high-potential driving voltage supplied to the gate terminal of the stabilization transistor T6. Gate-bias stress of the stabilization transistor T6 is reduced so that the shift of the threshold voltage can be alleviated. Therefore, the reliability of the driving element in the GIP can be improved and the reliability of the GIP can also be improved.

Through the above description, those skilled in the art will know that various changes and modifications are possible within the scope without departing from the technical spirit of the present invention. Therefore, the present invention should not be limited to the contents described in the detailed description, but should be defined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14A, 14B: data line and sensing line 15: gate line
16: memory 17: voltage generator
121: DAC 122: sensing unit
123: multiplexer 124: shift register
131: stage 132: node control unit

Claims (8)

a display panel provided with a plurality of pixels each including a driving element and an organic element;
a sensing unit connected to the pixels through a sensing line to sense an electrical characteristic value of at least one of the driving element and the organic element to obtain an analog sensing value;
an analog-to-digital converter converting the analog sensed value into a digital sensed value;
a gate driving circuit generating scan pulses by receiving a high potential driving voltage, and supplying the scan pulses to gate lines connected to the pixels;
a timing controller generating a power control signal based on the digital sensing value; and
A power regulator adjusting the high potential driving voltage according to the power control signal;
The power regulator,
and adjusting the high-potential driving voltage to rise by a predetermined voltage when the output value of the analog-to-digital converter overflows to an upper limit of an input voltage range. According to claim 1,
The gate driving circuit includes a shift register and stages connected dependently to the shift register;
each of the stages
a pull-up transistor outputting one of the shift clock signals as an n-th scan pulse of a gate high voltage according to the potential of the Q node;
a pull-down transistor connected to the pull-up transistor through an output node and outputting a low potential driving voltage as an n-th scan pulse of a gate low voltage according to a potential of a QB node; and
and a node controller including a stabilization transistor connected to the Q node for controlling a switching operation of the pull-up transistor and the QB node for controlling a switching operation of the pull-down transistor. According to claim 1,
The timing controller calculates compensation data for compensating for deterioration of the organic element of each pixel or compensating for threshold voltage deviation and mobility deviation of the driving element from the digital sensing value, and stores the compensation data in a memory. display device. According to claim 3,
The timing controller
An organic light emitting display device generating a power control signal based on the compensation data stored in the memory and supplying the generated power control signal to the power controller. According to claim 1,
When the scan pulse is output to the gate line in the form of a multi-pulse, the analog-to-digital converter increases the analog sensing value input through the sensing line in units of the gate line so that the output value of the analog-to-digital converter is the upper limit value of the input voltage range. An organic light emitting display device that overflows into . A method for sensing deterioration of an organic light emitting display device including a display panel having a plurality of pixels including a driving element and an organic element, respectively,
obtaining an analog sensing value by being connected to the pixels through a sensing line and sensing an electrical characteristic value of at least one of the driving element and the organic element;
converting the analog sensed value into a digital sensed value;
generating a scan pulse by receiving a high-potential driving voltage, and supplying the scan pulse to a gate line connected to the pixels;
generating a power control signal based on the digital sensing value; and
Adjusting the high potential driving voltage according to the power control signal; including,
Converting the analog sensing value into a digital sensing value
When the scan pulse is output to the gate line in the form of a multi-pulse, the analog sensing value input through the sensing line is increased in units of the gate line, so that an output value of the analog-to-digital converter overflows to an upper limit value of an input voltage range,
In the step of adjusting the high potential driving voltage,
and adjusting the high potential driving voltage to increase by a predetermined voltage when the overflow is detected in the digital sensing value. According to claim 6,
Generating a power control signal based on the digital sensing value
calculating compensation data for compensating for deterioration of the organic element of each pixel or compensating for threshold voltage deviation and mobility deviation of the driving element from the digital sensing value;
storing the compensation data; and
and generating the power control signal based on the stored compensation data. delete

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