KR102450704B1 - Display device and method of driving the same - Google Patents

Abstract

The present invention relates to a display device for sensing driving characteristics of a pixel and a driving method thereof, wherein a sensing timing signal defining an operation timing of a sensing circuit and a first command code indicating an update period of the sensing timing signal are included in a control data packet It is encoded in and transmitted to the source drive IC. When the first command code is activated, the sensing timing signal is updated with a time period less than one horizontal period.

Description

DISPLAY DEVICE AND METHOD OF DRIVING THE SAME

The present invention relates to a display device for sensing driving characteristics of pixels and a driving method thereof.

The active matrix type organic light emitting diode display includes an organic light emitting diode (hereinafter, referred to as "OLED") that emits light by itself, and has advantages of fast response speed, luminous efficiency, luminance, and viewing angle. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL). When a driving voltage is applied to the anode and cathode electrodes, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the light emitting layer (EML) to form excitons, and as a result, the light emitting layer (EML) is produces visible light.

Each of the pixels of the organic light emitting diode display includes a driving element that controls a current flowing through the OLED. The driving element may be implemented as a thin film transistor (TFT). Electrical characteristics of the driving element such as threshold voltage and mobility are preferably designed to be the same in all pixels, but electrical characteristics of the driving TFT are not uniform due to process conditions and driving environment. As the driving time increases, the driving device receives more stress, and there is a stress difference according to the data voltage. The electrical characteristics of the driving element are affected by stress. Accordingly, the electric characteristics of the driving TFTs change as the driving time elapses.

A compensation method for compensating for a change in driving characteristics of a pixel in an OLED display is divided into an internal compensation method and an external compensation method.

The internal compensation method automatically compensates the threshold voltage deviation between the driving TFTs inside the pixel circuit. Since the current flowing through the OLED must be determined regardless of the threshold voltage of the driving TFT for internal compensation, the configuration of the pixel circuit becomes complicated. The internal compensation method is difficult to compensate for the mobility deviation between the driving TFTs.

The external compensation method senses electrical characteristics (threshold voltage, mobility, etc.) of driving TFTs, and drives each pixel by modulating pixel data of an input image in a compensation circuit external to the display panel based on the sensing result. Compensate for characteristic changes.

The external compensation method senses the voltage or current of a pixel through a sensing signal wire connected to the pixels in the display panel, and digitally converts the sensing result using an analog-to-digital converter (hereinafter referred to as “ADC”). It is converted into data and transmitted to the timing controller. The timing controller compensates for a change in driving characteristics of a pixel by modulating digital video data of an input image based on a sensing result of the pixel.

The timing controller generates sensing timing signals for controlling an operation timing of a sensing circuit for sensing driving characteristics of pixels. These sensing timing signals are transmitted to source drive integrated circuits (hereinafter referred to as "IC"). The source drive ICs control the sensing circuit by receiving it through separate pins necessary for driving the sensing circuit.

In the prior art, wirings must be added between the timing controller and the source drive IC in order to sense the driving characteristics of pixels, and pins must be added to the source drive ICs. In addition, since wiring is added to the source printed circuit board (hereinafter referred to as "PCB") on which the source drive ICs are mounted, the size of the PCB increases and the number of connectors mounted on the PCB increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of sensing driving characteristics of pixels without adding wires and IC pins, and a driving method thereof.

A display device of the present invention includes a display panel including data lines, sensing lines, gate lines, and pixels; a source drive IC including an analog-to-digital converter (ADC) that supplies a data voltage to the data lines and converts a signal received through the sensing lines into digital data to output sensed data; and a timing controller that transmits a control data packet and a video data packet to the source drive IC through a first pair of wires and receives the sensing data through a second pair of wires.

The control data packet includes a sensing timing signal defining an operation timing of the sensing circuit and a first command code indicating an update period of the sensing timing signal. When the first command code is activated, the sensing timing signal is updated with a time period less than one horizontal period.

The sensing circuit includes the sensing lines and the analog-to-digital converter, and a switch element and a sampling circuit disposed between the sensing lines and the analog-to-digital converter.

The method of driving the display device may include encoding a sensing timing signal defining an operation timing of the sensing circuit and a first command code indicating an update period of the sensing timing signal into the control data packet; and updating the sensing timing signal with a time period less than one horizontal period in response to an activation logic value of the first command code.

According to the present invention, the driving characteristics of pixels can be sensed without adding wires and pins of the IC by transmitting a sensing timing signal and a command code indicating an update period thereof to the source drive IC through a wire pair through which the control data packet and the data packet are transmitted. have. Furthermore, the display device of the present invention can precisely sense the driving characteristics of pixels by using the command code to finely control the sensing timing signal for a time of one horizontal period or less.

1 is a diagram illustrating a threshold voltage sensing method of a driving TFT.
2 is a diagram illustrating a method of sensing the mobility of a driving TFT.
3 is a diagram illustrating wiring connections between a timing controller and source drive ICs in a display device according to an exemplary embodiment of the present invention.
4 is a diagram showing a signal format of an EPI interface protocol.
5 is a diagram illustrating data packets and clocks transmitted to source drive ICs.
6 is a diagram illustrating an example of updating a sensing timing signal in units of one horizontal period.
7 is a diagram illustrating an example of updating a sensing timing signal in units of control data packet lengths.
8 is a diagram illustrating an example of updating a sensing timing signal in units of sub control data packet lengths.
9 is a diagram showing a control data processing part on the EPI interface.
10 is a block diagram schematically showing an OLED display device according to an embodiment of the present invention.
FIG. 11 is a diagram illustrating the pixel array shown in FIG. 10 .
12 is a diagram illustrating a real-time sensing method performed within a vertical blank period.
13 is a detailed diagram illustrating a timing controller, a data driving circuit, and a pixel-to-pixel connection structure illustrated in FIG. 10 .
14 to 16 are diagrams for explaining a luminance deviation of a pixel.
17 is a waveform diagram illustrating a sensing timing signal for reducing a luminance deviation between an image image and an original image.
18 is a diagram illustrating an effect of reducing a luminance deviation between an image image and an original image by the method of driving a pixel using the sensing timing signal as in FIG. 17 .
19 is a diagram illustrating a method of reducing a luminance deviation between a sensing target display line and a non-sensing target display line by compensating for a decrease in luminance due to a black image.
20 is a flowchart illustrating a method of compensating for a decrease in luminance due to a black image.
21 is a diagram illustrating an example in which a compensation value for compensating for a decrease in luminance due to a black image varies according to a position of a display line.
22 is a view showing an OLED display device according to another embodiment of the present invention.
23 is a diagram illustrating a connection structure between a pixel of the display panel shown in FIG. 22 and a source drive IC.
24 and 25 are diagrams illustrating a connection structure between the pixel and the sensing unit shown in FIG. 23 and a sensing principle.
26 to 28 are diagrams illustrating a multi-time current sensing method according to an embodiment of the present invention.
29 is a flowchart illustrating a method of compensating for a pixel driving characteristic change during a power-on sequence.
30 is a flowchart illustrating a method of compensating for a pixel driving characteristic change using RT sensing.
31 and 32 are diagrams illustrating an initial non-display period, an effective display period, a vertical blank period, and the like in a power-on sequence.
33 is a diagram illustrating an over-range situation of an ADC that may appear in the multi-time current sensing method of the present invention.
34 is a diagram illustrating an embodiment capable of preventing an over-range phenomenon of an ADC.
35 to 37 are diagrams illustrating other embodiments capable of preventing an over-range phenomenon of an ADC.
38 is a diagram illustrating an example of a method for calculating a driving characteristic deviation of pixels.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

The display device of the present invention will be mainly described with reference to the OLED display device in the following embodiments, but is not limited thereto. For example, the present invention is applicable to any display device that needs to sense the driving characteristics of pixels, for example, a liquid crystal display (LCD), in order to increase the reliability and lifespan of the display device. The display device of the present invention senses driving characteristics of pixels in a sensing mode, and writes input image data to the pixels in the driving mode.

Hereinafter, pixels whose driving characteristics are sensed refer to at least one of a normal pixel disposed in the display area to which pixel data of an input image is written, and a dummy pixel disposed outside the display area. The pixels may include red (Red, R), green (Green, G), and blue (Blue, B) sub-pixels for color implementation. Also, the pixels may further include a white sub-pixel. The pixels may further include one or more of blue-violet (Cyan, C), red-violet (Magenta, M), and yellow (Yellow, Y) sub-pixels. The dummy pixel may be disposed on the display panel to indirectly sense a change in driving characteristics of the normal pixel. The dummy pixel may be manufactured to have the same or similar structure to the normal pixels. The present invention senses one or more pixels or sub-pixels among pixels disposed on a display panel. The driving characteristics of a pixel refer to driving characteristics of elements constituting a pixel, such as a driving element of the pixel and an OLED. For example, the driving characteristics of the pixel mean a change in threshold voltage or mobility of a transistor used as a driving element, change in the threshold voltage of an OLED, or the like. Hereinafter, a transistor used as a driving element will be described as a driving TFT (Thin Film Transistor).

The sensing circuit is driven in response to the sensing timing signal to sense driving characteristics of the pixel. The sensing circuit includes a wiring (sensing line) disposed between the pixels and the ADC, one or more switch elements disposed between the sensing line and the ADC, a sampling circuit, an integrator, and the like. The integrator may be omitted in voltage sensing protection. The configuration of the sensing circuit may be variously changed according to sensing parameters and sensing methods. The sensing circuit may be disposed on the display panel, and at least a portion of the sensing circuit may be embedded in the source drive IC. Since the gate driving circuit outputs a scan signal required for sensing in the sensing mode, it operates as a sensing circuit in the sensing mode.

The sensing timing signal is updated in time units of one horizontal period (1H) or less to maintain the previous logic value or inverted to another logic value at each update timing. The source drive IC may update the sensing timing signal in response to the command code of the control data packet received from the timing controller. On the other hand, in the conventional method, additional control pins are added to the source drive IC 12 in order to make the update cycle of the sensing timing signal faster than one horizontal period, and the sensing timing signal is applied to the control pins. It was necessary.

The display device of the present invention can control the sensing timing precisely by controlling the update time of the sensing timing signal to be short by additionally encoding a command code defining the update period of the sensing time signal in the control data packet transmitted through the EPI interface. can Also, according to the present invention, the sensing timing can be adjusted according to the sensing method and the pixel driving characteristics of the display panel by varying the update time of the sensing timing signal using the command code of the control data.

1 and 2 are diagrams simply showing the principle of a method of sensing driving characteristics of a driving TFT. 1 is a diagram illustrating a threshold voltage sensing method (hereinafter, referred to as a “first sensing method”). FIG. 2 is a diagram illustrating a mobility sensing method (hereinafter, “second sensing method”) of a driving TFT.

Referring to FIG. 1 , in the first sensing method, a sensing data voltage Vdata is supplied to the gate of the driving TFT DT, the driving TFT DT is operated in a source follower method, and then the driving TFT DT ( The source voltage Vs of the DT) is input as the sensing voltage Vsen A, and the threshold voltage Vth of the driving TFT DT is sensed based on the sensing voltage Vsen A. A capacitor Cst for storing the gate-source voltage of the driving TFT is connected between the gate and the source of the driving TFT. The source voltage (Vs) is Vs = Vdata - Vth = Vsen A. The threshold voltage of the driving TFT may be known according to the level of the sensing voltage Vsen A, and an offset value for compensating for the threshold voltage variation of the driving TFT may be determined. An offset value may be added to the data of the input image to compensate for the threshold voltage variation of the driving TFT. In the first sensing method, the threshold voltage of the driving TFT DT must be sensed after the gate-source voltage Vgs of the driving TFT DT operating as a source follower reaches a saturation state. The time required for sensing is relatively long. When the gate-source voltage Vgs of the driving TFT DT is saturated, the drain-source current of the driving TFT DT is zero.

Referring to FIG. 2 , the first sensing method 2 senses the mobility μ of the driving TFT DT. In the second sensing method, a voltage higher than the threshold voltage of the driving TFT DT (Vdata+X, where X is a voltage according to offset value compensation) is applied to the gate of the driving TFT DT to turn the driving TFT DT - is turned on, and the source voltage Vs of the driving TFT DT charged for a predetermined time is input as the sensing voltage VsenB. The mobility of the driving TFT is determined according to the magnitude of the sensing voltage Vsen B, and a gain value for data compensation is obtained through this. The second sensing method senses the mobility of the driving TFT DT when the driving TFT DT operates in the active period. During the active period of the driving TFT DT, the source voltage Vgs increases according to the gate voltage Vg. By multiplying the data of the input image by the gain value, the variation in mobility of the driving TFT may be compensated. In the second sensing method, since mobility is sensed in the active section of the driving TFT, the time required for sensing is short.

Since the first sensing method has a long sensing time, it may be performed until the delayed driving power is turned off timing in response to a power-off command signal received from a user through a user interface. In the second sensing method, since the sensing time is short, between the screen changes after driving power is stably supplied to the display device during the power-on-sequence of the display device, that is, the vertical blank period (VB). ) can be performed in

The sensing method of the present invention is not limited to FIGS. 1 and 2 , and a known method for sensing driving characteristics of pixels may be used. For example, the sensing method of the present invention is disclosed in Korean Patent Application 10-2013-0134256 (2013. 11. 06.), Korean Patent Application 10-2013-0141334 (2013. 11. 20.), Korean Patent Application 10-2013-0149395 (2013. 12. 03.), Korean Patent Application 10-2013-0166678 (2013. 12. 30.), Korean Patent Application 10-2014-0115972 (2014. 09. 02.), Korean Patent Application 10-2015- Voltage of driving TFT proposed in 0101228 (2015. 07. 16.), Korean Patent Application 10-2015-0093654 (2015. 06. 30.), and Korean Patent Application 10-2015-0149284 (2015. 10. 27.) Sensing method, Korean patent application 10-2014-0079255 (2014. 06. 26.), Korean patent application 10-2015-0186683 (2015. 12. 24.), Korean patent application 10-2015-0168424 (2015. 11) 30.) and the current sensing method of a driving TFT proposed in the Republic of Korea Patent Application 10-2014-0086901 (2014. 07. 10.), Korean Patent Application 10-2014-0119357 (2014. 09. 05.), Republic of Korea Patent application 10-2014-0175191 (2014. 12. 08.), Korean patent application 10-2015-0115423 (2015. 08. 17.), Korean patent application 10-2015-0188928 (2015. 12. 29.), The driving characteristic sensing method of OLED proposed in Korean Patent Application No. 10-2015-0117226 (2015. 08. 20.) and the like can be used.

The applicant of the present application has disclosed a signal transmission protocol (hereinafter referred to as "EPI interface protocol") for minimizing the number of wirings between the timing controller and the source drive ICs and stabilizing signal transmission, in Korean Patent Application No. 10-2008-0127458 (2008-12- 15), US Application 12/543,996 (2009-08-19), Korean Patent Application 10-2008-0127456 (2008-12-15), US Application 12/461,652 (2009-08-19), Korean Patent Application 10- 2008-0132466 (2008-12-23), US Application 12/537,341 (2009-08-07), etc. have been proposed.

The EPI interface protocol satisfies the interface regulations of (1) to (3) below.

(1) Connect the transmitting end of the timing controller and the receiving end of the source drive ICs in a point-to-point manner through a pair of data wires.

(2) Do not connect a separate pair of clock wires between the timing controller and the source drive ICs. The timing controller transmits control data and input image pixel data (hereinafter referred to as “video data”) along with a clock signal to the source drive ICs through a pair of data wires.

(3) Each of the source drive ICs has a built-in clock recovery circuit for CDR (Clok and Data Recovery). The timing controller transmits a clock training pattern (or preamble) signal to the source drive ICs so that the output phase and frequency of the clock recovery circuit can be locked. The clock recovery circuit built into the source drive ICs generates an internal clock when the clock training pattern signal and the clock signal input through the data line pair are input.

In the EPI interface protocol, as described above, the timing controller transmits a preamble signal to the source drive ICs before transmitting control data and video data of an input image. The clock recovery circuit of the source drive IC performs a clock training (CT) operation according to the preamble signal to stably fix the phase and frequency of the restored internal clock. After the phase and frequency of the internal clock are stably fixed, a data link through which input image data is transmitted is established between the source drive IC and the timing controller. The timing controller starts transmitting control data and video data to the source drive ICs after the lock signal received from the last source drive IC is received.

When the output phase and frequency of the built-in clock recovery circuit of any one of the source drive ICs are unlocked, the source drive IC transmits the lock signal transmitted to the timing controller to a low logic level. invert to The last source drive IC transmits a lock signal inverted to a low logic level to the timing controller. The timing controller retransmits the preamble signal to the source drive ICs to resume clock training of the source drive ICs when the lock signal is inverted to a low logic level.

The present invention transmits a sensing timing signal for controlling the operation timing of the sensing circuit to the source drive ICs using the EPI interface protocol. Therefore, the present invention transmits the sensing timing signal to the source drive IC without adding wiring on the PCB and adding pins of the source drive IC.

3 is a diagram illustrating wiring connections between a timing controller and source drive ICs in a display device according to an exemplary embodiment of the present invention. 4 is a diagram showing a signal format of an EPI interface protocol.

Referring to FIG. 3 , the display device of the present invention includes a display panel 10 , a timing controller 11 , and a source drive IC 12 . In FIG. 1, the gate driving circuit (or scan driving circuit) is omitted. In FIG. 3 , “TCON” denotes a timing controller, and “SYSTEM” denotes a host system. “SIC1~SIC12” is an example where the number of source drive ICs is 12. The number of source drive ICs is one or more, but is not limited to 12.

The display panel 10 includes a pixel array. The pixel array includes a display area on which an input image is displayed. The pixel array includes pixels arranged in a matrix form by an intersecting structure of data lines and gate lines. The pixel array further includes sensing lines coupled to the pixels. The ADC is connected to the sensing line. Touch sensors for implementing a touch user interface (UI) may be embedded in the pixel array.

The source drive ICs 12 receive data from the timing controller 11 through the EPI interface, and transmit ADC data to the timing controller 11 through a separate ADC data line pair SL. The source drive ICs 12 may update the sensing timing signal in response to the command code of the control data packet received from the timing controller 11 .

The timing controller 11 and the source drive ICs 12 are connected through the EPI line pair DL and also through the ADC data line pair SL. ADC data is digital data obtained as a result of sensing driving characteristics of a pixel. The EPI wiring pair DL connects the timing controller 11 and the source drive ICs 12 1:1 in a point-to-point form.

The timing controller 11 transmits a clock training pattern (or preamble) (CT), a control data packet (CTR) through the EPI line pair (DL) according to the EPI interface protocol as shown in FIG. 4 through the EPI line pair (DL). ), and serially transmits the video data packet DATA to the source drive ICs 12 in sequence. The control data packet CTR may be divided into a plurality of sub control data packets CTR1 to CTR4 as shown in FIGS. 6 to 8 .

In FIG. 4 , “VB” is a vertical blank period, and “HB” is a horizontal blank period. The vertical blank period VB is a blank period between the Nth (N is a positive integer) frame period and the N+1th frame period until the N+1th frame data is input. The horizontal blank period HB is a blank period between the N-th line data and the N+1-th line data. The N-th line data is data to be written in pixels disposed on the N-th horizontal line of the display panel 10 . The N+1th line data is data to be written in pixels disposed on the N+1th horizontal line of the display panel 10 .

Data received through the EPI wiring pair DL includes a clock PCLK. The clock is transmitted to the source drive ICs 12 along with the data of the etc. The length of one data packet may be 24 UIs as shown in FIG. 5, but is not limited thereto. 1 UI is 1 bit transmission time. 24 UI includes a clock (PCLK) of 4 bits and control/video data of 20 bits.

The control data packet transmitted through the EPI wiring pair DL includes source control data for controlling the operation timing of the source drive IC, an option signal, and a sensing timing signal for controlling the operation of the sensing circuit. The option signal includes a gate start pulse (GSP) that controls the shift register start timing of the gate driver circuit (scan driver circuit), a skew option signal of the source drive IC, and a power option signal. It may include various option signals such as an option signal and a command code defining an update period of the sensing timing signal. The gate timing signal for controlling the driving timing of the gate driving circuit (scan driving circuit) may be transmitted to the gate driving circuit through a separate line.

At least a portion of the sensing circuit, for example, a sensing wire, a switch element, and the like may be disposed in the pixel array. The source drive ICs 12 may include a part of a sensing circuit, for example, an ADC, an integrator, or the like. The gate driving circuit operates as a sensing circuit because it generates a scan signal necessary for a sensing operation in the sensing mode, and operates as a scan driving circuit that selects pixels into which data of an input image is written in the driving mode.

The ADC data line pair SL may connect the timing controller 11 to the plurality of source drive ICs 12 in parallel. For example, the source drive ICs 12 connected to the first PCB PCB1 are connected to the timing controller 11 through the first ADC data line pair SL. The source drive ICs 12 connected to the second PCB PCB2 are connected to the timing controller 11 through the second ADC data line pair SL. The source drive ICs 12 transmit ADC output data to the timing controller 11 through the ADC data line pair SL. ADC output data is a sensing result for driving characteristics of pixels.

The timing controller 11 transmits the input image data received from the host system 20 to the source drive ICs 12 to satisfy the EPI interface protocol. The timing controller 11 encodes the sensing timing signal in the control data packet. The sensing timing signal may include a plurality of signals to individually control a plurality of elements. The timing controller 11 may encode update time information of the sensing timing signal in some bits of the control data packet. The update time information reduces the update time of each of the sensing timing signals within one horizontal period (1 HT) or less, and defines the update time. The update time of each of the sensing timing signals may be varied according to the update time information.

One horizontal period (1 HT) is a time required to write data to all pixels arranged in one horizontal line of the display panel 10 . This one horizontal period (1 HT) includes a control data packet CTR serially transmitted to the source drive IC 12 through the EPI wiring pair DL, and a transmission time of one horizontal line of video data packets. According to the present invention, the designer can adjust the update time of each of the sensing timing signals to a desired time within one horizontal time limit (1 HT) by changing the command code defining the update time.

The host system 20 may be any one of a television system, a set-top box, a navigation system, a computer, a DVD player, a Blu-ray player, a home theater system, and a phone system. The host system, including a system on chip (SoC) having a built-in scaler, converts input image data into a format suitable for display on the display panel 100 . The host system transmits timing signals synchronized with the data of the input image to the timing controller 106 . The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK. In addition, the host system 20 executes an application program associated with the coordinate information of the touch input received from the touch sensing unit 110 .

6 to 8 are diagrams illustrating an update period of a sensing timing signal. 6 is a diagram illustrating an example of updating a sensing timing signal in units of one horizontal period. 7 is a diagram illustrating an example of updating a sensing timing signal in units of control data packet lengths. 8 is a diagram illustrating an example of updating a sensing timing signal in units of sub control data packet lengths. When the resolution of the display device is UHD (3840 x 2160), the EPI signal may be transmitted at a clock (PCLK) frequency of 64 MHz. In this case, one horizontal period (1 HT) may be approximately 3.5 μs and the transmission time of one control data packet may be approximately 62.5 ns.

Referring to FIG. 6 , each of the sensing timing signals SENSE may be updated in units of one horizontal period 1H. The code of the sensing timing signal SENSE is encoded in the control data packet CTR. The code of the sensing timing signal SENSE may be updated to a high level when SENSE = H, and updated to a high level when SENSE = L. The code value is not limited thereto. The sensing timing signal SENSE is a signal required to sense the driving characteristic of the pixel. For example, the sensing timing signal SENSE includes signals shown in FIGS. 17, 25, 26, and 28 .

During one horizontal period, one line of video data is transmitted to the source drive IC 12 following the Nth control data packet CTR, and the N+1th control data packet is transmitted when the next horizontal period begins. Accordingly, the sensing timing signal SENSE may be updated in units of one horizontal period (1 HT) due to the video data transmitted between the control data packets CTR. In this method, it is difficult to control the update period of the sensing timing signal SENSE to be less than one horizontal period.

According to the present invention, as shown in FIG. 7 , a first command code (F_CMD_MODE) indicating an update period of a sensing timing signal is added to the control data packet. In addition, the present invention adds second command codes (A_CMD_PERIOD1 to 4) defining the number of dummy data packets for varying the update period.

According to the signal format defined in the existing EPI interface protocol, since the control data packet period is one horizontal period, the update period of the sensing timing signal is also limited to at least one horizontal period. The first command code F_CMD_MODE is a command newly encoded in the control data in order to reduce the update period of the sensing timing signal in the EPI interface to a time period smaller than one horizontal period. When the first command code F_CMD_MODE is activated, the sensing timing signal is updated with a time period smaller than one horizontal period. The second command codes A_CMD_PERIOD1 to 4 indicate the fast sensing mode when the first command code F_CMD_MODE is an active logic value to define the number of dummy data packets for varying the update period of the sensing timing signal. The dummy data packet is sent to the source drive IC following the control data packet. When the first command code F_CMD_MODE is a deactivation logic value, the sensing timing signal is updated with one horizontal period period.

The present invention controls the update period of the sensing timing signal to be within one horizontal period. For example, according to the present invention, the update period of the sensing timing signal may be controlled to be shorter than one horizontal period or to one horizontal period according to the logic value of the first command code F_CMD_MODE. According to the present invention, the driving characteristics of pixels can be precisely sensed because the sensing timing signal can be finely controlled for a time of one horizontal period or less.

Referring to FIG. 7 , the control data packet CTR may be divided into a plurality of sub control data packets CTR1-4. In the fast sensing mode (F_CMD_MODE = H), the timing controller 11 continuously transmits the control data packets CTR1-4 without video data to the source drive IC 12 . Accordingly, in the fast sensing mode (F_CMD_MODE = H), the interval between the neighboring control data packets CTR1 to CTR4 is narrowed, so that the update period of the sensing timing signal SENSE is shorter than one horizontal period (1HT).

When the source drive IC 12 detects the fast sensing mode (F_CMD_MODE = H), it recognizes that the next control data packet is received without video data after the control data packets CTR1-4. Accordingly, the source drive IC 12 updates the sensing timing signal SENSE in units of the length of the control data packets CTR1 to CTR4 when the F_CMD_MODE bit in the control data packet is at a high level (H).

The control data packet unit is the time (62.5 ns) that one control data packet is transmitted. Accordingly, when F_CMD_MODE = H, the sensing timing signal SENSE is updated in units of 62.5 ns, which is much smaller than one horizontal period. 62.5ns is 1 control data packet transmission time during which 4 sub control data packets (CTR1-4) are transmitted. Based on PCLK 64Mhz, the transmission time of 4 clocks (PCLK) is 62.5ns.

The update period of the sensing timing signal SENSE may vary according to the number of dummy data packets DUM1 and DUM2. The dummy data packet length may be set to the same length as the sub control data packet. As with other data packets, a clock (PCLK) bit is encoded between dummy data packets. The dummy data packet makes it possible to vary the update period of the sensing timing signal SENSE without changing the period of the clock PCLK. When the dummy data packet is transmitted following the control data packet, the sensing timing signal is updated with a time period equal to the control data packet length + the dummy data packet length. Accordingly, the present invention can vary the sensing timing signal without changing the clock period defined in the signal format of the EPI interface protocol.

The update period of the sensing timing signal SENSE increases in proportion to the number of dummy data packets DUM1 and DUM2. The control data packets CTR1 to CTR4 may further include a code A_CMD defining the number of dummy data packets when F_CMD_MODE = H. A_CMD is exemplified as 4 bits (A_CMD_PERIOD1 to 4) as shown in FIG. 7, but is not limited thereto. In the example of FIG. 7 , the number of dummy data packets may vary from 0 to 15 according to the logical values of A_CMD_PERIOD1 to 4 .

In another embodiment of the present invention, the control data packet CTR may further include a third command code F_CMD2 instructing to update the sensing timing signal in units of sub control packet lengths. In this embodiment, the sensing timing signal is included in the first sub control packet CTR1 of the control data packet CTR, so that only this information can be updated for sensing. When F_CMD2_MODE = H, the source drive IC detects an update command code received in units of sub-control packet length, that is, 15.6 ns, as shown in FIG. 8, and updates the sensing timing signal according to the command code value. In another embodiment of the present invention, even in this case, the update time of the sensing timing signal SENSE may be varied by adding a dummy data packet using A_CMD.

The dummy data packets DUM1 and DUM2 may be encoded with any value. In the fast sensing mode (F_CMD_MODE = H or F_CMD2_MODE = H), the source drive IC may determine the number of dummy data packets according to the A_CMD code value, and ignores the data of these dummy data packets without restoring them.

The source drive IC 12 may update the sensing timing signal SENSE in units of one horizontal period (1HT) as shown in FIG. 6 in the slow sensing mode. The source drive IC 12 may recognize F_CMD_MODE = L or F_CMD2_MODE = L as the slow sensing mode. In the slow sensing mode, the A_CMD code value is recognized as a meaningless code. The source drive IC 12 ignores A_CMD in the control data packets CTR1-4 in the slow sensing mode. Accordingly, in the slow sensing mode, the update period of the sensing timing signal SENSE is fixed to one horizontal period 1HT.

The timing controller 10 may control the operation timing of the gate driving circuit by supplying the gate timing signal to the gate driving circuit through a separate wire. In this case, since the gate timing signal does not have to follow the EPI interface protocol, its update period can be precisely controlled. For example, the timing controller 10 may update the logic of the scan signal output from the gate driving circuit in units of 0.1 μs using the gate timing control signal (GDC of FIGS. 10 and 22 ).

9 is a diagram showing a control data processing part on the EPI interface. In FIG. 9, components other than the control data processing part in the timing controller 11 and the source drive IC 12 are omitted.

Referring to FIG. 9 , the timing controller 11 includes a scheduler 101 , a data generator 102 , and a transmitter Tx 103 . The source drive IC 12 includes a reception unit Rx 201 , a data separation unit 202 , a CTR data restoration unit 203 , and a video data restoration unit 204 .

The scheduler 101 generates an interrupt signal indicating a sensing mode and a driving mode. The sensing mode is divided into a fast sensing mode and a slow sensing mode as described above. The sensing circuit of the display panel 10 senses the driving characteristics of the pixel according to the sensing timing signal received from the timing controller 11 in the sensing mode. The driving circuit of the display panel 10 writes the data of the input image to the pixels in the driving mode under the control of the timing controller 11 . The driving circuit of the display panel 10 includes a gate driving circuit and a data driving circuit including a source driving IC 12 . In the driving mode, the gate driving circuit may generate a scan pulse synchronized with data of an input image and an EM (Emission) signal defining an emission timing of a pixel.

The data generator 102 generates EPI data in the data format of FIG. 4 that satisfies the EPI interface protocol in the driving mode in response to the interrupt signal. The data generator 102 encodes each code of the driving mode/sensing mode signal indicated by the interrupt signal, the command codes F_CMD and A_CMD of the sensing mode, and the sensing timing signals, into control data. The data generator 102 may generate a clock training pattern CT, a control data packet CTR, and a data packet DATA. The data packet DATA generated in the sensing mode includes preset sensing data regardless of the data of the input image.

The transmission unit 103 of the timing controller 11 converts the data having the clock PCLK into a differential signal pair defined in the EPI interface protocol, and through the EPI wiring pair DL, the source drive IC 12 ) is sent to The receiving unit 201 of the source drive IC 12 supplies the data received through the EPI wiring pair DL to the data separating unit 202 .

The data separation unit 202 recovers the clock PCLK from the received data using the clock recovery circuit and multiplies the clock PCLK to generate a data sampling clock and an ADC clock. The clock recovery circuit may be implemented as any one of a phase locked loop (PLL) and a delayed-locked loop (DLL).

The data separation unit 202 reads the command codes (F_CMD, A_CMD) of the sensing mode restored by the CTR data restoration unit 203 in the sensing mode, and when F_CMD = H, control data packets continuously input at a period defined in A_CMD are transmitted to the CTR data recovery unit 203 . The data separation unit 202 does not transmit the received dummy data to the video data restoration unit 204 when F_CMD = H in the sensing mode. Accordingly, since transmission of the dummy data packet is omitted by the data separation unit 202 , the video data restoration unit 204 does not recognize the dummy data packet in the sensing mode. The data separation unit 202 supplies the control data packet CTR to the CTR data restoration unit 203 in the driving mode, and transmits the video data packet DATA to the video data restoration unit 204 .

The CTR data restoration unit 203 generates signals for controlling the source drive IC and the sensing circuit by sampling and restoring the control data using the data sampling clock. The sensing mode/driving mode signal and the sensing mode command codes F_CMD and A_CMD restored by the CTR data restoration unit 203 are feedback-transmitted to the data separation unit.

The video data restoration unit 204 samples and restores the video data of the input image received from the data separation unit 202 with a data sampling clock, and is transmitted to a de-serializer (not shown) and converted into parallel data. do. The parallel data is transmitted to a digital-to-analog converter (hereinafter referred to as “DAC”), converted into a data voltage, and outputted to the data lines of the display panel 10 .

10 to 37 are diagrams illustrating in detail a sensing method of a display device according to an embodiment of the present invention. It should be noted that the sensing method of the present invention is not limited to FIGS. 10 to 37 .

10 and 11 schematically show an OLED display device according to an embodiment of the present invention. 12 is a diagram illustrating a real-time sensing method (hereinafter, referred to as “RT sensing”) performed within a vertical blank period.

10 and 11 , the OLED display device of the present invention includes a display panel 10 , a timing controller 11 , a data driving circuit, and a gate driving circuit 13 . The data drive circuit includes one or more source drive ICs 12 . The timing controller 11 and the source drive IC 12 are connected through the EPI interface as described above.

A plurality of data lines 14 and a plurality of gate lines 15 cross each other in the display panel 10 , and pixels P are arranged in a matrix form in each crossed area. The data lines 14 include m (m is a positive integer) data lines 14A_1 to 14A_m and m sensing lines 14B_1 to 14B_m. In addition, the gate lines 15 include n (n is a positive integer) first gate lines 15A_1 to 15A_n and n second gate lines 15B_1 to 15B_n.

Each of the pixels P receives a high potential power EVDD and a low potential power EVSS from a power generator (not shown). The pixel P may include an OLED, a driving TFT, first and second switch TFTs, and a storage capacitor (Cst) for external compensation. The TFTs constituting the pixel P may be implemented as p-type or n-type MOSFETs. The semiconductor layer of the TFTs may comprise amorphous silicon or polysilicon or oxide.

The pixel P is in any one of the data lines 14A_1 to 14A_m, in any one of the sensing lines 14B_1 to 14B_m, in any one of the first gate lines 15A_1 to 15A_n, and the second gate connected to any one of lines 15B_1 to 15B_n.

A plurality of horizontal display lines L#1 to L#n for implementing an image through a plurality of pixels P are formed on the display panel 10 . 12 , the display lines L#1 to L#n sequentially charge the image display data voltage according to the image display gate pulse within the image display period DP of one frame, and the display lines The sensing target display line in one frame corresponds to a change in electrical characteristics of the driving TFTs provided in the pixels P according to the sensing gate pulse during the vertical blank period VB except for the image display period DP in one frame. After outputting the voltage Vsen, the data voltage for luminance compensation is charged. The RT sensing method senses driving characteristics of pixels within a vertical blank period VB with respect to a sensing target display line. The sensing target display line may be sequentially selected along the data scan direction by one horizontal display line per frame, but is not limited thereto. For example, the sensing target display line may be selected by one horizontal display line per frame, and other horizontal display lines may be selected non-sequentially in the next frame period.

The gate driving circuit 13 may be implemented as an IC or may be directly formed on the display panel 10 through a gate-driver in panel (GIP) process. The gate driving circuit 13 performs an image on the gate lines 15 connected to the pixels P of the display lines L#1 to L#n during the image display period DP under the control of the timing controller 11 . A gate pulse for display is sequentially supplied, and a gate pulse for sensing is supplied to the gate line 15 connected to the pixels of the display line to be sensed during the vertical blank period. The gate driving circuit 13 receives the gate timing control signal through a separate wiring. Accordingly, since the gate pulse output from the gate driving circuit 13 is not limited by the signal format of the existing EPI interface, its logic value may be changed with an update cycle of about 0.1 μs under the control of the timing controller 11 .

The image display gate pulse is a first image display gate pulse sequentially supplied to the first gate lines 15A_1 to 15A_n, and a second image display gate pulse sequentially supplied to the second gate lines 15B_1 to 15B_n. include pulses. The sensing gate pulse is one of the first sensing gate pulses and the second gate lines 15B_1 to 15B_n supplied to any one of the first gate lines connected to the sensing target display line among the first gate lines 15A_1 to 15A_n. and a second sensing gate pulse supplied to any one of the second gate lines connected to the sensing target display line.

The overall pulse shape and pulse width of the gate pulse for sensing may be different from those of the gate pulse for displaying an image. However, in a predetermined period for charging the data voltage for luminance compensation, the sensing gate pulse is supplied in the same form as the image display gate pulse.

The source drive IC 12 supplies data voltages necessary for driving to the data lines 14A_1 to 14A_m under the control of the timing controller 11 , and supplies a reference voltage to the sensing lines 14B_1 to 14B_m, and performs sensing. The sensing voltage input through the lines 14B_1 to 14B_m is digitally processed and supplied to the timing controller 11 . The data voltage is divided into a data voltage for image display, a data voltage for sensing, a data voltage for black display, and a data voltage for luminance compensation.

The source drive IC 12 supplies a data voltage for image display to the data lines connected to the pixels of the display lines L#1 to L#n in synchronization with the gate pulse for image display, and applies the data voltage for sensing to the gate pulse for sensing. In synchronization, the data voltage for sensing, the data voltage for black display, and the data voltage for luminance compensation are supplied to data lines connected to the pixels of the display line to be sensed. Here, the data voltage for image display indicates a data voltage to which a compensation value for compensating for a change in electrical characteristics of the driving TFT is reflected. The compensation value may include an offset value and a gain value, but is not limited thereto.

The sensing data voltage indicates a data voltage applied to the gate electrode of the driving TFT to turn on the driving TFT of each of the pixels of the sensing target display line. The data voltage for black display indicates a data voltage applied to the gate electrode of the driving TFT to turn off the driving TFT of each of the pixels of the display line to be sensed. The data voltage for luminance compensation is a data voltage applied to restore the luminance of the sensing target display line to the image display level immediately before sensing, and is the image display data applied to the sensing target display line in the image display section DP immediately before sensing. It is selected with a voltage level equal to the voltage.

The timing controller 11 includes a source drive IC 12, a gate based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK, and a data enable signal DE. A timing control signal for controlling the operation timing of the driving circuit 13 and the sensing circuit is generated. The timing controller 11 controls the display lines L#1 to L#n during the image display period DP to compensate for the change in the driving characteristics of the pixel based on the sensing data SD supplied from the source drive IC 12 . . falsify The sensed data is digital data output through the ADC and is a result of sensing the driving characteristics of the pixel. Digital data for image display indicates data converted to data voltage for image display by the source drive IC 12, and digital data for luminance compensation indicates data converted into data voltage for luminance compensation in the source drive IC 12 do.

13 shows a connection structure between the timing controller 11 , the source drive IC 12 , and the pixel P. Referring to FIG. 13 , the first gate pulse SCAN may include a first image display gate pulse during the image display period DP and a first sensing gate pulse during the non-display period VB. In addition, the second gate pulse SEN may include a second image display gate pulse during the image display period DP and a second sensing gate pulse during the non-display period VB.

Referring to FIG. 13 , the pixel P includes an OLED, a driving TFT DT, a storage capacitor Cst, a first switch TFT ST, and a second switch TFT ST2.

The OLED includes an organic compound layer (HIL, HTL, EML, ETL, EIL) disposed between an anode and a cathode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL), but is not limited thereto. The OLED emits light due to excitons generated by holes and electrons moving to the light emitting layer (EML) when a voltage higher than its threshold voltage is applied between the anode and the cathode.

The driving TFT DT includes a gate electrode connected to the first node N1 , a drain electrode connected to the high potential power supply EVDD, and a source electrode connected to the second node N2 . The driving TFT DT controls the driving current Ioled flowing through the OLED according to the gate-source potential difference Vgs. The driving TFT DT is turned on when the gate-source potential difference Vgs is greater than the threshold voltage Vth, and as the gate-source potential difference Vgs increases, the current flowing between the source-drain of the driving TFT DT (Ids) increases. When the source potential of the driving TFT DT becomes larger than the threshold voltage of the OLED, the source-drain current Ids of the driving TFT DT flows through the OLED as the driving current Ioled. As the driving current Ioled increases, the amount of light emitted from the OLED increases, thereby realizing a desired gradation.

The storage capacitor Cst is connected between the first node N1 and the second node N2 .

The first switch TFT ST1 includes a gate electrode connected to the first gate line 15A, a drain electrode connected to the data line 14A, and a source electrode connected to the first node N1. The first switch TFT ST1 is switched in response to the first gate pulse SCAN to apply the data voltage Vdata charged in the data line 14A to the first node N1 .

The gate electrode of the second switch TFT ST2 is connected to the second gate line 15B, the drain electrode of the second switch TFT ST2 is connected to the second node N2, and the second switch TFT ST2 is connected to the second node N2. The source electrode of is connected to the sensing line 14B. The second switch TFT ST2 is switched in response to the second gate pulse SEN, thereby electrically connecting the second node N2 and the sensing line 14B.

The source drive IC 12 is connected to the pixel P through a data line 14A and a sensing line 14B. A sensing capacitor Cx for storing the source voltage of the second node N2 as the sensing voltage Vsen may be formed in the sensing line 14B. The source drive IC 12 includes a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), an initialization switch SW1, a sampling switch SW2, and the like.

The DAC receives digital data, generates a data voltage Vdata for driving, that is, a data voltage for image display, a data voltage for sensing, a data voltage for black display, and a data voltage for luminance compensation, and outputs it to the data line 14A. . The initialization switch SW1 outputs the reference voltage Vref to the sensing line 14B by being switched in response to the initialization control signal SPRE. The sampling switch SW2 is switched in response to the sampling control signal SSAM, so that the source voltage of the driving TFT DT stored in the sensing capacitor Cx of the sensing line 14B for a predetermined time is used as the sensing voltage Vsen as the ADC. supply to The ADC converts the analog sensing voltage stored in the sensing capacitor Cx into a digital value Vsen and supplies it to the timing controller 11 . The sensing capacitor Cx may be created as a separate capacitor or implemented as a parasitic capacitor connected to the reference line 14B.

14 and 15 are diagrams for explaining a luminance deviation of a pixel.

In FIG. 14 , a driving mode for realizing the original image of the input image signal in the image display period (DP) and the electrical characteristic change of the driving TFT in the vertical blank period (VB) are sensed and the same luminance as the original image is implemented A sensing mode for this is shown. In the driving mode, the pixels P may be driven in an initialization period for image display (①), a programming period for image display (②), and a light emitting period for image display (③). In the sensing mode, the pixels P have an initialization period T1 for sensing, a programming period T2 for sensing, a sensing period T3, a sampling period T4, an initialization period T5 for luminance compensation, and a luminance compensation period. It may be driven in the programming period T6 and the light emission period T7 for luminance compensation.

The image display gate pulses SCAN(D), SEN(D) corresponding to the image display initialization period (①) and the image display programming period (②) are the luminance compensation initialization period (T5) and the luminance compensation programming period (2). Compared to the luminance compensation gate pulses SCAN(S) and SEN(S) corresponding to the period T6, the pulse shape is different. This difference causes a variation in the filling amount of the pixels P as shown in FIG. 15 . Even if the luminance compensation programming period T6 is set to be the same as the image display programming period ②, the first luminance compensation gate pulse SCAN(S) is the first image display gate pulse SCAN(D). Since the saturation period is wider than , the charge amount C1 of the luminance compensation data voltage Vdata_RCV charged to the gate electrode of the driving TFT during the luminance compensation programming period T6 is determined during the image display programming period (②). It may be greater than the charge amount C2 of the image display data voltage Vdata_NDR charged in the gate electrode of the driving TFT during the operation. Accordingly, as shown in FIG. 16 , when the pixel P is supplied with the data voltage Vdata_RCV for luminance compensation with a relatively large amount of charge, the luminance may be increased.

When the luminance is different between the original image and the image image, a luminance deviation occurs between the sensing target display line in which RT sensing is performed and the non-sensing target display line in which RT sensing is not performed during the same image frame. The degree of the luminance deviation varies depending on the display position of the sensing target display line. As the sensing target display line is positioned closer to the lower end of the display panel in which the display duty of the original image becomes longer, the degree of the luminance deviation increases.

In the present invention, in order to minimize the luminance deviation between the sensing target display line and the non-sensing target display line, as shown in FIG. 17 , the gate pulse for image display for charging the image display data voltage and the luminance for charging the luminance compensation data voltage A method of supplying gate pulses for compensation in the same form is proposed.

Referring to FIG. 17 , the luminance compensation gate pulses SCAN(S) and SEN(S) corresponding to the luminance compensation initialization period T5 and the luminance compensation programming period T6 include the image display initialization period ( Compared with the image display gate pulses SCAN(D) and SEN(D) corresponding to ①) and the image display programming period (②), the pulse shape is similar.

The saturation holding width of the first luminance compensation gate pulse SCAN(S) becomes equal to that of the first image display gate pulse SCAN(D), so that during the luminance compensation programming period T6, the driving TFT The charge amount (C1) of the data voltage (Vdata_RCV) for luminance compensation charged in the gate electrode of becomes the same as Accordingly, as shown in FIG. 18 , the original image by the data voltage Vdata_RCV for luminance compensation can implement the same luminance as the image image by the data voltage Vdata_NDR for image display. As a result, during the same image frame, the luminance deviation between the sensing target display line and the non-sensing target display line is reduced.

14 and 17, the operation of the pixel P in each of the driving mode and the sensing mode will be described in detail as follows.

14 and 17 , in the driving mode, the pixel P is driven by dividing it into an initialization period for image display (①), a programming period for image display (②), and a light emission period for image display (③).

In the image display initialization period (①), the first switch TFT ST1 is turned off according to the first image display gate pulse SCAN(D) of the off level, and the second image display gate pulse of the on level is turned off. As the second switch TFT ST2 is turned on according to SEN(D), the source potential of the driving TFT DT is initialized to a preset reference voltage Vref.

In the image display programming period (②), the first and second switch TFTs ST1 and ST2 are turned on according to the first and second image display gate pulses SCAN(D) and SEN(D) of the on level. By being turned on, the image display data voltage Vdata_NDR is applied to the gate electrode of the driving TFT DT in a state in which the source potential of the driving TFT DT is initialized, and the driving TFT DT is turned on.

In the light emission period for image display (③), the first and second switch TFTs ST1 and ST2 are turned on according to the first and second image display gate pulses SCAN(D) and SEN(D) of the off level. turns off At this time, the gate-source voltage of the driving TFT DT programmed in the image display programming period (②) is stored in the storage capacitor Cst. Due to the gate-source potential difference of the driving TFT DT held in the storage capacitor Cst, a driving current for image display flows in the driving TFT DT, and this driving current causes the OLED to emit light to display the original image. do.

In the sensing mode, the pixel P has a sensing initialization period T1, a sensing programming period T2, a sensing period T3, a sampling period T4, a luminance compensation initialization period T5, and a luminance compensation programming period. (T6), and a light emission period for luminance compensation (T7).

In the sensing initialization period T1, the first switch TFT ST1 is turned off according to the off-level first sensing gate pulse SCAN(S), and the on-level second sensing gate pulse SEN(S) S)), as the second switch TFT ST2 is turned on, the source potential of the driving TFT DT is primarily initialized to the preset first reference voltage Vref. Here, the first reference voltage Vref may be selected as a voltage lower than the reference voltage Vref applied in the initialization period (①) for image display in order to increase the accuracy of sensing. For example, when the reference voltage Vref applied in the initialization period (①) for image display is 2 to 3V, the first reference voltage Vref may be selected to be 0V.

In the sensing programming period T2, the first and second switch TFTs ST1 and ST2 are turned on according to the on-level first and second sensing gate pulses SCAN(S) and SEN(S). , in a state in which the source potential of the driving TFT DT is initially initialized, the sensing data voltage Vdata_SDR is applied to the gate electrode of the driving TFT DT, and the driving TFT DT is set to a turned-on state.

In the sensing period T3, the first switch TFT ST1 is turned off according to the first sensing gate pulse SCAN(S) of the off level, and the second sensing gate pulse SEN(S) of the on level is turned off. ), as the second switch TFT ST2 is turned on, a source-drain current flows in the driving TFT DT, and the source voltage of the driving TFT increased by this current is sensed and stored.

In the sampling period T4, the first and second switch TFTs ST1 and ST2 are turned on according to the first and second sensing gate pulses SCAN(S) and SEN(S) of the on level, so that the The sensed source voltage is sampled and detected as a change in electrical characteristics of the driving TFT (DT). During the sampling period T4 , a data voltage for black display capable of turning off the driving TFT DT is applied to the gate electrode of the driving TFT DT to prevent unnecessary OLED emission during sampling.

In a predetermined period for charging the luminance compensation data voltage, the first sensing gate pulse SCAN(S) during the luminance compensation initialization period T5 so that the sensing gate pulse is supplied in the same form as the image display gate pulse. ) is maintained at the off level, and the second sensing gate pulse SEN(S) is maintained at the off level and then changed to the on level.

In the initialization period T5 for luminance compensation, the first switch TFT ST1 is turned off according to the first sensing gate pulse SCAN(S) of the off level, and the second sensing gate pulse SEN of the on level is turned off. As the second switch TFT ST2 is turned on according to (S)), the source potential of the driving TFT DT is secondarily initialized to the second reference voltage Vref. Here, the second reference voltage Vref may be selected at the same voltage level as the reference voltage Vref applied in the initialization period for image display (①), that is, 2 to 3V. This is to equalize the source potential of the driving TFT DT in the initialization periods ? and T5.

In the luminance compensation programming period T6, the first and second switch TFTs ST1 and ST2 are turned on according to the on-level first and second sensing gate pulses SCAN(S) and SEN(S). As a result, the data voltage Vdata_RCV for luminance compensation is applied to the gate electrode of the driving TFT DT while the source potential of the driving TFT DT is in the secondary initialized state. TFT (DT) is turned on.

In the light emission period T7 for luminance compensation, the first and second switch TFTs ST1 and ST2 are turned on according to the first and second image display gate pulses SCAN(S) and SEN(S) of the off level. turns off At this time, the gate-source voltage of the driving TFT DT programmed in the luminance compensation programming period T6 is stored in the storage capacitor Cst. Due to the gate-source potential difference of the driving TFT (DT) held in the storage capacitor (Cst), a driving current for luminance compensation flows through the driving TFT (DT), and this driving current causes the OLED to emit light to display the original luminance image. do.

The present invention modulates digital data for luminance compensation to be applied to the sensing target display line during the vertical blank period (VB) in the timing controller 11 to compensate for the luminance deviation between the sensing target display line and other display lines as shown in FIG. Compensates for luminance reduction due to black images.

19 and 20 , the timing controller 11 writes the data of the input image to the pixels P of all display lines to display the original image within the image display period DP of one frame period. (S10). The timing controller 11 starts RT sensing when the image display driving is completed and the vertical blank period VB of the frame period starts (S20) (S30).

The timing controller 11 counts the frame period to determine which frame period the current frame period is, and determines a sensing target display line to be RT-sensed in the blank period VB of the current frame period according to the determination result. (S40)

The timing controller 11 derives a compensation value for compensating for a decrease in luminance due to the black image, but derives a compensation value suitable for the position of the sensing target display line. To this end, the timing controller 11 may inquire a compensation value of a look-up table in which compensation values for each position are stored in advance, or obtain compensation values for each position directly from a function expression (S50).

The timing controller 11 may further reduce the difference in luminance between the sensing target display line and the non-sensing target display line by outputting the luminance compensation data compensated based on the compensation value.

The compensation value may vary depending on the position of the sensing target display line. For example, as shown in FIG. 21 , the compensation value is set to a smaller value from the first display line #1 of the display panel having the earliest data writing order to the last display line #1080 having the latest data writing order as shown in FIG. 21 . can be

22 and 23 show an OLED display device according to another embodiment of the present invention.

22 and 23 , the OLED display device of the present invention includes a display panel 10 , a timing controller 11 , a data driving circuit, a gate driving circuit 13 , and a memory 16 . The data drive circuit includes one or more source drive ICs 12 .

In the display panel 10 , a plurality of data lines 14A and sensing lines 14B and gate lines 15 cross each other, and pixels P are arranged in a matrix form at each intersection area.

Each pixel P is connected to any one of the data lines 14A, to any one of the sensing lines 14B, and to any one of the gate lines 15 . Each pixel P is electrically connected to the data line 14A in response to a gate pulse input through the gate line 15 , receives a data voltage from the data line 14A, and receives a data voltage through the sensing line 14B. Outputs a sensing signal.

Each of the pixels P receives a high potential driving voltage EVDD and a low potential driving voltage EVSS from a power generator (not shown). The pixel P of the present invention may include an OLED, a driving TFT, first and second switch TFTs, and a storage capacitor for external compensation. The TFTs constituting the pixel P may be implemented as p-type or n-type. In addition, the semiconductor layer of the TFTs constituting the pixel P may include amorphous silicon, polysilicon, or oxide.

Each of the pixels P operates in a driving mode for image implementation and a sensing mode for sensing driving characteristics of the pixel P. The sensing mode may be performed for a predetermined time prior to the driving mode during the power-on sequence, or may be performed during the vertical blank period VB within the driving mode.

The source drive IC 12 may include a DAC connected to the data line 14A, and a sensing unit and ADC connected to the sensing line 14B. The DAC converts the data RGB of the input image into a data voltage under the control of the timing controller 11 in the driving mode and supplies it to the data lines 14A. The DAC generates a sensing data voltage under the control of the timing controller 11 in the sensing mode and supplies it to the data lines 14A.

The sensing unit includes a current integrator CI input through the sensing line 14B and a sampling circuit SH for sampling and holding an output of the current integrator CI. The ADC of the source drive IC 12 sequentially converts the outputs of the sampling circuits SH into digital data and transmits them to the timing controller 11 as sensing data SD.

The gate driving circuit 13 generates a gate pulse for image display in the driving mode under the control of the timing controller 11, and shifts the gate pulse. The gate driving circuit 13 generates a sensing gate pulse in the sensing mode and shifts the gate pulse. The on-pulse period of the sensing gate pulse may be wider than that of the image display gate pulse. One (FIG. 26) or a plurality (FIG. 28) of the on-pulse period of the sensing gate pulse may be included in one line sensing on-time. Here, the 1-line sensing on time is a time required to simultaneously sense pixels of one horizontal line.

The timing controller 11 is configured to control operation timings of the source drive IC 12 , the gate driving circuit 13 , and the sensing circuit based on the timing signals Vsync, Hsync, MCLK, DE synchronized with the input image signal. Generates a timing control signal. The timing controller 11 separates the driving mode and the sensing mode, and controls the source drive IC 12 , the gate driving circuit 13 and the sensing circuit according to each driving.

The timing controller 11 may transmit digital data corresponding to the data voltage for sensing to the source drive IC 12 in the sensing mode. The timing controller 11 applies the sensing data SD transmitted from the source drive IC 12 in the sensing mode to a preset compensation algorithm to derive the threshold voltage deviation (ㅿVth) and the mobility deviation (ㅿK). Then, compensation data capable of compensating for the deviations is stored in the memory 16 . The timing controller 11 modulates digital video data (RGB) of an input image by using the compensation data stored in the memory 16 in the driving mode, and then transmits the modulated digital video data (RGB) to the source drive IC 12 .

24 is a diagram illustrating a connection structure between the pixel shown in FIG. 23 and a sensing unit. 25 shows a one-time sensing waveform for each pixel within a 1-line sensing on time defined as an on-pulse period of the sensing gate pulse SCAN.

Referring to FIG. 24 , the pixel P includes an OLED, a driving TFT DT, a storage capacitor Cst, a first switch TFT ST1 , and a second switch TFT ST2 .

The current integrator CI is connected to the sensing line 14B and receives the inverting input terminal (-) that receives the source-drain current Ids of the driving TFT from the sensing line 14B, and receives the reference voltage Vpre. An operational amplifier (AMP) including an inverting input terminal (+) and an output terminal for outputting an integral value (Vsen), and an integrating capacitor (Cfb) connected between an inverting input terminal (-) and an output terminal of the operational amplifier (AMP) and a first switch SW1 connected to both ends of the integrating capacitor Cfb.

The sampling circuit SH includes a second switch SW2 switched according to a sampling signal SAM signal, a third switch SW3 switched according to a holding signal HOLD signal, and a second switch SW2 and a third A holding capacitor (Ch) having one end connected between the switches SW3 and the other end connected to the ground voltage source (GND) is included.

Referring to FIG. 25 , the sensing mode is divided into an initialization period Tinit, a sensing period Tsen, and a sampling period Tsam.

Due to the turn-on of the first switch SW1 in the initialization period Tinit, the operational amplifier AMP operates as a unit gain buffer having a gain of 1. In the initialization period Tinit, the input terminals (+, -) and output terminals of the operational amplifier AMP, the sensing line 14B, and the second node N2 are all initialized to the reference voltage Vpre.

During the initialization period Tinit, the sensing data voltage Vdata-SEN is applied to the first node N1 through the DAC of the source drive IC 12 . Accordingly, a source-drain current Ids corresponding to the potential difference {(Vdata-SEN)-Vpre} between the first node N1 and the second node N2 flows through the driving TFT DT to be stabilized. Since the amplifier AMP continues to operate as a unit gain buffer during the initialization period Tinit, the potential of the output terminal is maintained at the reference voltage Vpre.

Due to the turn-off of the first switch SW1 in the sensing period Tsen, the operational amplifier AMP operates as a current integrator CI to integrate the source-drain current Ids flowing through the driving TFT DT. In the sensing period Tsen, the potential difference between both ends of the integrating capacitor Cfb due to the current Ids flowing into the inverting input terminal (-) of the operational amplifier AMP increases as the sensing time elapses, that is, the accumulated current value Ids. increases as the

Due to the characteristics of the operational amplifier (AMP), the inverting input terminal (-) and the non-inverting input terminal (+) are short circuited through the virtual ground and the potential difference between each other becomes 0, so in the sensing period (Tsen) The potential of the inverting input terminal (-) is maintained at the reference voltage Vpre regardless of the increase in the potential difference of the integrating capacitor Cfb. At this time, the output terminal potential of the operational amplifier AMP is lowered in response to the potential difference between the both ends of the integrating capacitor Cfb. According to this principle, the current Ids flowing in through the sensing line 14B in the sensing period Tsen is generated as an integral value Vsen, which is a voltage value, through the integrating capacitor Cfb. Since the falling slope of the current integrator output value Vout increases as the amount of current Ids flowing through the sensing line 14B increases, the magnitude of the integral value Vsen decreases as the amount of current Ids increases. In the sensing period Tsen, the integral value Vsen is stored in the holding capacitor Ch via the second switch SW2.

When the third switch SW3 is turned on in the sampling period Tsam, the integral value Vsen stored in the holding capacitor Ch is input to the ADC via the third switch SW3. The integral value Vsen is converted into digital data in the ADC, converted into sensing data SD, and transmitted to the timing controller 11 . The sensing data SD is used as basic data for determining compensation of the threshold voltage deviation ㅿVth and the mobility deviation ㅿK of the driving TFT in the timing controller 11 .

In the memory of the timing controller 11, the capacitance of the integrating capacitor Cfb, the reference voltage value Vpre, and the sensing time value Tsen are previously stored as digital codes. Accordingly, the timing controller 11 controls the source-drain current (Ids=Cfb*ㅿV/ㅿt) flowing from the sensing data SD, which is the digital code for the integral value Vsen, to the driving TFT DT, where ㅿ V=Vpre-Vsen, ㅿt=Tsen) can be calculated.

The timing controller 11 applies the source-drain current Ids flowing through the driving TFT DT to the compensation algorithm to compensate the deviation values (threshold voltage deviation (ㅿVth) and mobility deviation (ㅿK)) and deviation Compensation data (Vth+ㅿVth, K+ㅿK) for The compensation algorithm may be implemented as a lookup table or calculation logic.

Since the capacitor Cfb of the integrator CI has a capacity as small as a few hundredths compared to the parasitic capacitance of the sensing line 14B, the time required to input the current Ids to a senseable level is shorter than the voltage sensing method. much shorter In the voltage sensing method, the sensing time is prolonged because the voltage is sampled as the sensing voltage after the source voltage of the driving TFT is saturated when sensing the threshold voltage. In contrast, the current sensing method integrates the source-drain current of the driving TFT within a short time through current sensing during threshold voltage and mobility sensing, and samples the integrated value, thereby greatly reducing the sensing time.

Unlike the parasitic capacitance of the sensing line, the integrator capacitor Cfb of the current integrator CI does not change a stored value according to the load of the display panel 10 , and it is easy to calibrate, so that an accurate sensed value can be obtained.

The current sensing method of the present invention has the advantage of enabling low current sensing and high-speed sensing compared to the conventional voltage sensing method. Since low current and high-speed sensing are possible, in the current sensing method of the present invention, it is also possible to sense each pixel multiple times within one line sensing on time in order to improve sensing performance.

26 to 28 are diagrams illustrating a multi-time current sensing method according to an embodiment of the present invention. 26 to 28 , the multi-time current sensing method is exemplified as two-time current sensing, but is not limited thereto. For example, the multi-time current sensing method of the present invention may be applied to current sensing two or more times for each pixel.

26 and 27 , sensing and sampling operations may be performed twice for the same pixel within one line sensing on time. One line sensing on time is a first sensing & sampling period S&S1 for integrating a first source-drain current value Ids1 with a sensing data voltage Vdata-SEN of a first level LV1, and a second level A second sensing & sampling period S&S2 is included in which the second source-drain current value Ids2 is integrated with the sensing data voltage Vdata-SEN of LV2. An initialization period Tinit may be allocated prior to the first and second sensing and sampling periods S&S1 and S&S2, respectively.

The data voltage Vdata-SEN for sensing of the first level LV1 and the second level LV2 may be set to the same voltage, but it is more advantageous to set different voltages to improve sensing performance. The first level LV1 has a size corresponding to the low gray level current value Ids1 in a predetermined range in the entire gray level section, and the second level LV2 corresponds to the high gray level current value Ids2 in the predetermined range in the entire gray level section. A corresponding size may be input, and vice versa. The first level LV1 may be input as a voltage level corresponding to any one of a low gray level current value in a predetermined range and a high gray level current value in a predetermined range in the entire gray level section, and the second level LV2 may be input to the entire gray level range. In the section, a voltage level corresponding to the other one of the low gray level current value of the predetermined range and the high gray level current value of the predetermined range may be input.

In the first initialization period Tinit, the same operations as in the initialization period Tinit of FIG. 25 , that is, an initialization operation and an operation of stabilizing the source-drain current Ids are primarily performed.

In the first sensing & sampling period S&S1, the same operation as in the sensing period Tsen and the sampling period Tsam of FIG. 25 , the first source-drain current value Ids1 is sensed and first integrated, and the first integral value After sampling (Vsen1) and processing the first ADC, the first digital sensed value is stored in the internal latch.

In the second initialization period Tinit, the same operation as the initialization period Tinit of FIG. 25 , that is, an initialization operation and a source-drain current Ids stabilization operation are performed secondarily.

In the second sensing and sampling period S&S2, the same operation as in the sensing period Tsen and the sampling period Tsam of FIG. 25 , the second source-drain current value Ids2 is sensed and the second integration is performed, and the second integral value After sampling (Vsen2) and processing the second ADC, the second digital sensed value is stored in the internal latch.

The sizes of the sensing periods Tsen included in the first and second sensing and sampling periods S&S1 and S&S2 are the same.

The timing controller 11 calculates first and second source-drain current values Ids1 and Ids2 based on the first and second digital sensed values, and uses calculation logic or a look-up table to obtain desired deviation values ㅿ Vth,ㅿK) can be derived.

When using the calculation logic, the timing controller 11 applies the calculated first and second source-drain current values Ids1 and Ids2 to the OLED current equation (Ids=K(Vgs-Vth)2), respectively, to obtain two current equations. Ids1=K(Vgs1-Vth)2, Ids2=K(Vgs2-Vth)2), calculate the threshold voltage (Vth) of the corresponding pixel first by calculating these equations, and then convert the value to the OLED current The mobility (K) can be calculated by substituting any one of the formulas. In addition, desired deviation values ㅿVth and ㅿK may be derived by comparing the calculated threshold voltage Vth and mobility K with pre-stored reference values.

When using the lookup table, the timing controller 11 compares the calculated first and second source-drain current values Ids1 and Ids2 with a reference current value stored in advance to calculate first and second current deviation values, and the first and using the second current deviation value as a read address, respectively, a threshold voltage deviation value (Vth) and a mobility deviation value (ㅿK) may be derived.

It is known that the source-drain current of the driving TFT is greatly affected by a change in threshold voltage in a low grayscale section and is greatly affected by a change in mobility in a high grayscale section. Accordingly, the timing controller 11 may derive a threshold voltage deviation value (ㅿVth) based on a relatively small first source-drain current value (Ids1) as shown in FIG. 38 using a lookup table, A mobility deviation value ㅿK may be derived based on the relatively large second source-drain current value Ids2.

The timing controller 11 controls the operation of the gate driving circuit 13 to apply the same stabilization conditions to the first and second sensing & sampling periods S&S1 and S&S2, and as shown in FIG. 28, the sensing gate pulse ( The gate pulse SCAN for sensing may be generated in a multi-pulse form so that two or more on-pulse sections of the SCAN are included in one line sensing on-time. The stabilization condition may include a gate delay, a data charging delay, and the like.

29 is a flowchart illustrating a method of compensating for a pixel driving characteristic change during a power-on sequence. 30 is a flowchart illustrating a method of compensating for a pixel driving characteristic change using RT sensing. 31 and 32 are diagrams illustrating an initial non-display period, an effective display period, a vertical blank period, and the like in a power-on sequence.

The compensation method shown in FIG. 29 includes a sensing mode performed on all pixels during a predetermined initial non-display period X1 during a power-on sequence. The compensation method illustrated in FIG. 30 compensates for changes in driving characteristics of pixels based on a result of real-time sensing of pixels disposed on one horizontal display line in the vertical blank period BP during the driving mode period.

The initial non-display period X1 may be defined as a non-display period from the time when the driving power enable signal PON is applied until several tens to hundreds of frames have elapsed, as shown in FIG. 31 . The vertical blank period BP may be defined as a non-display period between valid display periods AP during which an image is displayed as shown in FIGS. 31 and 32 . The data enable signal DE is not generated in the initial non-display period X1 and the vertical blank period BP, and accordingly, the data voltage for image display is not supplied to the pixel in the vertical blank period BP.

Referring to FIG. 29 , in the present invention, the previous threshold voltage (Vth) and mobility (K) of pixels are read from the memory during the power-on sequence. Next, according to the present invention, sensing data SD is obtained from each of the pixels by applying the above-described multi-time current sensing method to the selected horizontal display line. Next, the present invention compares the current threshold voltage (Vth) and mobility (K) obtained from the sensing data (SD) in each pixel with the previous threshold voltage (Vth) and mobility (K) read from the memory, respectively. After calculating the threshold voltage deviation value (ㅿVth) and the mobility deviation value (ㅿK), compensation data (Vth+ㅿVth, K+ㅿK) capable of compensating for the deviation values is stored in the memory.

Referring to FIG. 30 , the previous threshold voltage Vth(n−1) and mobility K(n−1) of the pixels stored during the previous compensation in the vertical blank period BP are read from the memory. Next, according to the present invention, a plurality of sensing data SD is obtained by applying a multi-time current sensing method to each of the pixels of the selected horizontal display line. Next, according to the present invention, the current threshold voltage (Vth) and mobility (K) obtained from the sensing data SD are read from the memory, and the previous threshold voltage (Vth(n-1)) and mobility (K(n-1)) )) to calculate the threshold voltage deviation value (ㅿVth) and the mobility deviation value (ㅿK), and then store compensation data (Vth+ㅿVth, K+ㅿK) capable of compensating for the deviation values in the memory. do.

33 is a diagram illustrating an over-range situation of an ADC that may appear in the multi-time current sensing method of the present invention.

ADC is a special encoder that converts analog signals into digital signal data. ADC has a fixed input voltage range, that is, a sensing range. The voltage range of the ADC may vary depending on the resolution of the AD conversion, but it may be normally set from Evref (ADC reference voltage) to Evref+3V. Here, the resolution of AD conversion indicates a bit value capable of converting an analog input voltage into a digital value. When the analog signal input to the ADC is out of the input range of the ADC, the output value of the ADC may underflow to the lower limit of the input voltage range or overflow to the upper limit of the input voltage range.

According to a multi-time current sensing method, analog integral values Vsen of different sizes are generated through a sensing process of at least two times for each pixel according to the present invention. When the current value Ids flowing into the current integrator CI is large, the magnitude of the integral value Vsen becomes small. Conversely, when the current value Ids flowing into the current integrator CI is small, the output integral The magnitude of the value Vsen increases. Accordingly, some of the integral values Vsen of various magnitudes may be out of the input range of the ADC.

In the example of FIG. 33 , when the input range of the ADC is 2V to 5V, the first integral value Vsen1 according to the first current value Ids1 is 4V, and the second current value Ids2 greater than the first current value Ids1 ), the second integral value Vsen2 is 1.5V.

Referring to FIG. 33 , 4V, which is the first integral value (Vsen1), belongs to the input range (2V to 5V) of the ADC and can be output normally, whereas the second integral value (Vsen2), 1.5V, is the input range of the ADC. Since it is out of (2V to 5V), it can be output as underflow to the lower limit (2V) of the input voltage range (2V to 5V) close to it.

If the ADC over-range occurs, the sensing accuracy decreases. Accordingly, an additional method capable of preventing the over-range phenomenon of the ADC is required.

34 is a diagram illustrating an embodiment capable of preventing an over-range phenomenon of an ADC.

Referring to FIG. 34 , in the first sensing & sampling period S&S1 in which the falling slope of the output value Vout of the current integrator CI is relatively large, in the first sensing & sampling period S&S1, the falling slope of the current integrator CI output value Vout is relatively small. 2 Compared to the sensing & sampling period (S&S2), the possibility of underflow is high.

The present invention reduces the first integral value (Vsen1) at 2V by reducing the sensing period (Tsen1) in the first sensing & sampling period (S&S1) compared to the sensing period (Tsen2) in the second sensing & sampling period (S&S2). By raising it to 3.5V, the first integral value (Vsen1) can be corrected to satisfy the ADC's input voltage range (2V~5V).

35 to 37 are diagrams illustrating other embodiments capable of preventing an over-range phenomenon of an ADC.

35 , the display device of the present invention may further include a capacitance control unit 22 for adjusting the capacitance of the integrating capacitor Cfb included in the current integrator CI under the control of the timing controller 11. . The integrating capacitor Cfb includes a plurality of capacitors Cfb1, Cfb2, and Cfb3 connected in parallel to the inverting input terminal (-) of the operational amplifier AMP, and the other ends of the capacitors Cfb1, Cfb2, Cfb3 are connected to each other. It may be connected to the output terminal of the operational amplifier (AMP) through other capacitance adjustment switches (S1, S2, S3). The combined capacitance of the integrating capacitor Cfb is determined according to the number of turned-on capacitance adjustment switches S1, S2, and S3.

The timing controller 11 analyzes the sensed data SD, and controls the operation of the capacitance controller 22 according to the ratio of the digital sensed values SD equal to the lower limit value and the upper limit value of the ADC to generate an appropriate switching control signal. . The capacitance adjustment switches S1 , S2 , and S3 are turned on/off according to a switching control signal input from the capacitance control unit 22 . As the combined capacitance of the integrating capacitor Cfb increases, the falling slope with respect to the output value Vout of the current integrator unit CI becomes smaller. Conversely, as the combined capacitance of the integrating capacitor Cfb decreases, the output value ( Vout), the falling slope increases.

The timing controller 11 controls the number of the capacitance adjustment switches S1, S2, and S3 that are turned on through the capacitance control unit 22, so that the output value of the ADC is the lower limit of the input voltage range. The combined capacitance of the integrating capacitor Cfb is increased, and conversely, when the output value of the ADC overflows to the upper limit of the input voltage range, the combined capacitance of the integrating capacitor Cfb may be decreased.

By controlling the combined capacitance of the integrating capacitor Cfb, the ADC over-range situation can be prevented as shown in FIG. 36 . As shown in FIG. 36 , in the second sensing & sampling period in which the falling slope of the current integrator (CI) output value Vout is relatively large, the first sensing voltage (Vsen2) of the current integrator (CI) output value Vout is relatively small. & Compared to the sampling period, there is a high possibility of underflow.

The present invention doubles the combined capacitance (3pF) of the integrating capacitor (Cfb) operating during the second sensing & sampling period compared to the combined capacitance (1.5pF) of the integrating capacitor (Cfb) operating during the first sensing & sampling period By increasing, the first integral value Vsen1 can be adjusted upward from 2V to 4V, so that the second integral value Vsen2 can be corrected to satisfy the ADC's input voltage range (2V to 5V).

The display device of the present invention may further include a programmable voltage adjustment IC 24 for adjusting the ADC reference voltage Evref under the control of the timing controller 11 .

The timing controller 11 analyzes the digital sensed values SD, and controls the operation of the programmable voltage adjustment IC 24 according to the ratio of the digital sensed values SD equal to the lower limit value and the upper limit value of the ADC to control the ADC reference voltage. (Evref) can be adjusted.

An example in which an over-range situation of the ADC is prevented by adjusting the ADC reference voltage Evref is shown in FIG. 37 . In the multi-time current sensing method of the present invention, in the second sensing & sampling period in which the falling slope of the current integrator (CI) output value Vout is relatively large as shown in FIG. 37, the falling slope of the current integrator (CI) output value Vout Compared to the first sensing & sampling period in which is relatively small, it is highly likely that the second integral value Vsen2 underflows.

The present invention maintains the ADC reference voltage (Evref) at the time of digital processing of 4V, which is the first integral value (Vsen1), at the original 2V, and the ADC reference voltage when digital processing of the second integral value (Vsen2) of 2V (Evref) downgrades from the original 2V to 0V. By this downward adjustment, the 2nd integral value (Vsen2) of 2V satisfies the ADC's input voltage range (0V~3V) sufficiently.

The present invention controls the update period of the sensing timing signal using the command code defined in the control data packet of the EPI interface. This method can be applied not only to sensing the driving characteristics of the pixel but also to sensing the temperature compensation of the pixel.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: source drive IC 20: host system
101: scheduler 102: data generating unit
103: transmitter 201: receiver
202: data separation unit 203: CTR data restoration unit
204: video data restoration unit

Claims (15)

a display panel including data lines, sensing lines, gate lines, and pixels;
a source drive IC including an analog-to-digital converter (ADC) that supplies a data voltage to the data lines and converts a signal received through the sensing lines into digital data to output sensed data; and
a timing controller for transmitting a control data packet and a video data packet to the source drive IC through a first pair of wires and receiving the sensing data through a second pair of wires;
The control data packet includes a sensing timing signal defining an operation timing of the sensing circuit, and a first command code indicating an update period of the sensing timing signal,
the sensing timing signal is updated with a time period less than one horizontal period when the first command code is activated;
and the sensing circuit includes the sensing lines and the analog-to-digital converter, and a switch element and a sampling circuit disposed between the sensing lines and the analog-to-digital converter. delete The method of claim 1,
When the first command code is activated, the sensing timing signal is updated in units of the length of the control data packet. 4. The method of claim 3,
The sensing timing signal is updated with the one horizontal period period when the first command code is a deactivation logic value. 5. The method of claim 4,
The control data packet includes a second command code for varying an update period of the sensing timing signal by defining the number of dummy data packets transmitted subsequent to the control data packet. 6. The method of claim 5,
The control data packet is divided into a plurality of sub control data packets,
The control data packet further includes a third command code indicating an update period of the timing signal in units of the sub control data packets. 6. The method of claim 5,
The timing controller is
a scheduler generating an interrupt signal indicating a driving mode for displaying an input image on the pixels and a sensing mode for sensing driving characteristics of the pixels;
a data transmitter configured to generate the control data packet and the video data packet in a data format transmitted through the first pair of wires in the driving mode;
and a transmitter configured to transmit a signal in which a clock is embedded in data of the control data packet and the video data packet to the source drive IC through the first pair of wires. 8. The method of claim 7,
The source drive IC is
a receiver configured to receive a signal in which a clock is embedded in data of the control data packet and the video data packet through the first pair of wires;
a data separator for recovering the clock from the signal from the receiver using a clock recovery circuit and multiplying the clock to generate a data sampling clock and an ADC clock;
a control data restoration unit that restores control data from the data separation unit and generates a signal for controlling the source drive IC and the sensing circuit; and
and a video data restoration unit that restores video data that restores the video data received from the data separation unit. 9. The method of claim 8,
The control data restoration unit transmits the first and second command codes to the data separation unit,
In the sensing mode, when the first command code is an activation logic value, transmission of the dummy data packets is omitted by the data separation unit, so that the video data restoration unit does not recognize the dummy data packets. 10. The method of claim 9,
The data separating unit transmits the video data packet to the video data restoration unit in the driving mode. A source drive IC including an analog-to-digital converter (ADC) transmits a control data packet and a video data packet to the source drive IC through a first pair of wires, and receives the sensing data output from the analog-to-digital converter through a second pair of wires A method of driving a display device, comprising: a timing controller for receiving, and a sensing circuit including sensing lines of a display panel and the analog-to-digital converter, and a switching element and a sampling circuit disposed between the sensing lines and the analog-to-digital converter in,
encoding a sensing timing signal defining an operation timing of the sensing circuit and a first command code indicating an update period of the sensing timing signal into the control data packet; and
and updating the sensing timing signal with a time period smaller than one horizontal period in response to an activation logic value of the first command code. delete 12. The method of claim 11,
and updating the sensing timing signal in units of a length of the control data packet in response to an activation logic value of the first command code. 14. The method of claim 13,
and updating the sensing timing signal with the one horizontal period period in response to a deactivation logic value of the first command code. 15. The method of claim 14,
and encoding, in the control data packet, a second command code for varying an update period of the sensing timing signal by defining the number of dummy data packets transmitted subsequent to the control data packet.

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