KR101549343B1 - Organic Light Emitting Display For Sensing Electrical Characteristics Of Driving Element - Google Patents

Abstract

According to the present invention, an organic light emitting display device comprises: a display panel having an OLED and a driving TFT which controls the amount of light emitted by the OLED, wherein a plurality of pixels connected to sensing lines are formed; a sensing block having a plurality of current integrator units sensing current information of the pixels via a plurality of sensing channels connected to the sensing lines; and a calibration block connected to each current information input terminal of the current integrator units in a predetermined calibration mode. The calibration block comprises: a reference current source generating a reference current for calibration to correct a characteristic variation of the current integrator units; and a plurality of switches for calibration connected between the reference current source and the current integrator units.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light emitting display, and more particularly to an organic light emitting display capable of sensing electrical characteristics of a driving element.

The active matrix type organic light emitting display device includes an organic light emitting diode (OLED) which emits light by itself, has a high response speed, and has a high luminous efficiency, luminance, and viewing angle.

The organic light emitting diode (OLED) includes an anode electrode, a cathode electrode, and organic compound layers (HIL, HTL, EML, ETL, EIL) formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light.

The OLED display arranges pixels each including an OLED in a matrix form and adjusts the brightness of the pixels according to the gradation of the video data. Each of the pixels includes a driving TFT (Thin Film Transistor) that controls a driving current flowing in the OLED according to a voltage (Vgs) applied between the gate electrode and the source electrode of the pixel. The electrical characteristics of the driving TFT, such as threshold voltage, mobility, etc., deteriorate as the driving time elapses, and a deviation may occur for each pixel. If the electrical characteristics of the driving TFT are different for each pixel, the luminance between the pixels for the same video data is different, so that the desired image is difficult to implement.

An internal compensation method and an external compensation method are known in order to compensate an electric characteristic deviation of a driving TFT. The internal compensation scheme automatically compensates the threshold voltage deviation between the driving TFTs within the pixel circuit. In order to perform the internal compensation, the driving current flowing through the OLED must be determined regardless of the threshold voltage of the driving TFT, so that the configuration of the pixel circuit is very complicated. Moreover, the internal compensation scheme is unsuitable for compensating the mobility deviation between the driving TFTs.

The external compensation method measures sensing voltages corresponding to the electrical characteristics (threshold voltage, mobility) of the driving TFTs and compensates the electrical characteristic deviation by modulating video data in an external circuit based on the sensing voltages. In recent years, research on such external compensation schemes has been actively conducted.

In the conventional external compensation method, the data driving circuit directly receives a sensing voltage from each pixel through a sensing line, converts the sensing voltage into a digital sensing value, and transmits the digital sensing value to the timing controller. The timing controller modulates the digital video data based on the digital sensing value to compensate for the electrical characteristic deviation of the driving TFT.

Since the driving TFT is a current device, its electrical characteristics are represented by the magnitude of the current Ids flowing between the drain and the source in accordance with the constant gate-source voltage Vgs. However, the data driving circuit of the conventional external compensation method senses the voltage value corresponding to the current Ids, rather than directly sensing the current Ids flowing in the driving TFT to sense the electric characteristics of the driving TFT.

For example, in the external compensation scheme proposed by the applicant of the present application, such as the application No. 10-2013-0134256, No. 10-2013-0149395, etc., the driving TFT is operated in a source follower manner, (The source voltage of the driving TFT) stored in the line capacitor (parasitic capacitor) of the data driver circuit. When the source electrode potential of the driving TFT DT operated in the source follower mode is set to saturation state (that is, the driving TFT DT) becomes zero) is sensed. In this external compensation method, in order to compensate for the mobility deviation of the driving TFT, a linear state value before the source electrode potential of the driving TFT DT operated in the source follower method reaches the saturation state is set to Sensing.

Such conventional external compensation methods have the following problems.

First, in the conventional external compensation method, a current flowing in a driving TFT is changed to a source voltage by using a parasitic capacitor of a sensing line, and then the source voltage is sensed. At this time, the parasitic capacitance of the sensing line is relatively large, and the magnitude of the parasitic capacitance may fluctuate depending on the display load of the display panel. The parasitic capacitance can not be calibrated because it is not maintained at a constant level and varies with various environmental factors. If the magnitude of the parasitic capacitance accumulated in the current is different between the sensing lines, it is difficult to obtain an accurate sensing value.

Secondly, since the conventional external compensation method takes a voltage sensing method, it takes a long time until the source voltage of the driving TFT is sucked, and the time required for obtaining the sensing value is very long. In particular, if the parasitic capacitance of the sensing line is large, it takes a long time to draw the current to a voltage level that can be sensed. Such a problem becomes more serious in low tone sensing than in high tone sensing as in Fig.

Accordingly, it is an object of the present invention to provide an organic light emitting display capable of reducing sensing time and reliability of sensing and compensation in sensing electrical characteristics of a driving device.

In order to achieve the above object, an organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel including an OLED, a driving TFT for controlling an amount of light emitted from the OLED, and a plurality of pixels connected to sensing lines; A sensing block including a plurality of current integrator units sensing current information of the pixels through a plurality of sensing channels connected to the sensing lines; And a calibration block connected to each current information input of the current integrator units in a preset calibration mode; The calibration block includes a reference current source for generating a calibration reference current for correcting a characteristic deviation of the current integrator units and a plurality of calibration switches connected between the reference current source and the current integrator units.

The calibration switches are sequentially turned on to sequentially supply the calibration reference current to the current integrator units.

Each of the current integrator units includes an amplifier including an inverting input terminal connected to one of the sensing lines through a sensing channel, a non-inverting input terminal receiving a reference voltage for initialization, and an output terminal outputting an integral value, An integrating capacitor connected between the inverting input terminal and the output terminal of the amplifier, and a first switch connected to both ends of the integrating capacitor; Wherein the capacitor includes a plurality of capacitors connected in parallel to the inverting input terminal of the amplifier, the other terminal of each of the capacitors being connected to an output terminal of the amplifier through different capacitance adjustment switches, , And is turned on / off according to the switching control signal based on the integral value.

Each of the current integrator units operating in one of a current sensing mode for sensing current information of the pixels according to a sensing mode signal and a voltage sensing mode for sensing voltage information of the pixels; In the voltage sensing mode, the amplifier and the integral capacitor are deactivated and the first switch is turned on.

The present invention realizes a low current and a high-speed sensing through a current sensing method using an electric current integrator in sensing electric characteristic deviations of a driving element, thereby greatly reducing sensing time. Furthermore, the present invention can greatly enhance the reliability of sensing and compensation by providing a calibration block to compensate for the offset deviation between the current integrator units, and furthermore, the offset deviation between the ADCs.

1 is a view showing that a time required for obtaining a sensing value in the conventional voltage sensing method becomes very long at a low gray level.
FIG. 2 is a block diagram showing major components for implementing the current sensing of the present invention; FIG.
3 is a view illustrating an organic light emitting display according to an embodiment of the present invention.
FIG. 4 is a view showing the configuration of a pixel array formed in the display panel of FIG. 3 and a data driver IC for implementing a current sensing method; FIG.
5 is a diagram further illustrating a calibration block coupled to a sensing block in a data driver IC for implementing a current sensing scheme.
6 is a view showing a detailed configuration of a pixel configuration to which the current sensing method of the present invention is applied and a calibration unit, a current integrator unit, and a sample and hold unit sequentially connected to the pixel.
FIG. 7 shows waveforms of drive signals applied to FIG. 6 for current sensing and integration values according to a current sensing result; FIG.
8 is a diagram showing switching timings for sequentially calibrating current integrator units constituting a sensing block;
9 is a diagram for explaining a calibration operation for a current integrator.
FIG. 10 is a diagram illustrating a method for preventing an over-range phenomenon of an ADC. FIG.
FIG. 11 is a diagram illustrating implementation of voltage sensing using a sensing block for implementing the current sensing method of the present invention. FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2 to 10. FIG.

FIG. 2 is a block diagram illustrating the main components for implementing the current sensing of the present invention.

Referring to FIG. 2, the present invention includes a sensing block, a sample & hold block, and an ADC block necessary for current sensing in a data driver IC (SDIC), and senses current information from pixels of a display panel. The sensing block includes a plurality of current integrator units to integrate the current information input from the display panel. The integral value (expressed as a voltage value) output from the sensing block is passed to the ADC block via the sample and hold block. The ADC block converts the analog integral to a digital sensing value and sends it to the timing controller. The timing controller derives the compensation data for compensating for the deviation of the threshold voltage and the mobility deviation based on the digital sensing value, modulates the image data for image implementation using the compensation data, and transmits the data to the data driver IC (SDIC) do. The modulated image data is converted from the data driver IC (SDIC) to a data voltage for image implementation and then applied to the display panel.

In order to correct the characteristic deviation between the current integrator units constituting the sensing block, a calibration block is built in the data driver IC (SDIC), and a calibration reference Current can be sequentially supplied.

The present invention realizes low current and high-speed sensing through the current sensing method using the current integrator, and the sensing time can be greatly reduced. Further, according to the present invention, the characteristic deviation between the current integrators or the characteristic deviation between the ADCs can be corrected through the calibration block, and the accuracy of the compensation can be greatly increased. Hereinafter, the technical idea of the present invention will be described in detail by way of examples.

FIG. 3 illustrates an organic light emitting display according to an embodiment of the present invention. FIG. 4 shows a pixel array formed on the display panel of FIG. 3 and a data driver IC for implementing a current sensing method. 5 shows a calibration block connected to the sensing block in the data driver IC for realizing the current sensing method.

3 to 5, an OLED display according to an exemplary embodiment of the present invention includes a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, 16).

A plurality of data lines and sensing lines 14A and 14B and a plurality of gate lines 15 are intersected with each other in the display panel 10 and pixels P are arranged in a matrix form in each of the intersection areas.

Each pixel P is connected to any one of the data lines 14A, to one of the sensing lines 14B, and to one of the gate lines 15. Each pixel P is electrically connected to the data voltage supply line 14A in response to the gate pulse input through the gate line 15 to receive the data voltage from the data voltage supply line 14A and to receive the data voltage from the sensing line 14B.

Each of the pixels P is supplied with a high potential drive voltage EVDD and a low potential drive voltage EVSS from a power supply not shown. The pixel P of the present invention may include an OLED, a driver TFT, first and second switch TFTs, and a storage capacitor for external compensation. The TFTs constituting the pixel P may be implemented as a p-type or an n-type. In addition, the semiconductor layer of the TFTs constituting the pixel P may include amorphous silicon, polysilicon, or an oxide.

Each of the pixels P may operate differently at the time of normal driving for image implementation and at the sensing operation for sensing value acquisition. The sensing drive may be performed for a predetermined time prior to the normal drive, or may be performed in the vertical blank periods during the normal drive.

The normal driving can be performed by one operation of the data driving circuit 12 and the gate driving circuit 13 under the control of the timing controller 11. [ The sensing operation may be performed by different operations of the data driving circuit 12 and the gate driving circuit 13 under the control of the timing controller 11. [ The operation of deriving the compensation data for the deviation compensation based on the sensing result and the operation of modulating the digital video data using the compensation data are performed in the timing controller 11. [

The data driving circuit 12 includes at least one data driver IC (Integrated Circuit) (SDIC). The data driver IC SDIC includes a plurality of digital-to-analog converters (DACs) connected to each data line 14A and a sensing block connected to the sensing lines 14B through the sensing channels CH1 to CHn, And a sample and hold block and an ADC connected to the output of the sample and hold block. The data driver IC (SDIC) further includes a calibration block.

The DAC of the data driver IC (SDIC) converts digital video data (RGB) into image data voltage for data conversion in accordance with the data timing control signal (DDC) applied from the timing controller 11 during normal driving, . On the other hand, the DAC of the data driver IC (SDIC) generates a sensing data voltage in accordance with the data timing control signal (DDC) applied from the timing controller 11 during sensing driving and supplies the sensing data voltage to the data lines 14A.

The sensing block of the data driver IC (SDIC) includes a plurality of current integrator units (CI) that integrate the current information of the pixel (P), and the sample and hold block samples and amplifies the output of the current integrator units Hold units (SH) for holding the sample and hold units (SH). The ADC of the data driver IC (SDIC) digitally processes the outputs of the sample and hold units (SH) sequentially and transmits them to the timing controller (11).

The calibration block of the data driver IC (SDIC) includes a reference current source IREF for generating a calibration reference current Iref for correcting a characteristic deviation of the current integrator units CI, And a plurality of calibration switches S1 to Sn connected between the plurality of switches CI.

The calibration block further includes a plurality of selectors MUX. Each of the selectors MUX includes current information of pixels input from the sensing channels CH1 to CHn and current information of the pixels input from the calibration switches S1 to Sn And the reference current Iref for calibration is selectively inputted to the corresponding current integrator unit CI. Each of the selectors MUX may be operated according to the mode control signal MODE. The mode control signal MODE may have a first logic value in a preset calibration mode and a second logic value in a preset sensing drive mode. Each of the selectors MUX outputs the reference current Iref for calibration in response to the mode control signal MODE of the first logic value and generates the current information IX of the pixel in response to the mode control signal MODE of the second logic value, Can be output.

On the other hand, the reference current source IREF may be located outside the data driver IC (SDIC). The reference current source IREF may be implemented in a plurality of units so as to be independently connected to each of the current integrator units CI through the selection units MUX. However, when embedded in the data driver IC (SDIC), the reference current source IREF may be implemented as one as shown in FIG. 5 and connected in common to the current integrator units CI through the selectors MUX .

The gate drive circuit 13 generates an image display gate pulse on the basis of the gate control signal GDC during normal driving and then outputs the image display gate pulse to the gate lines (L # 1, L # 2, 15). The gate driving circuit 13 generates sensing gate pulses based on the gate control signal GDC during the sensing operation and then outputs the gate lines 15 (L # 1, L # 2, ...) ). The sensing gate pulse may have a larger on-pulse interval than the gate pulse for image display. The on-pulse section of the sensing gate pulse corresponds to the one-line sensing on-time. Here, the one-line sensing on-time is a period in which pixels of the one-row pixel line (L # 1, L # 2, This means scan time to be devoted to.

The timing controller 11 controls the operation of the data driving circuit 12 based on timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a dot clock signal DCLK and a data enable signal DE A data control signal DDC for controlling the timing and a gate control signal GDC for controlling the operation timing of the gate drive circuit 13 are generated. The timing controller 11 distinguishes between normal driving and sensing driving based on a predetermined reference signal (driving power enable signal, vertical synchronizing signal, data enable signal, etc.), and generates a data control signal DDC and a gate And generates the control signal GDC. In addition, the timing controller 11 can generate additional control signals (RST, SAM, HOLD, and the like in Fig. 6) necessary for sensing driving.

The timing controller 11 can transmit the digital data corresponding to the sensing data voltage to the data driving circuit 12 during sensing driving. The timing controller 11 applies the digital sensing value SD transmitted from the data driving circuit 12 at the time of sensing operation to a previously stored compensation algorithm to derive a threshold voltage deviation Vth and a mobility deviation K And stores the compensation data in the memory 16 that can compensate for the deviations.

The timing controller 11 modulates the digital video data RGB for image implementation with reference to the compensation data stored in the memory 16 during normal driving, and then transmits the digital video data RGB to the data driving circuit 12.

FIG. 6 shows a pixel configuration to which the current sensing method of the present invention is applied, and a detailed configuration of a calibration unit, a current integrator unit, and a sample and hold unit sequentially connected to the pixel. 7 shows waveforms of the driving signals applied to FIG. 6 for current sensing and integration values according to the current sensing result.

6 and 7 are merely examples for helping to understand the driving of the current sensing method. The pixel structure to which the current sensing of the present invention is applied and the driving timing thereof can be variously modified, so that the technical idea of the present invention is not limited to this embodiment.

6, the pixel PIX of the present invention includes an OLED, a driving TFT (Thin Film Transistor) DT, a storage capacitor Cst, a first switch TFT ST1, and a second switch TFT ST2 .

The OLED includes an anode electrode connected to the second node N2, a cathode electrode connected to the input terminal of the low potential driving voltage (EVSS), and an organic compound layer positioned between the anode electrode and the cathode electrode. The driving TFT DT controls the amount of current input to the OLED according to the gate-source voltage Vgs. The driving TFT DT has a gate electrode connected to the first node N1, a drain electrode connected to the input terminal of the high potential driving voltage EVDD, and a source electrode connected to the second node N2. The storage capacitor Cst is connected between the first node N1 and the second node N2. The first switch TFT ST1 applies the data voltage Vdata on the data voltage supply line 14A to the first node N1 in response to the gate pulse SCAN. The first switch TFT (ST1) has a gate electrode connected to the gate line 15, a drain electrode connected to the data voltage supply line 14A, and a source electrode connected to the first node N1. The second switch TFT (ST2) switches the current flow between the second node (N2) and the sensing line (14B) in response to the gate pulse (SCAN). The second switch TFT ST2 has a gate electrode connected to the second gate line 15D, a drain electrode connected to the sensing line 14B, and a source electrode connected to the second node N2.

The current integrator unit CI included in the sensing block of the present invention includes an inverting input terminal (-) connected to the sensing line 14B and receiving the source-drain current Ids of the driving TFT from the sensing line 14B, An amplifier AMP including a noninverting input terminal (+) for receiving a reference voltage Vpre and an output terminal for outputting an integral value Vsen and an amplifier AMP between an inverting input terminal (-) and an output terminal of the amplifier AMP A connected integrated capacitor Cfb, and a first switch SW1 connected to both ends of the integrating capacitor Cfb.

The sample-and-hold unit SH included in the sample-and-hold block of the present invention includes a second switch SW2 switched in accordance with a sampling signal SAM signal, a third switch SW2 switched in accordance with a holding signal HOLD signal, And a holding capacitor Ch having one end connected between the second switch SW2 and the third switch SW3 and the other end connected to the ground voltage source GND.

Referring to FIG. 7, the sensing operation includes an initialization period (Tinit), a sensing period (Tsen), and a sampling period (Tsam).

Due to the turn-on of the first switch SW1 in the initialization period Tinit, the amplifier AMP operates as a unit gain buffer having a gain of 1. Both the input terminals (+, -) and the output terminal of the amplifier AMP, the sensing line 14B, and the second node N2 are initialized to the reference voltage Vpre in the initialization period Tinit.

During the initialization period Tinit, the sensing data voltage Vdata-SEN is applied to the first node N1 through the DAC of the data driver IC (SDIC). The source-drain current Ids corresponding to the potential difference {(Vdata-SEN) -Vpre} between the first node N1 and the second node N2 flows and stabilizes in the driving TFT DT. However, during the initialization period (Tinit), since the amplifier AMP continues to operate as a unit gain buffer, the potential of the output terminal is maintained at the reference voltage Vpre.

The amplifier AMP operates as the current integrator unit CI due to the turn-off of the first switch SW1 in the sensing period Tsen and integrates the source-drain current Ids flowing in the driving TFT DT. The potential difference across the integrating capacitor Cfb due to the current Ids flowing into the inverting input terminal (-) of the amplifier AMP in the sensing period Tsen becomes smaller as the sensing time elapses, that is, the accumulated current value Ids The larger it increases. Since the inverting input terminal (-) and the non-inverting input terminal (+) are short-circuited through the virtual ground and the potential difference between them is zero, the inverting input terminal (- -) is maintained at the reference voltage Vpre regardless of the increase in the potential difference of the integrating capacitor Cfb. Instead, the output terminal potential of the amplifier AMP is lowered corresponding to the potential difference between both ends of the integral capacitor Cfb. With this principle, the current Ids flowing through the sensing line 14B in the sensing period Tsen changes into the integral value Vsen, which is the voltage value, through the integrating capacitor Cfb. The descending slope of the output value Vout of the current integrator unit CI increases as the amount of current Ids flowing through the sensing line 14B increases, so that the magnitude of the integral value Vsen becomes smaller as the current amount Ids is larger . In the sensing period Tsen, the integration value Vsen is stored in the holding capacitor Ch via the second switch SW2.

When the third switch SW3 is turned on in the sampling period Tsam, the integration value Vsen stored in the holding capacitor Ch is input to the ADC via the third switch SW3. The integral value (Vsen) is converted to a digital sensing value (SD) in the ADC and then transmitted to the timing controller (11). The digital sensing value SD is used by the timing controller 11 to derive the threshold voltage deviation (Vth) and the mobility deviation (K) of the driving TFT. In the timing controller 11, the capacitance of the integral capacitor Cfb, the reference voltage value Vpre, and the sensing time value Tsen are stored in advance in a digital code. Therefore, the timing controller 11 compares the source-drain current (Ids = Cfb * Vv / tt) flowing from the digital sensing value SD, which is a digital code for the integral value Vsen to the driving TFT DT, ㅿ V = Vpre-Vsen, ㅿ t = Tsen) can be calculated. The timing controller 11 applies the source-to-drain current Ids flowing in the driving TFT DT to the compensation algorithm to calculate deviation values (threshold voltage deviation (Vth) and mobility deviation (K)) and deviation compensation (Vth + [Delta] Vth, K + [Delta] K). The compensation algorithm may be implemented as a look-up table or computational logic.

The capacitance of the integral capacitor Cfb included in the current integrator unit CI of the present invention is smaller than the parasitic capacitance existing in the sensing line by a factor of a hundred so that the current sensing method of the present invention can detect the integrated value Vsen ) Is significantly shortened in comparison with the conventional voltage sensing method. Further, in the conventional voltage sensing method, since the source voltage of the driving TFT is sampled at the sensing voltage after the source voltage of the driving TFT is sampled at the threshold voltage sensing, the sensing time becomes very long. In the current sensing method of the present invention, The source-drain current of the driving TFT can be integrated within a short time through the current sensing during the sensing, and the integrated value can be sampled, so that the sensing time can be greatly shortened.

Unlike the parasitic capacitor of the sensing line, the integrated capacitor (Cfb) included in the current integrator unit (CI) of the present invention does not change the stored value according to the display load and is easy to calibrate, .

As described above, the current sensing method of the present invention is advantageous in that low current sensing is possible and high-speed sensing is possible as compared with the conventional voltage sensing method. The current sensing method of the present invention is also capable of sensing a plurality of times for each of the pixels within one line sensing on time in order to enhance the sensing performance.

8 shows switching timings for sequentially calibrating the current integrator units constituting the sensing block. 9 shows a calibration operation for one current integrator.

The calibration block of the present invention includes a reference current source IREF for generating a calibration reference current Iref for correcting a characteristic deviation of the current integrator units CI, a reference current source IREF and current integrator units CI, And a plurality of switches (S1 to Sn) for calibration connected to each other.

In the current-assisted calibration mode, the reference current Iref for calibration must be sufficiently inputted to each sensing block at a constant level. To this end, the calibration switches S1 to Sn can not be turned on at the same time and are sequentially turned on so that the calibration reference current Iref is sufficiently drawn into each sensing block. The reference current Iref for calibration is sequentially supplied to the current integrator units of the sensing block, sequentially integrated in the current integrator units, and then input to the ADC via the sample and hold block. The ADC digitally processes a plurality of integration values for calibration to generate digital sensing values for calibration, and then transmits the digital sensing values to the timing controller 11. The timing controller 11 calculates an offset deviation between the current integrator units based on the digital sensing values for calibration and further an offset deviation between the ADCs belonging to different data driver ICs (SDIC), and compensates the calculated deviation values And derives additional compensation data that can be used. When the timing controller 11 modulates the image data using the compensation data based on the current information of the pixels, it can reflect the derived additional compensation data to enhance the reliability of the compensation.

FIG. 10 shows a method for preventing an over-range phenomenon of the ADC.

The ADC is a special encoder that converts analog signals into digital signal form data. The ADC has its input voltage range, or sensing range. The voltage range of the ADC can be set to Evref (ADC reference voltage) to Evref + 3V, though it may vary depending on the resolution of the AD conversion. Here, the resolution of the AD conversion indicates a bit value capable of converting the analog input voltage into a digital value. When the analog signal input to the ADC is out of the input range of the ADC, the output of the ADC may underflow to the lower limit of the input voltage range or overflow to the upper limit of the input voltage range.

This over-range of the ADC reduces the accuracy of the sensing. In order to prevent the overrange phenomenon of the ADC, the present invention proposes a method of adjusting the integrated capacitance value of the current integrator unit (CI) according to an integral value (i.e., a digital sensing value).

To this end, the present invention may further include a capacitance control unit 22 for adjusting the capacitance of the integral capacitor Cfb included in the current integrator unit CI under the control of the timing controller 11 as shown in Fig. The integrating capacitor Cfb includes a plurality of capacitors Cfb1, Cfb2, and Cfb3 connected in parallel to the inverting input terminal (-) of the amplifier AMP, and the other ends of the capacitors Cfb1, Cfb2, And can be connected to the output terminal of the amplifier AMP through the capacitance adjustment switches S1, S2, and S3. The combined capacitance of the integral capacitor Cfb is determined by the number of switches S1, S2, and S3 that are turned on.

The timing controller 11 analyzes the digital sensing values SD and controls the operation of the capacitance control unit 22 according to the ratio of the digital sensing values SD equal to the lower limit value and the upper limit value of the ADC, . The capacitance adjustment switches (S1, S2, S3) are turned on / off in accordance with the switching control signal input from the capacitance control section (22). The larger the combined capacitance of the integrating capacitor Cfb is, the smaller the falling slope with respect to the output value Vout of the current integrator unit CI becomes, and conversely the smaller the combined capacitance of the integrating capacitor Cfb is, Vout) becomes large.

Accordingly, the timing controller 11 controls the number of the capacitance adjustment switches S1, S2, and S3 that are turned on through the capacitance control unit 22 so that the output value of the ADC underflows to the lower limit value of the input voltage range The combined capacitance of the integral capacitor Cfb may be increased and the combined capacitance of the integral capacitor Cfb may be decreased if the output value of the ADC overflows to the upper limit of the input voltage range.

FIG. 11 illustrates voltage sensing using a sensing block for implementing the current sensing method of the present invention.

The current integrator units (CI) included in the sensing block of the present invention have been proposed for a display panel 10 capable of current sensing. However, it is preferable that the current integrator unit (CI) of the present invention is designed so that it can be extended to a conventional display panel for voltage sensing so that compatibility between the data driver IC (SDIC) and the display panel 10 is enhanced.

To this end, each of the current integrator units CI includes a current sensing mode for sensing the current information of the pixels P in accordance with a sensing mode signal (not shown) input from the timing controller 11, P of the voltage sensing mode for sensing the voltage information. Here, the current information is the source-to-drain current Ids of the drive TFT DT described above, and the voltage information is the source side voltage Vs (the voltage across N2 in FIG. 6, VN2) of the drive TFT DT .

The operation of the current integrator unit (CI) in the current sensing mode is as described with reference to FIGS. On the other hand, in the voltage sensing mode, the amplifier AMP and the integral capacitor Cfb of the current integrator unit CI are stopped and the first switch of the current integrator unit CI can be turned on. To this end, in the voltage sensing mode, the driving power supply Vcc of the amplifier AMP can be cut off, and the connection between the integrating capacitor Cfb and the output terminal of the amplifier AMP can be released.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit
14: Data lines 15: Gate lines
16: Memory 22: Capacitance controller
CI: Current integrator unit SH: Sample & hold unit

Claims (5)

An OLED, and a driving TFT for controlling an amount of light emitted from the OLED, the display panel having a plurality of pixels connected to the sensing lines;
A sensing block including a plurality of current integrator units sensing current information of the pixels through a plurality of sensing channels connected to the sensing lines; And
And a calibration block connected to the current integrator units in a preset calibration mode;
Wherein the calibration block comprises:
A reference current source for generating a calibration reference current for correcting a characteristic deviation of the current integrator units,
And a plurality of calibration switches connected between the reference current source and the current integrator units. The method according to claim 1,
Wherein the calibration switches are sequentially turned on to sequentially supply the calibration reference current to the current integrator units. The method according to claim 1,
Each of the current integrator units comprising:
An amplifier including an inverting input terminal connected to one of the sensing lines through a sensing channel and connected to the calibration block, a non-inverting input terminal receiving a reference voltage for initialization, and an output terminal outputting an integral value,
An integral capacitor connected between the inverting input terminal and the output terminal of the amplifier,
And a first switch connected to both ends of the integrating capacitor;
Wherein the integrated capacitor includes a plurality of capacitors connected in parallel to the inverting input terminal of the amplifier and the other end of each of the capacitors is connected to an output terminal of the amplifier through different capacitance adjusting switches. Display device. The method of claim 3,
Each of the current integrator units comprising:
A current sensing mode for sensing current information of the pixels according to a sensing mode signal and a voltage sensing mode for sensing voltage information of the pixels;
In the voltage sensing mode,
Wherein the operation of the amplifier and the integrated capacitor is stopped, and the first switch is turned on. The method of claim 3,
And the capacitance adjustment switches are turned on / off according to a switching control signal based on the integrated value.

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