KR102542871B1 - Sensing Device and Organic Light Emitting Display Having The Same - Google Patents

Abstract

The present invention includes an amplifier, a reset switch, capacitors and switches. The amplifier has a first input terminal for receiving a pixel current through a first node connected to the sensing line, a second input terminal for receiving an initial integrator reference voltage or a first integrator reference voltage through a second node, and integration of the pixel current. and an output terminal for outputting the resulting integrator output voltage to a third node. A reset switch is connected to the first node and the third node. A plurality of capacitors are connected in parallel with each other between the first node and the third node. A plurality of switches are connected to the integrating capacitors one-to-one, and selectively connect a third node or an input terminal of an initial reference voltage.

Description

Sensing device and organic light emitting display including the same {Sensing Device and Organic Light Emitting Display Having The Same}

The present invention relates to a sensing device and an organic light emitting display device including the same, and more particularly, to an organic light emitting display device and a method for sensing deterioration of the organic light emitting diode.

The active matrix type organic light emitting display device includes an organic light emitting diode (OLED) that emits light by itself, and has advantages of fast response speed, high luminous efficiency, luminance, and viewing angle.

An organic light emitting diode, which is a self-light emitting device, includes an anode electrode, a cathode electrode, and organic compound layers (HIL, HTL, EML, ETL, EIL) formed between them. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer, EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes that have passed through the hole transport layer (HTL) and electrons that have passed through the electron transport layer (ETL) move to the light emitting layer (EML) to form excitons, and as a result, the light emitting layer (EML) visible light is generated.

An organic light emitting display device arranges pixels each including an organic light emitting diode in a matrix form, and adjusts luminance of the pixels according to gray levels of image data. Each of the pixels includes a driving transistor (Thin Film Transistor) that controls the pixel current flowing through the organic light emitting diode according to the voltage (Vgs) applied between its gate electrode and its source electrode. Adjust the display gradation (luminance) with the amount of light emitted.

The threshold voltage and electron mobility of the driving TFT, and the operating point voltage of the OLED determine the driving characteristics of the pixel, so they must be the same in all pixels. However, driving characteristics may vary between pixels due to various causes such as process characteristics and time-varying characteristics. This difference in driving characteristics causes a luminance deviation, which is a limitation in realizing a desired image. In order to compensate for a luminance deviation between pixels, an external compensation technique is known in which driving characteristics of pixels are sensed and data of an input image is corrected based on the sensing result.

In the external compensation technology, the circuit of the sensing unit that senses the driving characteristics of the pixels includes a large number of capacitors and elements, which increases the chip size and manufacturing cost of the drive IC.

Accordingly, an object of the present invention is to provide a sensing device capable of reducing the size and manufacturing cost of a drive IC by simplifying the configuration of a sensing unit, and an organic light emitting display device including the same.

To achieve the above object, the present invention includes an amplifier, a reset switch, capacitors and switches. The amplifier has a first input terminal for receiving a pixel current through a first node connected to the sensing line, a second input terminal for receiving an initial integrator reference voltage or a first integrator reference voltage through a second node, and integration of the pixel current. and an output terminal for outputting the resulting integrator output voltage to a third node. A reset switch is connected to the first node and the third node. A plurality of capacitors are connected in parallel with each other between the first node and the third node. A plurality of switches are connected to the integrating capacitors one-to-one, and selectively connect a third node or an input terminal of an initial reference voltage.

A display device according to the present invention includes a display panel having at least one pixel and a sensing line connected to the pixel, and a sensing device that senses driving characteristics of a pixel based on a pixel current from the pixel through the sensing line to generate sensing data. , Compensation unit for compensating the driving characteristics of the pixel based on the difference between the preset reference value and the sensing data. The sensing unit has a first input terminal receiving a pixel current through a first node connected to the sensing line, a second input terminal receiving an initial integrator reference voltage or a first integrator reference voltage through a second node, and integrating the pixel current. An amplifier having an output terminal for outputting the resulting integrator output voltage to a third node, a reset switch connected to the first node and the third node, n connected in parallel between the first node and the third node (n is a natural number) ) capacitors and integrating capacitors are connected one-to-one and include n switches selectively connecting a third node or an input terminal of the initial reference voltage.

In the present invention, voltage sensing driving as well as current sensing can be performed using a simple integrator circuit configuration.

In particular, since the present invention performs functions of sampling & holder and downscaling using an integrator, it does not require a capacitor required by the conventional sampling & holder and downscaler. Therefore, the circuit area of the sensing unit can be significantly reduced.

1 is a diagram showing an organic light emitting display device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram showing an example of a pixel array included in the display panel of FIG. 1 .
FIG. 3 is a diagram showing a configuration of a data driver connected to the pixel array of FIG. 2 .
FIG. 4 is an equivalent circuit diagram of the pixel shown in FIG. 3 .
5 is a view showing a sensing device according to the present invention.
6A to 6F are diagrams illustrating current sensing driving.
7 is a timing diagram illustrating a change in output voltage in current sensing driving.
8A to 8F are diagrams illustrating voltage sensing driving.
9 is a timing diagram illustrating a voltage change of an output node in voltage sensing driving.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various forms different from each other, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person who has the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, so the present invention is not limited to the details shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In the present specification, a pixel circuit formed on a substrate of a display panel may be implemented with an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure TFT or a p-type MOSFET structure TFT. A TFT is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the TFT, carriers start flowing from the source. The drain is an electrode through which carriers exit from the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type TFT (NMOS), since electrons are carriers, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in the n-type TFT, the direction of the current flows from the drain to the source. In contrast, in the case of a p-type TFT (PMOS), since a carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. Since holes flow from the source to the drain side in the p-type TFT, current flows from the source to the drain side. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can be changed depending on the applied voltage.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram showing an organic light emitting display device according to an exemplary embodiment of the present invention. Also, FIG. 2 is a diagram showing an example of a pixel array included in the display panel of FIG. 1 .

1 and 2 , an organic light emitting display device according to an exemplary embodiment of the present invention includes a display panel 100, a driver IC (D-IC) 200, a compensation IC 300, and a host system 10. , and a storage memory 50. The panel driver of the present invention includes a gate driver 40 included in the display panel 100 and a data driver 30 embedded in the driver IC (D-IC) 200 .

The display panel 100 includes a plurality of pixel lines HL1 to HL4, and each pixel line includes a plurality of pixels P and a plurality of signal lines. A "pixel line" described in the present invention is not a physical signal line, but means an aggregate of pixels P and signal lines adjacent to each other along the extension direction of the scan line. The signal lines include data lines DL for supplying the display data voltage VDIS and sensing data voltage VSEN to the pixels P, and the data lines DL for supplying the reference voltage VREF to the pixels P. reference voltage lines (RL), scan lines (SL) for supplying scan signals to pixels (P), and high potential power supply lines (PWL) for supplying high potential pixel voltages to pixels (P). can include

The pixels P of the display panel 100 are arranged in a matrix form to form a pixel array. Each pixel P included in the pixel array of FIG. 2 is connected to one of data lines DL, one of reference voltage lines RL, one of high potential power lines PWL, And it may be connected to any one of the scan lines SL. Each pixel P included in the pixel array of FIG. 2 may be connected to a plurality of scan lines SL. Also, each pixel P included in the pixel array of FIG. 2 may further receive a low-potential pixel voltage from the power generation unit. The power generation unit may supply a low potential pixel voltage to the pixel P through a low potential power line or pad unit.

A gate driver 40 may be embedded in the display panel 100 .

The gate driver 40 may include a plurality of stages connected to the scan lines SL of the pixel array of FIG. 2 . The stages may generate scan signals for controlling the switch elements of the pixels P and supply them to the scan lines SL.

The driver IC (D-IC) 200 includes a timing controller 20 and a data driver 30 . The data driver 30 may include a driving voltage generator 31 and a sensing unit 32, but is not limited thereto.

The timing controller 20 refers to timing signals input from the host system 10, for example, a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a dot clock signal (DCLK), and a data enable signal (DE). A gate timing control signal GDC for controlling the operation timing of the raw gate driver 40 and a data timing control signal DDC for controlling the operation timing of the data driver 30 may be generated.

The data timing control signal DDC may include, but is not limited to, a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls data sampling start timing of the driving voltage generator 31 . The source sampling clock is a clock signal that controls sampling timing of data based on a rising or falling edge. The source output enable signal controls output timing of the driving voltage generator 31 .

The gate timing control signal GDC may include, but is not limited to, a gate start pulse and a gate shift clock. A gate start pulse is applied to the stage that produces the first gate output to activate the operation of that stage. The gate shift clock is commonly input to the stages and is a clock signal for shifting the gate start pulse.

The timing controller 20 controls the operation timing of the panel driver to sense the driving characteristics of the pixels P in at least one of a power-on period, a vertical active period of each frame, a vertical blank period of each frame, and a power-off period. can do. Here, the power-on period is a period from when system power is applied until the screen is turned on, and the power-off period is a period from when the screen is turned off to before the system power is released. The vertical active period is a period in which image data is written on the display panel 100 for screen reproduction, and the vertical blank period is a period between adjacent vertical active periods and the writing of image data is stopped. The driving characteristics of the pixels P include threshold voltages and electron mobility of driving elements included in the pixels P.

The timing controller 20 may implement display driving and sensing driving by controlling the sensing driving timing and the display driving timing of the pixel lines HL1 to HL4 of the display panel 100 according to a predetermined sequence.

The timing controller 20 may generate different timing control signals GDC and DDC for display driving and timing control signals GDC and DDC for sensing driving. In the sensing drive, the driving characteristics of the corresponding pixels P are sensed by writing the sensing data voltage VSEN to the pixels P included in the sensing target pixel line, and the corresponding pixel P is based on the sensing data SD. ) means updating a compensation value for compensating for a change in driving characteristics. And, the display driving corrects the digital image data to be input to the corresponding pixels P based on the updated compensation value, and converts the display data voltage VDIS corresponding to the corrected image data CDATA to the corresponding pixels. It means displaying an input image by applying to (P).

The driving voltage generator 31 may be implemented as a digital to analog converter (hereinafter referred to as a DAC) that converts a digital signal into an analog signal. The driving voltage generation unit 31 generates the sensing data voltage VSEN required for sensing driving and the display data voltage VDIS required for display driving, and supplies them to the data lines DL.

The data voltage VDIS for display is a digital-to-analog conversion result for the digital image data CDATA corrected by the compensation IC 300, and its size may vary in pixel units according to the grayscale value and the compensation value. The data voltage VSEN for sensing may be set differently in units of R (red), G (green), B (blue), and W (white) pixels in consideration of the driving characteristics of the driving element for each color.

For sensing driving, the sensing unit 32 may sense driving characteristics of the pixels P, eg, threshold voltage and electron mobility of the driving element, and operating point voltage of the light emitting element through the sensing lines. The reference voltage line RL is connected to the sensing unit 32 through the first selection switch SEL1.

The sensing unit 32 may simultaneously process a plurality of analog sensing values in parallel using a plurality of analog-digital converters (ADCs), or sequentially process a plurality of analog sensing values in series using one ADC. . The ADC's sampling rate and sensing accuracy are in a trade-off relationship. Compared to serial processing ADCs, parallel processing ADCs can slow down the sampling rate, which is advantageous for increasing sensing accuracy. The ADC may be implemented as a flash type ADC, an ADC using a tracking technique, a successive approximation register type ADC, or the like. The ADC converts the analog sensing values into digital sensing data (SD) according to a predetermined sensing range, and supplies them to the storage memory 50 .

The storage memory 50 stores digital sensing data SD input from the sensing unit 32 during sensing operation. The storage memory 50 may be implemented as a flash memory, but is not limited thereto.

The compensation IC 300 may include a compensation unit 310 and a compensation memory 320 . The compensation memory 320 transfers the sensing data SD read from the storage memory 50 to the compensation unit 310 . The compensation memory 320 may be a random access memory (RAM), for example, a double date rate synchronous dynamic RAM (DDR SDRAM), but is not limited thereto. The compensation unit 310 calculates a compensation offset and a compensation gain for each pixel based on the digital sensing data SD read from the storage memory 50, and according to the calculated compensation offset and compensation gain. Image data received from the host system 10 is corrected, and the corrected image data (CDATA) is supplied to the driver IC 200 .

FIG. 3 is a diagram showing one configuration of the data driver 30 connected to the pixel array of FIG. 2 . FIG. 4 is an equivalent circuit diagram of the pixel shown in FIG. 3 . The data driver 30 of FIG. 3 illustrates an embodiment in which the driving characteristics of the pixels P are sensed through the reference voltage lines RL.

3 and 4 , the data driver 30 is connected to the gate node Ng of the pixel P through the data line DL and the source of the pixel P through the reference voltage line RL. It can be connected to the node Ns. Since the pixel current IPIX flows through the source node Ns of the pixel P, the reference voltage line RL connected to the source node Ns through the first select switch SEL1 can be used as a sensing line. there is.

The reference voltage line RL is selectively connected to the input terminal of the reference voltage VREF or the sensing unit 32 through the first and second select switches SEL1 and SEL2. A second selection switch SEL2 is connected between the reference voltage line RL and an input terminal of the reference voltage VREF, and a first selection switch SEL1 is connected between the reference voltage line RL and the sensing unit 32. do. The first selection switch SEL1 and the second selection switch SEL2 are selectively turned on. Only the second selection switch SEL2 is turned on in synchronization with the timing at which the reference voltage VREF is written to the pixel P, and the first selection switch SEL2 is turned on in synchronization with the timing at which the pixel current IPIX flowing in the pixel P is sensed. Only switch SEL1 is turned on. Therefore, the reference voltage line RL is selectively connected to the input terminal of the reference voltage VREF or the sensing unit 32 through the first and second select switches SEL1 and SEL2.

Referring to FIG. 4 , one pixel P using the reference voltage line RL as a sensing line includes an organic light emitting diode (OLED), a driving transistor DT, switch transistors ST1 and ST2, and a storage capacitor ( Cst) included. The driving transistor DT and the switch transistors ST1 and ST2 may be implemented with NMOS, but are not limited thereto.

The organic light emitting diode (OLED) is a light emitting device that emits light with an intensity corresponding to a pixel current drawn from the driving transistor DT. The anode electrode of the organic light emitting diode (OLED) is connected to the source node (Ns), and the cathode electrode is connected to the input terminal of the low potential driving voltage (EVSS).

The driving transistor DT is a driving element that generates a pixel current in response to a gate-source voltage. The gate electrode of the driving transistor DT is connected to the gate node Ng, the first electrode is connected to the input terminal of the high potential driving voltage EVDD through the high potential power supply line PWL, and the second electrode is connected to the source node of the driving transistor DT. (Ns) is connected.

The switch transistors ST1 and ST2 are switch elements that set the gate-source voltage of the driving transistor DT and connect the second electrode of the driving transistor DT to the reference voltage line RL.

The first switch transistor ST1 is connected between the data line DL and the gate node Ng and turned on according to the scan signal SCAN from the scan line SL. The first switch transistor ST1 is turned on during programming for display driving or sensing driving. When the first switch transistor ST1 is turned on, the sensing data voltage VSEN or the display data voltage VDIS is applied to the gate node Ng. The gate electrode of the first switch transistor ST1 is connected to the scan line SL, the first electrode is connected to the data line DL, and the second electrode is connected to the gate node Ng.

The second switch transistor ST2 is connected between the reference voltage line RL and the source node Ns and is turned on according to the scan signal SCAN from the scan line SL. The second switch transistor ST2 is turned on during programming for display driving or sensing driving, and applies the reference voltage VREF to the source node Ns. Also, the second switch transistor ST2 is turned on during the sensing period during sensing driving to apply the pixel current generated by the driving transistor DT to the reference voltage line RL. The gate electrode of the second switch transistor ST2 is connected to the scan line SL, the first electrode is connected to the reference voltage line RL, and the second electrode is connected to the source node Ns.

The storage capacitor Cst is connected between the gate node Ng and the source node Ns to maintain the gate-source voltage of the driving transistor DT for a predetermined period.

5 is a diagram showing a pixel sensing device according to an embodiment of the present invention. The pixel sensing device of FIG. 5 includes the sensing unit 32 of FIG. 1 .

Referring to FIG. 5 , the sensing unit 32 may include an integrator (CI) and an ADC. The integrator CI is connected to one pixel P through the reference voltage line RL of the display panel 10 . The integrator according to the present invention can be driven as a current integrator that accumulates and samples sensing current, and can also be used as an integrator for voltage sensing. To this end, the integrator CI includes an amplifier AMP, first to third integrating capacitors CF1, CF2, and CF3, a reset switch RST, first to third switches S1 to S2, and an initial integrator. A switch (hereinafter referred to as a 6th switch) S6, a first integrator switch (hereinafter referred to as a 5th switch) S5, a second integrator switch (hereinafter referred to as a 4th switch) S4, a node connection switch (hereinafter referred to as a 7th switch) switch) (S7), and a scale control switch (hereinafter referred to as an eighth switch) (S8).

First, a configuration for current sensing driving of the integrator (CI) is as follows.

The integrator CI integrates the pixel current IPIX flowing in the pixel P to generate an integrator output voltage CIA_OUT that is changed from the initial integrator reference voltage VREF_CI or the first integrator reference voltage VREF1.

The integrator amplifier (AMP) receives the pixel current (IPIX) from the reference voltage line (RL) through the first node (N1) and receives the integrator reference voltages through the first input terminal (-) and the second node (N2). A second input terminal (+) receiving any one integrator reference voltage among (VREF_CI, VREF1, VREF2) and a third node (N3) outputting the integrator output voltage (CIA_OUT), which is the result of integration of the pixel current (IPIX). includes The third node N3 of the amplifier AMP corresponds to the third node N3.

Among the integrator reference voltages VREF_CI, VREF1, and VREF2, only the initial integrator reference voltage VREF_CI and the first integrator reference voltage VREF1 are involved when operating as a current integrator. The initial integrator reference voltage VREF_CI is a reference voltage that is the reference voltage for ADC driving before downscaling in driving the current integrator, and the first integrator reference voltage VREF1 is the reference voltage that is the reference for ADC driving after downscaling. is the voltage

The sixth switch S6 is connected between the input terminal of the initial integrator reference voltage VREF_CI and the second input terminal (+), and the fifth switch S5 is connected between the input terminal of the first integrator reference voltage VREF1 and the second input terminal. It is connected between the terminals (+).

A first electrode of each of the first to third integrating capacitors CF1 , CF2 , and CF3 is connected to the first input terminal (-). The second electrode of each of the first to third integrating capacitors CF1 , CF2 , and CF3 is connected to the first to third switches S1 to S3 one-to-one. The first switch S1 selectively connects the first integrating capacitor CF1 to the third node N3 or the input terminal of the initial integrator reference voltage VREF_CI. The second switch S2 selectively connects the second integrating capacitor CF2 to the third node N3 or the input terminal of the initial integrator reference voltage VREF_CI. The third switch S3 selectively connects the third integrating capacitor CF3 to the third node N3 or the input terminal of the initial integrator reference voltage VREF_CI.

A reset switch RST is further connected between the first input terminal (-) of the integrator amplifier AMP and the third node N3 in parallel with the integrating capacitors CF1, CF2, and CF3.

The integrator amplifier (AMP) may be implemented as a negative type or a positive type. As shown in FIG. 5, in the negative type amplifier AMP, the first input terminal is the first input terminal (-) of the integrator amplifier (AMP) and the second input terminal is the second input terminal of the integrator amplifier (AMP). It becomes (+). In this negative type amplifier AMP, the integrator output voltage CIA_OUT gradually decreases from the integrator reference voltage VREF_CI as the pixel current IPIX is accumulated in the integrating capacitors CF1 to CF3. The falling slope of the integrator reference voltage VREF_CI is proportional to the magnitude of the pixel current IPIX.

Meanwhile, in the positive type amplifier AMP, the first input terminal becomes the second input terminal (+) of the integrator amplifier and the second input terminal becomes the first input terminal (-) of the integrator amplifier. In the positive type amplifier AMP, the integrator output voltage CIA_OUT gradually increases from the integrator reference voltage VREF_CI as the pixel current IPIX is accumulated in the integrating capacitors CF1 to CF3. The rising slope of the integrator reference voltage VREF_CI is proportional to the magnitude of the pixel current IPIX.

The technical idea of the present invention can be applied to a negative type amplifier (AMP) as well as a positive type amplifier (AMP). Hereinafter, this specification will be described centering on the negative type amplifier (AMP).

A configuration for voltage sensing of the integrator (CI) is as follows.

During the voltage sensing process, the amplifier AMP does not receive a driving voltage and maintains a disabled state.

The sensing voltage from the reference voltage line RL is sampled while the integrating capacitors CF1, CF2, and CF3 are directly charged.

The second node N2 is connected to the first to third switches S1 to S3 through a reference voltage selection switch (hereinafter referred to as a seventh switch). The integrating capacitors CF1, CF2, and CF3 maintain a state connected to the second node N2 through the first to third switches S1 to S3.

The fourth switch S4 is connected between the second node N2 and the input terminal of the second integrator reference voltage VREF2, and the fifth switch S5 is connected between the second node N2 and the first integrator reference voltage VREF1. ) is connected between the inputs of The second integrator reference voltage VREF2 is a reference voltage used to drive the ADC before downscaling, and the first integrator reference voltage VREF1 is a reference voltage used to drive the ADC after downscaling.

The capacitor control switch (hereinafter referred to as an eighth switch) S8 opens the first node N1 and the first capacitor CF1 for a predetermined period within the downscaling period.

During current integration or voltage sensing, the ADC converts an analog signal (ie, integrator output voltage) into a digital signal (ie, digital sensing data) according to a predetermined sensing range.

Hereinafter, the operation of the sensing unit according to the present invention will be described.

First, the current sensing drive is described as follows.

6A to 6F are views illustrating current sensing driving, and FIG. 7 is a timing diagram illustrating a change in output voltage in current sensing driving. In FIG. 7, "N1" represents the voltage change of the first node N1 corresponding to the second input terminal (+) of the amplifier AMP, and "N3" represents the voltage change of the third node corresponding to the output terminal of the amplifier AMP. It shows the voltage change of node N3.

In current sensing driving, the seventh switch S7 is always turned off, and the eighth switch S8 is always turned on.

Referring to FIGS. 6A and 7 , during the initialization period SF1, the first selection switch SEL1 and the reset switch RST are turned on, and the first to third switches S1 to S3 are turned on by the amplifier AMP. ) is connected to the third node N3. The sixth switch S6 is turned on.

In the initialization period SF1, the first selection switch SEL1 is turned on so that the reference voltage line RL is connected to the first input terminal (-). The reset switch RST is turned on so that the integrator CI operates as a unit gain buffer with a gain of 1. The initial reference voltage VREF_CI is applied to the second input terminal (+) of the amplifier AMP through the sixth switch S6. As a result, the input terminals (+, -) of the amplifier AMP, the third node N3, and the reference voltage line RL are initialized to the initial reference voltage VREF_CI.

Referring to FIGS. 6B and 7 , in the sensing period SF2 , the reset switch RST is turned off. The first select switch SEL1 and the sixth switch S6 maintain a turn-on state. The first to third switches S1 to S3 remain connected to the third node N3 of the amplifier AMP.

In the sensing period SF2, the potential difference between both ends of the integrating capacitor Cfb increases due to the charge flowing into the first input terminal (-) of the amplifier AMP. Due to the characteristics of the amplifier (AMP), the first input terminal (-) and the second input terminal (+) are shorted through a virtual ground and the potential difference between them is 0, so in the sensing period (SF2), the first input terminal ( The potential of -) is maintained as the initial integrator reference voltage VREF_CI regardless of the increase in the potential difference between the integrating capacitors CF1, CF2, and CF3. In addition, the output voltage CIA_OUT of the amplifier AMP is lowered in response to the potential difference between the ends of the integrating capacitors CF1, CF2, and CF3.

Referring to FIGS. 6C and 7 , in the sampling period SF3, the first select switch SEL1 and the reset switch RST are turned off and sample the output voltage CIA_OUT of the amplifier AMP. During the sampling period SF3, the variation Vin of the output voltage CIA_OUT of the amplifier AMP compared to the initial integrator reference voltage VREF_CI is proportional to the potentials of the first to third integrating capacitors CF1 to CF3. .

Referring to FIGS. 6D and 7 , during the first downscaling period SF4, the first selection switch SEL1 and the reset switch RST maintain a turned-off state.

The first switch S1 remains connected to the third node N3, and the second and third switches S2 and S3 are connected to the first input terminal (-). As a result, the voltages of the second and third integrating capacitors CF2 and CF3 are initialized.

Referring to FIGS. 6E and 7 , during the second downscaling period SF5, the first selection switch SEL1 and the reset switch RST maintain a turned-off state. The first to third switches S1 to S3 are connected to the third node N3. Charges stored in the first integrating capacitors CF1 are distributed to the second and third integrating capacitors CF2 and CF3, and each of the first to third integrating capacitors CF1, CF2 and CF3 has the same potential.

The charge stored in the first integrating capacitors CF1 is distributed to the second and third integrating capacitors CF2 and CF3, so that the potential difference between the first to third integrating capacitors CF1, CF2 and CF3 decreases. . As a result, the output voltage CIA_OUT of the amplifier AMP increases.

When the respective capacities of the first to third integrating capacitors CF1 , CF2 , and CF3 are the same, the potential of each of the first to third integrating capacitors CF1 , CF2 , and CF3 during the second downscaling period SF5 is 1/3 of the potential of each of the first to third integration capacitors CF1, CF2, and CF3 in the sampling period SF3. The magnitude of the output voltage CIA_OUT in the second downscaling period SF5 is proportional to the potentials of the first to third integrating capacitors CF1 , CF2 , and CF3 in the second downscaling period SF5 . Therefore, "the amount of change (Vin_d) of the output voltage decreased compared to the initial integrator reference voltage VREF_CI in the second downscaling period SF5" is "decreased compared to the initial integrator reference voltage VREF_CI in the sampling period SF3". It is 1/3 level compared to the change amount (Vin) of the output voltage.

Referring to FIGS. 6F and 7 , the first integrator reference voltage VREF1 is applied to the first input terminal (-) during the third downscaling period SF6. The first integrator reference voltage VREF1 is set to a lower voltage level than the initial integrator reference voltage VREF_CI.

The integrator output voltage CIA_OUT is proportional to the reference voltage applied to the second input terminal (+) of the amplifier AMP. Therefore, in the third downscaling period (SF6), the integrator output voltage (CIA_OUT) is reduced by the amount of change ('VREF_CI'-'VREF1') in which the reference voltage is lowered from the initial integrator reference voltage (VREF_CI) to the first integrator reference voltage (VREF1). also descend As such, according to the present invention, the level of the integrator output voltage CIA_OUT can be reduced by the first to third downscaling driving. Therefore, the integrator output voltage (CIA_OUT) can be controlled so as not to deviate from the input range of the ADC.

When the magnitude of the integrator reference voltage applied to the second input terminal (+) of the amplifier AMP changes due to downscaling driving, the compensator 310 sets a different reference value for generating a compensation value.

The ADC receives the output voltage (CIA_OUT) as a sensing voltage and converts it into digital data to generate sensing data (SD). Further, the compensator 310 generates a compensation value based on the sensing data SD, and compensates the image data using the generated compensation value. In this case, the reference value at which the compensation unit 310 generates the compensation value in the current sensing drive corresponds to the integrator reference voltage applied to the second input terminal (+) when the amplifier AMP generates the output voltage CIA_OUT.

Therefore, if the output voltage CIA_OUT of the amplifier AMP is generated using the initial integrator reference voltage VREF_CI before downscaling, the compensator 310 generates the first reference value matching the initial integrator reference voltage VREF_CI and A compensation value is generated by comparing the sensing data SD.

And, if the output voltage CIA_OUT of the amplifier AMP is generated using the first integrator reference voltage VREF1 in the third downscaling process of FIG. 6F, the compensator 310 generates the first integrator reference voltage VREF1 Compensation values are generated by comparing the second reference value matching with the sensing data SD.

Looking at voltage sensing driving using the sensing unit of the present invention is as follows.

8A to 8F are views illustrating current sensing driving, and FIG. 9 is a timing diagram illustrating a change in output voltage in voltage sensing driving. Particularly, in FIG. 9 , a solid line is a diagram showing a change in voltage of the first node N1.

In the voltage sensing drive, the amplifier (AMP) is maintained in an inoperable state.

In voltage sensing driving, the seventh switch S7 maintains a turned-on state, so that the second node N2 maintains a state connected to the first to third switches S1 to S3. That is, the integrating capacitors CF1 to CF3 remain connected to the second node N2 through the first to third switches S3.

The specific operation is as follows.

Referring to FIGS. 8A and 9 , the first selection switch SEL1 , the reset switch RST and the eighth switch S8 are turned on during the initialization period SF1 . The reset switch RST is turned on, and both electrodes of the first to third integration capacitors CF1 , CF2 , and CF3 are shorted. That is, both electrodes of the first to third integrating capacitors CF1 , CF2 , and CF3 are initialized to the second integrator reference voltage VREF2 .

Referring to FIGS. 8B and 9 , in the sensing period SF2 , the first select switch SEL1 is turned on so that the first node N1 is connected to the reference voltage line RL. When the reset switch RST is turned off, each of the first to third integration capacitors CF1 , CF2 , and CF3 forms a capacitance.

The sensing voltage applied from the reference voltage line RL is charged to the first electrodes of the first to third integration capacitors CF1, CF2, and CF3. Accordingly, the voltage of the first node N1 gradually rises from the second integrator reference voltage VREF2.

Referring to FIGS. 8C and 9 , in the sampling period SF3, the first select switch SEL1 and the reset switch RST are turned off, and the first to third integration capacitors CF1, CF2, and CF3 are turned off. Samples the sensing voltage charged in .

Referring to FIGS. 8D and 9 , during the first downscaling period SF4, the first select switch SEL1 maintains a turn-off voltage.

The reset switch RST is turned on, and the second and third integration capacitors CF2 and CF3 are initialized. That is, the first node N1 and the second node N2 become the second integrator reference voltage VREF2.

The eighth switch S8 is turned off so that the first electrode of the first integrating capacitor CF1 is in an open state with the first node N1. Accordingly, the first capacitor CF1 holds the charge charged in the sensing period SF2.

Referring to FIGS. 8E and 9 , during the second downscaling period SF5, the eighth switch S8 is turned on and the reset switch RST is turned off.

Charges stored in the first integrating capacitors CF1 are distributed to the second and third integrating capacitors CF1 and CF2, and the first to third integrating capacitors CF1, CF2 and CF3 have the same potential. In the second downscaling period SF5, the potential difference between the ends of the integrating capacitors CF1, CF2, and CF3 gradually increases.

When the respective capacities of the first to third integrating capacitors CF1 , CF2 , and CF3 are the same, the potential of each of the first to third integrating capacitors CF1 , CF2 , and CF3 in the second downscaling period SF5 . is 1/3 of the potential of each of the first to third integration capacitors CF1, CF2, and CF3 in the sampling period SF3. Therefore, "the potential difference between the first node N1 and the third node N3 increased from the second integrator reference voltage VREF2 in the second downscaling period SF5" is "the second integrator reference voltage in the sampling period SF3" The potential difference Vin" between the first node N1 and the third node N3 increased from the voltage VREF2 is 1/3 level.

Referring to FIGS. 8F and 9 , the first integrator reference voltage VREF1 is applied to the first input terminal (-) during the third downscaling period SF6. The first integrator reference voltage VREF1 is set to a lower voltage level than the second integrator reference voltage VREF2.

Accordingly, the voltages of the second electrodes of the first to third integrating capacitors CF1 , CF2 , and CF3 connected to the second node are lowered, and the coupling effect causes the first to third integrating capacitors CF1 , CF2 to , CF3) the voltage of the first electrode is lowered. Accordingly, the voltage of the first node N1 detected based on the amount of change in the voltage of the third node N3 is lowered. As a result, the voltage of the first node N1 does not deviate from the input range of the ADC and a sensing error does not occur.

When the magnitude of the integrator reference voltage applied to the third node N3 of the amplifier AMP changes due to downscaling driving, the compensator 310 sets a different reference value for generating a compensation value.

The ADC receives the output voltage (CIA_OUT) as a sensing voltage and converts it into digital data to generate sensing data (SD). Further, the compensator 310 generates a compensation value based on the sensing data SD, and compensates the image data using the generated compensation value. At this time, the reference value for which the compensator 310 generates the compensation value in the voltage sensing drive matches the integrator reference voltage connected to the third node N3.

Therefore, if the second integrator reference voltage VREF2 is applied to the third node N3 before downscaling and voltage sensing is driven based on this, the compensator 310 matches the second integrator reference voltage VREF2. A compensation value is generated by comparing the third reference value with the sensing data SD.

And, if the first integrator reference voltage VREF1 is applied to the third node N3 in the third downscaling process of FIG. Compensation values are generated by comparing the S and the sensing data SD.

As described above, in the present invention, voltage sensing driving as well as current sensing can be performed using a simple integrator circuit configuration.

In particular, the present invention performs functions of sampling & holder and downscaling using an integrator. Therefore, the capacitor required by the conventional sampling & holder and downscaler is not required. The number of capacitors connected in parallel at the first node and the second node of the present invention is increased compared to one existing feedback integration capacitor, but the sum of the capacitances of the capacitors connected in parallel is the same as that of the existing feedback integration capacitor. Accordingly, the plurality of capacitors connected in parallel at the first node and the second node have the same size as the conventional one. As a result, the present invention can reduce the area of the circuit part by the size of the capacitor required for the conventional sampling & holder and downscaler.

Through the above description, those skilled in the art will know that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

100: display panel 40: gate driver
200: driver IC 20: timing controller
32: sensing unit CI: integrator
SEL1: first selection switch

Claims (23)

A first input terminal receiving a pixel current through a first node connected to the sensing line, a second input terminal receiving an initial integrator reference voltage or a first integrator reference voltage through a second node, and a result of integrating the pixel current an amplifier having an output terminal for outputting the output voltage of the integrator to a third node;
a reset switch connected to the first node and the third node;
n (n is a natural number) capacitors connected in parallel to each other between the first node and the third node; and
n switches connected to the capacitors one-to-one and selectively connecting the third node or the input terminal of the initial integrator reference voltage;
The n switches are
In a first period, in a state where each of the n capacitors is connected to the second node, the n capacitors are controlled to integrate current;
In a second period, the sensing device reduces a potential difference between the first node and the second node by controlling one of the n capacitors to be connected to the initial integrator reference voltage. delete According to claim 1,
The initial integrator reference voltage is
A sensing device that is a reference voltage for initializing the first node, the second node, and the third node. A first input terminal receiving a pixel current through a first node connected to the sensing line, a second input terminal receiving an initial integrator reference voltage or a first integrator reference voltage through a second node, and a result of integrating the pixel current an amplifier having an output terminal for outputting the output voltage of the integrator to a third node;
a reset switch connected to the first node and the third node;
n (n is a natural number) capacitors connected in parallel to each other between the first node and the third node;
n switches connected to the capacitors one-to-one and selectively connecting the third node or an input terminal of the initial integrator reference voltage; and
A selection switch connected between the sensing line and the first node;
In the current sensing drive, during the initialization period,
The selection switch and the reset switch are turned on,
In each of the n switches, the capacitors are connected to the third node,
The second node receives the initial integrator reference voltage. According to claim 4,
During the sensing period following the initialization period,
The reset switch is turned off, and the capacitors integrate the pixel current from the sensing line. According to claim 5,
During a sampling period following the sensing period, the selection switch is turned off. According to claim 6,
During a first downscaling period following the sampling period,
At least one of the n switches is connected to an input terminal of the initial integrator reference voltage. According to claim 7,
During the second downscaling period following the first downscaling period,
The n switches are connected to the third node. According to claim 8,
During the third downscaling period following the second downscaling period,
The second node receives the first integrator reference voltage. According to claim 9,
The first integrator reference voltage is lower than the initial integrator reference voltage. A first input terminal receiving a pixel current through a first node connected to the sensing line, a second input terminal receiving an initial integrator reference voltage or a first integrator reference voltage through a second node, and a result of integrating the pixel current an amplifier having an output terminal for outputting the output voltage of the integrator to a third node;
a reset switch connected to the first node and the third node;
n (n is a natural number) capacitors connected in parallel to each other between the first node and the third node;
n switches connected to the capacitors one-to-one and selectively connecting an input terminal of the third node or the initial integrator reference voltage; a node connection switch connected between the second node and the third node;
a scale control switch connected between a first electrode of a first capacitor among the n capacitors and the first node; and
and a second integrator reference voltage switch connected between the second node and an input terminal of the second integrator reference voltage. According to claim 11,
In voltage sensing drive
The node connection switch maintains a turn-on voltage,
The n switches are connected to the third node,
The sensing device maintains a state in which the input terminal of the initial integrator reference voltage is electrically disconnected from the second node. According to claim 12,
Further comprising a selection switch connected between the sensing line and the first node,
In the initialization period of the voltage sensing drive,
The selection switch is turned off,
The second integrator reference voltage switch and the reset switch are turned on. According to claim 13,
During the sensing period following the initialization period,
The reset switch is turned off,
The selection switch is turned on to charge a voltage to the n capacitors. 15. The method of claim 14,
During the sampling period following the sensing period,
A sensing device for sampling voltages charged in the n capacitors by turning off the selection switch. According to claim 15,
During a first downscaling period following the sampling period,
A sensing device that initializes both ends of 'n-1' capacitors other than the first capacitor to the second integrator reference voltage by turning off the scale control switch and turning on the reset switch. 17. The method of claim 16,
During the second downscaling period following the first downscaling period,
A sensing device for distributing the voltage charged in the first capacitor by turning on the scale control switch and turning off the reset switch. 18. The method of claim 17,
During the third downscaling period following the second downscaling period,
The sensing device turns off the second integrator reference voltage switch and supplies the integrator reference voltage to the second node. a display panel having at least one pixel and a sensing line connected to the pixel;
a sensing device generating sensing data by sensing driving characteristics of the pixel based on the pixel current from the pixel through the sensing line; and
A compensation unit for compensating for driving characteristics of the pixel based on a difference between a preset reference value and the sensing data;
The sensing device
A first input terminal receiving a pixel current through a first node connected to the sensing line, a second input terminal receiving an initial integrator reference voltage or a first integrator reference voltage through a second node, and a result of integrating the pixel current an amplifier having an output terminal for outputting the output voltage of the integrator to a third node;
a reset switch connected to the first node and the third node;
n (n is a natural number) capacitors connected in parallel to each other between the first node and the third node; and
n switches connected to the capacitors one-to-one and selectively connecting the third node or the input terminal of the initial integrator reference voltage;
In the current sensing drive, the compensation unit,
Setting the reference value as a first reference value matched to the initial integrator reference voltage;
wherein the sensing device compares first sensing data acquired using the initial integrator reference voltage with the first reference value to generate a compensation value. delete According to claim 19,
In the current sensing drive, the compensation unit,
Setting the reference value as a second reference value matched to the first integrator reference voltage;
wherein the sensing device compares second sensing data acquired using the first integrator reference voltage with the second reference value to generate a compensation value. a display panel having at least one pixel and a sensing line connected to the pixel;
a sensing device generating sensing data by sensing driving characteristics of the pixel based on the pixel current from the pixel through the sensing line; and
A compensation unit for compensating for driving characteristics of the pixel based on a difference between a preset reference value and the sensing data;
The sensing device
A first input terminal receiving a pixel current through a first node connected to the sensing line, a second input terminal receiving an initial integrator reference voltage or a first integrator reference voltage through a second node, and a result of integrating the pixel current an amplifier having an output terminal for outputting the output voltage of the integrator to a third node;
a reset switch connected to the first node and the third node;
n (n is a natural number) capacitors connected in parallel to each other between the first node and the third node;
n switches connected to the capacitors one-to-one and selectively connecting the third node or an input terminal of the initial integrator reference voltage; and
A second integrator reference voltage switch connected between the second node and an input terminal of a second integrator reference voltage;
The second integrator reference voltage is set to a higher value than the first integrator reference voltage,
In the voltage sensing drive, the compensation unit,
Setting the reference value as a third reference value matched to the first integrator reference voltage;
wherein the sensing device compares third sensing data acquired using the first integrator reference voltage with the third reference value to generate a compensation value. 23. The method of claim 22,
In the voltage sensing drive, the compensation unit
Setting the reference value as a fourth reference value matched to the second integrator reference voltage;
wherein the sensing device compares fourth sensing data acquired using the second integrator reference voltage with the fourth reference value to generate a compensation value.

Images