KR20120041425A - Organic light emitting diode display device - Google Patents

Abstract

PURPOSE: An organic light emitting diode display apparatus is provided to remove deviations with respect to the threshold voltage of a driving transistor generated between pixels by compensating for the threshold voltage. CONSTITUTION: A first capacitor is formed between a first node(N1) and a second node(N2). A second capacitor is formed between a power voltage source and the second node. A driving transistor(Td) varies the amount of current flowing to an organic light emitting diode(OLED). A first transistor(T1) supplies data voltage to the second node. A second transistor(T2) supplies a reference voltage to the second node. A third transistor(T3) connects a third node(N3) to the first node. A fourth transistor(T4) supplies the reference voltage to the third node. A fifth transistor(T5) supplies voltage of the third node to an anode electrode of the organic light emitting diode.

Description

Organic light emitting diode display device {ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE}

The present invention relates to an organic light emitting diode display.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode are being developed. Various flat panel display devices such as organic light emitting diodes (OLEDs) are utilized. Among these flat panel display devices, organic light emitting diode display devices are capable of low voltage driving, are thin, have excellent viewing angles, and have fast response speeds. As the organic light emitting diode display, an active matrix type organic light emitting diode display for displaying an image in which a plurality of pixels are positioned in a matrix form is widely used.

The display panel of the active matrix type organic light emitting diode display includes a plurality of pixels defined by scan lines and data lines. In general, the pixel array includes a scan transistor that supplies a data voltage in response to a gate pulse of a scan line, and a driving transistor that adjusts an amount of current supplied to the OLED according to a data voltage supplied to a gate electrode. . However, due to the deviation of the threshold voltage of the driving transistor generated among the plurality of pixels, the current supplied to the organic light emitting diode OLED has a different value from the desired value, so that the luminance of the emitted light is different from the target luminance. A problem occurs. Therefore, in order to compensate for the threshold voltage of the driving transistor, various types of pixel structures and pixel driving methods have been proposed.

The present invention provides an organic light emitting diode display device capable of compensating the threshold voltage of a driving transistor.

The organic light emitting diode display according to the present invention has an mth (m is a natural number) data line, an n-1 (n is a natural number) gate line, an nth gate line, an nth initialization line, an nth light emission control line, and cross each other. And a plurality of pixels defined by the m-th data line and the n-th gate line, each pixel comprising: an organic light emitting diode; A first capacitor formed between the first node and the second node; A second capacitor formed between a power supply voltage source and the second node; A driving transistor configured to differently adjust an amount of current flowing to the organic light emitting diode according to the voltage of the first node; A first transistor configured to supply a data voltage to the second node in response to an nth scan pulse of the nth gate line; A second transistor configured to supply a reference voltage to the second node in response to an n−1 th scan pulse of the n−1 th gate line generated before the n th scan pulse; A third transistor connecting the first node and the third node between the organic light emitting diode and the driving transistor in response to the n−1 th scan pulse; A fourth transistor configured to supply the reference voltage to the third node in response to an nth initialization signal of the nth initialization line which is generated before the nth scan pulse; And a fifth transistor configured to supply a voltage of the third node to an anode electrode of the organic light emitting diode in response to an nth light emission control signal of the nth light emission control line synchronized with the n−1th scan pulse. The reference voltage may be a voltage for initializing the first to third nodes.

The present invention initializes the node connected to the gate electrode of the driving transistor for one horizontal period, samples the threshold voltage of the driving transistor, and then, the node connected to the gate electrode of the driving transistor for one horizontal period, the threshold voltage compensated data voltage. To charge. As a result, the present invention can eliminate the deviation of the threshold voltage of the driving transistor generated between the plurality of pixels by compensating the threshold voltage. In addition, the present invention can compensate for the threshold voltage even when the R data voltage is supplied to the R pixel, the G data voltage to the G pixel, and the B data voltage to the B pixel through the multiplexer.

1 is a circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment of the present invention.
2 is a waveform diagram illustrating signals input to a pixel according to a first exemplary embodiment of the present invention.
3 is a waveform diagram illustrating signals input to a pixel according to a second exemplary embodiment of the present invention.
4 is a circuit diagram of a multiplexer and a pixel of an organic light emitting diode display according to an exemplary embodiment of the present invention.
FIG. 5 is a waveform diagram illustrating a multiplexer and a signal input to a pixel according to a first exemplary embodiment of the present invention.
6 is a waveform diagram illustrating signals input to a multiplexer and a pixel according to a second exemplary embodiment of the present invention.
FIG. 7 is a waveform diagram illustrating voltages of N1 nodes of R, G, and B pixels of FIG. 4.
8 is a block diagram schematically illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The names of the components used in the following description are selected in consideration of the ease of preparation of the specification, and may be different from the names of the actual products.

1 is a circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment of the present invention. Referring to FIG. 1, a pixel P of an organic light emitting diode display is defined as a gate line GL and a data line DL that cross each other. Each pixel P includes first to fifth transistors T1, T2, T3, T4, and T5, a driving transistor Td, an organic light emitting diode OLED, and the like.

The first to fifth transistors T1, T2, T3, T4, and T5 serve as switches. The gate electrode of the first transistor T1 is connected to the nth (n is a natural number) gate line GLn, the source electrode is connected to an mth (m is a natural number) data line DLm, and the drain electrode is an N2 node. Is connected to N2. The gate electrode of the second transistor T2 is connected to the n-th gate line GLn-1, the source electrode is connected to the reference voltage Vref, and the drain electrode is connected to the N2 node N2. The gate electrode of the third transistor T3 is connected to the n-th gate line GLn-1, the source electrode is connected to the N1 node N1, and the drain electrode is connected to the N3 node N3. The gate electrode of the fourth transistor T4 is connected to the nth initialization line ILn, the source electrode is connected to the reference voltage Vref, and the drain electrode is connected to the N3 node N3. The gate electrode of the fifth transistor T5 is connected to the nth emission control line EMn, the source electrode is connected to the N3 node N3, and the drain electrode is connected to the anode electrode of the organic light emitting diode OLED. The gate electrode of the driving transistor Td is connected to the storage capacitor C, the source electrode is connected to the power supply voltage VDD, and the drain electrode is connected to the N3 node N3. The driving transistor Td adjusts the amount of current I _OLED passing through the driving transistor Td differently according to the data voltage applied to the gate electrode. The power supply voltage may be set to approximately 10V, which is set in consideration of the driving transistor Td, the organic light emitting diode OLED, and the like. The reference voltage is a voltage for initializing the nodes of each pixel P and may be set to a voltage between 0V and 1.5V.

The first to fifth transistors T1, T2, T3, T4, and T5 and the driving transistor Td may be implemented as a P type MOS-FET and an N type MOS-FET. Hereinafter, the first to fifth transistors T1, T2, T3, T4, and T5 and the driving transistor Td will be described based on the fact that they are P-type MOS-FETs.

The N1 node N1 is a contact between the gate electrode of the driving transistor Td and the source electrode of the third transistor T3, and the N2 node N2 is the drain electrode and the second transistor T2 of the first transistor T1. Contact between the drain electrodes. The N3 node N3 is a contact between the drain electrode of the driving transistor Td and the drain electrode of the third transistor T3, and is a contact between the drain electrode of the fourth transistor T4 and the source electrode of the fifth transistor T5. .

The anode electrode of the organic light emitting diode OLED is connected to the drain electrode of the fifth transistor T5, and the cathode electrode is connected to the ground voltage GND. The first capacitor C1 reflects the voltage of the N2 node N2 to the N1 node N1. The second capacitor C2 keeps the voltage of the N2 node N2 constant.

2 is a waveform diagram illustrating signals input to a pixel according to a first exemplary embodiment of the present invention. Referring to FIG. 2, an nth initialization signal ININ, an n−1th scan pulse SPn−1, an nth scan pulse SPn, and an nth emission control signal EMn are applied to each pixel P. Referring to FIG. Is entered.

Each pulse of the n-th scan pulse SPn-1 and the n-th scan pulse SPn is generated at a low logic voltage for one horizontal period 1H. The pulse of the nth initialization signal ININ is generated at a low logic voltage for a predetermined time shorter than one horizontal period 1H, and the pulse of the nth emission control signal EMn is generated at a high logic voltage for two horizontal periods. .

The pulse of the n-th scan pulse SPn-1, the pulse of the n-th initialization signal ININ, and the pulse of the n-th light emission control signal EMn occur simultaneously. The pulse of the nth initialization signal ININ occurs for a predetermined time t1 shorter than one horizontal period 1H. The predetermined time t1 may be determined to be an appropriate time in consideration of the initialization of the nodes of the pixel P by experiment. The pulse of the n-th scan pulse SPn-1 is generated for one horizontal period, followed by the pulse of the n-th scan pulse SPn in one horizontal period. The pulse of the nth light emission control signal EMn is generated for two horizontal periods. Each of the pulse of the nth initialization signal ININ, the pulse of the nth-1st scan pulse SPn-1, the pulse of the nth scan pulse SPn, and the pulse of the nth emission control signal EMn is one frame period. Repeated by the cycle.

Hereinafter, the operation of the pixel P of the present invention according to the waveform diagram of FIG. 2 will be described in detail. This will be described with reference to FIG. 1, and will be described sequentially according to predetermined t1 to t4 times.

First, the second transistor T2 and the third transistor T3 are turned on in response to a pulse of the n−1 th scan pulse SPn−1 having a low logic voltage for a time t1. The fourth transistor T4 is turned on in response to a pulse of the nth initialization signal ININ of the low logic voltage. The first transistor T1 and the fifth transistor T5 are turned off.

By turning on the fourth transistor T4, the N3 node N3 is initialized to the reference voltage Vref. In addition, with the turn-on of the second transistor T2, the N1 node N1 is initialized to the reference voltage Vref. Further, with the turn-on of the third transistor T3, the N2 node N2 is initialized to the reference voltage Vref.

Secondly, the second transistor T2 and the third transistor T3 remain turned on in response to the pulse of the n−1 th scan pulse SPn−1 of the low logic voltage for the time t2. Since the nth initialization signal ININ is inverted to the high logic voltage, the fourth transistor T4 is turned off. The first transistor T1 and the fifth transistor T5 maintain a turn-off state.

When the fourth transistor T4 is turned off and the third transistor T3 is turned on, since the difference Vgs between the gate voltage and the source voltage of the driving transistor Td is greater than the threshold voltage Vth, The voltage at the N1 node N1 increases until the difference Vgs between the gate voltage and the source voltage becomes equal to or smaller than the threshold voltage Vth. Therefore, the voltage at the N1 node N1 rises to (VDD-Vth). In addition, since the second transistor T2 maintains a turn-on state, the N2 node N2 maintains a state initialized to the reference voltage Vref.

Third, the first transistor T1 is turned on in response to the pulse of the nth scan pulse SPn of the low logic voltage for the time t3. Since the n-th scan pulse SPn-1 is inverted to a high logic voltage, the second transistor T2 and the third transistor T3 are turned off. The fourth transistor T4 and the fifth transistor T5 maintain the turn-off state.

When the second transistor T2 is turned off and the first transistor T1 is turned on, the N2 node N2 changes to the difference voltage Vref-Vdata of the reference voltage Vref and the data voltage Vdata. . As the third transistor T3 is turned off, the N1 node N1 maintains the power supply voltage VDD-Vth affected by the threshold voltage.

The first capacitor C1 reflects the voltage change amount Vref-Vdata of the N2 node N2 to the N1 node N1. Therefore, when a voltage change occurs at the N2 node N2, the voltage change amount ΔV is reflected by the first capacitor C1 at the N1 node N1. Therefore, the N1 node N1 becomes {(VDD-Vth)-(Vref-Vdata)} by the first capacitor C1. The current I _OLED passing through the driving transistor Td is represented by Equation 1 below. In Equation 1, the voltage of the N1 node N1 is substituted by the gate voltage Vg, and the power supply voltage VDD is substituted with the source voltage Vs.

In Equations 1 to 3, Vgs is the difference between the gate voltage Vg and the source voltage Vs of the driving transistor Td, μ is electron mobility, and C _ox is a parasitic capacitance of the driving transistor Td ( Capacitance, W denotes the channel width of the driving transistor Td, and L denotes the channel length of the driving transistor Td. As can be seen in Equation 3, the current I _OLED flowing through the driving transistor Td to the organic light emitting diode OLED is not affected by the threshold voltage Vth.

Fourth, the fifth transistor T5 is turned on in response to the nth light emission control signal EMn having a low logic voltage for a time t4. Since the nth scan pulse SPn is inverted to a high logic voltage, the first transistor T1 is turned off. The second transistor T2, the third transistor T3, and the fourth transistor T4 maintain a turn-off state.

Due to the turn-on of the fifth transistor T5, the threshold voltage Vth is compensated as shown in Equation 3 so that the current I _OLED which is not affected by the threshold voltage Vth flows to the organic light emitting diode OLED. The organic light emitting diode OLED emits light. As a result, by controlling the operation of the transistors of the pixel P according to a predetermined time t1 to t4, the current I _OLED whose threshold voltage Vth of the driving transistor Td is compensated is applied to the organic light emitting diode OLED. Will be supplied. Accordingly, the organic light emitting diode OLED may emit light at the target luminance by eliminating the deviation of the threshold voltage of the driving transistor Td generated between the plurality of pixels.

3 is a waveform diagram illustrating signals input to a pixel according to a second exemplary embodiment of the present invention. Referring to FIG. 3, an nth initialization signal ININ, an n−1th scan pulse SPn−1, an nth scan pulse SPn, and an nth emission control signal EMn are respectively applied to the pixels P. Referring to FIG. Is entered.

Each pulse of the n-th scan pulse SPn-1 and the n-th scan pulse SPn is generated at a low logic voltage for one horizontal period 1H. The pulse of the nth initialization signal ININ is generated at a low logic voltage for a predetermined time shorter than one horizontal period 1H, and the pulse of the nth emission control signal EMn is generated at a high logic voltage for two horizontal periods. .

The pulse of the n-th scan pulse SPn-1 and the pulse of the n-th light emission control signal EMn occur simultaneously. The pulse of the nth initialization signal ININ occurs for a predetermined time shorter than one horizontal period 1H. The pulse of the n-th initialization signal ININ occurs before the pulse of the n-th scan pulse SPn-1, and the pulse of the n-th scan pulse SPn-1 overlaps a portion of the pulse. The pulse of the n-th scan pulse SPn-1 is generated for one horizontal period, followed by the pulse of the n-th scan pulse SPn in one horizontal period. The pulse of the nth light emission control signal EMn is generated for two horizontal periods. Each of the pulse of the nth initialization signal ININ, the pulse of the nth-1st scan pulse SPn-1, the pulse of the nth scan pulse SPn, and the pulse of the nth emission control signal EMn is one frame period. Repeated by the cycle.

The waveform diagram of FIG. 3 differs from the waveform diagram of FIG. 2 in that the pulse of the n-th initialization signal ININ occurs earlier than the pulse of the n-th scan pulse SPn-1 and the n-th scan pulse SPn. The pulse of -1) and some sections overlap. By generating the pulse of the nth initialization signal ININ before the pulse of the n−1 th scan pulse SPn−1, the N3 node may be initialized first. As a result, the initialization time t1 of the N1 node N1 can be reduced, and the time t2 for sampling the threshold voltage Vth of the driving transistor Td can be increased. In addition, the operation of the pixel P of the present invention according to the waveform diagram of FIG. 3 is as described with reference to FIG. 2.

4 is a circuit diagram of a multiplexer and a pixel of an organic light emitting diode display according to an exemplary embodiment of the present invention. Referring to FIG. 4, the organic light emitting diode display of the present invention includes a multiplexer (MUX), an R pixel (R), a G pixel (G), and a B pixel (B). Each of the R pixel R, the G pixel G, and the B pixel B has a structure as described with reference to FIG. 1. In addition, each of the R pixel R, the G pixel G, and the B pixel B operates as described with reference to FIGS. 2 and 3.

The multiplexer MUX connects one output terminal of the data driving circuit for supplying the data voltage to the m th data line DLm and the m th data line by 1: N (N is a natural number of 2 or more). The multiplexer MUX divides the data voltage of one output terminal of the data driving circuit into N data lines DLm1, DLm2,..., DLmN. Hereinafter, as illustrated in FIG. 4, the multiplexer MUX in which one output terminal and the m-th data line of the data driving circuit are connected by 1: 3 will be described.

In FIG. 4, the data driving circuit supplies the R data voltage, the G data voltage, and the B data voltage through the m th data line DLm, and the multiplexer MUX of the present invention transfers the R data voltage to the R pixel R. In FIG. The G data voltage is supplied to the G pixel G, and the B data voltage is supplied to the B pixel B by time division.

The multiplexer MUX of the present invention includes sixth to eighth transistors T6, T7, and T8 connected to the m th data line DLm. The sixth to eighth transistors T6, T7, and T8 serve as switches. The gate electrode of the sixth transistor T6 is connected to the n th R data voltage control line RDLn, the source electrode is connected to the m th data line DLm, and the drain electrode is connected to the R pixel R. The gate electrode of the seventh transistor T7 is connected to the nth G data voltage control line GDLn, the source electrode is connected to the mth data line DLm, and the drain electrode is connected to the G pixel G. The gate electrode of the eighth transistor T8 is connected to the n-th B data voltage control line BDLn, the source electrode is connected to the m-th data line DLm, and the drain electrode is connected to the B pixel B.

FIG. 5 is a waveform diagram illustrating a multiplexer and a signal input to a pixel according to a first exemplary embodiment of the present invention. This will be described with reference to FIG. 4. 4 and 5, the n-th initialization signal ININ, the n-th scan pulse SPn-1, and the n-th pixel are included in the R pixel R, the G pixel G, and the B pixel B. Referring to FIGS. The scan pulse SPn and the n-th light emission control signal EMn are input. The n th R data voltage control signal RDn, the n th G data voltage control signal GDn, and the n th B data voltage control signal BDn are input to the multiplexer MUX. The n-th initialization signal ININ, the n-th scan pulse SPn-1, the n-th scan pulse SPn, and the n-th emission control signal EMn have been described with reference to FIG. 2.

In the case of the multiplexer MUX in which one output terminal of the data driving circuit and the m th data line are connected 1: 3, the pulse of the n th R data voltage control signal RDn and the n th G data voltage control signal GDn The pulse of and the pulse of the n-th B data voltage control signal BDn are each generated at a low logic voltage for 1/3 horizontal period (1/3 H). In the multiplexer (MUX) in which one output terminal of the data driving circuit and the m-th data line are connected by 1: N, each of the data voltage control signals input to each of the N data lines is 1 / N horizontal period (1). / NH) occurs at a low logic voltage.

The pulse of the n th R data voltage control signal RDn, the pulse of the n th G data voltage control signal GDn, and the pulse of the n th B data voltage control signal BDn are sequentially generated as shown in FIG. 5. The pulse of the n th R data voltage control signal RDn, which is the first pulse, is generated in synchronization with the pulse of the n th scan line SPn. The pulses of the n th R data voltage control signal RDn, the n th G data voltage control signal GDn, and the pulses of the n th B data voltage control signal BDn are each repeated in one frame period. .

Hereinafter, the operation of the multiplexer MUX and the pixel of the present invention according to the waveform diagram of FIG. 5 will be described in detail. This will be described with reference to FIG. 4. Since the operation of each of the R pixel R, the G pixel G, and the B pixel B has already been described above with reference to FIGS. 2 and 3, the operation of the multiplexer MUX will be described here.

4 and 5, the pulse of the n th R data voltage control signal RDn is synchronized with the pulse of the n th scan pulse SPn. The sixth transistor T6 is turned on in response to a pulse of the n-th R data voltage control signal RDn for a 1/3 horizontal period (1/3 H). The seventh transistor T7 and the eighth transistor T8 are turned off. By turning on the sixth transistor T6, the R data voltage is supplied to the R pixel R.

After 1/3 horizontal period (1/3 H), a pulse of the nth G data voltage control signal GDn is supplied to the gate electrode of the seventh transistor. The seventh transistor T7 is turned on in response to the pulse of the n-th G data voltage control signal GDn for 1/3 horizontal period (1/3 H). Since the n th data voltage control signal RDn is inverted to a high logic voltage, the sixth transistor T6 is turned off. The eighth transistor T8 maintains a turn-off state. By turning on the seventh transistor T7, the G data voltage is supplied to the G pixel G.

When 1/3 horizontal period (1/3 H) passes again, the pulse of the n-th B data voltage control signal BDn is supplied to the gate electrode of the eighth transistor. The eighth transistor T8 is turned on in response to the pulse of the n-th B data voltage control signal BDn for 1/3 horizontal period (1/3 H). Since the nth G data voltage control signal GDn is inverted to a high logic voltage, the seventh transistor T7 is turned off. The sixth transistor T6 maintains a turn-off state. With the turn-on of the eighth transistor T8, the B data voltage is supplied to the B pixel (B).

After 1/3 horizontal period (1/3 H), the n-th B data voltage control signal BDn is inverted to a high logic voltage, and thus the eighth transistor T8 is turned off. The sixth transistor T6 and the seventh transistor T7 maintain a turn-off state.

6 is a waveform diagram illustrating signals input to a multiplexer and a pixel according to a second exemplary embodiment of the present invention. Referring to FIG. 6, the R pixel R, the G pixel G, and the B pixel B may include an n th initialization signal ININ, an n−1 th scan pulse SPn−1, and an n th scan pulse ( SPn) and an nth emission control signal EMn are input. The n th R data voltage control signal RDn, the n th G data voltage control signal GDn, and the n th B data voltage control signal BDn are input to the multiplexer MUX.

The n-th initialization signal ININ, the n-th scan pulse SPn-1, the n-th scan pulse SPn, and the n-th emission control signal EMn have been described with reference to FIG. 3. The n th R data voltage control signal RDn, the n th G data voltage control signal GDn, and the n th B data voltage control signal BDn are as described with reference to FIG. 5.

Referring to the operation of the multiplexer (MUX) and the pixel of the present invention according to the waveform diagram of FIG. 6, the operation of each of the R pixel R, the G pixel, and the B pixel B will be described with reference to FIGS. 1 and 3. In the above description, the operation of the multiplexer (MUX) has been described above in connection with FIGS. 4 and 5.

FIG. 7 is a waveform diagram illustrating voltages of N1 nodes of R, G, and B pixels of FIG. 4. Referring to FIG. 7, the n th R data voltage control signal RDn, the n th G data voltage control signal GDn, the n th B data voltage control signal BDn, and the N1 node N1 of the R pixel R ), The voltage change, the N1 node N1 voltage change of the G pixel G, and the N1 node N1 voltage change of the B pixel B are shown. In FIG. 7, the data voltages supplied to the R pixel R, the G pixel G, and the B pixel B are the same.

As illustrated in FIG. 7, the N1 node voltages of each of the R pixel, the G pixel, and the B pixel are initialized to the reference voltage Vref during the first one horizontal period 1H, and then rise to the voltage VDD-Vth. During the next horizontal period 1H, when the pulse of the n-th R data voltage control signal RDn is input, the voltage of the N2 node N2 of the R pixel R becomes (Vref-Vdata). In addition, since the voltage change amount Vref-Vdata of the N2 node N2 is reflected in the N1 node N1 by the first capacitor, the N1 node N1 becomes {VDD-Vth- (Vref-Vdata)}. . Voltage changes of the N1 node N1 and the N2 node N2 have been described above in detail with reference to FIGS. 1, 2, and Equations 1 to 3.

In addition, when the pulse of the n-th G data voltage control signal GDn is input, the voltage of the N1 node N1 of the G pixel G is lowered due to the influence of the voltage Vref-Vdata of the N2 node N2. VDD-Vth- (Vref-Vdata)}. When the pulse of the n-th B data voltage control signal BDn is input, the voltage of the N1 node N1 of the B pixel B is lowered due to the influence of the voltage Vref-Vdata of the N2 node N2 {VDD-Vth -(Vref-Vdata)}. Since the current I _OLED flowing through the driving transistor Td to the organic light emitting diode OLED is not affected by the threshold voltage Vth, the threshold voltage Vth is also set to the same voltage in the experiment of FIG. 7. Therefore, the N1 node N1 voltage of the R pixel R, the N1 node N1 voltage of the G pixel G, and the N1 node N1 voltage of the B pixel B have the same voltage.

Originally, in the case of the G pixel G, after the nth scan pulse SPn is input and 1/3 horizontal period (1/3 H) has elapsed, the pulse of the nth G data voltage control signal GDn is inputted. Therefore, the voltage of the N2 node N2 is floating. If the voltage of the N2 node N2 is floating, a problem occurs in which the voltage of the N1 node N1 is reflected to the N2 node N2 by the first capacitor C1.

However, according to the present invention, since the second capacitor C2 keeps the voltage of the N2 node N2 constant, after the nth scan pulse SPn is input and 1/3 horizontal period (1/3 H) has elapsed, Even when a pulse of the n th G data voltage control signal GDn is input, the voltage change amount Vref-Vdata of the N2 node N2 may be reflected by the first capacitor C1 to the N1 node N1. The same applies to the B pixel B. FIG. Accordingly, the R data voltage of the m th data line DLm is transferred to the R pixel R by using the multiplexer MUX connecting one output terminal of the data driving circuit and the m th data line DLm to 1: N. Also, in the method of supplying the G data voltage to the G pixel G and time-dividing and supplying the B data voltage to the B pixel B, the organic light emitting diode display device of the present invention is a driving transistor of each pixel ( The threshold voltage Vth of Td may be compensated for.

8 is a block diagram schematically illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention. Referring to FIG. 8, the organic light emitting diode display of the present invention includes a display panel 10, a data driving circuit, a scan driving circuit, a timing controller 20, and the like.

The display panel 10 includes data lines DL and gate lines GL that cross each other, and a pixel array disposed in a matrix form. Each pixel of the pixel array of the display panel 10 has been described in detail above with reference to FIG. 1.

The data driver circuit includes a plurality of source drive ICs 30. The source drive ICs 30 receive the digital video data RGB from the timing controller 20. The source drive ICs 30 convert the digital video data RGB into a gamma compensation voltage in response to a source timing control signal from the timing controller 20 to generate a data voltage, and synchronize the data voltage with a scan pulse. The data lines DL of the display panel 10 are supplied. The source drive ICs may be connected to data lines DL of the display panel 10 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The scan driving circuit includes a level shifter 40 and a GIP driving circuit 50 connected between the timing controller 20 and the gate lines GL of the display panel 10. The level shifter 40 converts the TTL logic level voltages of the gate shift clocks (GCLKs) input from the timing controller 20 to the gate high voltage VGH and the gate low voltage VGL. Level shift

The GIP driving circuit 50 is connected to the gate lines GL and connected to shift registers and initialization lines IL that output scan pulses SP to control the scan transistor Tscan of each pixel. An initialization control unit outputs an initialization signal INI for controlling initialization of each pixel, and an emission control unit connected to the emission line EL to output an emission control signal EM for controlling emission of each pixel.

The shift register shifts the gate start pulse GSP to the gate shift clocks GCLKs to output the scan pulse SP. The initialization controller outputs an initialization signal INI for controlling initialization of each pixel through the initialization line IL, and the emission controller outputs an emission control signal EM for controlling emission through the emission control line EL. . The initialization signal INI and the emission control signal EM may be calculated from timing signals output from the timing controller 20. The scan pulse SP, the initialization pulse INI, and the emission control signal EM have been described with reference to FIGS. 2 and 3.

The GIP driving circuit 50 is directly formed on the lower substrate of the display panel 10 by a gate drive-IC in panel (GIP) method. The GIP driving circuit 50 may be connected between the gate lines GL of the display panel 10 and the timing controller 20 in a TAB manner. In the GIP method, the level shifter 40 may be mounted on a printed circuit board (PCB) 60, and the GIP driving circuit 50 may be formed on the lower substrate of the display panel 10.

The timing controller 20 receives digital video data (RGB) from an external host computer through an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. The timing controller 20 transmits digital video data RGB input from the host computer to the source drive ICs 30.

The timing controller 20 uses the LVDS or TMDS interface receiving circuits to control the timing of the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal Data Enable, and the main clock MCLK. Receive a signal. The timing controller 20 generates timing control signals for controlling the operation timing of the data driving circuit and the scan driving circuit based on the timing signal from the host computer. The timing control signals include a scan timing control signal for controlling the operation timing of the scan driving circuit, and a data timing control signal for controlling the operation timing of the source drive ICs 30 and the polarity of the data voltage.

The scan timing control signal includes a gate start pulse GSP, gate shift clocks, a gate output enable signal GOE, and the like. The gate start pulse GSP is input to the GIP driving circuit 50 to control the shift start timing. The gate shift clocks GCLKs are input to the level shifter 40 and level shifted, and then input to the GIP driving circuit 50, and are used as clock signals for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the GIP driving circuit 50.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (Polarity, POL), a source output enable signal (Source Output Enable, SOE), and the like. It includes. The source start pulse SSP controls the shift start timing of the source drive ICs 30. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 30 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltages output from the source drive ICs. If the data transfer interface between the timing controller 20 and the source drive ICs 30 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

The voltage level of the low logic voltage is equal to the gate low voltage VGL, and the voltage level of the high logic voltage is equal to the gate high voltage VGH. The gate low voltage VGL may be set to −0 V to 5 V, and the gate high voltage VGH may be set to 10 V to 15 V.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

10: display panel 20: timing controller
30: source drive IC 40: level shifter
50: GIP drive circuit 60: PCB

Claims (9)

Mth (m is a natural number) data line, n-1 (n is a natural number) gate line, nth gate line, nth initialization line, nth light emission control line, and the mth data line and the includes a plurality of pixels defined by n gate lines,
Each of the pixels,
Organic light emitting diodes;
A first capacitor formed between the first node and the second node;
A second capacitor formed between a power supply voltage source and the second node;
A driving transistor configured to differently adjust an amount of current flowing to the organic light emitting diode according to the voltage of the first node;
A first transistor configured to supply a data voltage to the second node in response to an nth scan pulse of the nth gate line;
A second transistor configured to supply a reference voltage to the second node in response to an n−1 th scan pulse of the n−1 th gate line generated before the n th scan pulse;
A third transistor connecting the first node and the third node between the organic light emitting diode and the driving transistor in response to the n−1 th scan pulse;
A fourth transistor configured to supply the reference voltage to the third node in response to an nth initialization signal of the nth initialization line which is generated before the nth scan pulse; And
A fifth transistor configured to supply a voltage of the third node to an anode electrode of the organic light emitting diode in response to an nth light emission control signal of the nth light emission control line synchronized with the n−1th scan pulse;
And the reference voltage is a voltage for initializing the first to third nodes. The method of claim 1,
Each pulse of the n-th scan pulse and the n-th scan pulse is generated at a low logic voltage for one horizontal period,
The pulse of the n-th initialization signal is generated at a low logic voltage for a predetermined time shorter than the one horizontal period,
And the pulse of the nth light emission control signal is generated at a high logic voltage for two horizontal periods. The method of claim 2,
And the pulse of the n-th scan pulse and the pulse of the n-th initialization signal are synchronized with each other. The method of claim 2,
The pulse of the n-th initialization signal is generated before the pulse of the n-th scan pulse, and a portion of the pulse of the n-th initialization signal overlaps with a pulse of the n-th scan pulse. An organic light emitting diode display device. The method of claim 1,
A data driving circuit which supplies the data voltage to the mth data line; And
And a multiplexer for connecting one output terminal of the data driving circuit and the m-th data line to 1: N (N is a natural number of 2 or more) and time-divisionally supplying the data voltage of the output terminal to N data lines. Organic light emitting diode display. The method of claim 5, wherein
The multiplexer comprising:
And first through N-th transistors for switching the data voltage of the output terminal to each of the N data lines. The method according to claim 6,
And a pulse of the first through Nth data voltage control signals for controlling the operation of each of the first through Nth transistors is generated at a low logic voltage during a 1 / N horizontal period. The method of claim 7, wherein
And the pulses of the first to Nth data voltage control signals are sequentially generated. The method of claim 7, wherein
And the pulse of the first data voltage control signal is synchronized with the pulse of the nth scan pulse.

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