KR20170081078A - Organic Light Emitting Display and Device for driving the same - Google Patents

Abstract

The present invention relates to an organic light emitting display and a driving apparatus thereof, and includes a gate driving circuit for supplying a scan signal and a light emission control signal to pixels. The gate driving circuit includes a signal generating circuit for outputting a signal including first and second pulses, and a second switching circuit for separating the first and second pulses of the signal received from the signal generating circuit in response to the first and second switch clocks And a switch circuit for supplying the first pulse to the first pixel and then supplying the second pulse to the second pixel. The first switch clock is synchronized with the first pulse, and the second switch clock is synchronized with the second pulse. The present invention can reduce the size of the GIP circuit by separating into two using a switch circuit.

Description

[0001] The present invention relates to an organic light emitting display,

The present invention relates to an organic light emitting display including a circuit for outputting a scan signal and a light emission control signal (EM), and a driving apparatus therefor.

The active matrix type organic light emitting display device includes an organic light emitting diode (OLED) which emits light by itself, has a high response speed, and has a high luminous efficiency, luminance, and viewing angle. The OLED includes an organic compound layer formed between the anode and the cathode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL) and the like. When a drive voltage is applied to the anode and the cathode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emission layer (EML) to form excitons, Thereby generating visible light.

The driving circuit of the OLED display device includes a data driving circuit for generating a data signal and a gate driving circuit for generating a scanning signal and a light emission control signal (hereinafter referred to as " EM " signal). The gate driving circuit includes a scan driver for generating a scan signal and an EM driver for generating an EM signal. The scan driver sequentially supplies a scan signal synchronized with the data signal to the scan lines during the compensation time of the pixel using a shift register. The scan signal is generated as an On level signal in synchronization with the data signal in order to compensate the threshold voltage of the transistor used as the driving element of the pixel. Hereinafter, the ON level is a voltage level at which the transistor is turned on. The Off Level is the voltage level at which the transistor is turned off. The EM driver sequentially outputs EM signals using a shift register and an inverter as shown in FIG. Level pulse during the compensation time of the pixel, and then maintains the ON level after the compensation time of the pixel to emit the OLED.

The EM driver includes a shift register for sequentially generating EM signals and an inverter for inverting the output of the shift register to sequentially shift the EM signal and supply the shifted EM signal to the EM signal lines . The shift register includes latches SR (n), SR (n + 1) that are connected in a dependent manner. n is a positive integer. The shift register sequentially receives the start pulse VST and the shift clocks CLK (n) and CLK (n + 1) and outputs them sequentially. In the latches SR (n) and SR GST is a start pulse input terminal and Out is an output terminal. The inverter includes a plurality of inverters INV (n), INV (n + 1) connected in 1: 1 to the output terminals of the shift register .

2, SCAN (n) and EM (n) are scan signals and EM signals applied to the n-th pixel PXL (n) arranged on the n-th line of the display panel. SCAN (n + 1) and EM (n + 1) are scan signals and EM signals applied to the (n + 1) th pixel PXL (n + 1) disposed on the (n + 1) th line of the display panel.

The gate driving circuit may be disposed directly on the display panel 100 together with the pixel array in a gate-driver In Panel (GIP) process. Hereinafter, such a gate driving circuit is referred to as a " GIP circuit ". In the GIP circuit, the scan driver and the EM driver are formed on a bezel which is a non-display area of the display panel.

The unit channel width of the signal generating circuit that generates one output in each of the scan driver and the EM driver must be designed within the height of the pixels PXL (n) and PXL (n + 1). As a result, the GIP circuit is formed to be long along the width direction of the bezel, thereby increasing the width of the bezel. The unit channel means a circuit which generates one output, and includes one latch SR (n) in the example of FIG. 1 and one inverter Inv connected to the latch. In the case of a high-resolution / high-density display panel, since the pixel height is small, in order to maintain the same circuit area, the GIP circuit becomes larger in width as the height decreases, resulting in an increase in the bezel width. Therefore, the current GIP circuit has a large circuit area, which makes narrow bezel design of the display panel difficult.

The present invention provides an organic light emitting display device and a driving apparatus thereof that can reduce the size of a GIP circuit.

The organic light emitting diode display of the present invention includes a display panel on which pixels are arranged, and a gate driving circuit for supplying a scan signal and a light emission control signal to the pixels.

The gate driving circuit includes a signal generating circuit for outputting a signal including first and second pulses, and a second switching circuit for separating the first and second pulses of the signal received from the signal generating circuit in response to the first and second switch clocks And a switch circuit for supplying the first pulse to the first pixel and then supplying the second pulse to the second pixel.

The first switch clock is synchronized with the first pulse, and the second switch clock is synchronized with the second pulse.

The first pulse supplied to the first pixel and the second pulse supplied to the second pixel are the scan signal or the emission control signal.

The driving circuit generates the output signal in response to a clock including first and second pulses. The first pulse of the clock is synchronized with the first switch clock, and the second pulse of the clock is synchronized with the second switch clock.

After the first pulse is output through the first output terminal of the switch circuit, the second pulse is output through the second output terminal of the switch circuit.

Wherein the switch circuit comprises: a first switch element responsive to the first switch clock for outputting a first pulse of a signal received from the drive circuit through the first output terminal; A second switch element for outputting a second pulse of a signal received from the second output terminal through the second output terminal, a third switch element for outputting an off level voltage through the second output terminal in response to the first switch clock, And a fourth switch element for outputting an off level voltage through the first output terminal in response to the second switch clock.

The driving apparatus of the OLED display includes a scan driver for generating the scan signal and an EM driver for outputting the emission control signal.

Wherein at least one of the scan driver and the EM driver separates the first and second pulses of the input signal in response to the first and second switch clocks to supply the first pulse to the first pixel, And a switch circuit for supplying the second pixel to the second pixel.

The present invention can realize the narrow bezel of the display panel by reducing the size of the GIP circuit by dividing the first and second pulses of the output signal of the unit channel into two by using the switch circuit in the GIP circuit.

1 is a diagram showing a conventional GIP circuit configuration.
2 is a waveform diagram showing an input / output waveform of the GIP circuit shown in FIG.
3 is a circuit diagram showing a GIP circuit configuration according to the first embodiment of the present invention.
4 is a waveform diagram showing an input / output waveform of the GIP circuit shown in FIG.
5 is a waveform diagram showing an input / output waveform of the GIP circuit according to the second embodiment of the present invention.
6 is a block diagram illustrating a GIP circuit according to a second embodiment of the present invention.
7 is a circuit diagram showing a part of the GIP circuit shown in FIG. 6 in detail.
8 is a waveform diagram showing an input / output waveform of the GIP circuit according to the third embodiment of the present invention.
9 is a block diagram illustrating a GIP circuit according to a third embodiment of the present invention.
10 is a circuit diagram showing a part of the GIP circuit shown in FIG. 9 in detail.
11 is a block diagram showing a GIP circuit according to a fourth embodiment of the present invention.
12 is a view showing a bezel reducing effect due to a size reduction of the GIP circuit of the present invention.
13 is a block diagram showing an organic light emitting diode display of the present invention.
14A and 14B are diagrams illustrating a pixel circuit and its operation according to an embodiment of the present invention.
15A and 15B are diagrams illustrating a pixel circuit and its operation according to another embodiment of the present invention.
Figs. 16A to 16D are diagrams showing stepwise the internal compensation method of the pixel circuit shown in Fig.
17 is a circuit diagram showing an example of a latch circuit in the shift register circuit of the scan driver.
18A to 18H are views showing the operation of the latch shown in Fig.
19 is a diagram showing an example of an inverter circuit of the EM driver.
20A to 20D are views showing the operation of the inverter shown in Fig.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

FIG. 3 and FIG. 4 are views showing the configuration of a GIP circuit according to the first embodiment of the present invention. In Fig. 4, CLK1 and CLK2 are shift clocks, and SWCLK1 and SWCLK2 are switch clocks. OUT (n / n + 1) is an output signal of the unit channel SC / EM (n / n + 1).

3 and 4, the OLED display of the present invention includes a display panel on which pixels PXL (n) and PXL (n + 1) and a GIP circuit 30 for supplying at least one of a scan signal and an EM signal to the scan electrodes (n + 1) and (n + 1).

The GIP circuit 30 of the present invention includes a signal generation circuit for outputting at least one of a scan signal and a light emission control signal and a switch circuit for separating pulses from an output signal of the signal generation circuit.

The unit channel SC / EM (n / n + 1) of the signal generating circuit outputs a signal in which the first pulse and the second pulse are continuous through one output terminal.

The unit channel SC / EM (n / n + 1) receives the shift clock CLK1 in which the first and second pulses 31 and 32 of the ON level are successively generated. / n + 1) outputs the output signal OUT (n / n + 1) including the first and second pulses through one output terminal. The first and second pulses are generated at the ON level. The first pulse 31 of the shift clock CLK1 is synchronized with the first switch clock SWCLK1 and the second pulse 32 is synchronized with the second switch clock SWCLK2.

The switch circuit SW includes first to fourth switch elements S1 to S4. The switch circuit SW outputs the output signal OUT (n / n + 1) of the unit channel SC / EM (n / n + 1) in response to the first and second switch clocks SWCLK1 and SWCLK2 (N) and SCAN / EM (n + 1) by separating the first and second pulses 33, The switch circuit SW supplies the first pulse to the n-th pixel PXL (n) by separating the first and second pulses 33 and 34 and then supplies the second pulse to the (n + 1) -th pixel PXL +1). The first switch clock SWCLK1 is synchronized with the first pulse 33 and the second switch clock SWCLK2 is synchronized with the second pulse 34. [ The first and second pulses may be either a scan signal or an EM signal.

The switch elements S1 to S4 are connected to a thin film transistor (TFT) as in the case of the transistors constituting the pixels PXL (n), PXL (n + 1) and the unit channel SC / EM In the p-type MOSFET, the ON level is set to be a constant level, and the switching elements S1 to S4 may be implemented as a transistor of a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) The first switch clock SWCLK1 is a gate-low voltage VGL and the off-level voltage is a gate high voltage VGH. VGH is a voltage higher than VGL Hereinafter, the switch elements S1 to S4 are referred to as TFTs. Is synchronized with the first pulse 33 of OUT (n / n + 1). The first TFT S1 is responsive to the first switch clock SWCLK1 to output the first pulse of OUT (n / n + 1) 33) to the n-th pixel PXL (n) via the first output terminal. The first TFT S1 has a gate to which the first switch clock SWCLK1 is input, a source connected to the first output terminal, The drain connected to the input terminal OUT (n / n + 1) from the unit channel of the signal generating circuit is received at the input terminal of the switch circuit SW.

The fourth TFT S4 supplies the off-level voltage VGH to the second output terminal in response to the first switch clock SWCLK1. Therefore, when the first switch clock signal SWCLK1 is generated, the first pulse of the on-level voltage VGL is outputted through the first output terminal of the switch circuit SW and at the same time, the second output of the switch circuit SW The off-level voltage VGH is output through the terminal. The fourth TFT S4 includes a gate to which the first switch clock SWCLK1 is input, a drain connected to the second output terminal, and a source to which the off level voltage VGH is supplied.

The second switch clock (SWCLK2) is generated following the first switch clock (SWCLK1). And the second switch clock SWCLK2 is synchronized with the second pulse 34 of OUT (n / n + 1).

The second TFT S2 outputs the second pulse 34 of OUT (n / n + 1) through the second output terminal in response to the second switch clock SWCLK2 to the (n + 1) th pixel PXL ). The second TFT S2 includes a gate to which the second switch clock SWCLK2 is input, a source coupled to the second output terminal, and a drain to which OUT (n / n + 1) is input. The drains of the first and second TFTs S1 and S2 are connected to an input terminal to which OUT (n / n + 1) is input.

The third TFT (S3) supplies the off-level voltage (VGH) to the first output terminal in response to the second switch clock (SWCLK2). Thus, when the second switch clock signal SWCLK2 is generated, a second pulse of the on level voltage VGL is outputted through the second output terminal of the switch circuit SW, and at the same time, the first output of the switch circuit SW The off-level voltage VGH is output through the terminal. The third TFT S3 includes a gate to which the second switch clock SWCLK2 is input, a drain connected to the first output terminal, and a source to which the off level voltage VGH is supplied. The sources of the third and fourth TFTs S3 and S4 are connected to a power input terminal VGH / VGL.

When the switch elements of the switch circuit SW are implemented as n-type MOSFETs, the phases of the shift clocks CLK1 and CLK2 and the switch clocks SWCLK1 and SWCLK2 input to the signal generation circuit are inverted, The off level voltage supplied to the elements S3 and S4 is changed to the gate low voltage VGL.

The GIP circuit of the present invention divides first and second pulses output from a unit channel (SC / EM (n / n + 1)) into two by using a switch circuit (SW) The present invention can increase the height of one unit channel circuit in the GIP circuit by the height of the vertically neighboring pixels * 2, as shown in FIG. 3 As a result, the present invention can reduce the width of the GIP circuit by reducing the size of the GIP circuit and increasing the height of the unit channel circuit. By reducing the area, the narrow bezel can be implemented in a high-resolution, high-resolution / high-density display panel.

The switch circuit SW of the present invention can be applied to various GIP circuits.

5 is a waveform diagram showing an input / output waveform of the GIP circuit according to the second embodiment of the present invention. In Fig. 5, 1H means one horizontal period. 6 is a block diagram illustrating a GIP circuit according to a second embodiment of the present invention. 7 is a circuit diagram showing a part of the GIP circuit shown in FIG. 6 in detail.

5 to 7, the GIP circuit 30 includes two scan signals SCAN1 (n / n + 1) and SCAN2 (n / n + 1) can be generated and supplied to each of the pixels PXL1 to PXL4.

The GIP circuit 30 includes a first scan driver 62 for sequentially outputting an on-level A scan signal SCAN1 (n / n + 1), a second scan driver 62 for receiving the output of the first scan driver 62, An EM driver 66 for outputting an EM signal EM (n / n + 1) of the on-level and a second scan driver 64 for sequentially outputting an on-level B scan signal SCAN2 ). The first scan driver 62 includes a first scan driver SC1 (1/2), a first switch SC1 (3/4), and a first switch circuit SWC1 (1/2), SWC1 (3/4) And a shift register. The second scan driver 64 includes a second scan driver SC2 (1/2), a second switch SC2 (3/4) and a switch circuit SWC2 (1/2), SWC2 (3/4) And a shift register. The EM driver 66 includes a plurality of inverters INV (1/2), INV (3/4).

The first and second shift registers may be separated from each other in the display panel via the pixel arrays PXL1 to PXL4 and disposed in the left and right bezels, respectively. The arrangement of the first and second shift registers is not limited to Fig.

The first shift register includes latches SC1 (1/2) and SC1 (n) which sequentially output the A scan signal SCAN1 (n / n + 1) in response to the start pulse G1VST and the shift clocks G1CLK1 to G1CLK4, (1/2), SWC1 (3/4) arranged between the latches SC1 (1/2) and SC1 (3/4)) and the latches SC1 . The latches SC1 (1/2) and SC1 (3/4)) and the switch circuits SWC1 (1/2) and SWC1 (3/4) are connected so that one switch circuit is connected between neighboring latches in the first shift register. 3/4) are arranged alternately. Each of the switch circuits SWC1 (1/2) and SWC1 (3/4) receives one latch output in response to the first and second switch clocks SWCLK1 and SWCLK2, Time-dividing the two pulses.

The start pulse G1VST is input to the first latch SC1 (1/2) to control the drive start timing of the first shift register. The start pulse G1VST may be synchronized with the second pulse of the third shift clock G1CLK3 and the first pulse of the fourth shift clock G1CLK4 as shown in FIG. 5, but is not limited thereto. The shift clocks G1CLK1 to G1CLK4 are sequentially shifted in phase. The shift clocks G1CLK1 to G1CLK4 include first and second pulses, respectively.

Each of the latches SC1 (1/2) and SC1 (3/4) of the first shift register is responsive to the first and second pulses of the shift clocks G1CLK1 to G1CLK4, And continuously outputs the second pulse.

The first latch SC1 (1/2) latches the start pulse G1VST and sequentially outputs the first pulse and the second pulse in response to the first and second pulses of the shift clocks G1CLK1, G1CLK3 and G1CLK4 . The output signal of the first latch SC1 (1/2) is supplied to the first inverter INV (1/2) and the first switch circuit SWC1 (1/2) of the EM driver through one output terminal do.

The first inverter INV (1/2) inverts and latches the first and second pulses from the first latch SC1 (1/2) and toggles the output at the falling edge of the end clock EndCLK And sequentially outputs the first and second EM signals separated from the polling edge of the end clock (EndCLK) as shown in FIG. The first and second EM signals outputted from the first inverter INV (1/2) are simultaneously supplied to the first and second pixels PXL1 and PXL2. The first pixel PXL1 is disposed in the first line of the display panel. And the second pixel PXL2 is disposed in the second line of the display panel.

The first switch circuit SWC1 (1/2) includes the first to fourth TFTs S1 to S4. The first switch circuit SWC1 (1/2) separates the first and second pulses input from the first latch SC1 (1/2) in response to the first and second switch clocks SWCLK1 and SWCLK2 do. The first pulse is supplied to the first pixel PXL1 as the first A scan signal SCAN112. The second pulse is supplied to the start terminal of the second latch SC1 (3/4) while being supplied to the second pixel PXL2 as the second A scan signal SCAN12.

The second latch SC1 3/4 latches the second pulse input from the first switch circuit SWC1 (1/2) and outputs the first and second pulses of the shift clocks G1CLK1, G1CLK2 and G1CLK3 And outputs the first and second pulses in succession in response. The output signal of the second latch SC1 (3/4) is supplied to the second inverter INV (3/4) and the second switch circuit SWC1 (3/4) through one output terminal.

The second inverter INV (3/4) inverts and latches the first and second pulses from the second latch SC1 (3/4) and toggles the output at the falling edge of the end clock (EndCLK) And sequentially outputs two third and fourth EM signals separated from the falling edge of the clock EndCLK. The third and fourth EM signals output from the second inverter INV (3/4) are simultaneously supplied to the third and fourth pixels PXL3 and PXL4. And the third pixel PXL3 is disposed in the third line of the display panel. The fourth pixel PXL4 is disposed in the fourth line of the display panel.

The second switch circuit SWC1 (3/4) includes the first to fourth TFTs S1 to S4. The second switch circuit SWC1 (3/4) separates the first and second pulses input from the second latch SC1 (3/4) in response to the first and second switch clocks SWCLK1 and SWCLK2 do. The first pulse is supplied to the third pixel PXL3. The fourth pulse is supplied to the fourth pixel PXL4 and simultaneously supplied to the start terminal of the third latch (not shown).

The second shift register includes latches SC2 (1/2) and SC2 (n) which sequentially output the B scan signal SCAN2 (n / n + 1) in response to the start pulse G2VST and the shift clocks G2CLK1 to G2CLK4, (1/2), SWC2 (3/4) arranged between the latches SC2 (1/2) and SC2 (3/4)) and the latches SC2 . The rising edge of the B scan signal SCAN2 has a phase earlier than the rising timing of the A scan signal SCAN1 by a predetermined initialization period (refer to FIGS. 14A and 14B) and the B scan signal SCAN2 falling edge can be synchronized to the falling edge of the A scan signal SCAN1.

The start pulse G2VST is input to the first latch SC2 (1/2) to control the drive start timing of the second shift register. The start pulse G2VST may be synchronized with the second pulse of the third shift clock G2CLK3 and the first pulse of the fourth shift clock G2CLK4 as shown in FIG. The shift clocks G2CLK1 to G2CLK4 are sequentially shifted in phase. The shift clocks G2CLK1 to G2CLK4 include first and second pulses, respectively.

Each of the latches SC2 (1/2) and SC2 (3/4) of the second shift register is responsive to the first and second pulses of the shift clocks G2CLK1 to G2CLK4, And continuously outputs the second pulse.

The first latch SC2 (1/2) latches the start pulse G2VST and sequentially outputs the first pulse and the second pulse in response to the first and second pulses of the shift clocks G2CLK1, G2CLK3, and G2CLK4 . The output signal of the first latch SC2 (1/2) is supplied to the first switch circuit SWC2 (1/2) through one output terminal.

The first switch circuit SWC2 (1/2) includes the first to fourth TFTs S1 to S4. The first switch circuit SWC2 (1/2) separates the first and second pulses input from the first latch SC2 (1/2) in response to the first and second switch clocks SWCLK1 and SWCLK2 do. The first pulse is supplied to the first pixel PXL1 as the first B scan signal SCAN21. The second pulse is supplied to the start terminal of the second latch SC1 (3/4) while being supplied to the second pixel PXL2 as the first B scan signal SCAN22.

The second latch SC2 3/4 latches the second pulse inputted from the first switch circuit SWC2 (1/2) and outputs the first and second pulses of the shift clocks G1CLK1, G1CLK2 and G1CLK3 And outputs the first and second pulses in succession in response. The output signal of the second latch SC2 (3/4) is supplied to the second switch circuit SWC2 (3/4) through one output terminal.

The second switch circuit SWC2 (3/4) includes the first to fourth TFTs S1 to S4. The second switch circuit SWC2 (3/4) separates the first and second pulses input from the second latch SC2 (3/4) in response to the first and second switch clocks SWCLK1 and SWCLK2 do. The first pulse is supplied to the third pixel PXL3. The fourth pulse is supplied to the fourth pixel PXL4 and simultaneously supplied to the start terminal of the third latch (not shown).

8 is a waveform diagram showing an input / output waveform of the GIP circuit according to the third embodiment of the present invention. In Fig. 8, 1H means one horizontal period. 9 is a block diagram illustrating a GIP circuit according to a third embodiment of the present invention. 10 is a circuit diagram showing a part of the GIP circuit shown in FIG. 9 in detail.

8 to 10, the GIP circuit 30 generates one scan signal SCAN (n / n + 1) and one EM signal EM (n / n + 1) PXL1 to PXL4, respectively.

The GIP circuit 30 includes a scan driver 92 for sequentially outputting an ON level scan signal SCAN (n / n + 1) and a scan driver 92 for sequentially outputting an OFF level EM signal EM (n / n + 1) And an EM driver 96 for outputting the EM driving signal. The scan driver includes a first shift register in which the latches SC (1/2) and SC (3/4) and the switch circuits SWC (1/2) and SWC (3/4) are connected in a dependent manner . The EM driver includes a second shift register in which the inverters INV (1/2) and INV (3/4) and the switch circuits SWE (1/2) and SWE (3/4) are connected in a dependent manner .

The first and second shift registers may be separated from each other in the display panel via the pixel arrays PXL1 to PXL4 and disposed in the left and right bezels, respectively. The arrangement of the first and second shift registers is not limited to Fig.

The first shift register includes latches SC (1/2) and SC (n) for sequentially outputting the scan signal SCAN (n / n + 1) in response to the start pulse GVST and the shift clocks GCLK1 to GCLK4, (SWC (1/2), SWC (3/4)) arranged between the latches SC (1/3/4)) and the latches SC do. The latches SC (1/2) and SC (3/4)) and the switch circuits SWC (1/2) and SWC (3/4) are connected so that one switch circuit is connected between the adjacent latches in the first shift register. 3/4) are arranged alternately. Each of the switch circuits SWC (1/2) and SWC (3/4) receives one latch output in response to the first and second switch clocks SWCLK1 and SWCLK2, Time-dividing the two pulses.

The start pulse GVST is input to the first latch SC (1/2) to control the drive start timing of the first shift register. The start pulse GVST may be synchronized with the first pulse of the third shift clock GCLK3 and the first pulse of the fourth shift clock GCLK4 as shown in FIG. 8, but is not limited thereto. The phases of the shift clocks GCLK1 to GCLK4 are sequentially shifted. The shift clocks GCLK1 to GCLK4 include first and second pulses, respectively.

Each of the latches SC (1/2) and SC (3/4) of the first shift register is responsive to the first and second pulses of the shift clocks GCLK1 to GCLK4, And continuously outputs the second pulse.

The first latch SC (1/2) latches the start pulse GVST and successively outputs the first and second pulses in response to the first and second pulses of the shift clocks GCLK1, G1CLK3 and G1CLK4 . The output signal of the first latch SC (1/2) is supplied to the first switch circuit SWC (1/2) through one output terminal.

The first switch circuit SWC (1/2) includes the first to fourth TFTs S1 to S4. The first switch circuit SWC (1/2) separates the first and second pulses input from the first latch SC (1/2) in response to the first and second switch clocks SWCLK1 and SWCLK2 do. The first pulse is supplied to the first pixel PXL1. The second pulse is supplied to the start terminal of the second latch SC (3/4) while being supplied to the second pixel PXL2.

The second latch SC 3/4 latches the second pulse input from the first switch circuit SWCl (1/2) and outputs the first and second pulses of the shift clocks GCLK1, GCLK2 and GCLK3 And outputs the first and second pulses in succession in response. The output signal of the second latch SC (3/4) is supplied to the second switch circuit SWC (3/4) through one output terminal.

The second switch circuit SWC (3/4) includes the first to fourth TFTs S1 to S4. The second switch circuit SWC (3/4) separates the first and second pulses input from the second latch SC (3/4) in response to the first and second switch clocks SWCLK1 and SWCLK2 do. The first pulse is supplied to the third pixel PXL3. The fourth pulse is supplied to the fourth pixel PXL4 and simultaneously supplied to the start terminal of the third latch (not shown).

The second shift register includes inverters INV (1/2) and INV (n) which sequentially output the EM signal EM (n / n + 1) in response to the start pulse EVST and the shift clocks ECLK1 to ECLK4, 3/4)) and switch circuits SWE (1/2), SWE (3/4) arranged between the inverters INV (1/2). In the second shift register, Inverters INV (1/2) and INV (3/4) and switch circuits SWE (1/2) and SWE (3/4) are alternately switched so that one switch circuit is connected between the inverters . Each of the switch circuits SWE (1/2) and SWE (3/4) receives one inverter output in response to the first and second switch clocks SWCLK1 and SWCLK2, Time-dividing the two pulses.

The first inverter INV (1/2) receives the start pulse EVST and the shift clocks ECLK1 through ECLK4 and outputs first and second off-level pulses in the inverted signal form of the shift clocks ECLK1 through ECLK4 Sequentially. The first and second pulses output from the first inverter INV (1/2) are supplied to the first switch circuit SWE (1/2).

The first switch circuit SWE (1/2) includes the first to fourth TFTs S1 to S4. The first switch circuit SWC2 (1/2) separates the first and second pulses inputted from the first inverter INV (1/2) in response to the first and second switch clocks SWCLK1 and SWCLK2 do. The first pulse is supplied to the first pixel PXL1 as the first EM signal EM1. The second pulse is supplied to the second pixel PXL2 as the second EM signal EM2.

The second inverter INV 3/4 receives the second pulse and the shift clocks ECLK1 to ECLK4 from the second switch circuit SWE (1/2) and outputs the inverted signal form of the shift clocks ECLK1 to ECLK4 And sequentially outputs the first and second pulses of the off-level. The first and second pulses output from the second inverter INV (3/4) are supplied to the second switch circuit SWE (3/4).

The second switch circuit SWE (3/4) includes the first to fourth TFTs S1 to S4. The second switch circuit SWC (3/4) separates the third and fourth pulses inputted from the second inverter INV (3/4) in response to the first and second switch clocks SWCLK1 and SWCLK2 do. The first pulse is supplied to the third pixel PXL3 as the third EM signal. The second pulse is supplied to the fourth pixel PXL4 as the fourth EM signal.

11 is a block diagram showing a GIP circuit according to a fourth embodiment of the present invention.

Referring to FIG. 11, the GIP circuit 30 may generate A and B scan signals and one EM signal to supply to each of the pixels PXL1 to PXL4.

The GIP circuit 30 includes a first scan driver 112 for sequentially outputting an A scan signal at an on level and an EM driver 116 for receiving an output of the first scan driver 112 and outputting an EM signal at an off- And a second scan driver 114 sequentially outputting an on-level B scan signal. The first scan driver 112 includes a first scan driver SC1 (1/2), a first switch SC1 (3/4), and a first switch circuit SWC1 (1/2), SWC1 (3/4) And a shift register. The second scan driver 114 is connected between the latches SC2 (1/2) and SC2 (3/4) and the switch circuits SWC2 (1/2) and SWC2 (3/4) And a shift register.

The first and second shift registers may be separated from each other in the display panel via the pixel arrays PXL1 to PXL4 and disposed in the left and right bezels, respectively. The arrangement of the first and second shift registers is not limited to Fig.

The first shift register includes latches SC1 (1/2), SC1 (3/4)) for sequentially outputting the A scan signal in response to the start pulse G1VST and the shift clocks G1CLK1 to G1CLK4, (SW1 (1/2), SWC1 (3/4)) disposed between the switches SC1 (1/2) and SC1 (3/4). The latches SC1 (1/2) and SC1 (3/4)) and the switch circuits SWC1 (1/2) and SWC1 (3/4) are connected so that one switch circuit is connected between neighboring latches in the first shift register. 3/4) are arranged alternately. Each of the switch circuits SWC1 (1/2) and SWC1 (3/4) receives one latch output in response to the first and second switch clocks SWCLK1 and SWCLK2, Time-dividing the two pulses.

Each of the latches SC1 (1/2) and SC1 (3/4) of the first shift register is responsive to the first and second pulses of the shift clocks G1CLK1 to G1CLK4, And continuously outputs the second pulse. The first latch SC1 (1/2) latches the start pulse G1VST and sequentially outputs the first pulse and the second pulse in response to the first and second pulses of the shift clocks G1CLK1, G1CLK3 and G1CLK4 . The output signal of the first latch SC1 (1/2) is supplied to the first inverter INV (1/2) and the first switch circuit SWC1 (1/2) of the EM driver through one output terminal do.

The first switch circuit SWC1 (1/2) includes the first to fourth TFTs S1 to S4. The first switch circuit SWC1 (1/2) separates the first and second pulses input from the first latch SC1 (1/2) in response to the first and second switch clocks SWCLK1 and SWCLK2 do. The first pulse is supplied to the first pixel PXL1. The second pulse is supplied to the start terminal of the second latch SC1 (3/4) while being supplied to the second pixel PXL2.

The second latch SC1 3/4 latches the second pulse input from the first switch circuit SWC1 (1/2) and outputs the first and second pulses of the shift clocks G1CLK1, G1CLK2 and G1CLK3 And outputs the first and second pulses in succession in response. The output signal of the second latch SC1 3/4 is supplied to the second inverter INV 3/4 and the second switch circuit SWC1 3/4 of the EM driver through one output terminal do.

The second switch circuit SWC1 (3/4) includes the first to fourth TFTs S1 to S4. The second switch circuit SWC1 (3/4) separates the first and second pulses input from the second latch SC1 (3/4) in response to the first and second switch clocks SWCLK1 and SWCLK2 do. The first pulse is supplied to the third pixel PXL3. The fourth pulse is supplied to the fourth pixel PXL4 and simultaneously supplied to the start terminal of the third latch (not shown).

The EM driver 116 includes the inverters INV (1/2) and INV (3/4) and the switch circuits SWE (1/2) and SWE (3/4) which are connected in a dependent manner. One switch circuit SWE (1/2), SWE (3/4) is disposed between adjacent inverters INV (1/2) and INV (3/4).

The first inverter INV (1/2) inverts and latches the first and second pulses from the first latch SC1 (1/2) and toggles the output at the falling edge of the end clock EndCLK And sequentially outputs the first and second EM signals separated from the falling edge of the end clock (EndCLK) as shown in FIG. The first and second EM signals output from the first inverter INV (1/2) are supplied to the first switch circuit SWE (1/2).

The first switch circuit SWE (1/2) includes the first to fourth TFTs S1 to S4. The first switch circuit SWE (1/2) outputs the first and second EM signals inputted from the first inverter INV (1/2) in response to the first and second switch clocks SWCLK1 and SWCLK2 Separate. The first EM signal is supplied to the first pixel PXL1. The second EM signal is supplied to the second pixel PXL2.

The second inverter INV (3/4) inverts and latches the first and second pulses from the second latch SC1 (3/4) and toggles the output at the falling edge of the end clock EndCLK And sequentially outputs the third and fourth EM signals separated at the falling edge of the end clock (EndCLK) as shown in FIG. The third and fourth EM signals output from the second inverter INV (3/4) are supplied to the second switch circuit SWE (3/4).

The second switch circuit SWE (3/4) includes the first to fourth TFTs S1 to S4. The second switch circuit SWE (1/2) outputs the third and fourth EM signals input from the second inverter INV (3/4) in response to the first and second switch clocks SWCLK1 and SWCLK2 Separate. And the third EM signal is supplied to the third pixel PXL3. The fourth EM signal is supplied to the fourth pixel PXL4.

The second shift register includes latches SC2 (1/2), SC2 (3/4)) for sequentially outputting the B scan signal in response to the start pulse G2VST and the shift clocks G2CLK1 to G2CLK4, (SW2 (1/2), SWC2 (3/4)) disposed between the switches SC2 (1/2) and SC2 (3/4).

Each of the latches SC2 (1/2) and SC2 (3/4) of the second shift register is responsive to the first and second pulses of the shift clocks G2CLK1 to G2CLK4, And continuously outputs the second pulse. The first latch SC2 (1/2) latches the start pulse G2VST and sequentially outputs the first pulse and the second pulse in response to the first and second pulses of the shift clocks G2CLK1, G2CLK3, and G2CLK4 . The output signal of the first latch SC2 (1/2) is supplied to the first switch circuit SWC2 (1/2) through one output terminal.

The first switch circuit SWC2 (1/2) includes the first to fourth TFTs S1 to S4. The first switch circuit SWC2 (1/2) separates the first and second pulses input from the first latch SC2 (1/2) in response to the first and second switch clocks SWCLK1 and SWCLK2 do. The first pulse is supplied to the first pixel PXL1. The second pulse is supplied to the start terminal of the second latch SC1 (3/4) while being supplied to the second pixel PXL2.

The second latch SC2 3/4 latches the second pulse inputted from the first switch circuit SWC2 (1/2) and outputs the first and second pulses of the shift clocks G1CLK1, G1CLK2 and G1CLK3 And outputs the first and second pulses in succession in response. The output signal of the second latch SC2 (3/4) is supplied to the second switch circuit SWC2 (3/4) through one output terminal.

The second switch circuit SWC2 (3/4) includes the first to fourth TFTs S1 to S4. The second switch circuit SWC2 (3/4) separates the first and second pulses input from the second latch SC2 (3/4) in response to the first and second switch clocks SWCLK1 and SWCLK2 do. The first pulse is supplied to the third pixel PXL3. The fourth pulse is supplied to the fourth pixel PXL4 and simultaneously supplied to the start terminal of the third latch (not shown).

As described above, the present invention separates the first and second pulses successively outputted in the unit channel of the GIP circuit using the switch circuit disposed between the GIP and the pixel array. Accordingly, by distributing the output signal of the unit channel of the GIP circuit to the pixels arranged in a plurality of lines of the display panel in a time division manner, the size of the GIP circuit is reduced as shown in FIG. 12 (B) Can be reduced. The present invention can reduce the bezel area by 25% or more compared to the conventional (Fig. 25 (A)) by using a switch circuit.

13 is a block diagram showing an organic light emitting diode display of the present invention.

Referring to FIG. 13, an organic light emitting display according to an embodiment of the present invention includes a display panel 100 and a driving circuit thereof. The display panel drive circuit includes a data driver 102 and GIP circuits (GIP1, GIP2) 104, 106. The GIP circuits 104 and 106 may be disposed on the bezel BZ of the display panel 100. [ Each of the first and second GIP circuits 104 and 104 includes at least one of a scan driver and an EM driver. At least one of the scan driver and the EM driver includes the above-described switch circuit.

The display panel 100 includes a pixel array AA in which an input image is displayed and a bezel area BZ outside the pixel array AA. The pixel array AA includes a plurality of data lines 12, a plurality of scan lines 14, and a plurality of EM lines 16. The scan lines 14 and the EM lines 16 are orthogonal to the data lines 12. The pixels 10 of the pixel array AA are arranged in a matrix form.

The display panel 100 further includes a VDD line for supplying VDD to the pixels 10, and a VSS electrode for supplying a base voltage VSS. In addition, the display panel may further include an induced voltage line for supplying a reference voltage (or an initialization voltage) to the pixels.

Each of the pixels is divided into a red subpixel, a green subpixel, and a blue subpixel for color implementation. The pixels may further include a white subpixel. The subpixels may be implemented with pixel circuits as shown in Figs. 14 to 16, but are not limited thereto.

The data driver 102 converts the data DATA of the input image received from the timing controller 110 into a gamma compensation voltage under the control of the timing controller 110 to generate a data signal and supplies the data signal to the data lines 12). The data voltage is supplied to the pixels 10 via the data lines 12. [

The first GIP circuit 104 is assumed to be a scan driver, and the second GIP circuit 106 is assumed to be an EM driver. The scan driver 104 sequentially supplies a scan signal synchronized with the data signal to the scan lines 12 under the control of the timing controller 110. The EM driver 106 sequentially supplies EM signals to the EM lines 16 under the control of the timing controller 110.

The timing controller 110 controls the operation timings of the data driver 102, the scan driver 104 and the EM driver 106 to synchronize the operation timings of the drivers 102, 104, and 106. The timing controller 110 receives digital video data of an input video from a host system (not shown) and a timing signal synchronized with the digital video data. The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal CLK, and a data enable signal DE. The host system may be any one of a TV system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, a phone system, and a virtual reality It can be one.

The timing controller 110 generates a data timing control signal for controlling the operation timing of the data driver 102 based on the timing signal received from the host system, a scan timing control signal for controlling the operation timing of the scan driver 104, And generates an EM timing control signal for controlling the operation timing of the EM driver 106. [ 5 and 8 show an example of a scan timing control signal and an EM timing control signal. Each of the scan timing control signal and the EM timing control signal includes a start pulse, a shift clock, and switch clocks SWCLK1 and SWCLK2. The start pulse defines the start timing at which the first output is generated in each of the shift registers of the scan driver 104 and the EM driver 106. [ The shift register starts to be driven when the start pulse is input and generates the first output signal at the first clock timing. The shift clock defines a shift timing of the output signal output from the shift register.

14A and 14B are diagrams illustrating a pixel circuit and its operation according to an embodiment of the present invention.

14A and 14B, each of the pixels of the present invention includes an OLED, a driving TFT (Thin Film Transistor) DT, first through fifth switch TFTs T001, T002, T03 through T05, a storage capacitor Cst ). The TFTs (TD, T001, T002, T03 to T05) are illustrated as p-type MOSFETs, but are not limited thereto. For example, the TFTs (TD, T001, T002, T03 to T05) may be implemented as n-type MOSFETs. In this case, the phases of the scan signals SCAN1 and SCAN2 and the EM signal shown in FIG. 14B are inverted. The TFTs (TD, T001, T002, T03 to T05) may be implemented by any one of amorphous silicon (a-Si) TFT, polysilicon TFT and oxide semiconductor TFT or a combination thereof.

The anode of the OLED is connected to the driving TFT DT through the fourth switch TFT (T04). The cathode of the OLED is connected to the VSS electrode and is supplied with the ground voltage VSS. The base voltage may be a low-potential DC voltage of negative polarity.

The driving TFT DT is a driving element for adjusting the current Ioled flowing in the OLED according to the gate-source voltage. The driving TFT DT includes a gate to which the data voltage is supplied from the first switch TFT T001 through the B node, a source to which the VDD line is supplied to the VDD line, and a drain to which the fourth switch TFT T04 is connected . The storage capacitor Cst is connected between the A node and the B node.

The first switch TFT T001 is turned on in response to the A scan signal SCAN1 from the first scan line 14 during the scan period to supply the data signal to the gate of the drive TFT DT And maintains the off state during the light emission period Te. The first switch TFT T001 includes a gate connected to the first scan line 14, a source connected to the data line 12, and a source connected to the A node. The scan period is approximately one horizontal period.

The second switch TFT T002 is turned on in response to the B scan signal SCAN2 from the second scan line during the scan period to short-circuit the drain D and the gate G of the drive TFT DT ) To operate the driving TFT DT as a diode. The gate G of the second switch TFT T002 is connected to the gate connected to the second scan line 14, the source connected to the gate G of the drive TFT DT through the B node, and the drain D). The second switch (TFT (T002)) has a leakage current problem because it keeps the remaining period except one scan period of one horizontal period in an OFF state in one frame period. In order to reduce the leakage current, the second switch TFT (T002) may be implemented as a dual gate combining two TFTs.

The third switch TFT T03 is turned on in accordance with the on level voltage of the EM signal EM to initialize the A node with the reference voltage Vref. The reference voltage Vref may be set to a voltage lower than the threshold voltage of the OLED, for example, a voltage between approximately 1V and 2V. The third switch TFT T03 includes a gate connected to the EM line 16, a source supplied with the reference voltage Vref, and a drain connected to the A node.

The fourth switch TFT (T04) is a switch element for switching the current flowing in the OLED in response to the EM signal EM from the EM line 16. [ The fourth switch TFT M4 is turned on / off in response to the EM signal EM generated in the off-level pulse during the scan period and maintained at the on level during the light emitting period Te, thereby switching the current path of the OLED. The fourth switch TFT (T04) includes a gate connected to the EM line 16, a source connected to the driver TFT (DT), and a drain connected to the anode of the OLED.

The fifth switch TFT T05 is turned on in response to the ON level pulse of the B scan signal SCAN2 to supply the reference voltage Vref to the anode of the OLED to initialize the OLED. The fifth switch TFT T05 includes a gate connected to the second scan line 14, a source to which the reference voltage Vref is supplied, and a drain connected to the anode of the OLED.

One frame period of the OLED display is divided into a scan period and a light emission period Te in which pixels emit light after the scanning period. Since the scan period is only about one horizontal period, most of the one frame period is the light emitting period. The present invention can sample the threshold voltage of a driving TFT (Thin Film Transistor) and compensate the data voltage (DATA) by the amount of the writing voltage in order to compensate the current deviation of the OLED by a known internal compensation method during a scan period. To this end, the scan period is divided into an initialization period Ti, a sampling & program period Ts, a hold period Th, and an emission period Te as shown in FIG. 14B . The pixel circuit is driven by the internal compensation method to initialize the pixels during the scan period, to sample the threshold voltage of the driving TFT DT, and to compensate the threshold voltage at the data voltage to drive the OLED and emit the OLED during the light emitting period Te.

It should be noted that the pixel circuit is not limited to Fig. 14A. The pixel circuit is modified as shown in FIG. 15A so that the first, second and fifth switch TFTs can be turned on / off with the same scan signal. Further, a switch element and a capacitor may be added to the pixel circuit for internal compensation, and a sensing path may be further added for external compensation. The sensing path includes at least one switch element, a sample holder, and an analog-to-digital converter (ADC), which senses the threshold voltage of the driving TFT or OLED of the pixel and converts the sensed value into digital data To the timing controller 110

15A and 15B are diagrams illustrating a pixel circuit and its operation according to another embodiment of the present invention.

15A and 15B, each of the pixels of the present invention includes an OLED, a driving TFT DT, first through fifth switch TFTs T01 through T05, and a storage capacitor Cst. This pixel circuit differs from the pixel circuit shown in FIG. 14A in that the first, second and fifth switch TFTs T01, T02 and T05 are driven by the same scan signal, Are substantially the same. The first, second and fifth switch TFTs (T01, T02, T05) will be described with respect to the structure of this pixel circuit, and detailed description of other elements will be omitted.

The first switch TFT T01 is turned on in response to the scan signal SCAN from the scan line to supply a data signal to the gate of the drive TFT DT during the scan period, ). The first switch TFT T001 includes a gate coupled to the scan line 14, a source coupled to the data line 12, and a source coupled to the A node.

The second switch TFT T002 is turned on in response to the scan signal SCAN during the scan period to short-circuit the drain D and the gate G of the drive TFT DT to operate the drive TFT DT as a diode . The gate G of the second switch TFT T002 is connected to the gate connected to the scan line 14, the source connected to the gate G of the driver TFT DT via the B node, and the drain D of the driver TFT DT, Lt; / RTI >

The fifth switch TFT (T05) is turned on according to the ON level pulse of the scan signal (SCAN) to supply the reference voltage (Vref) to the anode of the OLED to initialize the OLED. The fifth switch TFT (T05) includes a gate connected to the scan line, a source supplied with the reference voltage (Vref), and a drain connected to the anode of the OLED.

One frame period of the OLED display is divided into a scan period and a light emission period Te in which pixels emit light after the scanning period. Since the scan period is only about one horizontal period, most of the one frame period is the light emitting period. The present invention can sample the threshold voltage of a driving TFT (Thin Film Transistor) and compensate the data voltage (DATA) by the amount of the writing voltage in order to compensate the current deviation of the OLED by a known internal compensation method during a scan period. To this end, the scan period is divided into an initialization period Ti, a sampling & program period Ts, a hold period Th, and an emission period Te as shown in FIG. 15B . The pixel circuit is driven by the internal compensation method to initialize the pixels during the scan period, to sample the threshold voltage of the driving TFT DT, and to compensate the threshold voltage at the data voltage to drive the OLED and emit the OLED during the light emitting period Te. This will be described in detail with reference to Figs. 16A to 16D. The pixel circuit shown in Fig. 14A is driven in the same way as the internal compensation method of Figs. 16A to 16D although there is a difference in the number of necessary scan signals.

Figs. 16A to 16D are diagrams showing stepwise the internal compensation method of the pixel circuit shown in Fig.

Referring to FIGS. 15B and 16A, the scan signal SCAN is generated at the on level pulse (-6V) and the EM signal is maintained at the on level voltage (-6V) in the initialization period Ti. At this time, all the switch TFTs (T01 to T05) are turned on and the anode of the A node, the B node, and the OLED are initialized to Vref = 1.5V. VDD = 8.5 V is supplied to the driving TFT DT and the off state is maintained in the initialization period Ti. The source voltage Vs of the driving TFT DT is equal to VDD.

15B and 16B, the scan signal SCAN maintains an on-level pulse (-6V) and the EM signal is inverted to an off-level (12V) pulse during the sampling & program period Ts. Therefore, the first, second and fifth switch TFTs T01, T02 and T05 are kept on during the sampling & program period Ts, and the third and fourth switch TFTs T03 and T04 are turned- Off. The voltage of the data signal output from the data driver 102 (hereinafter referred to as the "data voltage") is supplied to the node A through the first switch TFT T01 during the sampling & program period Ts. During the sampling and programming period (Ts), the voltages of the A and B nodes change as shown in Table 1, and the source voltage (Vs) of the driving TFT (DT) is equal to VDD. The second switch TFT T02 is turned on so that the gate G and the drain D of the driving TFT DT are short-circuited and operate as diodes. The gate voltage Vg and the drain voltage Vd of the driving TFT DT are equal to the B node voltage.

After the off-level inversion of the EM signal, the drain voltage Vd of the driving TFT DT rises due to Vs (= VDD) but rises to Vg = Vs + Vth due to the p-type MOSFET operating condition Vgs <Vth. Vth is the threshold voltage of the driving TFT DT. Since Vs = VDD, Vg = VDD + Vth is finally stored, and this voltage is stored in the storage capacitor Cst.

Initial (Ti) Sampling & program (Ts) Hold (Th) Emission (Te) A Vref Vdata Vdata ? V: Vdata-Vref B Vref VDD + Vth VDD + Vth VDD + Vth + (Vdata-Vref) Vs VDD VDD VDD VDD

Referring to FIGS. 15B and 16C, the scan signal SCAN is inverted to the off level voltage 12V and the EM signal is maintained at the off level (12V) in the hold period Th. Therefore, during the hold period Th, all the switch TFTs T01 to T05 are kept off, and the A and B nodes are floating to maintain the voltage.

15B and 16D, the scan signal SCAN maintains the off level voltage 12V and the EM signal is inverted to the on level voltage -6V in the light emitting period Te. Therefore, the first, second and fifth switch TFTs T01, T02 and T05 are kept off during the light-emitting period Ti, while the third and fourth switch TFTs T03 and T04 are turned- Is turned on. During the light emission period, the A node voltage changes from the data voltage (Vdata) to the reference voltage (Vref). The B-node voltage, that is, the gate voltage Vg of the driving TFT is changed to VDD + Vth + (Vdata-Vref).

는 수학식 1과 같다. 데이터 전압(Vdata)과 기준 전압(Vref) 간의 차에 따라 OLED의 전류(

가 결정된다. The current of the OLED during the light emitting period

Is expressed by Equation (1). The difference between the data voltage (Vdata) and the reference voltage (Vref)

Is determined.

Here, K is a constant value determined by the mobility μ of the driving TFT DT, the parasitic capacitance Cox, and the channel ratio W / L. Vgs is the gate-source voltage of the driving TFT DT.

17 is a circuit diagram showing one latch in the shift register circuit of the scan driver. 18A to 18I are views showing the operation of the latch shown in FIG.

Referring to Figs. 17 to 18i, the shift register includes latches (or stages) that are connected in a dependent manner. The shift register receives the start pulse VST and the shift clocks CLK1 to CLK4 and generates the output signal VOUT and shifts the output signal EM signal EM to match the timing of the shift clock CLK. For convenience of explanation, it is assumed that the shift clocks (CLK1 to CLK4) and the output signal (VOUT) are signals generated by a single conventional pulse. The present invention generates the shift clocks CLK1 to CLK4 and the output signal VOUT as signals including the first and second pulses as described above.

The start pulse VST and the shift clocks CLK1 to CLK4 are generated as pulses of an on level. The start pulse VST is synchronized with the fourth clock CLK4. The shift clocks (CLK1 to CLK4) are sequentially shifted in phase between clocks. For example, the second clock CLK2 is generated following the first clock CLK1, and the third clock CLK3 is generated following the second clock CLK2. The on level is VDD = -6V, and the off level is VSS = 12V.

The first TFT T1 is turned on in response to the start pulse VST input through the VST terminal or the output (or carry signal) of the previous stage latch. The second TFT T2 is turned on in response to the clock CLK4 input through the first clock terminal. When the first and second TFTs T1 and T2 are simultaneously turned on, the Q node Q is charged to VDD = -6V. The first to fourth TBV TFTs TBV1, TBV2, TBV3, and TBV4 maintain an ON state as long as VDD is input. The gate of the first TFT (T1) is connected to the VST terminal. The drain of the first TFT (T1) is connected to the VDD terminal, and the source of the first TFT (T1) is connected to the drain of the second TFT (T2). The gate of the second TFT (T2) is connected to the first clock terminal, and the source of the second TFT (T2) is connected to the drain of the second TBV TFT (TBV2). The gates of the TBV TFTs TBV1, TBV2, TBV3 and TBV4 are connected to the VDD terminal. The drain of the first TBV TFT TBV1 is connected to the Q node, and the source of the first TBV TFT TBV1 is connected to the drain of the reset TFT TQRST. The source of the second TBV TFT (TBV2) is connected to the Q node, and the drain of the second TBV TFT (TBV2) is connected to the source of the second TFT (T2). The drain of the third TBV TFT TBV3 is connected to the node Q, and the source of the third TBV TFT TBV3 is connected to the drain of the third TFT T3. The drain of the fourth TBV TFT TBV4 is connected to the Q node, and the source of the fourth TBV TFT TBV4 is connected to the gate of the eighth TFT T8.

The reset TFT (TQRST) resets the voltage of the Q node to VSS = 12V in response to the reset signal (QRST). The gate of the reset TFT (TQRST) is connected to the reset terminal. The drain of the reset TFT (TQRST) is connected to the source of the first TBV TFT (TBV1), and the source of the reset TFT (TQRST) is connected to the VSS terminal.

The third TFT T3 is turned on / off according to the voltage of the QB node QB. The gate of the third TFT (T3) is connected to the QB node (QB). The drain of the third TFT (T3) is connected to the source of the third TBV TFT (TBV3), and the source of the third TFT (T3) is connected to the VSS terminal. The third TFT T3 may be implemented with a TFT of a dual gate structure.

The fourth TFT T4 is turned on in response to the clock CLK3 inputted through the second clock terminal to connect the Q node Q to the VDD terminal. And the gate of the fourth TFT T4 is connected to the second clock terminal. The drain of the fourth TFT (T4) is connected to the Q node (Q), and the source of the fourth TFT (T4) is connected to the VDD terminal. The fourth TFT T4 may be implemented as a TFT of a dual gate structure.

The fifth TFT T5 is turned on in response to a start pulse VST input through the VST terminal to connect the QB node QB to the VSS terminal. The gate of the fifth TFT (T5) is connected to the VST terminal. The drain of the fifth TFT (T5) is connected to the QB node (QB), and the source of the fifth TFT (T5) is connected to the VSS terminal. The fifth TFT (T5) may be implemented as a TFT of a dual gate structure.

The sixth TFT T6 is a pull-up transistor for turning on the output signal when the Q-node voltage is pre-charged and is turned on when the clock CLK1 is input through the third clock terminal. The gate of the sixth TFT (T6) is connected to the Q node (Q). The source of the sixth TFT (T6) is connected to the output terminal, and the drain of the sixth TFT (T6) is connected to the third clock terminal.

The seventh TFT T7 is a pull-down transistor that is turned on according to the QB node voltage to discharge the voltage of the output terminal to the VSS potential. The gate of the seventh TFT (T7) is connected to the QB node (QB). The drain of the seventh TFT (T7) is connected to the output terminal, and the source of the seventh TFT (T7) is connected to the VSS terminal. The capacitor CB is connected between the Q node Q and the output terminal.

The eighth TFT T8 is turned on according to the Q-node voltage to connect the QB node QB to the VSS terminal. The gate of the eighth TFT (T8) is connected to the Q node through the fourth TBV4 TFT (TBV4). The drain of the eighth TFT (T8) is connected to the QB node (QB), and the source of the eighth TFT (T8) is connected to the VSS terminal. The eighth TFT (T8) may be implemented as a TFT of a dual gate structure.

Hereinafter, the operation of the latch will be described step by step.

Referring to FIGS. 18A and 18B, in the first section (1), VST and CLK4 are generated as on-level pulses. Therefore, the first, second, and fifth TFTs T1, T2, and T5 are turned on in the first section (1). As a result of turning on the first and second TFTs T1 and T2, the Q node Q is connected to the VDD terminal and VDD is supplied to the Q node Q so that the voltage (VDD = -6V) .

18C and 18D, the sixth and eighth TFTs T6 and T8 are turned on according to the Q-node voltage (-6V) during the second section (2). As a result, the ON level voltage -6V of CLK1 is supplied to the output terminal, the voltage VOUT of the output terminal is inverted to the OFF level, and the QB node QB is charged to the off level voltage, that is, VSS = 12V.

Referring to FIGS. 18E and 18F, CLK1 is inverted to an off level voltage during the third period (3). During the third period (3), the voltage of the Q node (Q) rises due to bootstrapping due to coupling between the Q node and the third clock terminal. At the same time, the sixth TFT (T6) is turned on and the output voltage changes to the off level.

18G and 18H, CLK3 is generated as an on-level pulse during the fourth period (4) so that the fourth TFT T4 is turned on. As a result, the third and seventh TFTs T3 and T7, Turn on. During the fourth period (4), the voltage of the Q node Q rises to the VSS potential and is inverted to the off level, and the voltage VOUT of the output terminal rises to the VSS level to maintain the off level.

19 is a diagram showing an example of an inverter circuit of the EM driver. 20A to 20D are views showing the operation of the inverter shown in Fig.

Referring to Fig. 19, the inverter includes a plurality of TFTs T11 to T16 and a capacitor (ECB).

The fifteenth TFT T15 is turned on in response to End CLK input through the clock terminal to connect the Q node Q to the VDD terminal. The gate of the fifteenth TFT (T15) is connected to the clock terminal. The drain of the fifteenth TFT (T15) is connected to the VDD terminal, and the source of the fifteenth TFT (T15) is connected to the Q node (Q).

The sixteenth TFT (T16) connects the Q node (Q) to the VSS terminal according to the voltage of the QB node (QB) connected to the input terminal. The QB node QB receives the input signal SRO through the input terminal. The gate of the sixteenth TFT (T16) is connected to the QB node (QB). The drain of the sixteenth TFT (T16) is connected to the Q node (Q), and the source of the sixteenth TFT (T16) is connected to the VSS terminal. The sixteenth TFT (T16) may be implemented as a TFT of a dual gate structure.

The fourteenth TFT (T14) is turned on according to the voltage of the output terminal to connect the Q node (Q) to the VDD terminal. The gate of the fourteenth TFT (T14) is connected to the output terminal. The drain of the fourteenth TFT (T14) is connected to the VDD terminal, and the source of the fourteenth TFT (T15) is connected to the Q node (Q).

The thirteenth TFT T13 is turned on in accordance with the voltage of the output terminal to connect the node between the source of the 12th TFT T12a and the drain of the 12th TFT T12b to the VDD terminal. The gate of the thirteenth TFT (T13) is connected to the output terminal. The drain of the thirteenth TFT T13 is connected to the VDD terminal and the source of the thirteenth TFT T13 is connected to the node between the source of the twelfth TFT T12a and the drain of the twelfth TFT T12b.

The twelfth and twelfth TFTs T12a and T12b are dual-gate structure pull-down transistors that are turned on according to the QB node voltage to discharge the voltage of the output terminal to the VSS potential. The gates of the twelfth and twelfth TFTs T12a and T12b are connected to the QB node QB. The drain of the 12th TFT T12a is connected to the output terminal and the source of the 12th TFT T12a is connected to the drain of the 12th TFT T12b and the source of the 13th TFT T13. The drain of the 12b TFT (T12b) is connected to the source of the 12th TFT (T12a), and the source of the 12th TFT (T12a) is connected to the VSS terminal.

The eleventh TFT T11 is a pull-up transistor which is turned on according to the Q-node voltage and connects the output terminal to the VDD terminal. The gate of the eleventh TFT (T11) is connected to the Q node (Q). The source of the eleventh TFT (T11) is connected to the output terminal, and the drain of the eleventh TFT (T6) is connected to the VDD terminal.

Hereinafter, the operation of the inverter will be described with reference to Figs. 20A to 20D.

20A and 20B, the input signal SRO is inverted to the ON level voltage (-6V) in the first section (1). Thus, the 16th, 12th, and 12b TFTs T16, T12a, and T12b are turned on. The voltage of the Q node Q rises to VSS = 6V because the sixteenth TFT T16 is turned on. Therefore, the eleventh, thirteenth, fourteenth, and fifteenth TFTs T11, T13, T14, and T15 connected to the Q node are in the off state during the first period (1).

Referring to FIGS. 20C and 20D, the input signal SRO is inverted to the off level (12V) in the second section (2). Therefore, the 16th, 12th, and 12b TFTs T16, T12a, and T12b connected to the QB node QB during the second period (2) are turned off.

In the second section (2), End CLK is generated as an on-level pulse. The voltage of the Q node Q is changed to VDD = -6V because the fifteenth TFT T15 is turned on due to EndCLK, and thus the eleventh, thirteenth, fourteenth, and fifteenth TFTs T11, T13, T14, T15) are turned on. Since the VDD terminal and the output terminal are connected through the eleventh TFT T11, the voltage VOUT of the output terminal is inverted to VDD = -6V in the second section (2).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

30: Gate drive circuit (GIP circuit) Scan driver: 62, 64, 92, 112, 114
EP driving unit: 66, 96, 116 100: Display panel
110: timing controller 102: data driver
104, 106: GIP circuit (gate driving circuit) PXL: pixel
INV: Inverter SW, SWC, SWE of EM drive part: Switch circuit
SC, SC1, SC2: Latch of shift register

Claims (17)

A display panel on which pixels are arranged; And
And a gate driving circuit for supplying either one of a scan signal and a light emission control signal to the pixels,
Wherein the gate driving circuit comprises:
A signal generating circuit for outputting a signal including first and second pulses;
The first and second pulses of the signal received from the signal generation circuit in response to the first and second switch clocks are supplied to the first pixel and the second pulse is supplied to the second pixel And a switching circuit for supplying the switching circuit,
Wherein the first switch clock is synchronized with the first pulse, and the second switch clock is synchronized with the second pulse. The method according to claim 1,
Wherein the first pulse supplied to the first pixel and the second pulse supplied to the second pixel are the scan signal or the emission control signal. The method according to claim 1,
Wherein the gate driving circuit generates the output signal in response to a clock including first and second pulses,
Wherein a first pulse of the clock is synchronized with the first switch clock, and a second pulse of the clock is synchronized with the second switch clock. The method according to claim 1,
And the second pulse is output through the second output terminal of the switch circuit after the first pulse is outputted through the first output terminal of the switch circuit. 5. The method of claim 4,
The switch circuit includes:
A first switch element for outputting a first pulse of a signal received from the driving circuit in response to the first switch clock through the first output terminal;
A second switch element for outputting a second pulse of a signal received from the driving circuit in response to the second switch clock through the second output terminal;
A third switch element for outputting an off level voltage through the first output terminal in response to the second switch clock; And
And a fourth switch element for outputting an off level voltage through the second output terminal in response to the first switch clock. The method according to claim 1,
The switch circuit includes:
A first switch element including a gate to which the first switch clock is input, a source connected to the first output terminal of the switch circuit, and a drain connected to the input terminal of the switch circuit;
A second switch element including a gate to which the second switch clock is input, a source connected to the second output terminal of the switch circuit, and a drain connected to the input terminal of the switch circuit;
A third switch element including a gate to which the second switch clock is input, a drain connected to the first output terminal, and a source to which an off level voltage is supplied; And
And a fourth switch element including a gate to which the first switch clock is input, a drain connected to the first output terminal, and a source to which the off level voltage is supplied. An apparatus for driving an organic light emitting display device that supplies a scan signal and a light emission control signal to pixels of a display panel,
A scan driver for generating the scan signal; And
And an EM driver for outputting the emission control signal,
Wherein at least one of the scan driver and the EM driver comprises:
And a switch circuit which separates the first and second pulses of the input signal in response to the first and second switch clocks, supplies the first pulse to the first pixel, and supplies the second pulse to the second pixel ,
Wherein the first switch clock is synchronized with the first pulse, and the second switch clock is synchronized with the second pulse. 8. The method of claim 7,
The scan driver may include:
A first shift register for generating an A scan signal; And
And a second shift register for generating a B scan signal. 9. The method of claim 8,
The first shift register includes:
A first latch for outputting first and second pulses in response to a first start pulse and a first clock;
A first latch for supplying the first pulse as a first A scan signal to the first pixel, and a second pulse for supplying the first pulse as a first A scan signal to the first pixel, And a first switch circuit for supplying a pulse to the second pixel as a second A scan signal. 10. The method of claim 9,
The EM driver,
Inverting and latching the first and second pulses input from the first latch and toggling the output at the polling edge of the end clock to generate the first and second emission control signals separated at the falling edge of the end clock Including,
Wherein the first and second emission control signals are simultaneously supplied to the first and second pixels. 11. The method of claim 10,
Wherein the second shift register comprises:
A second latch for outputting the B scan signal in response to a second start pulse and a second clock; And
A first switch for supplying a first pulse as a first B scan signal to the first pixel, and a second switch for supplying a first pulse as a first B scan signal to the first pixel, And a second switch circuit for supplying a pulse to the second pixel as a second B scan signal. 8. The method of claim 7,
The scan driver
A latch for outputting a first pulse and a second pulse in response to a first start pulse and a first clock; And
A first switch for supplying a first pulse as a first scan signal to the first pixel, and a second switch for supplying the first pulse as a first scan signal to the first pixel, And a second switch circuit for supplying the second pixel as a first scan signal and a second scan signal to the second pixel. 13. The method of claim 12,
The EM driver,
An inverter receiving the second start pulse and the second clock and outputting first and second pulses in the form of an inverted signal of the clock; And
A first switch for supplying a first pulse as a first light emission control signal to the first pixel, and a second switch for supplying the first pulse as a first light emission control signal to the first pixel, And a first switch circuit for supplying the second light emission control signal to the second pixel as a second light emission control signal. 10. The method of claim 9,
The EM driver,
An inverter for inverting and latching the first and second pulses input from the first latch and for toggling an output at a polling edge of the end clock to generate first and second emission control signals separated at a polling edge of the end clock; And
The first and second light emission control signals are separated from the first and second light emission control signals inputted from the inverter in response to the first and second switch clocks to supply the first light emission control signal to the first pixel, And a second switch circuit for supplying the second pixel to the second pixel. 15. The method of claim 14,
Wherein the second shift register comprises:
A second latch for outputting the B scan signal in response to a second start pulse and a second clock; And
A first switch for supplying a first pulse as a first B scan signal to the first pixel, and a second switch for supplying a first pulse as a first B scan signal to the first pixel, And a third switch circuit for supplying a pulse to the second pixel as a second B scan signal. 16. The method according to any one of claims 7 to 15,
Each of the switch circuits includes:
A first switch element for outputting a first pulse of a signal received from the driving circuit in response to the first switch clock through the first output terminal;
A second switch element for outputting a second pulse of a signal received from the driving circuit in response to the second switch clock through the second output terminal;
A third switch element for outputting an off level voltage through the first output terminal in response to the second switch clock; And
And a fourth switch element for outputting an off level voltage through the second output terminal in response to the first switch clock signal. 16. The method according to any one of claims 7 to 15,
Each of the switch circuits includes:
A first switch element including a gate to which the first switch clock is input, a source connected to the first output terminal of the switch circuit, and a drain connected to the input terminal of the switch circuit;
A second switch element including a gate to which the second switch clock is input, a source connected to the second output terminal of the switch circuit, and a drain connected to the input terminal of the switch circuit;
A third switch element including a gate to which the second switch clock is input, a drain connected to the first output terminal, and a source to which an off level voltage is supplied; And
And a fourth switch element including a gate to which the first switch clock is input, a drain connected to the first output terminal, and a source to which the off level voltage is supplied.

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