KR20190138470A - Electroluminescent Display Device - Google Patents

Abstract

The present invention relates to an electroluminescent display device including a pixel structure capable of reducing the unit cost of production. The electroluminescent display device comprises: a light emitting element receiving a drive current and emitting light; a drive transistor adjusting the drive current according to a voltage difference between a gate and a source; a first switching means charging a reference voltage to one end of a capacitor connected to the gate of the drive transistor according to a scan signal; a second switching means charging a data voltage to the other end of the capacitor according to the scan signal; and a third switching means connecting the other end of the capacitor and the source of the drive transistor according to an emission signal.

Description

Electroluminescent Display Device

The present invention relates to an electroluminescent display.

Electroluminescent displays are roughly classified into inorganic light emitting displays and organic light emitting displays according to materials of the light emitting layer. Among these, the organic light emitting display of the active matrix type includes an organic light emitting diode (hereinafter, referred to as "OLED") that emits light by itself.

The OLED display arranges pixels including OLEDs in a matrix form and adjusts luminance of the pixels according to the gray level of the image data. Each of the pixels basically includes a driving thin film transistor (TFT) for controlling a driving current flowing through the OLED according to the gate-source voltage, and one or more switch TFTs for programming the gate-sort voltage of the driving TFT.

The organic light emitting display device is advantageous in thinning, low power consumption, fast response speed, high luminous efficiency, high luminance, and wide viewing angle.

Accordingly, there is a need for a technology development for a pixel structure that can reduce the cost and reduce the production cost while maintaining the advantages of the organic light emitting display device.

The present invention provides an electroluminescent display device including a pixel structure that enables a thinner design and can reduce production costs.

An electroluminescent display device according to an embodiment of the present invention includes a light emitting device for emitting light by receiving a driving current; A driving transistor adjusting the driving current according to a voltage difference between a gate and a source; First switching means for charging a reference voltage to one end of a capacitor connected to the gate of the driving transistor according to a scan signal; Second switching means for charging a data voltage at the other end of the capacitor according to the scan signal; And third switching means for connecting the other end of the capacitor and the source of the driving transistor according to an emission signal.

An electroluminescent display device according to an exemplary embodiment of the present invention includes a display panel in which a plurality of pixels are connected to a data line supplied with a data voltage, a reference power line supplied with a reference voltage, and a high potential power voltage line supplied with a high potential power voltage. Each pixel arranged in an n (n is a natural number) pixel row among the pixels includes: a light emitting TFT connected to an input terminal to which a high potential power voltage is input; A light emitting element having a cathode electrode connected to an input terminal of a low potential driving voltage and an anode electrode connected to a third node; A driving TFT controlling a driving current applied to the light emitting device, including a gate electrode connected to a first node, a source electrode connected to the third node, and a drain electrode to which the high potential power voltage is input; A first TFT connected between the first node and the reference power line; A second TFT connected between a second node and the data line; A capacitor having one end connected to the first node and the other end connected to the second node; And a third TFT connected between the second node and the third node.

Since the electroluminescent display of the present invention uses a scan line for applying a data voltage for driving a pixel and a scan line for applying a reference voltage in common, the electroluminescent display does not need to increase the bezel area, and the narrow bezel ( Narrow Bezel) has the advantage of implementing.

The electroluminescent display device of the present invention can directly sense the current of the OLED of each pixel, thereby improving the accuracy of compensation for image quality.

Since the electroluminescent display device of the present invention applies a positive drive IC to drive a pixel, the electroluminescent display device can reduce production cost and improve driving stability compared to applying a negative drive IC.

1 is a diagram illustrating an electroluminescent display device according to an exemplary embodiment of the present invention.
2 is a diagram illustrating a pixel row included in an electroluminescent display according to a first embodiment of the present invention.
FIG. 3 is a waveform diagram illustrating driving waveforms of the pixel illustrated in FIG. 2.
FIG. 4A is an equivalent circuit diagram of a pixel corresponding to the data writing period t1 of FIG. 3.
4B is a drive waveform diagram showing the data writing period t1 and the voltage state of each node in the drive waveform of the pixel of FIG.
FIG. 5A is an equivalent circuit diagram of a pixel corresponding to the data transfer period t3 of FIG. 3.
FIG. 5B is a driving waveform diagram showing a data transfer period t3 and a voltage state of each node in the driving waveform of the pixel of FIG. 3.
FIG. 6A is an equivalent circuit diagram of a pixel corresponding to the light emission period t4 of FIG. 3.
FIG. 6B is a drive waveform diagram showing the light emission period t4 and the voltage state of each node in the drive waveform of the pixel of FIG.
7 and 8 are diagrams showing the simulation results of the present invention.
9 is a diagram illustrating a pixel row included in an electroluminescent display according to a second embodiment of the present invention.
FIG. 10 is a waveform diagram illustrating driving waveforms of a pixel illustrated in FIG. 9.

Advantages and features of the present specification, and a method of accomplishing the same will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but may be implemented in various forms, and the present embodiments are merely provided to make the disclosure of the present disclosure complete, and those of ordinary skill in the art to which the present disclosure belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims.

Shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present specification are exemplary, and thus, the present specification is not limited thereto. Like reference numerals refer to like elements throughout. When 'comprises', 'haves', 'consists of' and the like mentioned in the present specification are used, other parts may be added unless 'only' is used. In the case where the component is expressed in the singular, the plural includes the plural unless specifically stated otherwise.

In interpreting a component, it is interpreted to include an error range even if there is no separate description.

In the case of the description of the positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on top', 'on bottom', 'next to', etc. Alternatively, one or more other parts may be located between the two parts unless 'direct' is used.

The first, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component referred to below may be a second component within the spirit of the present specification.

Like reference numerals refer to like elements throughout.

In the present specification, the pixel circuit and the gate driver formed on the substrate of the display panel may be implemented as TFTs having an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, but are not limited thereto and may be implemented with TFTs having a p-type MOSFET structure. have. The TFT is a three-electrode element that includes a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers start to flow from the source. The drain is an electrode from which the carrier goes out of the TFT. That is, the carrier flow in the MOSFET flows from the source to the drain. In the case of an n-type TFT (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in the n-type TFT, the direction of the current flows from the drain to the source. In contrast, in the case of the p-type TFT (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In the p-type TFT, current flows from the source to the drain because holes flow from the source to the drain. Note that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET can be changed according to the applied voltage. Therefore, in the description of the embodiments of the present specification, one of the source and the drain is described as the first electrode, and the other of the source and the drain as the second electrode.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described based on an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical spirit of the present disclosure is not limited to an organic light emitting display device, but may be applied to an inorganic light emitting display device including an inorganic light emitting material.

In the following description, when it is determined that a detailed description of known functions or configurations related to the present disclosure may unnecessarily obscure the subject matter of the present disclosure, the detailed description thereof will be omitted.

1 is a diagram illustrating an electroluminescent display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, an organic light emitting display device according to an exemplary embodiment of the present invention includes a display panel 10 in which pixels PXL are formed, a data driving circuit 12 for driving data lines 14, A gate driving circuit 13 for driving the gate lines 15 and a timing controller 11 for controlling the driving timing of the data driving circuit 12 and the gate driving circuit 13 are provided.

In the display panel 10, a plurality of data lines 14 and a plurality of gate lines 15 intersect each other, and pixels PXL are arranged in a matrix form at each of the crossing regions. Pixels PXL arranged on the same horizontal line form one pixel row. Pixels PXL arranged in one pixel row may be connected to one gate line 15, and one gate line 15 may include at least one scan line and at least one emission line. That is, each pixel PXL may be connected to one data line 14 and at least one scan line and an emission line. The pixels PXL may be supplied with the high potential and low potential driving voltages EVDD and EVSS and the reference voltage Vref in common.

The pixels PXL may include an OLED. The OLED, which is a self-luminous element, includes an anode electrode and a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection Layer, EIL). When a power supply voltage is applied to the anode electrode and the cathode electrode, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emission layer EML to form excitons, and as a result, the emission layer EML becomes Visible light is generated.

Each of the pixels PXL may be one of a red pixel, a green pixel, a blue pixel, and a white pixel. The red pixel, the green pixel, the blue pixel, and the white pixel may constitute one unit pixel for color implementation. The color implemented in the unit pixel may be determined according to the emission ratio of the red pixel, the green pixel, the blue pixel, and the white pixel. Meanwhile, the white pixel may be omitted from the unit pixel.

The timing controller 11 rearranges the digital video data RGB input from the outside to the data driving circuit 12 in accordance with the resolution of the display panel 10. In addition, the timing controller 11 may use the data driving circuit 12 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. A data control signal DDC for controlling the operation timing of the gate signal and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13 are generated.

The data driving circuit 12 converts the digital video data RGB input from the timing controller 11 into an analog data voltage VD based on the data control signal DDC.

The data driving circuit 12 may further include a power generator. The power generator may generate an initialization voltage to supply the data line 14, and generate a reference voltage Vref to supply the reference voltage to the reference power line. The reference voltage Vref may be set to a voltage range sufficiently lower than the operating point voltage of the OLED so as to prevent unnecessary light emission of the OLED during the sampling period and the data writing period.

The gate driving circuit 13 may generate a scan signal and an emission signal based on the gate control signal GDC. The gate driving circuit 13 may include a scan driver generating a scan signal and an emission driver generating an emission signal. The scan driver and the emission driver may be modified in various ways according to the pixel structure. The scan driver generates scan signals in a row sequential manner and supplies the scan lines to the at least one scan line connected to each pixel row. The emission driver may generate an emission signal in a row sequential manner and supply the emission lines to drive at least one emission line connected to each pixel row. The gate driving circuit 13 may be directly formed on the non-display area of the display panel 10 according to a gate-driver in panel (GIP) method.

FIG. 2 illustrates a pixel array included in an electroluminescent display according to a first embodiment of the present invention.

Referring to FIG. 2, a plurality of data lines 14 and a plurality of gate lines 15 intersect each other in a pixel array, and pixels PXL are arranged in a matrix form at each intersection area.

The gate line 15 may include a scan line to which the scan signal SCAN is input and an emission line to which at least one emission signal EM is input. The data line 14 may include a data line to which data voltages VD _R , VD _G , and VD _B output from the data driving circuit 12 are input. In addition, the pixels PXL may be commonly supplied with the high potential and low potential driving voltages EVDD and EVSS and the reference voltage V _REF from a power generator not shown.

The pixel PXL disposed in the i-th pixel row is connected to the i-th scan signal SCAN [i], the i-th emission signal EM [i], and the emi of the immediately preceding stage through the gate line 15. An i-1 emission signal EM [i-1] that is a selection signal may be input. The data voltage VD may be input through the data line 14. R, G, B, has a data voltage corresponding to the pixel which emits light of a corresponding color _{(VD R, VD G, VD} B) it can be input when the data voltage _{(VD R, VD G, VD} B) are inputted.

Each pixel receives a driving current and emits light, the driving transistor DR for adjusting the driving current according to a voltage difference between a gate and a source, and the driving transistor according to a scan signal SCAN [i]. The other end of the capacitor Cst according to the first switching means SW1 and the scan signal SCAN [i] which provide a path for charging the reference voltage V _REF to one end of the capacitor Cst connected to the gate of the DR. The other end of the capacitor Cst and the driving transistor DR according to the second switching means SW2 and the previous stage emission signal EM [i-1] that provide a path for charging the data voltage VD. It may include a third switching means (SW3) for connecting the source of. The light emitting transistor EM may include a light emitting transistor EM that turns on the light emitting device OLED according to the i th emission signal EM [i]. In this case, the light emitting transistor EM may be provided for each pixel PXL and configured to control one pixel grouped into R, G, and B unit pixels PXL _R , PXL _G , and PXL _B. In addition, one emission signal EM [i] may be configured such that R, G, and B unit pixels PXL _R , PXL _G , and PXL _B are simultaneously turned on and off.

According to an exemplary embodiment of the present invention, the pixel PXL disposed in the i-th pixel row includes the i-th scan signal SCAN [i], the i-th emission signal EM [i], and the i-1th emission signal. Enter (EM [i-1]).

The i-th scan signal SCAN [i] is shared by the first switching means SW1 and the second switching means SW2 so that the first switching means SW1 and the second switching means SW2 are simultaneously turned on and off. do. As described above, the number of scan lines can be reduced by half by sharing the scan signal SCAN between the first switching means SW1 and the second switching means SW2.

When the first switching means SW1 and the second switching means SW2 are turned on, one end of the capacitor Cst is connected to the reference power line and the other end is connected to the data line. Accordingly, the data voltage VD _R may be charged in the capacitor Cst.

When the first switching means SW1 and the second switching means SW2 are turned off, the third switching means SW3 is turned on. Thus, one end of the capacitor Cst is connected to the gate of the driving transistor DR and the other end is connected to the source terminal. Accordingly, the data voltage VD _R charged in the capacitor Cst may be reflected in the potential between the gate and the source of the driving transistor DR. In this principle, since a data voltage is applied to the driving transistor DR, data can be written by applying a positive drive IC. Therefore, the production cost can be reduced and the driving stability can be improved compared to the application of the negative drive IC.

FIG. 3 is a waveform diagram illustrating driving waveforms of the pixel illustrated in FIG. 2.

Referring to FIG. 3, one frame period for driving the pixels PXL arranged in the i-th pixel row includes a data writing period t1 in which a data voltage VD _R is charged in a capacitor Cst, and a data writing period. After completion, the data holding period t2 during which the data voltage VD _R of the capacitor Cst is maintained, and the potential between the gate and the source of the driving transistor DR are the data voltage VD _R charged in the capacitor Cst. It may include a data transfer period (t3) and a light emitting period (t4) for emitting a light emitting element reflected in.

In the data writing period t1, the i-th emission signal EM [i-1] and the i-th emission signal EM [i] are applied at a high level. In the case of the emission signal, the low level is on level and the high level is off level. Therefore, the third switching means SW3 and the light emitting transistor EM are turned off. The i th scan signal SCAN [i] is applied at a high level. In the case of a scan signal, the high level is on level and the low level is off level. Therefore, in the data writing period t1, the first switching means SW1 and the second switching means SW2 are turned on at the same time.

In the data retention period t2, the i-th emission signal EM [i-1] and the i-th emission signal EM [i] are maintained at a high level. Therefore, the third switching means SW3 and the light emitting transistor EM are kept in the off state. The i th scan signal SCAN [i] is applied at a low level. In the case of a scan signal, the high level is on level and the low level is off level. Therefore, in the data writing period t2, the first switching means SW1 and the second switching means SW2 are turned off at the same time.

In the data transfer period t3, the i-th emission signal EM [i-1] is switched to the low level and the i-th emission signal EM [i] is maintained at the high level. In the case of the emission signal, the low level is on level and the high level is off level. Accordingly, the third switching means SW3 is turned on and the light emitting transistor EM is kept in the off state. The i th scan signal SCAN [i] is maintained at a low level. Therefore, the first switching means SW1 and the second switching means SW2 are kept in the off state.

In the light emission period t4, the i-th emission signal EM [i-1] is kept at a low level and the i-th emission signal EM [i] is switched to a low level. In the case of the emission signal, the low level is on level and the high level is off level. Therefore, both the third switching means SW3 and the light emitting transistor EM are turned on. The i th scan signal SCAN [i] is maintained at a low level. Therefore, the first switching means SW1 and the second switching means SW2 are kept in the off state.

As described above, according to the embodiment of the driving waveform of the present invention, the nth scan signal is input so that the first switching means SW1 and the second switching means SW2 are turned on only during the data writing period, and the nth emission The signal may be input so that the light emitting transistor EM is turned on only during the light emission period, and the n−1th emission signal may be input so that the third switching means SW3 is turned on only during the data transfer period.

4 to 6 are diagrams for describing a method of driving a pixel according to an exemplary embodiment of the present invention.

In the pixel according to the embodiment of the present invention, the first to third switching means SW1 to SW3, the driving transistor DR, and the light emitting transistors EM are n-type MOSFETs (metal-oxide-semiconductor field-effect transistors) and p. It may be implemented as a type MOSFET, a complementary metal semiconductor (CMOS) TFT, or the like. In the following embodiment, the light emitting TFT (EM) and the third TFT (SW3) is implemented in the p type, the first TFT (SW1), the second TFT (SW2) and the driving TFT (DR) is implemented in the n type Let's explain.

Therefore, the pixel of the present invention is connected to the light emitting TFT (EM) connected to the input terminal to which the high potential power voltage EVDD is input, and to the cathode electrode and the third node N3 connected to the input terminal of the low potential driving voltage EVSS. The light emitting device OLED having the connected anode electrode, the gate electrode connected to the first node N1, the source electrode connected to the third node N3, and the drain electrode to which the high potential power voltage EVDD is inputted are provided. And a driving TFT DR for controlling a driving current applied to the light emitting device OLED. The first TFT SW1 is connected between the first node N1 and the supply line of the reference voltage V _REF . The second TFT SW2 is connected between the second node N2 and the data line VD _R. One end of the capacitor Cst is connected to the first node N1 and the other end is connected to the second node N2. The third TFT SW3 is connected between the second node N2 and the third node N3.

The gate electrodes of the first TFT SW1 and the second TFT SW2 share the same scan line SCAN [i]. The i-th emission signal EM [i] is input to the gate electrode of the light emitting TFT EM, and the i-1th emission signal EM [i-1] is supplied to the gate of the third TFT SW3. do.

4A is an equivalent circuit diagram of a pixel corresponding to the data writing period t1, and FIG. 4B is a driving waveform diagram showing the data writing period t1 and the voltage state of each node in the driving waveform of the pixel.

In the data writing period t1, the i-th emission signal EM [i-1] and the i-th emission signal EM [i] are applied at a high level. Since the light emitting TFT EM and the third TFT SW3 that receive the emission signals EM [i] and EM [i-1] are implemented in p type, the emission signals EM [i] and EM [i -1]), the low level is on level and the high level is off level. Therefore, the light emitting TFT EM and the third TFT SW3 are turned off in the data writing period t1. Therefore, the light emitting device OLED is maintained in the off state and the second node N2 and the third node N3 are disconnected.

The i th scan signal SCAN [i] is applied at a high level. Since the first TFT SW1 and the second TFT SW2 that receive the scan signal SCAN [i] are implemented in n type, the high level is on and the low level is off in the case of the scan signal SCAN [i]. Level. Therefore, the first TFT SW1 and the second TFT SW2 are turned on in the data writing period t1.

When the first TFT SW1 is turned on, one end of the capacitor Cst is connected to the reference power line and the other end is connected to the data line. When the second TFT SW2 is turned on, the other end of the capacitor Cst is connected to the data line. Accordingly, the reference voltage V _REF is applied to the first node N1 to which the capacitor Cst is connected, and the data voltage VD _R is applied to the second node N2. Accordingly, the data voltage VD _R may be charged in the capacitor Cst. Here, the reference voltage V _REF may be set to about 7-8V, and the data voltage VD _R may be set to a voltage lower than the reference voltage V _REF .

Through the above process, the data voltage VD _R may be charged in the capacitor Cst while the light emitting device OLED is maintained in the off state during the data writing period t1.

After that, when the i th scan signal SCAN [i] is switched to the low level, the voltage of the first node N1 and the voltage of the second node N2 are gradually decreased, but the potential difference stored in the capacitor Cst is It can be maintained (t2 interval).

FIG. 5A is an equivalent circuit diagram of a pixel corresponding to the data transfer period t3, and FIG. 5B is a drive waveform diagram showing the data transfer period t3 and the voltage state of each node in the driving waveform of the pixel.

In the data transfer period t3, the i-th emission signal EM [i-1] is switched to the low level and the i-th emission signal EM [i] is maintained at the high level. Thus, the third TFT SW3 is turned on and the light emitting TFT EM is kept in the off state. As a result, in the data transfer period t3, the light emitting device OLED is maintained in the off state and the second node N2 and the third node N3 are connected.

The i th scan signal SCAN [i] is maintained at a low level. Therefore, both the first TFT SW1 and the second TFT SW2 are kept in the off state.

When the first TFT SW1 is turned off, the first node N1 to which the capacitor Cst is connected is connected to the gate electrode of the driving TFT DR. When the second TFT SW2 is turned off, the second node N2 of the capacitor Cst is connected to the source electrode of the driving TFT DR through the third TFT SW3. That is, the gate electrode and the source electrode of the driving TFT DR are connected through the capacitor Cst.

Through the above process, the data voltage VD _R stored in the capacitor Cst is driven by the gate electrode and the source electrode of the driving TFT DR while the light emitting device OLED is kept off in the data transfer period t3. It can be reflected as the potential difference between the liver.

6A is an equivalent circuit diagram of a pixel corresponding to the light emission period t4, and FIG. 6B is a drive waveform diagram showing the light emission period t4 and the voltage state of each node in the drive waveform of the pixel.

In the light emission period t4, the i-th emission signal EM [i-1] is maintained at a low level, and the i-th emission signal EM [i] is also switched to a low level. Thus, both the third TFT SW3 and the light emitting TFT EM are turned on. When the light emitting TFT EM is turned on, the high potential power voltage EVDD is supplied to the light emitting device OLED.

The i th scan signal SCAN [i] is maintained at a low level. Therefore, both the first TFT SW1 and the second TFT SW2 are kept in the off state.

When the first TFT SW1 is turned off, the first node N1 to which the capacitor Cst is connected is connected to the gate electrode of the driving TFT DR. When the second TFT SW2 is turned off, the second node N2 of the capacitor Cst is connected to the source electrode of the driving TFT DR through the third TFT SW3.

Through the above process, during the light emitting period t4, the high potential power voltage EVDD is controlled by the driving TFT DR and supplied to the light emitting device OLED. A capacitor Cst may be connected between the gate electrode and the source electrode of the driving TFT DR to adjust the amount of driving current supplied to the light emitting device OLED according to the data voltage VD _R stored in the capacitor Cst. .

7 and 8 are diagrams showing the simulation results of the present invention.

FIG. 7 is a graph showing a result of simulating the relationship between the data voltage applied to the R, G, and B pixels and the amount of current supplied to the light emitting device OLED.

In the simulation, the high potential supply voltage (EVDD) is 8V, the low potential supply voltage (EVSS) is applied at -1.5V, the reference voltage (V _REF ) is set at 7V, and the data voltage (for R, G, B pixels) When VD _R , VD _G , and VD _B ) are applied at +5 to + 9V, the results of simulation of the amount of current supplied to each light emitting device OLED are as shown in the graph.

Referring to the graph, it can be seen that the data voltage of 7 V or more, which is the reference voltage V _REF , for all of the R, G, and B pixels has little effect on the amount of current of the light emitting device OLED.

As a result, when the data voltage of 7V or less, which is the reference voltage V _REF , the peak value is applied when data voltages of about 5.2V for blue pixels, about 5.9V for red pixels, and about 6.3V for green pixels are applied. It was confirmed to record.

8 is a graph simulating a voltage change at each node when driving a pixel structure according to an exemplary embodiment of the present invention.

As shown in FIG. 8, it is confirmed that the change in voltage value sensed at each node actually shows a change value almost similar to the graphs shown in FIGS. 4B, 5B, and 6B. That is, the data voltage VD _R charged in the capacitor Cst in the data writing period t1 is the gate and the source of the driving transistor DR in the data transfer period t3 after the data holding period t2. It can be seen that it is reflected in the liver potential and acts in the light emission period t4.

FIG. 9 is a diagram illustrating a pixel row included in an electroluminescent display according to a second exemplary embodiment of the present invention, and FIG. 10 is a waveform diagram illustrating driving waveforms of the pixel illustrated in FIG. 9.

In the pixel according to the second exemplary embodiment of the present invention, all of the first to third switching means SW1 to SW3, the driving transistor, and the light emitting transistors may be implemented with an n-type MOSFET (metal-oxide-semiconductor field-effect transistor).

Referring to FIG. 9, the pixel PXL disposed in the i-th pixel row includes the i-th scan signal SCAN [i], the i-th emission signal EM [i], and the emission immediately before the i-th stage. The signal i-1 may receive an emission signal EM [i-1]. The data voltage VD may be input through the data line. R, G, B, has a data voltage corresponding to the pixel which emits light of a corresponding color _{(VD R, VD G, VD} B) it can be input when the data voltage _{(VD R, VD G, VD} B) are inputted.

Each pixel according to the second exemplary embodiment of the present invention is configured to emit light by receiving a driving current, a driving transistor DR, and a scan signal SCAN [i] which adjust the driving current according to a voltage difference between a gate and a source. According to the first switching means SW1 and the scan signal SCAN [i] that provide a path for charging the reference voltage V _REF to one end of the capacitor Cst connected to the gate of the driving transistor DR. The other end of the capacitor Cst and the driving transistor according to the second switching means SW2 and the previous stage of the emission signal EM [i-1] which provide a path for charging the data voltage at the other end of the capacitor Cst. Third switching means (SW3) for connecting the source of the (DR). The light emitting transistor EM may include a light emitting transistor EM that turns on the light emitting device OLED according to the i th emission signal EM [i]. The light emitting transistor EM may be provided for each pixel PXL, and when configured to control one pixel grouped into R, G, and B unit pixels PXL _R , PXL _G , and PXL _B , one The emission signals EM [i] of R, G, and B unit pixels PXL _R , PXL _G , and PXL _B may be configured to be turned on / off at the same time.

According to the second embodiment of the present invention, the light emitting TFT (EM), the driving TFT (DR), and the first to third TFTs may all be n-type MOSFETs (metal-oxide-semiconductor field-effect transistors).

Referring to FIG. 10, one frame period for driving the pixels PXL arranged in the i-th pixel row includes a data writing period t1 in which a data voltage VD _R is charged in a capacitor Cst, and a data writing period. After completion, the data holding period t2 during which the data voltage VD _R of the capacitor Cst is maintained, and the potential between the gate and the source of the driving transistor DR are the data voltage VD _R charged in the capacitor Cst. It may include a data transfer period (t3) and a light emitting period (t4) for emitting a light emitting element reflected in.

In the data writing period t1, the i-1 th emission signal EM [i-1] and the i th emission signal EM [i] are applied at a low level. In the case of the emission signal, the high level is on level and the low level is off level. Therefore, the third switching means SW3 and the light emitting transistor EM are turned off. The i th scan signal SCAN [i] is applied at a high level. In the case of a scan signal, the high level is on level and the low level is off level. Therefore, in the data writing period t1, the first switching means SW1 and the second switching means SW2 are turned on at the same time.

In the data retention period t2, the i-th emission signal EM [i-1] and the i-th emission signal EM [i] are maintained at a low level. Therefore, the third switching means SW3 and the light emitting transistor EM are kept in the off state. The i th scan signal SCAN [i] is applied at a low level. In the case of a scan signal, the high level is on level and the low level is off level. Therefore, in the data writing period t2, the first switching means SW1 and the second switching means SW2 are turned off at the same time.

In the data transfer period t3, the i-th emission signal EM [i-1] is switched to the high level and the i-th emission signal EM [i] is maintained at the low level. In the case of the emission signal, the high level is on level and the low level is off level. Accordingly, the third switching means SW3 is turned on and the light emitting transistor EM is kept in the off state. The i th scan signal SCAN [i] is maintained at a low level. Therefore, the first switching means SW1 and the second switching means SW2 are kept in the off state.

In the light emission period t4, the i-th emission signal EM [i-1] is maintained at a high level and the i-th emission signal EM [i] is switched to a high level. In the case of the emission signal, the high level is on level and the low level is off level. Therefore, both the third switching means SW3 and the light emitting transistor EM are turned on. The i th scan signal SCAN [i] is maintained at a low level. Therefore, the first switching means SW1 and the second switching means SW2 are kept in the off state.

As described above, according to the embodiment of the driving waveform according to the second embodiment of the present invention, the nth scan signal is input such that the first switching means SW1 and the second switching means SW2 are turned on only during the data writing period. The nth emission signal may be input so that the light emitting transistor EM is turned on only during the light emission period, and the n−1th emission signal may be input so that the third switching means SW3 is turned on only during the data transfer period. .

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present specification. Therefore, the technical scope of the present specification should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

10: display panel 11: timing controller
12: data driver 13: gate driver

Claims (15)

A light emitting device that receives a driving current and emits light;
A driving transistor configured to adjust the driving current according to a voltage difference between a gate and a source;
First switching means for charging a reference voltage to one end of a capacitor connected to the gate of the driving transistor according to a scan signal;
Second switching means for charging a data voltage at the other end of the capacitor according to the scan signal; And
And a third switching means for connecting the other end of the capacitor and the source of the driving transistor in accordance with an emission signal. The method of claim 1,
And a light emitting transistor supplying a high potential voltage to a drain of the driving transistor. The method of claim 2,
And the third switching means is turned on by an N-1th signal, which is a previous signal of an Nth emission signal for turning on the light emitting transistor. The method of claim 1,
When the first switching means and the second switching means are turned on, the third switching means remains turned off to charge the data voltage to the capacitor.
When the third switching means is turned on, the first switching means and the second switching means maintain the turn-off state so that the data voltage stored in the capacitor is reflected in the potential between the gate and the source of the driving transistor. . The method of claim 4, wherein
And the light emitting transistor is turned off while the data voltage is charged in the capacitor and the data voltage stored in the capacitor is reflected in the potential between the gate and the source of the driving transistor. A display panel having a plurality of pixels connected to a data line supplied with a data voltage, a reference power line supplied with a reference voltage, and a high potential power voltage line supplied with a high potential power voltage;
Of the pixels, each pixel disposed in an n (n is a natural number) pixel row includes:
A light emitting TFT connected to an input terminal to which the high potential power voltage is input;
A light emitting element having a cathode electrode connected to an input terminal of a low potential driving voltage and an anode electrode connected to a third node;
A driving TFT controlling a driving current applied to the light emitting device, including a gate electrode connected to a first node, a source electrode connected to the third node, and a drain electrode to which the high potential power voltage is input;
A first TFT connected between the first node and the reference power line;
A second TFT connected between a second node and the data line;
A capacitor having one end connected to the first node and the other end connected to the second node; And
And a third TFT connected between the second node and the third node. The method of claim 6,
And the first TFT and the second TFT include a gate electrode to which the same signal is supplied. The method of claim 6,
The light emitting TFT includes a gate electrode to which an nth emission signal is supplied;
The third TFT includes an electroluminescence display device including a gate electrode to which an n-1th emission signal is supplied. The method of claim 6,
When the first TFT and the second TFT are turned on, the third TFT maintains a turn-off state so that the data voltage is charged in the capacitor.
And turning on the first TFT and the second TFT so that the data voltage stored in the capacitor is reflected to the potentials of the gate and the source of the driving TFT when the third TFT is turned on. The method of claim 6,
1 frame period,
A data writing period in which the data voltage is charged in the capacitor;
A data transfer period in which the data voltage stored in the capacitor is reflected in the potential of the gate and the source of the driving TFT; And
And a light emitting period for emitting the light emitting device according to the potentials of the gate and the source of the driving TFT. The method of claim 10,
The first TFT and the second TFT are switched according to an nth scan signal,
The light emitting TFT is switched by receiving an nth emission signal,
And the third TFT is switched upon receiving an n-1 emission signal. The method of claim 11,
In the data writing period,
The n-th scan signal is input at an on level,
The n-th emission signal is input at an off level,
And an n-th emission signal input to an off level. The method of claim 11,
In the data transfer period,
The n-th scan signal is input at an off level,
The n-th emission signal is input at an off level,
And the n-th emission signal is input at an on level. The method of claim 11,
In the light emitting period,
The n-th scan signal is input at an off level,
The nth emission signal is input at an on level,
And the n-th emission signal is input at an on level. The method of claim 11,
The nth scan signal is input such that the first TFT and the second TFT are turned on only during the data writing period.
The nth emission signal is input so that the light emitting TFT is turned on only during the light emitting period.
And the n-th emission signal is input such that the third TFT is turned on only during the data transfer period.

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