KR20210027970A - Pixel circuits for driving display material and display device including thereof - Google Patents

Abstract

The present invention relates to a pixel circuit and a display device including the same, and more particularly, to a pixel circuit for driving a display device and a display device including the same.
A pixel circuit according to an embodiment of the present invention includes: a storage capacitor; Display elements; A first transistor connected between a data line and one end of the storage capacitor, and a scan line connected to a gate; A second transistor connected between a reference voltage and one end of the storage capacitor and connected to a gate with an emission control signal line; A driving transistor to which a first power signal is applied to a source and the other end of the storage capacitor is connected to a gate; A third transistor connected between the gate and the drain of the driving transistor and the scan line connected to the gate; A fourth transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line; And a fifth transistor connected between a drain of the driving transistor and a reset voltage, and a reset control signal line connected to a gate.

Description

A pixel circuit for driving a display device and a display device including the same {PIXEL CIRCUITS FOR DRIVING DISPLAY MATERIAL AND DISPLAY DEVICE INCLUDING THEREOF}

The present invention relates to a pixel circuit and a display device including the same, and more particularly, to a pixel circuit for driving a display device and a display device including the same.

In a general display device, as shown in Figure 1, mХn pixels are arranged in two dimensions.

In the case of a display that drives pixels in an analog manner, each pixel has a circuit that stores an analog value, and the color of the screen is determined according to the value stored in the circuit.

To save the value in each pixel, as shown in the line selection timing diagram in Figure 1, turn on the row line sequentially from SCAN _{1 to SCAN m} , and the desired analog value in each column line (DATA ₁ ~ DATA _{n ).} (Current or voltage) can be applied.

After the values are stored in all pixels, change them to new values and repeat the above method.

The display element connected to the pixel circuit mainly uses liquid crystal (LC) or LED/OLED. For LC, the brightness is determined according to the voltage across the LC element, and LED/OLED is dependent on the current flowing across the diode. Thus, the brightness is determined. Thus, in the case of LED/OLED, the pixel circuit includes a function of converting the stored analog voltage value into a current value. In this case, when a difference in voltage-current conversion value occurs between several pixels, the overall uniformity of the screen deteriorates, which degrades the quality of the display device.

1 is a view for explaining a conventional LED/OLED display device and a driving method thereof.

Referring to FIG. 1, a conventional LED/OLED display device includes a plurality of scan lines (SCAN ₁ , SCAN ₂ , SCAN ₃ ,??, SCAN _m ), a plurality of data lines (DATA ₁ , DATA ₂ , DATA ₃ ,? ?, DATA _n ), a pixel circuit connected to each scan line and each data line, and a display element (or display material) connected to the pixel circuit. Here, the display device may be a light emitting diode (LED) or an organic light emitting diode (OLED).

Such a conventional LED/OLED display device stores analog data (or analog voltage) in each pixel through a column line while sequentially selecting row lines.

LED or OLED is a device that generates light when a current flows between both ends of the diode. Therefore, each pixel circuit has a function of converting the stored analog voltage value into a current value.

In general, the pixel circuit is a capacitor for storing an analog voltage value, a switch transistor for line selection, and a driving transistor for voltage-current conversion and LED/OLED driving. ).

Here, even if the transistors of each pixel circuit are designed to have the same type/size/shape, their characteristics may be slightly different during the manufacturing process. Due to the difference in transistor characteristics between the pixel circuits, even if the same voltage value is stored in each pixel circuit, different current values may occur, which deteriorates the uniformity characteristics of the LED/OLED display device.

For example, FIG. 2 shows an example of a 2T1C pixel circuit composed of two transistors and one capacitor.

The circuit shown in Fig. 2 operates in two phases. State 1 is data program and state 2 is emission.

3A to 3B are diagrams for explaining the principle of operation of the pixel circuit shown in FIG. 2.

Referring to (a) of FIG. 3, in the 1 state (data program), when the SCAN signal goes low, the switch transistor T ₁ is turned on, and the data is V _DATA is applied and stored in the capacitor (C ₁ ).

Referring to FIG. 3B, in the 2 state (Emission), when the SCAN signal becomes high, the switch transistor T ₁ is turned off. _{A current flows through the current driving transistor T D} by the voltage value stored in the capacitor C ₁ , and this current flows through the display device (LED/OLED). Here, the current _{flowing through the current driving transistor T D} and the display device (LED/OLED) is as shown in Equation 1 below.

In the <Equation 1>, V _{SG _TD} is V _{S_TD} -V _{G _ TD} , V _{S_TD} is the source voltage of the current driving transistor T _D (here, V _DD ), and V _{G _TD} is the current driving transistor T _Is the gate voltage of D). V _{th _TD} is threaded upon the hold voltage (threshold) of the current driving transistor (T _{D), TD} k is a value determined by the shape / size of the transistor manufacturing process, and T _D.

Here, when a plurality of the same type / size / shape of the transistors making, k _TD values are similar, but the V _{th _TD} value may vary widely. Thus, the current can vary significantly because in some cases to use a pixel circuit 2, even if the stored voltage values as the number of pixels (that is, V _{G _TD} value be the same), V _{th _TD} difference. Accordingly, the uniformity of the display device can be greatly deteriorated. Considering the high specification (high frame rate/resolution/gray scale, etc.) and low price of LED/OLED display devices in recent years, a function of compensating for a mismatch between pixels is almost indispensable.

A pixel circuit capable of solving this problem is shown in FIG. 4.

4 is an example of a conventional pixel circuit capable of compensating for _{a V th mismatch between pixels (pixels).}

Referring to FIG. 4, the conventional pixel circuit operates in three phases. State 1 is reset, state 2 is compensation/program, and state 3 is emission.

5A to 5C are diagrams for explaining the principle of operation of the pixel circuit shown in FIG. 4.

Referring to FIG. 5A, when a very low reference voltage (V _REF ) is applied _{to the data (DATA) in the 1 state (Reset), current flows to T 3} and eventually does not flow. Therefore, the gate of _{T D} The voltage becomes (V _REF + |V _{th_T3} |).

Referring to FIG. 5(b), in the second state (Compensation/program), if V DATA relatively higher than _{V REF} is applied to the _{data DATA , the current flows in T 2} and eventually stops flowing, so T _D of the gate voltage - that is _{(V DATA | | V th_T2)} .

Referring to (c) of FIG. 5, current flows in _{T D} and LED/OLED by the voltage value stored _{in C 1 in the three states (Emission).} Here, the current value is as shown in Equation 2 below.

The V _th mismatch of transistors increases as the distance between devices increases, and decreases between adjacent devices. Thus, the <Equation 2> V _{th _T2} and V _{th _TD} that has the extremely small value, I _TD is almost independent of V _th of the transistor, homogeneity (uniformity) characteristics of the display device using a pixel circuit Can be improved.

However, in general, since the current driving transistor (T _D ) is designed to be relatively large and the remaining switch transistors (T ₁ , T ₂ , T ₃ ) are designed to be relatively small, V _{th _T2} and V _{th due to the difference in size} There is a difference in _{_TD.} If this difference is the same value between several pixels, it does not affect the uniformity of the display device, but it is likely not. In addition, the V _th of the transistor varies according to the magnitude of the source-body voltage difference (this is called a body effect). To facilitate the layout of the pixel circuit, both the bodies of _{T 3} and T _{D are connected to V DD} . When connected, a _{difference in V th} occurs due to a difference in source voltage between _{the two transistors T 2} and T _D. Accordingly, the pixel circuit illustrated in FIG. 4 may have better uniformity than the pixel circuit illustrated in FIG. 2, but the degree may not be sufficient.

The disadvantage of the pixel circuit of FIG. 4 compared to the pixel circuit of FIG. 2 _{is that V REF} and V _DATA must be sequentially applied to the data line during the _{scan time T SCAN.} To this end, a column line drive that drives a data line must operate at high speed. Therefore, power consumption may increase.

Another disadvantage of the pixel circuit of FIG. 4 is that T _D is _{applied while resetting data to the pixel (that is, while applying V REF to the data DATA as in FIG. 5A).} It is turned on and current flows through the display device (LED/OLED). Since the current is _{determined by the V REF} value, it is constant regardless of the gray level (ie, V _{DATA value) to be actually applied to the pixel.} Therefore, even when a low gray level value is to be applied to the pixel, the display device (LED/OLED) has a certain brightness value. This may be a cause of lowering the contrast ratio of the display device.

Another conventional pixel circuit for improving the V _th mismatch compensation function of the pixel circuit of FIG. 4 will be described with reference to FIG. 6.

6 is another example of a conventional pixel circuit capable of compensating for _{a V th} mismatch between pixels (pixels).

Referring to FIG. 6, the pixel circuit operates in three phases. State 1 is reset, state 2 is compensation/program, and state 3 is emission.

7A to 7C are diagrams for explaining the principle of operation of the pixel circuit shown in FIG. 6.

Referring to (a) of 7, in the first state (Reset) and a gate and a drain of T _D is connected to V _DD, a source of T _D is applied to V _DATA and V _SS at the same time.

Referring to (b) of FIG. 7, T _D is _{separated from V DD} and the display device (LED/OLED) in _{the two states (Compensation/program), and only V DATA} is applied to the source of _{T D.} At this time, _{the current value of T D} gradually decreases and eventually becomes zero. Therefore, the gate voltage value of _{T D becomes (V DATA} + V _{th _TD_comp} ). Here, V _{th _TD_comp} is the V _th value of _{T D} in the two state (compensation/program). The V _{th_TD_comp} value is stored in _{C 1.}

Referring to (c) of FIG. 7, _{T D} is _{connected to V DD} and the display device (LED/OLED) while maintaining the voltage value stored _{in C 1 in the three states (Emission).} At this time, _{the current values of T D} and the display device (LED/OLED) are as shown in Equation 3 below.

In Equation 3, V _{th_TD_EMIT} is the V _th value of _{T D} in the 3 state (emission).

)값이 0이 아닐 수 있다. 상기 값은 입력하고자 하는 V_DATA 값에 따라서 달라지게 되는데, 같은 V_DATA 값에서 화소 간의 (

)값의 차이만 없으면, 디스플레이 장치의 균일성(uniformity)에 영향을 주지 않는다. 하지만, 화소 간의 T_D 소자의 V_th 미스매치(mismatch) 때문에, 상기 값도 차이가 날 수 있다. 따라서, 도 6의 화소 회로는 도 4의 화소 회로보다 균일성(uniformity)을 더 좋게 할 수 있지만, 그 정도가 충분하지 않을 수 있다.Referring to Equation 3, it can be seen that _{unlike Equation 2, V th} mismatch between internal elements of a pixel is not affected. However, the source voltage of T _D in the second state (compensation / program) and the source voltage of the third state T _D (emission) in varies, (

) Value may not be 0. The above value _{varies depending on the V DATA} value to be input. At the same V _DATA value, the (

If there is only a difference in) value, it does not affect the uniformity of the display device. However, due to a V _{th mismatch of the T D} element between pixels, the above value may also be different. Accordingly, the pixel circuit of FIG. 6 may have better uniformity than the pixel circuit of FIG. 4, but the degree may not be sufficient.

Another advantage of the pixel circuit of FIG. 6 compared to the pixel circuit of FIG. 4 is that, as shown in FIG. 7 (b), the display device (LED/OLED) is used while programming data into the pixel. ) Is that no current flows. Accordingly, the display device using the pixel circuit of FIG. 6 may have a higher contrast ratio than the display device using the pixel circuit of FIG. 4.

In addition, unlike the pixel circuit of FIG. 4, since only V _{DATA is applied to the data line of the pixel circuit of FIG. 6 during T SCAN} , the column line driver does not need to operate at high speed. Therefore, low power design of the column line driver is possible.

Meanwhile, the disadvantage of the pixel circuit of FIG. 6 compared to the pixel circuit of FIG. 4 is that the total number of transistors is increased from 4 to 7. Therefore, there is a limit to reducing the pixel size, which may adversely affect the screen resolution of the display device.

Another disadvantage of the pixel circuit of FIG. 6 is _{that V DATA} and V _SS are simultaneously applied to the source of _{T D in the first state (reset).} In this case, a voltage collision may occur, and unnecessary overcurrent may flow through a column line driver that drives _{V DATA.}

A pixel circuit having fewer transistors than the pixel circuit of FIG. 6 and capable of improving screen uniformity than the pixel circuit of FIG. 4 will be described with reference to FIG. 8.

8 is another example of a conventional pixel circuit capable of compensating for _{a V th mismatch between pixels (pixels).}

Referring to FIG. 8, the pixel circuit operates in three phases. State 1 is compensation, state 2 is program, and state 3 is emission.

9A to 9C are diagrams for explaining the principle of operation of the pixel circuit shown in FIG. 8.

Referring to FIG. 9A, in the first state (Compensation), T _D is separated from the display device (LED/OLED) while the gate and drain are tied, and V _REF is applied to _{C 2.} At this time, T _D is flowed as a discharge current in the prior three-state (emission) and no current flows after all, the gate voltage of T _D is the V _{th _TD.} Therefore, the _{voltage across C 1} becomes (V _REF -V _{th_TD} ).

Referring to (b) of FIG. 9, V _DATA is applied to _{C 2 in the 2 state (Program).} Thus, _{the gate of T D} is floating, so the voltage across _{C 1} is kept at _{(V REF} -V _{th _TD ).} As a result, the gate voltage of T _D is _{[V DATA - (V REF -} V th _TD) = (V DATA -V _REF ) + V _{th_TD} ].

Referring to (c) of FIG. 9, the _{voltage values stored in C 1} and C ₂ in the three states (Emission) are maintained as they are. At this time, _{the current values of T D} and the display device (LED/OLED) are as shown in Equation 4 below.

Referring to the <Equation 4>, it can be seen that unlike the <Equation 2> and <Equation 3>, there is no effect on the _{V th mismatch between the internal elements of the pixel. In addition, since the source of T D} is always _{connected to V SS} in the first state (compensation) and the third state (emission), it can be seen that there is no influence _{of V th} change due to a body effect. Accordingly, the pixel circuit of FIG. 8 may have better uniformity than the pixel circuits of FIGS. 4 and 6.

However, the pixel circuit of FIG. 8 does not have an initial reset state (or step). Therefore, in the case, the time of the first state (compensation) is not long enough to as flowing current is discharged in the previous third state (emission) in the first state (compensation), the gate voltage of T _D converges to V _{th _TD,} The gate voltage of T _D may be different from _{V th _TD.} This difference value becomes dependent on the _{previous V DATA value.} Accordingly, when pixels having different previous values of the display device must display the same gray level, uniformity may deteriorate.

Meanwhile, the pixel circuit of FIG. 8 does not have a reset state (or step), but since current does not flow through the display device (LED/OLED) in the first state (compensation), a high contrast ratio as in the pixel circuit of FIG. 6 Can have. However, in the pixel circuit of FIG. 8, like the pixel circuit of FIG. 4 _{, since V REF} and V _DATA must be sequentially applied to the data (DATA) line during _{T SCAN} , the data (DATA) line is The column line driver to be driven must operate at high speed. Accordingly, power consumption of the column line driver may increase.

Another disadvantage of the pixel circuit of FIG. 8 is that, unlike previous pixel circuits, two capacitors are used. When two capacitors are used in a given area, each capacitance value decreases. In this case, the voltage value stored in the capacitor may vary over time due to a leakage current. If the screen resolution or frame rate of the display device is high, T _SCAN Since the value is small, this problem can be okay, but in this case, as mentioned above, the column line driver must operate at very high speed.

Sang-Hoon Jung, A new voltage modulated AMOLED pixel design compensating threshold voltage variation of poly-Si TFTs, SID Digest. 2002. Jae-Hoon Lee, A new a-Si:H TFT pixel design compensating threshold voltage degradation of TFT and OLED, SID Digest. 2004. Sang-Hoon Jung, An active-matrix organic light-emitting-diode pixel circuit for the compensation of IХR voltage drop in power line, Journal of the SID. 2007.

The present invention provides a pixel circuit that is not affected by _{a threshold voltage (V th} ) of a transistor and a display device (LED or OLED), and a display device including the same.

In addition, a pixel circuit capable of minimizing a voltage-current conversion difference between pixels, and a display device including the same are provided.

Further, a pixel circuit capable of improving quality and yield, and a display device including the same are provided.

A pixel circuit according to an embodiment of the present invention includes: a storage capacitor; Display elements; A first transistor connected between a data line and one end of the storage capacitor, and a scan line connected to a gate; A second transistor connected between a reference voltage and one end of the storage capacitor and connected to a gate with an emission control signal line; A driving transistor to which a first power signal is applied to a source and the other end of the storage capacitor is connected to a gate; A third transistor connected between the gate and the drain of the driving transistor and the scan line connected to the gate; A fourth transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line; And a fifth transistor connected between a drain of the driving transistor and a reset voltage, and a reset control signal line connected to a gate.

A pixel circuit according to another embodiment of the present invention includes: a storage capacitor; Display elements; A first transistor connected between a data line and one end of the storage capacitor, and a scan line connected to a gate; A second transistor connected between a reference voltage and one end of the storage capacitor and connected to a gate with a complementary scan line opposite to the scan line; A driving transistor to which a first power signal is applied to a source and the other end of the storage capacitor is connected to a gate; A third transistor connected between the gate and the drain of the driving transistor and the scan line connected to the gate; And a fourth transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line.

A pixel circuit according to another embodiment of the present invention includes: a first storage capacitor to which a first power signal is applied to one end; A second storage capacitor having one end connected to the other end of the first storage capacitor; Display elements; A first transistor connected between a data line and the other end of the first storage capacitor, and a scan line connected to a gate; A driving transistor to which the first power signal is applied to a source and the other end of the second storage capacitor is connected to a gate; A second transistor connected between a gate and a drain of the driving transistor and a digital input/output line connected to the gate; A third transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line; And a fourth transistor connected between a drain of the driving transistor and a reset voltage, and a reset control signal line connected to a gate.

A pixel circuit according to another embodiment of the present invention includes: a first storage capacitor to which a first power signal is applied to one end; A second storage capacitor having one end connected to the other end of the first storage capacitor; Display elements; A first transistor connected between a data line and the other end of the first storage capacitor, and a scan line connected to a gate; A driving transistor to which the first power signal is applied to a source and the other end of the second storage capacitor is connected to a gate; A second transistor connected between a gate and a drain of the driving transistor and a digital input/output line connected to the gate; And a third transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line.

A pixel circuit according to another embodiment of the present invention includes: a first storage capacitor; A second storage capacitor to which a first power signal is applied and the other end is connected to the other end of the first storage capacitor; Display elements; A first transistor connected between a data line and one end of the first storage capacitor, and a scan line connected to a gate; A driving transistor to which the first power signal is applied to a source and the other end of the second storage capacitor is connected to a gate; A second transistor connected between a gate and a drain of the driving transistor and a digital input/output line connected to the gate; A third transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line; And a fourth transistor connected between a drain of the driving transistor and a reset voltage, and a reset control signal line connected to a gate.

A pixel circuit according to another embodiment of the present invention includes: a first storage capacitor to which a first power signal is applied to one end; A second storage capacitor having one end connected to the other end of the first storage capacitor; Display elements; A first transistor connected between a data line and the other end of the first storage capacitor, and a scan line connected to a gate; A second transistor connected between a reference voltage and the other end of the first storage capacitor, and a digital input/output line connected to a gate; A driving transistor to which the first power signal is applied to a source and the other end of the second storage capacitor is connected to a gate; A third transistor connected between the gate and the drain of the driving transistor and the digital input/output line connected to the gate; A fourth transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line; And a fifth transistor connected between a drain of the driving transistor and a reset voltage, and a reset control signal line connected to a gate.

A pixel circuit according to another embodiment of the present invention includes: a first storage capacitor to which a first power signal is applied to one end; A second storage capacitor having one end connected to the other end of the first storage capacitor; Display elements; A first transistor connected between a data line and the other end of the first storage capacitor, and a scan line connected to a gate; A second transistor connected between a reference voltage and the other end of the first storage capacitor, and a digital input/output line connected to a gate; A driving transistor to which the first power signal is applied to a source and the other end of the second storage capacitor is connected to a gate; A third transistor connected between the gate and the drain of the driving transistor and the digital input/output line connected to the gate; And a fourth transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line.

A pixel circuit according to another embodiment of the present invention includes: a first storage capacitor; A second storage capacitor to which a first power signal is applied and the other end is connected to the other end of the first storage capacitor; Display elements; A first transistor connected between a data line and one end of the first storage capacitor, and a scan line connected to a gate; A second transistor connected between a reference voltage and one end of the first storage capacitor, and a digital input/output line connected to a gate; A driving transistor to which the first power signal is applied to a source and the other end of the second storage capacitor is connected to a gate; A third transistor connected between the gate and the drain of the driving transistor and the digital input/output line connected to the gate; A fourth transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line; And a fifth transistor connected between a drain of the driving transistor and a reset voltage, and a reset control signal line connected to a gate.

A display device according to an embodiment of the present invention includes at least one of the aforementioned various pixel circuits.

The use of the pixel circuit and the display device including the same according to an embodiment of the present invention has an advantage that is not affected by _{a threshold voltage (V th) of a transistor and a display device (LED or OLED).} Accordingly, it is possible to improve the screen uniformity of the display device.

In addition, there is an advantage of minimizing a voltage-current conversion difference between pixels.

In addition, there is an advantage that can improve the quality and yield.

In addition, since it is advantageous for high-speed operation, there is an advantage that it can be easily used in a display device requiring a high frame rate.

1 is a view for explaining a driving method of a display device having a conventional general display device (LED/OLED).
2 is an example of a conventional pixel circuit applicable to the display device shown in FIG. 1.
3A to 3B are diagrams for explaining the principle of operation of the pixel circuit shown in FIG. 2.
4 is an example of a conventional pixel circuit capable of compensating for _{a V th mismatch between pixels (pixels).}
5A to 5C are diagrams for explaining the principle of operation of the pixel circuit shown in FIG. 4.
6 is another example of a conventional pixel circuit capable of compensating for _{a V th} mismatch between pixels (pixels).
7A to 7C are diagrams for explaining the principle of operation of the pixel circuit shown in FIG. 6.
8 is another example of a conventional pixel circuit capable of compensating for _{a V th mismatch between pixels (pixels).}
9A to 9C are diagrams for explaining the principle of operation of the pixel circuit shown in FIG. 8.
10 is a pixel circuit of a display device according to an embodiment of the present invention.
11A to 11C are diagrams for explaining the principle of operation of the pixel circuit according to the embodiment of the present invention shown in FIG. 10.
12 is a pixel circuit of a display device according to another embodiment of the present invention.
13A to 13C are diagrams for explaining the principle of operation of the pixel circuit according to the embodiment of the present invention shown in FIG. 12.
14 is a pixel circuit of a display device according to still another embodiment of the present invention.
15A to 15D are diagrams for explaining an operating principle of a pixel circuit according to still another embodiment of the present invention shown in FIG. 14.
16 is a pixel circuit of a display device according to still another embodiment of the present invention.
17A to 17D are diagrams for explaining an operating principle of a pixel circuit according to still another embodiment of the present invention shown in FIG. 16.
18 is a pixel circuit of a display device according to still another embodiment of the present invention.
19A to 19D are diagrams for explaining an operating principle of a pixel circuit according to still another embodiment of the present invention shown in FIG. 18.
20 is a pixel circuit of a display device according to still another embodiment of the present invention.
21A to 21D are diagrams for explaining the principle of operation of the pixel circuit according to still another embodiment of the present invention shown in FIG. 20.
22 is a pixel circuit of a display device according to still another embodiment of the present invention.
23A to 23D are diagrams for explaining an operating principle of a pixel circuit according to still another embodiment of the present invention shown in FIG. 22.
24 is a pixel circuit of a display device according to still another embodiment of the present invention.
25A to 25D are diagrams for explaining an operating principle of a pixel circuit according to still another embodiment of the present invention shown in FIG. 24.

Hereinafter, exemplary embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but identical or similar elements are denoted by the same reference numerals regardless of reference numerals, and redundant descriptions thereof will be omitted. The suffix "unit" for the constituent elements used in the following description is given or used interchangeably in consideration of only the ease of writing the specification, and does not itself have a distinct meaning or role from each other.

In addition, in describing the embodiments disclosed in the present specification, when it is determined that a detailed description of related known technologies may obscure the subject matter of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are for easy understanding of the embodiments disclosed in the present specification, and the technical idea disclosed in the present specification is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention It should be understood to include equivalents or substitutes.

Terms including ordinal numbers such as first and second may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another component.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Singular expressions include plural expressions unless the context clearly indicates otherwise.

In this application, terms such as "comprises" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, but one or more other features. It is to be understood that the presence or addition of elements, numbers, steps, actions, components, parts, or combinations thereof, does not preclude in advance the possibility of being excluded.

10 is a pixel circuit of a display device according to an embodiment of the present invention.

The pixel circuit according to the embodiment of the present invention illustrated in FIG. 10 has a higher uniformity than the conventional pixel circuits illustrated in FIGS. 2, 4, 6, and 8 and has a high contrast ratio. There is an advantage in that there is no need to maintain, use a capacitor to a minimum (for example, one), and to operate a column line driver at high speed.

Referring to FIG. 10, a pixel circuit according to an embodiment of the present invention includes a storage capacitor C ₁ , a driving transistor T _D , a display device, and a plurality of transistors T ₁ , T ₂ , T ₃ , and T _4. , T ₅ ).

The driving transistor T _D and the display device are connected between _{the first power signal V DD} and the second power signal V _SS. The driving transistor T _D is connected to the other end of the storage capacitor C _{1 and a first power signal V DD} is applied to the source.

A plurality of transistors (T ₁ , T ₂ , T ₃ , T ₄ , T ₅ ) are connected between the data line (DATA) and _{one end of the storage capacitor (C 1} ), and the scan line (SCAN) is connected to the gate. _{1 A second transistor T 2} connected between the transistor T ₁ , the reference voltage V _REF and one end of the storage capacitor C ₁ , and the emission control signal line EMIT connected to the gate, and the driving transistor T _{The third transistor T 3} is connected between the gate and the drain of _D ) and the scan line SCAN is connected to the gate, and the emission control signal line EMIT is connected between the driving transistor T _{D and the display device.} The connected fourth transistor T _{4 includes a fifth transistor T 5} connected between the drain of the driving transistor T _D and the reset voltage V _RST , and the reset control signal line RST connected to the gate.

The scan line SCAN, the reset control signal line RST, the emission control signal line EMIT, and the data line DATA are consecutive first state period ((1)), second state period ((2)) and It has a predetermined timing diagram according to the third state period (3). Specifically, the scan line SCAN is low in the first and second state periods and high in the third state period. The reset control signal line RST is low in the first state period and high in the second and third state periods. The emission control signal line EMIT is high in the first and second state periods and low in the third state period. The data line DATA is applied with a _{predetermined data voltage V DATA} in the first and second state periods.

The pixel circuit according to the embodiment of the present invention illustrated in FIG. 10 operates in three phases according to three state periods. The first state is reset, the second state is compensation/program, and the third state is emission.

11A to 11C are diagrams for explaining the principle of operation of the pixel circuit according to the embodiment of the present invention shown in FIG. 10. More specifically, FIG. 11(a) is an equivalent circuit of the pixel circuit shown in FIG. 10 in the first state period ((1)), and FIG. 11(b) is the second state period ((2) )) is an equivalent circuit of the pixel circuit shown in FIG. 10, and FIG. 11(c) is an equivalent circuit of the pixel circuit shown in FIG. 10 in the third state period (3).

Referring to FIG. 11A, in the first state period (Reset), T _D is electrically connected to a gate and a drain to be connected to V _RST , and separated from the display device (LED/OLED). And, C ₁ is applied to the V _DATA.

Referring to FIG. 11B, in the second state period (Compensation/Program), V _DATA is applied as it is _{to C 1 , and the gate and drain of T D} are electrically connected and floating. Therefore, the gate voltage of _{T D becomes (V DD-} |V _{th_TD} |).

Referring to (c) of FIG. 11, when T ₁ is off and T ₂ is on in _{the third state period (Emission), the connection of C 1} is V in the data line (DATA). _It will be changed to REF. Also, the gate of _{T D is floating.} At this time, the voltage value stored in the _{C 1 (V DATA - (V} DD - | V th _TD |)) is retained. Thus, the gate voltage of T _D is _{[V REF - (V DATA -} (V DD - |) | V th_TD)] because it is, [(V _REF -V _DATA ) + V _DD- |V _{th _TD} |]. Here, T _D and the current values of the display device (LED/OLED) are as shown in Equation 5 below.

Referring to <Equation 5>, similar to the above-described <Equation 4>, there is no effect on _{V th mismatch between devices within a pixel, and V th} change due to a body effect It can be seen that there is also no influence of. Accordingly, the pixel circuit of FIG. 10 may have better uniformity than the pixel circuits of FIGS. 4 and 6.

In the pixel circuit according to the embodiment of the present invention illustrated in FIG. 10, unlike the pixel circuit of FIG. 8, since an initial reset state (first state period) exists separately, the previous data of the current current (data ) It has the advantage of no dependence.

In addition, the pixel circuit according to the embodiment of the present invention shown in FIG. 10 is, as shown in FIG. 11B, while programming data in the pixel (second state period). Since no current flows through the display device (LED/OLED), it can have a high contrast ratio.

Further, in the pixel circuit according to the embodiment of the present invention shown in FIG. 10, _{since only V DATA} is applied to the data line DATA, the column line driver does not need to operate at high speed. Therefore, there is also an advantage that a low power design of a column line driver is possible.

12 is a pixel circuit of a display device according to another embodiment of the present invention.

The pixel circuit according to another embodiment of the present invention illustrated in FIG. 12 uses a smaller number of transistors than the pixel circuit illustrated in FIG. 10. Accordingly, the pixel circuit according to another embodiment of the present invention shown in FIG. 12 has an advantage that can be used when a small pixel design is required.

Referring to FIG. 12, a pixel circuit according to another embodiment of the present invention includes a storage capacitor C ₁ , a driving transistor T _D , a display device, and a plurality of transistors T ₁ , T ₂ , T ₃ , and T _4. ).

The driving transistor T _D and the display device are connected between _{the first power signal V DD} and the second power signal V _SS. The driving transistor T _D is connected to the other end of the storage capacitor C _{1 and a first power signal V DD} is applied to the source.

The plurality of transistors T ₁ , T ₂ , T ₃ , T ₄ are connected between the data line DATA and _{one end of the storage capacitor C 1} , and the first transistor SCAN is connected to the gate. T1), _{the second transistor T 2 connected between the reference voltage V REF} and one end of the storage capacitor C ₁ and the complementary scan line SCAN_R connected to the gate, and the gate of the driving transistor T _{D A third transistor T 3} connected between the drain and connected to the gate with a scan line SCAN, and a fourth transistor connected between the driving transistor T _D and the display device and connected to the gate with an emission control signal line EMIT T ₄ ).

The scan line (SCAN), the complementary scan line (SCAN_R), the emission control signal line (EMIT), and the data line (DATA) are connected to the first state section ((1)), the second state section ((2)), and the second state section ((2)). It has a predetermined timing diagram according to the three-state period (3). Specifically, the scan line SCAN is low in the first and second state periods and high in the third state period. Complementary scan line SCAN_R As a signal opposite to the scan line SCAN, it is high in the first and second state periods and low in the third state period. The emission control signal line EMIT is low in the first and third state periods and high in the second state period. The data line DATA is applied with a _{predetermined data voltage V DATA} in the first and second state periods.

The pixel circuit according to another embodiment of the present invention illustrated in FIG. 12 operates in three phases according to three state periods. The first state period is reset, the second state period is compensation/program, and the third state period is emission.

13A to 13C are diagrams for explaining the principle of operation of the pixel circuit according to the embodiment of the present invention shown in FIG. 12. More specifically, FIG. 13(a) is an equivalent circuit of the pixel circuit shown in FIG. 12 in the first state period, and FIG. 13(b) is the pixel circuit shown in FIG. 12 in the second state period. And FIG. 13C is an equivalent circuit of the pixel circuit shown in FIG. 12 in the third state section.

Comparing FIGS. 13A to 13C with FIGS. 11A to 11C, a first state section of the pixel circuit according to another embodiment of the present invention shown in FIG. 13 is shown in FIG. It is different from the illustrated first state period of the pixel circuit according to the exemplary embodiment of the present invention. On the other hand, the second state and the third state section of the pixel circuit according to another embodiment of the present invention shown in FIG. 13 is the second state and the third state of the pixel circuit according to the embodiment of the present invention shown in FIG. Same as section.

Referring to FIG. 13A, in the first state period (Reset), _{the gate and drain of T D} are electrically connected to the display device (LED/OLED). At this time, since a current flows through the display device (LED/OLED), the pixel circuit illustrated in FIG. 12 may have a slightly lower contrast ratio than the pixel circuit illustrated in FIG. 10. However, by adjusting the timing of the emission control signal line EMIT to make the reset period as small as possible, deterioration of the contrast ratio can be prevented as much as possible.

14 is a pixel circuit of a display device according to still another embodiment of the present invention.

The pixel circuit shown in FIG. 14 according to another embodiment of the present invention has an advantage of maintaining a high contrast ratio while reducing the number of transistors by one compared to the pixel circuit shown in FIG. 10.

Referring to FIG. 14, a pixel circuit according to another embodiment of the present invention includes a first storage capacitor C ₁ , a second storage capacitor C ₂ , a driving transistor T _D , a display element, and a plurality of transistors. (T ₁ , T ₂ , T ₃ , T ₄ ).

The driving transistor T _D and the display device are connected between _{the first power signal V DD} and the second power signal V _SS. The driving transistor T _D is connected to the other end of the second storage capacitor C _{2 and a first power signal V DD} is applied to the source.

One end of the first storage capacitor C ₁ is connected to the first power signal V _DD , and the other end is connected to one end of the second storage capacitor C ₂ . The other end of the second storage capacitor C ₂ is connected to the gate of the _{driving transistor T D.}

The plurality of transistors T ₁ , T ₂ , T ₃ , T _{4 are} connected between the data line DATA and the _{other end of the first storage capacitor C 1} , and the scan line SCAN is connected to the gate. _{The second transistor T 2} is connected between the gate and the drain of the transistor T ₁ and the driving transistor T _D and the digital input/output line DIO is connected to the gate, and the driving transistor T _D is connected between the display element. _{And the third transistor T 3} to which the emission control signal line EMIT is connected to the gate, the drain of the driving transistor T _D and the reset voltage V _RST are connected, and the reset control signal line RST is connected to the gate. And a fourth transistor T ₄ .

The scan line (SCAN), the digital input/output line (DIO), the reset control signal line (RST), the emission control signal line (EMIT), and the data line (DATA) are in a continuous first state period ((1)), and a second state. It has a predetermined timing diagram according to the period (2)), the third state period (3), and the fourth state period (4). Specifically, the scan line SCAN is low in the first through third state period and high in the fourth state period. The digital input/output line DIO is low in the first and second state periods and high in the third and fourth state periods. The reset control signal line RST is low in the first state period and high in the second to fourth state periods. The emission control signal line EMIT is high in the first to third state periods and low in the fourth state period. The data line DATA _{is applied with V DATA} or V _REF in the first and second state periods, and is applied opposite to the first and second state periods in the third and fourth state periods.

The pixel circuit according to another embodiment of the present invention illustrated in FIG. 14 operates in four phases according to four state periods. The first state period is reset, the second state period is compensation, the third state period is program, and the fourth state period is emission.

15A to 15D are diagrams for explaining an operating principle of a pixel circuit according to still another embodiment of the present invention shown in FIG. 14. More specifically, FIG. 15(a) is an equivalent circuit of the pixel circuit shown in FIG. 14 in the first state period, and FIG. 15(b) is the pixel circuit shown in FIG. 14 in the second state period. 15(c) is the equivalent circuit of the pixel circuit shown in FIG. 14 in the third state period, and FIG. 15(d) is the pixel circuit shown in FIG. 14 in the fourth state period. Is the equivalent circuit of

Referring to FIG. 15A, in the first state period (Reset), T _D is electrically connected to a gate and a drain to be connected to V _RST , and separated from a display device (LED/OLED). And, C ₁ is applied to the V _DATA.

Referring to FIG. 15B, in the second state period (Compensation), V _{DATA is applied to C 1} as it is, and _{the gate and drain of T D} are electrically connected to be floating. Therefore, the gate voltage of _{T D becomes (V DD-} |V _{th_TD} |).

Referring to (c) of FIG. 15, the voltage on the data line (DATA) is changed from V _{DATA to V REF in the third state period (Program).} Also, the gate of _{T D is floating.} At this time, the voltage value stored in _{C 2 (V DATA - (V} DD - | V th _TD |)) is retained. Thus, the gate voltage of T _D is _{[V REF - (V DATA -} (V DD - | V th _TD |))] because it is, (V _REF -V _DATA ) + V _DD- |V _{th_TD} |

_{Referring to FIG. 15D, voltage values stored in C 1} and C ₂ are maintained as they are in the fourth state period (Emission). At this time, T _D and the current values of the display device (LED/OLED) are as shown in Equation 6 below.

Referring to <Equation 6>, it is the same as <Equation 5> described above. Accordingly, it can be seen _{that there is no effect on V th} mismatch between devices in the pixel, and there is no effect of V _{th change due to a body effect.}

On the other hand, if _{the order of applying V DATA} and V _REF is changed from above, the operation is the same, and the T _D and the current value of the display element (LED/OLED) in the fourth state period (Emission) are the following equation. It changes as shown in 7.

In contrast to the pixel circuit shown in FIG. 10, the pixel circuit shown in FIG. 14 has one more capacitor instead of one smaller transistor. Accordingly, the pixel circuit shown in FIG. 10 or the pixel circuit shown in FIG. 14 may be selectively used in consideration of the minimum transistor size and the capacitance size per area for a given fabrication process.

In the pixel circuit shown in FIG. 14, since _{V REF} and V _DATA must be sequentially applied to the data (DATA) line during _{T SCAN} , compared to the pixel circuit shown in FIG. 10, the data (DATA) line ( line) must operate at high speed, and thus power consumption may increase.

16 is a pixel circuit of a display device according to still another embodiment of the present invention.

The pixel circuit shown in FIG. 16 according to another embodiment of the present invention has an advantage of reducing the number of transistors by one more than the pixel circuit shown in FIG. 14. Therefore, it is possible to downsize the pixel circuit.

The pixel circuit according to another embodiment of the present invention illustrated in FIG. 16 includes a first storage capacitor C ₁ , a second storage capacitor C ₂ , a driving transistor T _D , a display element, and a plurality of transistors. T ₁ , T ₂ , T ₃ ).

The driving transistor TD and the display device are connected between _{the first power signal V DD} and the second power signal V _SS. The driving transistor T _D is connected to the other end of the second storage capacitor C _{2 and a first power signal V DD} is applied to the source.

One end of the first storage capacitor C ₁ is connected to the first power signal V _DD , and the other end is connected to one end of the second storage capacitor C ₂ . The other end of the second storage capacitor C ₂ is connected to the gate of the _{driving transistor T D.}

The plurality of transistors T ₁ , T ₂ , and T _{3 are} connected between the data line DATA and the _{other end of the first storage capacitor C 1} , and the first transistor T is connected to the gate with the scan line SCAN. _{1 ), the second transistor T 2} connected between the gate and the drain of the driving transistor T _D and the digital input/output line DIO connected to the gate, the second transistor T 2 connected between the driving transistor T _D and the display device, and connected to the gate. _{And a third transistor T 3} to which the emission control signal line EMIT is connected.

The scan line (SCAN), the digital input/output line (DIO), the emission control signal line (EMIT), and the data line (DATA) are connected to the first state section ((1)), the second state section ((2)), and the second state section. It has a predetermined timing diagram according to the three state period (3) and the fourth state period (4). Specifically, the scan line SCAN is low in the first through third state period and high in the fourth state period. The digital input/output line DIO is low in the first and second state periods and high in the third and fourth state periods. The emission control signal line EMIT is high in the second and third state periods and low in the first and fourth state periods. The data line DATA _{is applied with V DATA} or V _REF in the first and second state periods, and is applied opposite to the first and second state periods in the third and fourth state periods.

The pixel circuit according to still another embodiment of the present invention illustrated in FIG. 16 operates in four phases according to four state periods. The first state period is reset, the second state period is compensation, the third state period is program, and the fourth state period is emission.

17A to 17D are diagrams for explaining an operating principle of a pixel circuit according to still another embodiment of the present invention shown in FIG. 16. More specifically, FIG. 17(a) is an equivalent circuit of the pixel circuit shown in FIG. 16 in the first state period, and FIG. 17(b) is the pixel circuit shown in FIG. 16 in the second state period. 17(c) is the equivalent circuit of the pixel circuit shown in FIG. 16 in the third state period, and FIG. 17(d) is the pixel circuit shown in FIG. 16 in the fourth state period. Is the equivalent circuit of

Comparing FIGS. 17A to 17D and 15A to 15D, a first state section of the pixel circuit according to another embodiment of the present invention shown in FIG. 17 is shown in FIG. 15. It is different from the illustrated first state period of the pixel circuit according to another embodiment of the present invention. On the other hand, the second to fourth state periods of the pixel circuit according to another embodiment of the present invention shown in FIG. 17 are the second to fourth states of the pixel circuit according to another embodiment of the present invention shown in FIG. 15. It is the same as the state section.

Referring to FIG. 17A, in the first state period (Reset), _{the gate and drain of T D} are electrically connected to the display device (LED/OLED). At this time, since current flows through the display device (LED/OLED), the pixel circuit of FIG. 16 may have a slightly lower contrast ratio than the pixel circuit of FIG. 14. However, by adjusting the timing of the emission (EMIT) signal to make the reset period as small as possible, deterioration of the contrast ratio can be prevented as much as possible.

Referring to <Equation 5>, <Equation 6>, and <Equation 7> described above, the current value of the display element (LED/OLED) of the pixel circuits of FIGS. 10, 12, 14, and 16 is V _It is proportional to the square of DATA. This _{is assuming that the channel of T D} is strong inversion. In some cases, it is necessary to operate in a sub-threshold region where the channel is not sufficiently inverted. In particular, this is the case when it is necessary to input a voltage of a very low gray level to a pixel (that is, when a very small current is to be passed through a display device (LED/OLED)).

When the transistor operates in the sub-threshold region, the current is not proportional to the square of the input voltage, but increases according to the exponential function as shown in Equation 8 below. do.

In Equation 8, a and b are constant values determined by the fabrication process and the size/shape of the transistor.

When the current of the transistor changes according to Equation 8, even if the input voltage changes slightly, the current changes very much. Therefore, when it is necessary to change the current of the transistor little by little, the input voltage must be adjusted very finely. This can be a burden on column line driver design.

18 is a pixel circuit of a display device according to still another embodiment of the present invention.

The pixel circuit shown in FIG. 18 according to another embodiment of the present invention can reduce the design burden of the column line driver included in the pixel circuit shown in FIG. 16.

The pixel circuit according to another embodiment of the present invention illustrated in FIG. 18 includes a first storage capacitor C ₁ , a second storage capacitor C ₂ , a driving transistor T _D , a display element, and a plurality of transistors. T ₁ , T ₂ , T ₃ , T ₄ ).

The driving transistor T _D and the display device are connected between _{the first power signal V DD} and the second power signal V _SS. The driving transistor T _D is connected to the other end of the first storage capacitor C _{1 and a first power signal V DD} is applied to the source.

One end of the second storage capacitor C ₂ is connected to the first power signal V _DD and the other end is connected to the other end of the first storage capacitor C ₁ .

The plurality of transistors T ₁ , T ₂ , T ₃ , T _{4 are} connected between the data line DATA and _{one end of the first storage capacitor C 1} , and the scan line SCAN is connected to the gate. _{The second transistor T 2} is connected between the gate and the drain of the transistor T ₁ and the driving transistor T _D and the digital input/output line DIO is connected to the gate, and the driving transistor T _D is connected between the display element. _{And the third transistor T 3} to which the emission control signal line EMIT is connected to the gate, the drain of the driving transistor T _D and the reset voltage V _RST are connected, and the reset control signal line RST is connected to the gate. And a fourth transistor T ₄ .

The scan line (SCAN), the digital input/output line (DIO), the reset control signal line (RST), the emission control signal line (EMIT), and the data line (DATA) are in a continuous first state period ((1)), and a second state. It has a predetermined timing diagram according to the period (2)), the third state period (3), and the fourth state period (4). Specifically, the scan line SCAN is low in the first through third state period and high in the fourth state period. The digital input/output line DIO is low in the first and second state periods and high in the third and fourth state periods. The reset control signal line RST is low in the first state period and high in the second to fourth state periods. The emission control signal line EMIT is high in the first to third state periods and low in the fourth state period. The data line DATA _{is applied with V DATA} or V _REF in the first and second state periods, and is applied opposite to the first and second state periods in the third and fourth state periods.

The pixel circuit according to another embodiment of the present invention illustrated in FIG. 18 operates in four phases according to four state periods. The first state period is reset, the second state period is compensation, the third state period is program, and the fourth state period is emission.

19A to 19D are diagrams for explaining an operating principle of a pixel circuit according to still another embodiment of the present invention shown in FIG. 18. More specifically, FIG. 19(a) is an equivalent circuit of the pixel circuit shown in FIG. 18 in the first state period, and FIG. 19(b) is the pixel circuit shown in FIG. 18 in the second state period. 19(c) is the equivalent circuit of the pixel circuit shown in FIG. 18 in the third state period, and FIG. 19(d) is the pixel circuit shown in FIG. 18 in the fourth state period. Is the equivalent circuit of

The operating principle of the pixel circuit according to another embodiment of the present invention shown in FIG. 18 is substantially the same as that of the pixel circuit according to another embodiment of the present invention shown in FIG. 14.

Referring to (a) of FIG. 19, in the first state period (Reset), T _D is electrically connected to a gate and a drain, connected to V _RST , and separated from a display device (LED/OLED). And, C ₁ is applied to the V _DATA.

Referring to FIG. 19B, in the second state period (Compensation), V _DATA is applied as it is _{to C 1 , and the gate and drain of T D} are electrically connected and floating. Therefore, the gate voltage of _{T D becomes (V DD-} |V _{th_TD} |).

Referring to (c) of FIG. 19, the voltage on the data line DATA is changed from V _{DATA to V REF in the third state period Program.} Also, the gate of _{T D is floating.} At this time, the voltage value stored in _{C 2 (V DATA - (V} DD - | V th _TD |)) is retained. Thus, the gate voltage of T _D is _{[V REF - (V DATA -} (V DD - | V th _TD |))] because it is, (V _REF -V _DATA ) + V _DD- |V _{th_TD} |

Referring to FIG. 19D, voltage values stored _{in C 1} and C ₂ are maintained as they are in the fourth state period (Emission). Here, _{the gate voltage of T D} is as shown in Equation 9 below.

Referring to Equation 9 above, since the amount of change in the _{input voltage (V DATA ) is reduced by C 1} /(C ₁ +C ₂ ) at the gate of _{T D,} the range of change of the input voltage for the same amount of current change. You may increase it. Accordingly, the column line driver may have a wider voltage range.

Meanwhile, one of the drawbacks of the pixel circuits of FIGS. 10 and 12 is _{that when the voltage of V REF} commonly used for all pixels is unstable, the current values of the pixels in the emission state (or mode) are affected. Is to receive. For example, as shown in FIG. 1, if the display screen is scanned line-by-line, V _REF becomes the corresponding line whenever the scan of each line is finished. _{It is connected to internal capacitors (C 1} of FIGS. 10 and 12) of pixels connected to (line). At this time, the V _REF voltage fluctuates, and the degree of vibration is the V _{DATA stored in each pixel.} It will be affected by the value. Therefore, the current values of all pixels are affected by the shaking of _{V REF} each time each line is scanned.

20 is a pixel circuit of a display device according to still another embodiment of the present invention.

The pixel circuit shown in FIG. 20 according to another embodiment of the present invention may be for solving a problem of the pixel circuit shown in FIG. 18.

The pixel circuit according to another embodiment of the present invention illustrated in FIG. 20 has one more capacitor than the pixel circuit of FIG. 10 and one more transistor than the pixel circuit of FIG. 14.

The pixel circuit according to another embodiment of the present invention illustrated in FIG. 20 includes a first storage capacitor C ₁ , a second storage capacitor C ₂ , a driving transistor T _D , a display element, and a plurality of transistors. T ₁ , T ₂ , T ₃ , T ₄ , T ₅ ).

The driving transistor T _D and the display device are connected between _{the first power signal V DD} and the second power signal V _SS. The driving transistor T _D is connected to the other end of the second storage capacitor C _{2 and a first power signal V DD} is applied to the source.

One end of the second storage capacitor C ₂ is connected to the other end of the first storage capacitor C _1. The first power signal V _DD is applied to one end of the first storage capacitor C _1.

A plurality of transistors (T ₁ , T ₂ , T ₃ , T ₄ , T ₅ ) are connected between the data line (DATA) and the _{other end of the first storage capacitor (C 1} ), and a scan line (SCAN) is connected to the gate. connected to the first transistor (T _1), a reference voltage (V _REF) and a second transistor connected between the first other terminal of the storage capacitor (C ₁₎ is connected to the digital input and output lines (DIO) to the gate (T _2), the driving _{The third transistor T 3} is connected between the gate and the drain of the transistor T _D and the digital input/output line DIO is connected to the gate, and the emission control signal line is connected between the driving transistor T _{D and the display device and is connected to the gate. A fourth transistor T 4} to which (EMIT) is connected, a fifth transistor T5 connected between the drain of the driving transistor T _D and the reset voltage V _RST , and the reset control signal line RST is connected to the gate. Includes.

The scan line (SCAN), the digital input/output line (DIO), the reset control signal line (RST), the emission control signal line (EMIT), and the data line (DATA) are in a continuous first state period ((1)), and a second state. It has a predetermined timing diagram according to the period (2)), the third state period (3), and the fourth state period (4). Specifically, the scan line SCAN is high in the first and second state periods, and low in the third and fourth state periods. The digital input/output line DIO is low in the first and second state periods and high in the third and fourth state periods. The reset control signal line RST is low in the first state period and high in the second to fourth state periods. The emission control signal line EMIT is high in the first to third state periods and low in the fourth state period. _{V DATA} is applied to the data line DATA in the third and fourth state periods.

The pixel circuit according to another embodiment of the present invention illustrated in FIG. 20 operates in four phases according to four state periods. The first state period is reset, the second state period is compensation, the third state period is program, and the fourth state period is emission.

21A to 21D are diagrams for explaining the principle of operation of the pixel circuit according to still another embodiment of the present invention shown in FIG. 20. More specifically, (a) of FIG. 21 is an equivalent circuit of the pixel circuit shown in FIG. 20 in the first state section, and (b) of FIG. 21 is the pixel circuit shown in FIG. 20 in the second state section. (C) of FIG. 21 is an equivalent circuit of the pixel circuit shown in FIG. 20 in the third state section, and (d) of FIG. 21 is the pixel circuit shown in FIG. 20 in the fourth state section. Is the equivalent circuit of

Referring to (a) of FIG. 21, in the first state period (Reset), T _D is electrically connected to a gate and a drain to be connected to V _RST , and separated from a display device (LED/OLED). Then, T ₂ is turned on and V _REF is applied to _{C 1.}

Referring to FIG. 21B, in the second state period (Compensation), V _{REF is applied to C 1} as it is, and _{the gate and drain of T D} are electrically connected to be floating. Therefore, the gate voltage of _{T D becomes (V DD-} |V _{th_TD} |).

Referring to FIG. 21C, in the third state period Program, T ₂ is turned off and T ₁ is turned on. Therefore, the C ₁ voltage changes from V _REF to V _DATA voltage. Also, the gate of _{T D is floating.} At this time, the voltage value stored in _{C 2 (V REF - (V} DD - | V th _TD |)) is retained. Therefore, the gate voltage of T _D is _{[V DATA - (V REF -} (V DD - | V th_TD |))] is the | | V _{th_TD} - _{so, (V DATA - V REF)} + V DD.

Referring to FIG. 22D, voltage values stored _{in C 1} and C ₂ are maintained as they are in the fourth state period (Emission). At this time, T _D and the current values of the display device (LED/OLED) are as shown in Equation 10 below.

The pixel circuit shown in FIG. 20 is almost similar to the pixel circuit of FIG. 10, and one difference and advantage compared to the pixel circuit of FIG. 10 are T _D and display devices (LED/OLED) in the fourth state period (emission). ) Is not affected by _{V REF.} To this end, one more capacitor was used compared to the pixel circuit of FIG. 10.

22 is a pixel circuit of a display device according to still another embodiment of the present invention.

If the method of changing from the pixel circuit of FIG. 10 to the pixel circuit of FIG. 12 is applied as it is, the pixel circuit of FIG. 22 can be derived from the pixel circuit of FIG. 20.

The pixel circuit according to another embodiment of the present invention illustrated in FIG. 22 includes a first storage capacitor C ₁ , a second storage capacitor C ₂ , a driving transistor T _D , a display element, and a plurality of transistors. T ₁ , T ₂ , T ₃ , T ₄ ).

The driving transistor T _D and the display device are connected between _{the first power signal V DD} and the second power signal V _SS. The driving transistor T _D is connected to the other end of the second storage capacitor C _{2 and a first power signal V DD} is applied to the source.

One end of the second storage capacitor C ₂ is connected to the other end of the first storage capacitor C1. The first power signal VDD is applied to one end of the first storage capacitor C1.

The plurality of transistors T ₁ , T ₂ , T ₃ , T _{4 are} connected between the data line DATA and the _{other end of the first storage capacitor C 1} , and the scan line SCAN is connected to the gate. _{The second transistor T 2} is connected between the transistor T ₁ , the reference voltage V _REF and the other end of the first storage capacitor C ₁ and the digital input/output line DIO is connected to the gate, and the driving transistor T _{A third transistor (T 3 ) connected between the gate and the drain of D} ) and the digital input/output line (DIO) connected to the gate, and the emission control signal line (EMIT) connected between the driving transistor T _{D and the display device and connected to the gate.} And the connected fourth transistor T ₄ .

The scan line (SCAN), the digital input/output line (DIO), the emission control signal line (EMIT), and the data line (DATA) are connected to the first state section ((1)), the second state section ((2)), and the second state section ((2)). It has a predetermined timing diagram according to the three state period (3) and the fourth state period (4). Specifically, the scan line SCAN is high in the first, second, and fourth state periods and low in the third state period. The digital input/output line DIO is low in the first and second state periods and high in the third and fourth state periods. The emission control signal line EMIT is high in the second and third state periods and low in the first and fourth state periods. _{V DATA} is applied to the data line DATA in the third state period.

The pixel circuit according to another embodiment of the present invention illustrated in FIG. 22 operates in four phases according to four state periods. The first state period is reset, the second state period is compensation, the third state period is program, and the fourth state period is emission.

23A to 23D are diagrams for explaining an operating principle of a pixel circuit according to still another embodiment of the present invention shown in FIG. 22. More specifically, (a) of FIG. 23 is an equivalent circuit of the pixel circuit shown in FIG. 22 in the first state section, and (b) of FIG. 23 is the pixel circuit shown in FIG. 22 in the second state section. 23(c) is the equivalent circuit of the pixel circuit shown in FIG. 22 in the third state section, and FIG. 23(d) is the pixel circuit shown in FIG. 22 in the fourth state section. Is the equivalent circuit of

Referring to FIG. 23A, in the first state period (Reset), T _D is electrically connected to a gate and a drain. Then, T ₂ is turned on and V _REF is applied to _{C 1.}

Referring to FIG. 23B, in the second state period (Compensation), V _REF is applied as it is _{to C 1 , and the gate and drain of T D} are electrically connected to be floating. Therefore, the gate voltage of _{T D becomes (V DD-} |V _{th_TD} |).

Referring to FIG. 23C, in the third state period Program, T ₂ is turned off and T ₁ is turned on. Therefore, the C ₁ voltage changes from V _REF to V _DATA voltage. Also, the gate of _{T D is floating.} At this time, the voltage value stored in _{C 2 (V REF - (V} DD - | V th _TD |)) is retained. Therefore, the gate voltage of T _D is _{[V DATA - (V REF -} (V DD - | V th_TD |))] is the | | V _{th_TD} - _{so, (V DATA - V REF)} + V DD.

Referring to FIG. 23D, voltage values stored _{in C 1} and C ₂ are maintained as they are in the fourth state period (Emission).

The pixel circuit shown in FIG. 22 has a smaller number of transistors than the pixel circuit shown in FIG. It can be slightly degraded. However, by adjusting the timing of the emission control signal line EMIT to make the reset period as small as possible, deterioration of the contrast ratio can be prevented as much as possible.

24 is a pixel circuit of a display device according to still another embodiment of the present invention.

If the method of changing the position of the capacitor in the pixel circuit of FIG. 14 to the pixel circuit of FIG. 18 is applied as it is, the pixel circuit of FIG. 24 can be derived from the pixel circuit of FIG. 20.

The pixel circuit according to another embodiment of the present invention illustrated in FIG. 24 includes a first storage capacitor C ₁ , a second storage capacitor C ₂ , a driving transistor T _D , a display element, and a plurality of transistors. T ₁ , T ₂ , T ₃ , T ₄ , T ₅ ).

The driving transistor T _D and the display device are connected between _{the first power signal V DD} and the second power signal V _SS. The driving transistor T _D is connected to the other end of the first storage capacitor C1 and a first power signal V _DD is applied to the source.

The other end of the first storage capacitor C _{1 is} connected to the other end of the second storage capacitor C ₂ . The first power signal V _DD is applied to one end of the second storage capacitor C _2.

A plurality of transistors (T ₁ , T ₂ , T ₃ , T ₄ , T ₅ ) are connected between the data line (DATA) and _{one end of the first storage capacitor (C 1} ), and a scan line (SCAN) is connected to the gate. connected to the first transistor (T _1), a reference voltage (V _REF) and the first storage a second transistor (T ₂₎ a connection between the stage and attached with a digital input and output lines (DIO) to the gate of the capacitor (C _1), the driving _{The third transistor T 3} is connected between the gate and the drain of the transistor T _D and the digital input/output line DIO is connected to the gate, and the emission control signal line is connected between the driving transistor T _{D and the display device and is connected to the gate. A fourth transistor T 4} to which (EMIT) is connected _{, a fifth transistor T 5} connected between the drain of the driving transistor T _D and the reset voltage V _RST and the reset control signal line RST is connected to the gate Includes.

The scan line (SCAN), the digital input/output line (DIO), the reset control signal line (RST), the emission control signal line (EMIT), and the data line (DATA) are in a continuous first state period ((1)), and a second state. It has a predetermined timing diagram according to the period (2)), the third state period (3), and the fourth state period (4). Specifically, the scan line SCAN is high in the first, second, and fourth state periods and low in the third state period. The digital input/output line DIO is low in the first and second state periods and high in the third and fourth state periods. The reset control signal line RST is low in the first state period and high in the second to fourth state periods. The emission control signal line EMIT is high in the first to third state periods and low in the fourth state period. _{V DATA} is applied to the data line DATA in the third state period.

The pixel circuit according to another embodiment of the present invention illustrated in FIG. 24 operates in four phases according to four state periods. The first state period is reset, the second state period is compensation, the third state period is program, and the fourth state period is emission.

25A to 25D are diagrams for explaining an operating principle of a pixel circuit according to still another embodiment of the present invention shown in FIG. 24. More specifically, (a) of FIG. 25 is an equivalent circuit of the pixel circuit shown in FIG. 24 in the first state section, and (b) of FIG. 25 is the pixel circuit shown in FIG. 24 in the second state section. 25(c) is the equivalent circuit of the pixel circuit shown in FIG. 24 in the third state period, and FIG. 25(d) is the pixel circuit shown in FIG. 24 in the fourth state period. Is the equivalent circuit of

Referring to FIG. 25A, in the first state period (Reset), T _D is electrically connected to a gate and a drain, connected to V _RST , and separated from a display device (LED/OLED). Then, T ₂ is turned on and V _REF is applied to _{C 1.}

Referring to FIG. 25B, in the second state period (Compensation), V _REF is applied as it is _{to C 1 , and the gate and drain of T D} are electrically connected to be floating. Therefore, the gate voltage of _{T D becomes (V DD-} |V _{th_TD} |).

Referring to FIG. 25C, in the third state period Program, T ₂ is turned off and T ₁ is turned on. Therefore, the C ₁ voltage changes from V _REF to V _DATA voltage. Also, the gate of _{T D is floating.} At this time, the voltage value stored in _{C 2 (V REF - (V} DD - | V th _TD |)) is retained. Therefore, the gate voltage of T _D is _{[V DATA - (V REF -} (V DD - | V th_TD |))] is the | | V _{th_TD} - _{so, (V DATA - V REF)} + V DD.

Referring to FIG. 25D, voltage values stored _{in C 1} and C ₂ are maintained as they are in the fourth state period (Emission).

Compared to the pixel circuit of FIG. 20, the pixel circuit of FIG. 24 has the advantage of being able to design a wide voltage range of a column line driver.

Features, structures, effects, and the like described in the embodiments above are included in one embodiment of the present invention, and are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, and the like illustrated in each embodiment can be implemented by combining or modifying other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to such combinations and modifications should be construed as being included in the scope of the present invention.

In addition, although the embodiments have been described above, these are only examples and do not limit the present invention, and those of ordinary skill in the field to which the present invention pertains will not depart from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications that are not illustrated are possible. For example, each constituent element specifically shown in the embodiment can be modified and implemented. And differences related to these modifications and applications should be construed as being included in the scope of the present invention defined in the appended claims.

Claims (17)

Storage capacitors;
Display elements;
A first transistor connected between a data line and one end of the storage capacitor, and a scan line connected to a gate;
A second transistor connected between a reference voltage and one end of the storage capacitor and connected to a gate with an emission control signal line;
A driving transistor to which a first power signal is applied to a source and the other end of the storage capacitor is connected to a gate;
A third transistor connected between the gate and the drain of the driving transistor and the scan line connected to the gate;
A fourth transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line; And
A fifth transistor connected between a drain of the driving transistor and a reset voltage, and a reset control signal line connected to a gate;
Including a pixel circuit.
The method of claim 1,
The first to third state periods are repeated in time,
The scan line is low in the first and second state periods, and high in the third state period,
The reset control signal line is low in the first state period and high in the second and third state periods,
The emission control signal line is high in the first and second state periods, and low in the third state period,
A pixel circuit to which a predetermined data voltage is applied to the data line in the first and second state periods.
Storage capacitors;
Display elements;
A first transistor connected between a data line and one end of the storage capacitor, and a scan line connected to a gate;
A second transistor connected between a reference voltage and one end of the storage capacitor and connected to a gate with a complementary scan line opposite to the scan line;
A driving transistor to which a first power signal is applied to a source and the other end of the storage capacitor is connected to a gate;
A third transistor connected between the gate and the drain of the driving transistor and the scan line connected to the gate; And
A fourth transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line;
Including a pixel circuit.
The method of claim 3,
The first to third state periods are repeated in time,
The scan line is low in the first and second state periods, and high in the third state period,
The emission control signal line is low in the first and third state periods and high in the second state period,
A pixel circuit to which a predetermined data voltage is applied to the data line in the first and second state periods.
A first storage capacitor to which a first power signal is applied to one end;
A second storage capacitor having one end connected to the other end of the first storage capacitor;
Display elements;
A first transistor connected between a data line and the other end of the first storage capacitor, and a scan line connected to a gate;
A driving transistor to which the first power signal is applied to a source and the other end of the second storage capacitor is connected to a gate;
A second transistor connected between a gate and a drain of the driving transistor and a digital input/output line connected to the gate;
A third transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line; And
A fourth transistor connected between a drain of the driving transistor and a reset voltage, and a reset control signal line connected to a gate;
Including a pixel circuit.
The method of claim 5,
The first to fourth state periods are repeated in time,
The scan line is low in the first to third state period and high in the fourth state period,
The digital input/output line DIO is low in the first and second state periods and high in the third and fourth state periods,
The reset control signal line is low in the first state period and high in the second to fourth state periods,
The emission control signal line is high in the first to third state period and low in the fourth state period,
A pixel circuit, wherein a predetermined data voltage or a reference voltage is applied to the data line in the first and second state periods, and in the third and fourth state periods, opposite to the first and second state periods.
A first storage capacitor to which a first power signal is applied to one end;
A second storage capacitor having one end connected to the other end of the first storage capacitor;
Display elements;
A first transistor connected between a data line and the other end of the first storage capacitor, and a scan line connected to a gate;
A driving transistor to which the first power signal is applied to a source and the other end of the second storage capacitor is connected to a gate;
A second transistor connected between a gate and a drain of the driving transistor and a digital input/output line connected to the gate; And
A third transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line;
Including a pixel circuit.
The method of claim 7,
The first to fourth state periods are repeated in time,
The scan line is low in the first to third state period and high in the fourth state period,
The digital input/output line DIO is low in the first and second state periods and high in the third and fourth state periods,
The emission control signal line is high in the second and third state periods, and low in the first and fourth state periods,
A pixel circuit, wherein a predetermined data voltage or a reference voltage is applied to the data line in the first and second state periods, and in the third and fourth state periods, opposite to the first and second state periods.
A first storage capacitor;
A second storage capacitor to which a first power signal is applied and the other end is connected to the other end of the first storage capacitor;
Display elements;
A first transistor connected between a data line and one end of the first storage capacitor, and a scan line connected to a gate;
A driving transistor to which the first power signal is applied to a source and the other end of the second storage capacitor is connected to a gate;
A second transistor connected between a gate and a drain of the driving transistor and a digital input/output line connected to the gate;
A third transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line; And
A fourth transistor connected between a drain of the driving transistor and a reset voltage, and a reset control signal line connected to a gate;
Including a pixel circuit.
The method of claim 9,
The first to fourth state periods are repeated in time,
The scan line is low in the first to third state period and high in the fourth state period,
The digital input/output line is low in the first and second state periods, and high in the third and fourth state periods,
The reset control signal line is low in the first state period and high in the second to fourth state periods,
The emission control signal line is high in the first to third state period and low in the fourth state period,
A pixel circuit, wherein a predetermined data voltage or a reference voltage is applied to the data line in the first and second state periods, and in the third and fourth state periods, opposite to the first and second state periods.
A first storage capacitor to which a first power signal is applied to one end;
A second storage capacitor having one end connected to the other end of the first storage capacitor;
Display elements;
A first transistor connected between a data line and the other end of the first storage capacitor, and a scan line connected to a gate;
A second transistor connected between a reference voltage and the other end of the first storage capacitor, and a digital input/output line connected to a gate;
A driving transistor to which the first power signal is applied to a source and the other end of the second storage capacitor is connected to a gate;
A third transistor connected between the gate and the drain of the driving transistor and the digital input/output line connected to the gate;
A fourth transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line; And
A fifth transistor connected between a drain of the driving transistor and a reset voltage, and a reset control signal line connected to a gate;
Including a pixel circuit.
The method of claim 11,
The first to fourth state periods are repeated in time,
The scan line is high in the first and second state periods, and low in the third and fourth state periods,
The digital input/output line is low in the first and second state periods, and high in the third and fourth state periods,
The reset control signal line is low in the first state period and high in the second to fourth state periods,
The emission control signal line is high in the first to third state period and low in the fourth state period,
A pixel circuit to which a predetermined data voltage is applied to the data line in the third and fourth state periods.
A first storage capacitor to which a first power signal is applied to one end;
A second storage capacitor having one end connected to the other end of the first storage capacitor;
Display elements;
A first transistor connected between a data line and the other end of the first storage capacitor, and a scan line connected to a gate;
A second transistor connected between a reference voltage and the other end of the first storage capacitor, and a digital input/output line connected to a gate;
A driving transistor to which the first power signal is applied to a source and the other end of the second storage capacitor is connected to a gate;
A third transistor connected between the gate and the drain of the driving transistor and the digital input/output line connected to the gate; And
A fourth transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line;
Including a pixel circuit.
The method of claim 13,
The first to fourth state periods are repeated in time,
The scan line is high in the first, second, and fourth state periods, and is low in the third state period,
The digital input/output line is low in the first and second state periods and high in the third and fourth state periods,
The emission control signal line is high in the second and third state periods, and low in the first and fourth state periods,
A pixel circuit to which a predetermined data voltage is applied to the data line in the third state period.
A first storage capacitor;
A second storage capacitor to which a first power signal is applied and the other end is connected to the other end of the first storage capacitor;
Display elements;
A first transistor connected between a data line and one end of the first storage capacitor, and a scan line connected to a gate;
A second transistor connected between a reference voltage and one end of the first storage capacitor, and a digital input/output line connected to a gate;
A driving transistor to which the first power signal is applied to a source and the other end of the second storage capacitor is connected to a gate;
A third transistor connected between the gate and the drain of the driving transistor and the digital input/output line connected to the gate;
A fourth transistor connected between the drain of the driving transistor and the display device and connected to a gate with an emission control signal line; And
A fifth transistor connected between a drain of the driving transistor and a reset voltage, and a reset control signal line connected to a gate;
Including a pixel circuit.
The method of claim 15,
The first to fourth state periods are repeated in time,
The scan line is high in the first, second, and fourth state periods, and is low in the third state period,
The digital input/output line is low in the first and second state periods and high in the third and fourth state periods,
The reset control signal line is low in the first state period and high in the second to fourth state periods,
The emission control signal line is high in the first to third state period and low in the fourth state period,
A pixel circuit to which a predetermined data voltage is applied to the data line in the third state period.
A display device comprising the pixel circuit according to any one of claims 1 to 16.

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