KR20160049586A - Organic Light Emitting Display - Google Patents

Abstract

The present invention relates to an organic light emitting display device capable of programming a driving current regardless of a parasitic capacitance deviation of an OLED when compensating a threshold voltage. Each of pixels of the organic light emitting display device comprises: an organic light emitting diode connected to a point between node C and an input terminal of a low-potential driving voltage; a driving TFT having a gate connected to node A, a drain connected to node D and a source connected to node B so as to control a driving current applied to the organic light emitting diode; a first scan TFT connected to a point between a data line and the node A, and switched in accordance with a first scan signal from a first scan line; a second scan TFT connected to a point between the node C and an input terminal of an initialization voltage, and switched in accordance with a second scan signal from a second scan line; a first emission TFT connected to a point between an input terminal of the high-potential driving voltage and the node D, and switched in accordance with a first emission signal from a first emission line; a second emission TFT connected to a point between the node B and the node C, and switched in accordance with a second emission signal from a second emission line; a first capacitor connected to a point between the node A and the node B; and a second capacitor to a point between the input terminal of the high-potential driving voltage and the node B.

Description

[0001] The present invention relates to an organic light emitting display,

The present invention relates to an active matrix type organic light emitting display.

The active matrix type organic light emitting display device includes an organic light emitting diode (OLED) which emits light by itself, has a high response speed, and has a high luminous efficiency, luminance, and viewing angle.

The OLED, which is a self-luminous element, has the structure shown in FIG. The OLED includes an anode electrode and a cathode electrode, and organic compound layers (HIL, HTL, EML, ETL, EIL) formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light.

The organic light emitting display device arranges the pixels each including the OLED in a matrix form and adjusts the brightness of the pixels according to the gradation of the video data. Each of the pixels includes a driving TFT (Thin Film Transistor) for controlling the driving current flowing in the OLED according to the gate-source voltage, a capacitor for keeping the gate-source voltage of the driving TFT constant for one frame, And at least one switch TFT for programming the gate-source voltage of the drive TFT. The driving current is determined by the gate-source voltage of the driving TFT according to the data voltage, and the luminance of the pixel is proportional to the magnitude of the driving current flowing in the OLED.

In such an OLED display device, a threshold voltage of a driving TFT between pixels is changed due to a process deviation, a gate-bias stress due to a driving time lapse, etc., and a deviation occurs in a driving current corresponding to the same data voltage There is a problem.

In order to solve this problem, the gate-source voltage of the driving TFT is programmed by using a compensating TFT or a compensation capacitor added to each pixel, and the effect of the threshold voltage change of the driving TFT on the driving current Various internal compensation pixel structures are known. In the compensating method of programming the gate-source voltage of the driving TFT using the voltage division between the capacitors, the pixel structure for compensation can be simplified. However, The accuracy of the compensation is deteriorated due to the influence of the parasitic capacitors. The parasitic capacitance of the OLED is sensitive to the thickness difference of the OLED. Since the parasitic capacitance of the OLED is included in the compensating current type voltage division factor in the above compensation method, the driving current flowing in the OLED also changes when the parasitic capacitance of the OLED changes. When the driving current is changed due to the parasitic capacitance deviation of the OLED during compensation, the compensation becomes a factor to lower accuracy.

Accordingly, it is an object of the present invention to provide a method of programming a driving current irrespective of a parasitic capacitance deviation of an OLED when employing a threshold voltage compensation method of programming a gate-source voltage of a driving TFT using a voltage distribution between the capacitors And to provide an organic light emitting display device.

According to an aspect of the present invention, there is provided an OLED display including: a display panel including a plurality of pixels; A gate driving circuit for driving first scan lines, second scan lines, first emission lines, and second emission lines of the display panel; And a data driving circuit for driving the data lines of the display panel; each of pixels connected to the jth first and second scan lines and the jth first and second emission lines arranged at j (j is a natural number) pixel row is connected between the node C and the input terminal of the low potential driving voltage An organic light emitting diode connected to the organic light emitting diode; A driving TFT for controlling a driving current applied to the organic light emitting diode, including a gate connected to the node A, a drain connected to the node D, and a source connected to the node B; A first scan TFT connected between the data line and the node A and switched according to a first scan signal from the jth first scan line; A second scan TFT connected between the node C and an input terminal of an initialization voltage and switched according to a second scan signal from the jth second scan line; A first emissive TFT connected between an input terminal of a high potential driving voltage and the node D and switched according to a first emission signal from the jth first emission line; A second emission TFT connected between the node B and the node C, the second emission TFT being switched according to a second emission signal from the jth second emission line; A first capacitor connected between the node A and the node B; And a second capacitor connected between the node B and an input terminal of the high potential driving voltage.

One frame period includes an initialization period in which a reference voltage from the data line is applied to the node A and the initialization voltage is applied to the node B; A sampling period in which a threshold voltage of the driving TFT is sampled and stored in the first capacitor; Applying a data voltage from the data line to the node A and reflecting a result of voltage division between the first and second capacitors with respect to the potential change of the node A to the node B, A programming period for programming the voltage; And an emission period for applying a driving current according to the programmed gate-source voltage to the OLED to emit the OLED; In the programming period, the second emission TFT is turned off according to the second emission signal of the off level so that the parasitic capacitance of the OLED is not reflected in the voltage distribution result.

The first scan TFT is turned on in accordance with the first scan signal of the on level in the initialization period, the sampling period, and the programming period, and is turned off in accordance with the first scan signal of the off level in the emission period; The second scan TFT is turned on in accordance with the second scan signal of the on level during the initialization period and is turned off according to the second scan signal of the off level during the sampling period, the programming period, and the emission period ; The first emission control TFT is turned on in accordance with the first emission signal of the on level in the sampling period and the emission period and is turned on in accordance with the first emission signal of the off level in the initialization period and the programming period Off; The second emission TFT is turned on in accordance with the second emission signal of the on level in the initialization period, the sampling period, and the emission period.

Wherein the data driving circuit alternately supplies the reference voltage and the data voltage to the data line at intervals of a 1/2 horizontal period so as to be synchronized with a first scan signal applied to each pixel line; The initialization period corresponds to a period in which a reference voltage is supplied to the data line in a (j-1) -th horizontal period allocated to drive the (j-1) th pixel row; Wherein the sampling period corresponds to a period in which a reference voltage is supplied to the data line within a jth horizontal period allocated to drive the jth pixel row; The programming period corresponds to a period during which the data voltage is supplied to the data line in the j-th horizontal period allocated for driving the j-th pixel row.

The driving TFT is implemented as an N type, and the first and second scan TFTs and the first and second emission TFTs are implemented as N type or P type.

According to another aspect of the present invention, there is provided an OLED display including: a display panel having a plurality of pixels; A gate driving circuit for driving the first scan lines, the second scan lines, and the emission lines of the display panel; And a data driving circuit for driving the data lines of the display panel; (j is a natural number) pixel row, and each of the pixels connected to the jth first and second scan lines, the jth emission line, and the j + 2th emission line is connected to the node C and the low potential driving voltage An organic light emitting diode connected between the input terminals of the organic light emitting diode; A driving TFT for controlling a driving current applied to the organic light emitting diode, including a gate connected to the node A, a drain connected to the node D, and a source connected to the node B; A first scan TFT connected between the data line and the node A and switched according to a first scan signal from the jth first scan line; A second scan TFT connected between the node C and an input terminal of an initialization voltage and switched according to a second scan signal from the jth second scan line; A first emission TFT connected between an input terminal of a high potential driving voltage and the node D and switched according to a first emission signal from the jth emission line; A second emission TFT connected between the node B and the node C, the second emission TFT being switched according to a second emission signal from the j + 2th emission line; A first capacitor connected between the node A and the node B; And a second capacitor connected between the node B and an input terminal of the high potential driving voltage.

The present invention adds a separate emission TFT between the source of the OLED and the driving TFT when adopting a threshold voltage compensation scheme for programming the gate-source voltage of the driving TFT using the voltage distribution between the capacitors, By turning off this emission TFT, the driving current can be programmed irrespective of the parasitic capacitance deviation of the OLED. The present invention can improve the accuracy and reliability of compensation by eliminating the parasitic capacitance effect of the OLED in the threshold voltage compensation.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing an OLED and its luminescence principle. Fig.
2 is a view illustrating an organic light emitting display according to an embodiment of the present invention.
3 is a view showing an example of a connection configuration of a pixel array and a gate driving circuit for supplying a gate signal to a pixel array;
4 is a view showing another example of a connection configuration of a pixel array and a gate driving circuit for supplying a gate signal to a pixel array;
Fig. 5 is a diagram showing one equivalent circuit of a pixel included in the pixel array of Fig. 3; Fig.
6 is a view showing an example of a data signal and a gate signal applied to the pixel of FIG.
Fig. 7 is a circuit diagram showing one equivalent circuit of a pixel included in the pixel array of Fig. 4; Fig.
8 is a diagram showing an example of a data signal and a gate signal applied to the pixel of FIG.
9A is an equivalent circuit diagram of a pixel corresponding to an initialization period.
9B is an equivalent circuit diagram of a pixel corresponding to the sampling period.
9C is an equivalent circuit diagram of a pixel corresponding to a programming period.
9D is an equivalent circuit diagram of a pixel corresponding to a light emission period.
10 is a view showing a change in potential of each pixel of a pixel during compensation driving and a drive current applied to the OLED.
FIGS. 11A and 11B are simulation results showing driving current deviations according to a threshold voltage change. FIG.
12A and 12B are simulation results showing driving current deviations according to the parasitic capacitor effect of an OLED.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2 to 12B.

2 illustrates an organic light emitting display according to an embodiment of the present invention. Figs. 3 and 4 show examples of the connection configuration of the pixel array and the gate driving circuit for supplying the gate signal to the pixel array.

2, an organic light emitting display according to an embodiment of the present invention includes a display panel 10 in which pixels PXL are arranged in a matrix form, a data driving circuit (not shown) for driving the data lines 14, A gate driving circuit 13 for driving the gate lines 15 and a timing controller 11 for controlling the driving timings of the data driving circuit 12 and the gate driving circuit 13 .

In the display panel 10, a plurality of data lines 14 and a plurality of gate lines 15 cross each other, and the pixels PXL are arranged in a matrix form for each of the intersection regions. Each gate line 15 may include two scan lines and at least one emission line. Each pixel PXL may be connected to one data line 14, two scan lines, and two emission lines. The pixels PXL can receive the high potential and low potential driving voltages EVDD and EVSS and the initialization voltage Vinit in common from a power source not shown. It is preferable that the initialization voltage Vinit is selected within a range sufficiently lower than the low-potential driving voltage so that unnecessary light emission of the OLED is prevented.

The TFTs constituting the pixel PXL may be implemented as an oxide TFT including an oxide semiconductor layer. The oxide TFT is advantageous for large-sized display panel 10 when considering both electron mobility and process variations. However, the present invention is not limited to this, and the semiconductor layer of the TFT may be formed of amorphous silicon, polysilicon, or the like.

Each of the pixels PXL includes a plurality of TFTs and capacitors for compensating a threshold voltage change of the driving TFT, and when the gate-source voltage of the driving TFT is programmed through a voltage distribution between the capacitors, Is not reflected in the voltage distribution result. This will be described in Fig. 5 and Fig.

The timing controller 11 rearranges the digital video data RGB input from the outside in accordance with the resolution of the display panel 10 and supplies the digital video data RGB to the data driving circuit 12. The timing controller 11 is also connected to the data driving circuit 12 based on timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a dot clock signal DCLK and a data enable signal DE, A data control signal DDC for controlling the operation timing of the gate driving circuit 13 and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13. [

The data driving circuit 12 converts the digital video data RGB input from the timing controller 11 into an analog data voltage based on the data control signal DDC. The data driving circuit 12 can alternately supply the data voltage and the reference voltage at a constant level to the data lines 14 at intervals of a 1/2 horizontal period (see FIGS. 6 and 8). Here, May be generated in the data driving circuit 12 or may be generated in the external power supply circuit and then supplied to the data driving circuit 12. [ The reference voltage should be set higher than the initialization voltage (Vinit). In particular, the difference between the reference voltage and the initialization voltage (Vinit) should be set so as to be larger than the threshold voltage of the driving TFT so that the driving TFT can be turned on in an initialization period to be described later.

The gate driving circuit 13 may generate a scan signal and an emission signal based on the gate control signal GDC.

The gate driver circuit 13 includes first scan drivers 131 for individually driving a plurality of first scan lines 151 [1] to 151 [n], n as natural numbers) as shown in FIG. 3, The second scan driver 132 for driving the second scan lines 152 [1] to 152 [n] individually and the plurality of first emission lines 153 [1] to 153 [n] And second emission driving units 134 for driving the plurality of second emission lines 154 [1] to 154 [n] individually, as shown in Fig. . The first scan drivers 131 sequentially operate to generate a first scan signal Scan1 in accordance with the row sequence R # 1 to R # n and then scan the first scan lines 151 [1] to 151 [n]). The second scan drivers 132 sequentially operate to generate a second scan signal Scan2 according to the row sequence R # 1 to R # n, and then the second scan lines 152 [1] to 152 [n]). The first emissionion driving units 133 sequentially operate to generate the first emission signal EM1 according to the row sequence R # 1 to R # n, and then the first emission lines 153 [ ] To 153 [n]). The second emission driving units 134 sequentially operate to generate the second emission signal EM2 according to the row sequential (R # 1 to R # n) scheme and then the second emission lines 154 [1 ] To 154 [n]).

In this case, each of the pixels PXL arranged in j (j is a natural number) pixel row R # j is divided into a plurality of pixels PXL from the jth first and second scan lines 151 [j] and 152 [j] 1 and the second emission signal from the jth first and second emission lines 153 [j] and 154 [j], and the first and second scan signals Scan1 [j] and Scan2 [j] (EM1 [j], EM2 [j]).

The gate driver circuit 13 includes first scan drivers 131 for driving the first scan lines 151 [1] to 151 [n], n as natural numbers) The second scan driver 132 for driving the plurality of second scan lines 152 [1] to 152 [n] individually and the plurality of emission lines 153 [1] to 153 [n] And an emission driving unit 133 for individually driving the light emitting diodes. The first scan drivers 131 sequentially operate to generate a first scan signal Scan1 in accordance with the row sequence R # 1 to R # n and then scan the first scan lines 151 [1] to 151 [n]). The second scan drivers 132 sequentially operate to generate a second scan signal Scan2 according to the row sequence R # 1 to R # n, and then the second scan lines 152 [1] to 152 [n]). The emission driving units 133 sequentially operate to generate emission signals EM in accordance with the row sequence R # 1 to R # n and then emit the emission lines 153 [1] to 153 [n] ).

In this case, each of the pixels PXL arranged in j (j is a natural number) pixel row R # j is divided into a plurality of pixels PXL from the jth first and second scan lines 151 [j] and 152 [j] The first and second scan signals Scan1 [j] and Scan2 [j], the first emission signal EM [j] from the jth emission line 153 [j] The second emission signal EM [j + 2] from the first line 153 [j + 2] can be received.

The gate drive circuit 13 may be formed directly on the non-display area of the display panel 10 according to a GIP (Gate-Driver In Panel) method. FIG. 3 shows an advantage in that programming necessary for compensation can be completed within a relatively short period of time, thereby sufficiently securing a time required for light emission during one frame period. FIG. 4 shows an advantage that the opening ratio can be increased by reducing the formation area of the gate drive circuit 13 and the number of the gate lines 15. FIG.

Fig. 5 shows one equivalent circuit of a pixel included in the pixel array of Fig. FIG. 6 shows an example of a data signal and a gate signal applied to the pixel of FIG.

Referring to Fig. 5, a connection configuration of the pixels PXL [j, k] arranged in the jth pixel row and arranged in the kth pixel column will be described.

The pixel PXL [j, k] includes the OLED, the driving TFT DT, the first scanning TFT ST1, the second scanning TFT ST2, the first emission TFT ET1, the second emission TFT ET2 ), A first capacitor C1 and a second capacitor C2, and may have a 5T2C structure (implemented with five TFTs and two capacitors). The first and second scan TFTs ST1 and ST2 and the first and second emission TFTs ET1 and ET2 may be implemented as N type or P type, have. Although the first and second scan TFTs ST1 and ST2 and the first and second emission TFTs ET1 and ET2 are implemented as N type in the embodiment of the present invention, In this case, when the first and second scan TFTs ST1 and ST2 and the first and second emission TFTs ET1 and ET2 are implemented as P type (in this case, Scan1 [j] and Scan2 [j] , EM1 [j], EM2 [j] must be inverted).

The OLED emits light by the driving current supplied from the driving TFT DT. As shown in FIG. 1, a multi-layer organic compound layer is formed between the anode electrode and the cathode electrode of the OLED. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). The anode electrode of the OLED is connected to the node C, and its cathode electrode is connected to the input terminal of the low potential driving voltage EVSS.

The driving TFT DT controls the driving current applied to the OLED according to its own gate-source voltage Vgs. The gate electrode of the driving TFT DT is connected to the node A, the drain electrode is connected to the node D, and the source electrode is connected to the node B.

The first scan TFT ST1 turns on / off the current path between the data line 14 [k] and the node A by switching in response to the first scan signal Scan1 [j]. The gate electrode of the first scan TFT ST1 is connected to the jth first scan line 151 [j], the drain electrode thereof is connected to the data line 14 [k], and the source electrode thereof is connected to the node A .

The second scan TFT ST2 is turned on / off in response to the second scan signal Scan2 [j] by turning on / off the current path between the input terminal of the initialization voltage Vinit and the node C. The gate electrode of the second scan TFT ST2 is connected to the jth second scan line 152 [j], the drain electrode thereof is connected to the node C, and the source electrode thereof is connected to the input terminal of the initialization voltage Vinit.

The first emission pixel ET1 is switched in response to the first emission signal EM1 [j] to turn on / off the current path between the input terminal of the high potential driving voltage EVDD and the node D. The gate electrode of the first emission pixel ET1 is connected to the jth first emission line 153 [j], the drain electrode thereof is connected to the input terminal of the high potential driving voltage EVDD, Respectively.

The second emission pixel ET2 is switched in response to the second emission signal EM2 [j] to turn on / off the current path between the node B and the node C. The gate electrode of the second emission TFT ET2 is connected to the jth second emission line 154 [j], the drain electrode thereof is connected to the node B, and the source electrode thereof is connected to the node C. [ The second emission pixel TFT2 is turned off in accordance with the second emission signal EM2 [j] of the OFF level in the programming period to be described later, so that the parasitic capacitance ColED of the OLED is set to the first and second capacitors C1 , C2) of the voltage distribution.

A first capacitor (C1) is connected between node A and node B. The first capacitor C1 is used to sample the threshold voltage of the driving TFT in accordance with the source-follower scheme. The second capacitor C2 is connected between the input terminal of the high potential driving voltage EVDD and the node B. The first and second capacitors C1 and C2 perform a function of distributing the voltage to the node B when the potential of the node A is changed by the data voltage in the programming period.

The pixel operation of FIG. 5 will be described with reference to FIGS. 9A to 9D and FIG. 10 together with FIG.

One frame period can be divided into an initialization period Ti, a sampling period Ts, a programming period Tp, and an emission period Te as shown in Fig.

The initialization period Ti is set such that the reference voltage Vref is applied to the data line 14 [k] within the j-1th horizontal period ((j-1) th H) ]). In the initialization period Ti, the reference voltage Vref from the data line 14 [k] is applied to the node A and the initialization voltage Vinit is applied to the node B. The first scan signal Scan1 [j] is input to the on level Lon to turn on the first scan TFT ST1 and the second scan signal Scan2 [j] is turned on during the setup period Ti, The first emission signal EM1 [j] is input to the off-level (Loff), and the first emission TFT ET1 is turned on to turn on the second scan TFT ST2, And the second emission signal EM2 [j] is input to the on level (Lon) to turn on the second emission TFT ET2.

As a result, the reference voltage Vref from the data line 14 [k] is applied to the node A by the turn-on of the first scan TFT ST1 during the setup period Ti as shown in Figs. 9A and 10 The initializing voltage Vinit is applied to the node B through the node C by turning on the second scan TFT ST2 and the second emission TFT ET2.

The sampling period Ts corresponds to a period in which the reference voltage Vref is supplied to the data line 14 [k] within the j-th horizontal period (jth H) allocated to drive the jth pixel row as shown in Fig. 6 . In the sampling period Ts, the threshold voltage of the driving TFT DT is sampled and stored in the first capacitor C1. To this end, during the sampling period Ts, the first scan signal Scan1 [j] is input to the on level Lon to turn on the first scan TFT ST1 and the second scan signal Scan2 [j] Is input at the off level Loff to turn off the second scan TFT ST2 and the first emission signal EM1 [j] is input to the on level Lon to turn off the first emission TFT ET1, And the second emission signal EM2 [j] is input to the on level (Lon) to turn on the second emission TFT ET2.

As a result, during the sampling period Ts as shown in Figs. 9B and 10, the reference voltage Vref from the data line 14 [k] is applied to the node A by the turn-on of the first scan TFT ST1 , The high-potential driving voltage EVDD is applied to the node D by the turn-on of the first emission pixel ET1. As a result, the driving TFT DT is turned on to pass the drain-source current Ids. In the sampling period Ts, the potential of the node A is maintained at the reference voltage Vref, while the potential of the node B is raised by the drain-source current Ids, To a level (Vref-Vth) at which it can turn off. According to such a source-follower scheme, the gate-source voltage Vgs of the driving TFT DT is sampled at the threshold voltage Vth of the driving TFT DT, and the sampled threshold voltage Vth is And is stored in the first capacitor C1.

The programming period Tp is a period during which the data voltage Vdata [kj] is supplied to the data line 14 [k] within the j-th horizontal period jthH allocated to the driving of the j- Lt; / RTI > 6, "Vdata [kj-1]" means a data voltage supplied in the (j-1) th horizontal period (j-1) th H allocated to the driving of the j-1 th pixel row . In the programming period Tp, the data voltage Vdata [kj] from the data line 14 [k] is applied to the node A and the first and second voltages Vdata- The voltage division result between the capacitors C1 and C2 is reflected to the node B, so that the gate-source voltage Vgs of the drive TFT DT is programmed. To this end, during the programming period Tp, the first scan signal Scan1 [j] is input at the on level Lon to turn on the first scan TFT ST1 and the second scan signal Scan2 [j] Is inputted at the off level Loff to turn off the second scan TFT ST2 and the first emission signal EM1 [j] is inputted at the off level (Loff) And the second emission signal EM2 [j] is input to the off level (Loff) to turn off the second emission TFT ET2.

As a result, during the programming period Tp as shown in Figs. 9C and 10, the data voltage Vdata [kj] from the data line 14 [k] by the turn-on of the first scan TFT ST1 reaches the node A . Accordingly, the potential of the node A is changed from the reference voltage Vref set through the sampling period Ts to the data voltage Vdata. The potential change (Vdata-Vref) of the node A is reflected to the node B as a voltage distribution result C '* (Vdata-Vref) between the first and second capacitors C1 and C2. The potential of the node B is obtained by adding the voltage distribution result C '* (Vdata-Vref) between the first and second capacitors C1 and C2 to "Vref-Vth" set through the sampling period Ts and " + C '* (Vdata-Vref) ". As a result, the gate-source voltage Vgs of the driving TFT DT is programmed to "Vdata-Vref + Vth-C * (Vdata-Vref)" through the programming period Tp. Here, C 'denotes CST1 / (CST1 + CST2), CST1 denotes the first capacitance of the first capacitor C1, and CST2 denotes the second capacitance of the second capacitor C2.

If the second emission TFT ET2 is not provided in the pixel PXL of the present invention, the OLED is directly connected to the node B, so that C 'in the programming period Tp is CST1 / (CST1 + CST2 + Coled). Here, "Coled" is the parasitic capacitance of the OLED. The parasitic capacitance (Coled) of the OLED is sensitive to the thickness difference of the OLED. Therefore, when the parasitic capacitance of the OLED between the pixels is changed due to the process variation, the drift current deviation between the pixels still exists despite the threshold voltage compensation, so that the reliability of the threshold voltage compensation is lowered.

In the present invention, the second emission pixel ET2 is indispensable, and the second emission pixel TFT ET2 responds to the second emission signal EM2 [j] of the off level Loff during the programming period Tp And is turned off to prevent the parasitic capacitance (Coled) of the OLED from being reflected in the voltage distribution result.

The emission period Te continues from the programming period Tp to the initialization period Ti of the next frame. In the emission period Te, the driving current Ioled is applied to the OLED according to the gate-source voltage programmed through the programming period Tp to emit the OLED. To this end, during the emission period Te, the first scan signal Scan1 [j] is input at the off level Loff to turn off the first scan TFT ST1, and the second scan signal Scan2 [j ] Is input at the off level Loff to turn off the second scan TFT ST2 and the first emission signal EM1 [j] is input to the on level Lon and the first emission TFT ET1 , And the second emission signal EM2 [j] is input to the on level (Lon) to turn on the second emission TFT ET2.

As shown in FIGS. 9D and 10, a relational expression for the driving current Ioled flowing in the OLED in the emission period Te is represented by the following equation (1). The OLED emits light by this driving current to realize a desired display gradation.

In Equation (2), k indicates a proportional constant determined by electron mobility, parasitic capacitance, channel capacity, and the like of the driving TFT (DT).

Since the Vth component is already included in the Vgs programmed through the programming period Tp, the driving current Ioled relationship is k / 2 (Vgs-Vth) ² . The ingredients are cleared. Thus, the influence of the change in the threshold voltage Vth on the drive current Ioled is eliminated.

FIG. 7 shows one equivalent circuit of a pixel included in the pixel array of FIG. FIG. 8 shows an example of a data signal and a gate signal applied to the pixel of FIG.

Referring to Fig. 7, the connection configuration of the pixels PXL [j, k] arranged in the jth pixel row and arranged in the kth pixel column will be described. The pixel PXL [j, k] in FIG. 7 is compared with the pixel PXL [j, k] in FIG. 5 so that the first emission pixel ET1 is shifted from the jth emission line 153 [ And the second emission TFT ET2 receives the emission signal EM [j] of the j + 2th emission line 153 [j + 2] as the first emission signal EM1 [j] (EM [j + 2]) from the first emission signal EM2 [j + 2], and the rest are substantially the same.

The pixel PXL [j, k] includes the OLED, the driving TFT DT, the first scanning TFT ST1, the second scanning TFT ST2, the first emission TFT ET1, the second emission TFT ET2 ), A first capacitor C1 and a second capacitor C2, and may have a 5T2C structure (implemented with five TFTs and two capacitors). The first and second scan TFTs ST1 and ST2 and the first and second emission TFTs ET1 and ET2 may be implemented as N type or P type, have. Although the first and second scan TFTs ST1 and ST2 and the first and second emission TFTs ET1 and ET2 are implemented as N type in the embodiment of the present invention, When the first and second scan TFTs ST1 and ST2 and the first and second emission TFTs ET1 and ET2 are implemented as a P type (in this case, Scan1 [j] and Scan2 [j] , EM1 [j], and EM2 [j + 2] must be inverted).

The anode electrode of the OLED is connected to the node C, and its cathode electrode is connected to the input terminal of the low potential driving voltage EVSS.

The gate electrode of the driving TFT DT is connected to the node A, the drain electrode is connected to the node D, and the source electrode is connected to the node B.

The first scan TFT ST1 turns on / off the current path between the data line 14 [k] and the node A by switching in response to the first scan signal Scan1 [j]. The gate electrode of the first scan TFT ST1 is connected to the jth first scan line 151 [j], the drain electrode thereof is connected to the data line 14 [k], and the source electrode thereof is connected to the node A .

The second scan TFT ST2 is turned on / off in response to the second scan signal Scan2 [j] by turning on / off the current path between the input terminal of the initialization voltage Vinit and the node C. The gate electrode of the second scan TFT ST2 is connected to the jth second scan line 152 [j], the drain electrode thereof is connected to the node C, and the source electrode thereof is connected to the input terminal of the initialization voltage Vinit.

The first emission pixel ET1 is switched in response to the first emission signal EM1 [j] to turn on / off the current path between the input terminal of the high potential driving voltage EVDD and the node D. The gate electrode of the first emission TFT ET1 is connected to the jth emission line 153 [j], the drain electrode thereof is connected to the input terminal of the high potential driving voltage EVDD, do.

The second emission pixel ET2 is switched in response to the second emission signal EM2 [j + 2], thereby turning on / off the current path between the node B and the node C. [ The gate electrode of the second emission TFT ET2 is connected to the j + 2th emission line 154 [j + 2], the drain electrode thereof is connected to the node B, and the source electrode thereof is connected to the node C. The second emission pixel ET2 is turned off in accordance with the second emission signal EM2 [j + 2] of the off level in the above-described programming period, so that the parasitic capacitance of the OLED (Coled) (C1, C2).

A first capacitor (C1) is connected between node A and node B. The first capacitor C1 is used to sample the threshold voltage of the driving TFT in accordance with the source-follower scheme. The second capacitor C2 is connected between the input terminal of the high potential driving voltage EVDD and the node B. The first and second capacitors C1 and C2 perform a function of distributing the voltage to the node B when the potential of the node A is changed by the data voltage in the programming period.

The pixel operation of FIG. 7 will be described with reference to FIGS. 9A to 9D and FIG. 10 together with FIG.

One frame period can be divided into an initialization period Ti, a sampling period Ts, a programming period Tp, and an emission period Te as shown in Fig.

The first scan TFT ST1 is turned on in accordance with the first scan signal Scan [j] of the on level Lon in the initialization period Ti, the sampling period Ts and the programming period Tp, Is turned off according to the first scan signal Scan [j] of the off level Loff in the scan period Te.

The second scan TFT ST2 is turned on in accordance with the second scan signal Scan [j] of the on level Lon in the initialization period Ti and the sampling period Ts, the programming period Tp, And is turned off in accordance with the second scan signal Scan [j] of the off level Loff in the emission period Te.

The first emission pixel ET1 is turned on in accordance with the sampling period Ts and the first emission signal EM [j] of the on level in the above-mentioned emission period Te, Is turned off according to the first emission signal EM [j] of the off level (Loff) in the programming period Tp.

The second emission TFT ET2 is controlled in accordance with the second emission signal EM [j + 2] of the on level Lon in the initialization period Ti, the sampling period Ts and the emission period Te. And is turned off according to the second emission signal EM [j + 2] of the off level (Loff) in the programming period Tp, while being turned on.

During the frame period, the data driving circuit 12 applies the reference voltage Vref and the data voltage Vdata to the 1/2 horizontal period (1/2 H) so as to be synchronized with the first scan signal Scan1 applied to each pixel row, ) To the data line 14 alternately.

Here, the initialization period Ti is set such that the reference voltage Vref is supplied to the data line 14 in the (j-2) th horizontal period (j-2) th H allocated to the drive of the j- Period. The sampling period Ts is a period in which the reference voltage Vref is supplied to the data line 14 within the (j-1) th horizontal period (j-1) th H allocated to the driving of the Period. The programming period Tp corresponds to a period during which the data voltage Vdata is supplied to the data line 14 within the jth horizontal period jthH allocated to the driving of the jth pixel row.

In addition, the detailed pixel operation of FIGS. 7 and 8 is substantially the same as that described with reference to FIG. 5 and FIG. 6, and therefore will not be described.

11A and 11B are simulation results showing a driving current deviation according to a threshold voltage change. 12A and 12B are simulation results showing the driving current deviation according to the parasitic capacitor effect of the OLED.

11A to 12B, " 5T2C "represents the pixel of the present invention and" 4T2C "represents the pixel to be compared in which the second emission TFT ET2 is removed in the present invention.

Referring to FIGS. 11A and 11B, it can be seen that the pixel of the present invention has a better compensation characteristic for the threshold voltage shift in the positive direction as compared with the pixel to be compared. That is, the driving current Ioled change amount according to the threshold voltage variation (Vth) is 4.9% in the pixel to be compared, whereas the driving current Ioled variation amount according to the threshold voltage variation (Vth) And 2.9%, respectively.

Referring to FIGS. 12A and 12B, it can be seen that the pixel of the present invention is superior in the compensation characteristic to the deviation of the OLED parasitic capacitance (Coled) as compared with the pixel to be compared. That is, the driving current Ioled change amount according to the OLED parasitic capacitance (Coled) deviation is 6.6% in the comparison target pixel, whereas the variation amount of the driving current Ioled according to the OLED parasitic capacitance (Coled) 1.0%, respectively.

As described above, the present invention adopts a threshold voltage compensation method of programming the gate-source voltage of the driving TFT by using the voltage distribution between the capacitors, so that a separate emission TFT is provided between the source of the OLED and the driving TFT And by turning off the emission TFT in the programming period, the driving current can be programmed irrespective of the parasitic capacitance deviation of the OLED. The present invention can improve the accuracy and reliability of compensation by eliminating the parasitic capacitance effect of the OLED in the threshold voltage compensation.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit
14: Data line 15: Gate line

Claims (10)

A display panel having a plurality of pixels;
A gate driving circuit for driving first scan lines, second scan lines, first emission lines, and second emission lines of the display panel; And
And a data driving circuit for driving the data lines of the display panel;
each of pixels connected to the jth first and second scan lines and the jth first and second emission lines arranged at j (j is a natural number)
An organic light emitting diode connected between the node C and an input terminal of the low potential driving voltage;
A driving TFT for controlling a driving current applied to the organic light emitting diode, including a gate connected to the node A, a drain connected to the node D, and a source connected to the node B;
A first scan TFT connected between the data line and the node A and switched according to a first scan signal from the jth first scan line;
A second scan TFT connected between the node C and an input terminal of an initialization voltage and switched according to a second scan signal from the jth second scan line;
A first emissive TFT connected between an input terminal of a high potential driving voltage and the node D and switched according to a first emission signal from the jth first emission line;
A second emission TFT connected between the node B and the node C, the second emission TFT being switched according to a second emission signal from the jth second emission line;
A first capacitor connected between the node A and the node B;
And a second capacitor connected between an input terminal of the high potential driving voltage and the node B. The method according to claim 1,
In one frame period,
An initialization period for applying a reference voltage from the data line to the node A and applying the initialization voltage to the node B;
A sampling period in which a threshold voltage of the driving TFT is sampled and stored in the first capacitor;
Applying a data voltage from the data line to the node A and reflecting a result of voltage division between the first and second capacitors with respect to the potential change of the node A to the node B, A programming period for programming the voltage; And
And an emission period in which a driving current according to the programmed gate-source voltage is applied to the OLED to emit the OLED;
In the programming period,
And the second emission TFT is turned off according to the second emission signal of the off level so that the parasitic capacitance of the OLED is not reflected in the voltage distribution result. 3. The method of claim 2,
The first scan TFT is turned on in accordance with the first scan signal of the on level in the initialization period, the sampling period, and the programming period, and is turned off in accordance with the first scan signal of the off level in the emission period;
The second scan TFT is turned on in accordance with the second scan signal of the on level during the initialization period and is turned off according to the second scan signal of the off level during the sampling period, the programming period, and the emission period ;
The first emission control TFT is turned on in accordance with the first emission signal of the on level in the sampling period and the emission period and is turned on in accordance with the first emission signal of the off level in the initialization period and the programming period Off;
And the second emission TFT is turned on in accordance with the second emission signal of the on level in the initialization period, the sampling period, and the emission period. The method of claim 3,
Wherein the data driving circuit alternately supplies the reference voltage and the data voltage to the data line at intervals of a 1/2 horizontal period so as to be synchronized with a first scan signal applied to each pixel line;
The initialization period corresponds to a period in which a reference voltage is supplied to the data line in a (j-1) -th horizontal period allocated to drive the (j-1) th pixel row;
Wherein the sampling period corresponds to a period in which a reference voltage is supplied to the data line within a jth horizontal period allocated to drive the jth pixel row;
Wherein the programming period corresponds to a period during which the data voltage is supplied to the data line in the j-th horizontal period allocated for driving the j-th pixel row. The method according to claim 1,
Wherein the driving TFT is implemented as an N type, and the first and second scan TFTs and the first and second emission TFTs are implemented as N type or P type. A display panel having a plurality of pixels;
A gate driving circuit for driving the first scan lines, the second scan lines, and the emission lines of the display panel; And
And a data driving circuit for driving the data lines of the display panel;
Each of the pixels, which are disposed at jth (j is a natural number) pixel row and are connected to the jth first and second scan lines, the jth emission line, and the j + 2th emission line,
An organic light emitting diode connected between the node C and an input terminal of the low potential driving voltage;
A driving TFT for controlling a driving current applied to the organic light emitting diode, including a gate connected to the node A, a drain connected to the node D, and a source connected to the node B;
A first scan TFT connected between the data line and the node A and switched according to a first scan signal from the jth first scan line;
A second scan TFT connected between the node C and an input terminal of an initialization voltage and switched according to a second scan signal from the jth second scan line;
A first emission TFT connected between an input terminal of a high potential driving voltage and the node D and switched according to a first emission signal from the jth emission line;
A second emission TFT connected between the node B and the node C, the second emission TFT being switched according to a second emission signal from the j + 2th emission line;
A first capacitor connected between the node A and the node B;
And a second capacitor connected between an input terminal of the high potential driving voltage and the node B. The method according to claim 6,
In one frame period,
An initialization period for applying a reference voltage from the data line to the node A and applying the initialization voltage to the node B;
A sampling period in which a threshold voltage of the driving TFT is sampled and stored in the first capacitor;
Applying a data voltage from the data line to the node A and reflecting a result of voltage division between the first and second capacitors with respect to the potential change of the node A to the node B, A programming period for programming the voltage; And
And an emission period in which a driving current according to the programmed gate-source voltage is applied to the OLED to emit the OLED;
In the programming period,
And the second emission TFT is turned off according to the second emission signal of the off level so that the parasitic capacitance of the OLED is not reflected in the voltage distribution result. 8. The method of claim 7,
The first scan TFT is turned on in accordance with the first scan signal of the on level in the initialization period, the sampling period, and the programming period, and is turned off in accordance with the first scan signal of the off level in the emission period;
The second scan TFT is turned on in accordance with the second scan signal of the on level during the initialization period and is turned off according to the second scan signal of the off level during the sampling period, the programming period, and the emission period ;
The first emission control TFT is turned on in accordance with the first emission signal of the on level in the sampling period and the emission period and is turned on in accordance with the first emission signal of the off level in the initialization period and the programming period Off;
And the second emission TFT is turned on in accordance with the second emission signal of the on level in the initialization period, the sampling period, and the emission period. 9. The method of claim 8,
Wherein the data driving circuit alternately supplies the reference voltage and the data voltage to the data line at intervals of a 1/2 horizontal period so as to be synchronized with a first scan signal applied to each pixel line;
The initialization period corresponds to a period in which a reference voltage is supplied to the data line in an (j-2) -th horizontal period allocated for driving the (j-2) th pixel row;
The sampling period corresponds to a period in which a reference voltage is supplied to the data line in a (j-1) -th horizontal period allocated to drive the j-th pixel row;
Wherein the programming period corresponds to a period during which the data voltage is supplied to the data line in the j-th horizontal period allocated for driving the j-th pixel row. The method according to claim 6,
Wherein the driving TFT is implemented as an N type, and the first and second scan TFTs and the first and second emission TFTs are implemented as N type or P type.

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