KR20140085970A - Light emitting diode display device - Google Patents

Abstract

The present invention relates to a light emitting diode display device capable of improving the durability of a light emitting diode. The light emitting diode display device includes a plurality of pixels in which light emitting diodes are formed, wherein each pixel includes a driving switching device controlled according to a signal applied to a gate electrode thereof and connected between a first driving power line through which a first driving voltage is transmitted and an anode electrode of the light emitting diode; a data switching device controlled according to a scan signal from a scan line and connected between a data line and the gate electrode of the driving switching device; a reference switching device controlled according to a gate signal from a gate line and a recovery signal, and connected to the anode electrode and a reference power line through which a reference voltage is transmitted; a storage capacitor connected between the gate electrode of the driving switching device and the anode electrode, wherein a second driving power line through which a second driving voltage is transmitted is connected to a cathode electrode of the light emitting diode, and wherein one of the reference voltage and the second driving voltage varies based on the other while interworking with the gate signal and the recovery signal.

Description

[0001] LIGHT EMITTING DIODE DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode display, and more particularly, to a light emitting diode display capable of increasing the lifetime of the light emitting diode.

The light emitting diode is an element controlled by a current. At this time, the current flowing through the light emitting diode is controlled by adjusting the gate voltage of the driving switching element connected to the light emitting diode.

Conventionally, since the voltage according to the forward bias is continuously applied to such a light emitting diode, the lifetime of the light emitting diode is shortened.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a light emitting diode display device capable of increasing lifetime of a light emitting diode by periodically supplying a voltage according to a forward bias and a reverse bias to a light emitting diode It has its purpose.

According to an aspect of the present invention, there is provided a light emitting diode display comprising: a plurality of pixels having light emitting diodes formed therein; Each pixel is controlled according to a signal applied to its gate electrode and is connected between a first driving power supply line for transmitting a first driving voltage and an anode electrode of the light emitting diode; A data switching element controlled in accordance with a scan signal from the scan line and connected between the data line and the gate electrode of the drive switching element; A reference switching element controlled in accordance with a gate signal and a recovery signal from a gate line and connected between the anode electrode and a reference power supply line for transmitting a reference voltage; And a storage capacitor connected between the gate electrode of the drive switching element and the anode electrode; A second driving power supply line for transmitting a second driving voltage is connected to a cathode electrode of the light emitting diode; One of the reference voltage and the second driving voltage is changed based on the other one in conjunction with the gate signal and the recovery signal.

A scan driver for outputting the scan signal in a display period and a non-display period; A gate driver for outputting the gate signal in the display period and outputting the recovery signal in the non-display period; A reference voltage having the first driving voltage, the second driving voltage, and the first magnitude is generated in the display period, and the reference voltage having the first driving voltage, the second driving voltage, A generating power supply unit; And a timing controller for controlling the scan driver, the gate driver, and the power supply unit; Wherein the timing controller supplies a scan control signal, a gate control signal, and a first power control signal to the scan driver, the gate driver, and the power supply unit during the display period, And outputs the recovery control signal and the second power control signal to the scan driver, the gate driver, and the power supply unit; Wherein the scan driver sequentially supplies scan signals to the scan lines according to the scan control signal; Wherein the gate driver sequentially supplies gate signals to gate lines in accordance with the gate control signal and simultaneously supplies a recovery signal to the gate lines in accordance with the recovery control signal; The power supply unit generates a reference voltage having a first driving voltage, a second driving voltage, and a first magnitude according to the first power supply control signal and supplies the generated reference voltage to the corresponding power supply lines, A reference voltage having a first driving voltage, a second driving voltage, and a second magnitude is generated and supplied to the corresponding power supply lines.

The reference voltage having the first magnitude has a larger value than the second driving voltage; The reference voltage having the second magnitude may have a value smaller than or equal to the second driving voltage.

The reference voltage having the second magnitude has a value between a predetermined lower limit value and an upper limit value; The lower limit value is a value obtained by subtracting 15 [V] from the second drive voltage; And the upper limit value is a value obtained by subtracting 5 [V] from the second drive voltage.

Wherein the non-display period includes a period of several frames after the power is inputted to the LED display device, a period during which the LED display device is driven in the standby mode, a period during which the power of the LED display device is turned off, A blank period of the channel, and a period during which the channel is changed.

And the pulse width of the gate signal and the pulse width of the recovery signal are different from each other.

And the pulse width of the recovery signal is larger than the pulse width of the gate signal.

Further comprising: a period determiner for sensing the state of the LED display device in real time and determining whether the current period is the display period or the non-display period; The timing controller is configured to output the scan control signal, the gate control signal, the recovery control signal, the first power control signal, and the second power control signal based on a result of the period determination unit .

Further comprising: a driving time calculating unit for accumulating image data corresponding to a data voltage supplied to each of the pixels to calculate an accumulated driving time for each pixel; Wherein the timing controller adjusts a value of the recovery control signal based on a largest value among cumulative driving times calculated from the driving time calculating unit; The gate driver adjusts the magnitude of the pulse width of the recovery signal according to the value of the recovery control signal.

A scan driver for outputting the scan signal in a display period and a non-display period; A gate driver for outputting the gate signal in the display period and outputting the recovery signal in the non-display period; A reference voltage having the first driving voltage, the second driving voltage, and the first magnitude is generated in the display period, and the reference voltage having the first driving voltage, the second driving voltage, A generating power supply unit; And a timing controller for controlling the scan driver, the gate driver, and the power supply unit; Wherein the timing controller supplies a scan control signal, a gate control signal, and a first power control signal to the scan driver, the gate driver, and the power supply unit during the display period, And outputs the recovery control signal and the second power control signal to the scan driver, the gate driver, and the power supply unit; Wherein the scan driver sequentially supplies scan signals to the scan lines according to the scan control signal; Wherein the gate driver sequentially supplies gate signals to gate lines in accordance with the gate control signal and sequentially supplies recovery signals to the gate lines in accordance with the recovery control signal; The power supply unit generates a reference voltage having a first driving voltage, a second driving voltage, and a first magnitude according to the first power supply control signal and supplies the generated reference voltage to the corresponding power supply lines, A reference voltage having a first driving voltage, a second driving voltage, and a second magnitude is generated and supplied to the corresponding power supply lines.

According to another aspect of the present invention, there is provided a light emitting diode display comprising: a plurality of pixels having light emitting diodes formed therein; Each pixel is controlled according to a signal applied to its gate electrode and is connected between a first driving power supply line for transmitting a first driving voltage and an anode electrode of the light emitting diode; A data switching element which is controlled according to an A-scan signal or a B-scan signal from a scan line and is connected between a data line and a gate electrode of the drive switching element; A reference switching element controlled in accordance with a gate signal and a recovery signal from a gate line and connected between the anode electrode and a reference power supply line for transmitting a reference voltage; And a storage capacitor connected between the gate electrode of the drive switching element and the anode electrode; A second driving power supply line for transmitting a second driving voltage is connected to a cathode electrode of the light emitting diode; One of the reference voltage and the second driving voltage is changed based on the other one in conjunction with the gate signal and the recovery signal.

A scan driver for outputting the A-scan signal in a display period and outputting the B-scan signal in the non-display period; A gate driver for outputting the gate signal in the display period and outputting the recovery signal in the non-display period; A reference voltage having the first driving voltage, the second driving voltage, and the first magnitude is generated in the display period, and the reference voltage having the first driving voltage, the second driving voltage, A generating power supply unit; And a timing controller for controlling the scan driver, the gate driver, and the power supply unit; Wherein the timing controller outputs the A-scan control signal, the gate control signal, and the first power control signal to the scan driver, the gate driver, and the power supply unit during the display period, And outputs a scan control signal, a recovery control signal, and a second power control signal to the scan driver, the gate driver, and the power supply unit; The scan driver sequentially supplies A-scan signals to the scan lines according to the A-scan control signal and sequentially supplies B-scan signals to the scan lines according to the B-scan control signal. Wherein the gate driver sequentially supplies gate signals to gate lines in accordance with the gate control signal and sequentially supplies recovery signals to the gate lines in accordance with the recovery control signal; The power supply unit generates a reference voltage having a first driving voltage, a second driving voltage, and a first magnitude according to the first power supply control signal and supplies the generated reference voltage to the corresponding power supply lines, A reference voltage having a first driving voltage, a second driving voltage, and a second magnitude is generated and supplied to the corresponding power supply lines.

The pulse width of the A-scan signal is different from the pulse width of the B-scan signal; The pulse width of the gate signal and the pulse width of the recovery signal are different from each other.

The pulse width of the B-scan signal is larger than the pulse width of the A-scan signal; A pulse width of the recovery signal is larger than a pulse width of the gate signal.

Further comprising: a period determiner for sensing the state of the LED display device in real time and determining whether the current period is the display period or the non-display period; The timing controller controls the timing of the A-scan control signal, the B-scan control signal, the gate control signal, the recovery control signal, the first power control signal, And outputs a signal.

A scan driver for outputting the A-scan signal in a display period and outputting the B-scan signal in the non-display period; A gate driver for outputting the gate signal in the display period and outputting the recovery signal in the non-display period; A reference voltage having the first driving voltage, the second driving voltage, and the first magnitude is generated in the display period, and the reference voltage having the first driving voltage, the second driving voltage, A generating power supply unit; And a timing controller for controlling the scan driver, the gate driver, and the power supply unit; Wherein the timing controller outputs the A-scan control signal, the gate control signal, and the first power control signal to the scan driver, the gate driver, and the power supply unit during the display period, And outputs a scan control signal, a recovery control signal, and a second power control signal to the scan driver, the gate driver, and the power supply unit; The scan driver sequentially supplies A-scan signals to the scan lines according to the A-scan control signal and sequentially supplies B-scan signals to the scan lines according to the B-scan control signal. Wherein the gate driver sequentially supplies gate signals to gate lines in accordance with the gate control signal and simultaneously supplies a recovery signal to the gate lines in accordance with the recovery control signal; The power supply unit generates a reference voltage having a first driving voltage, a second driving voltage, and a first magnitude according to the first power supply control signal and supplies the generated reference voltage to the corresponding power supply lines, A reference voltage having a first driving voltage, a second driving voltage, and a second magnitude is generated and supplied to the corresponding power supply lines.

According to another aspect of the present invention, there is provided a light emitting diode display comprising: a plurality of pixels having light emitting diodes formed therein; Each pixel is controlled according to a signal applied to its gate electrode and is connected between a first driving power supply line for transmitting a first driving voltage and an anode electrode of the light emitting diode; A data switching element controlled in accordance with a scan signal from the scan line and connected between the data line and the gate electrode of the drive switching element; A reference switching element which is controlled according to a gate signal from a gate line and is connected between the anode electrode and a reference power supply line for transmitting a reference voltage; And a storage capacitor connected between the gate electrode of the drive switching element and the anode electrode; A second driving power supply line for transmitting a second driving voltage is connected to a cathode electrode of the light emitting diode; The reference voltage is smaller than the second driving voltage.

And a polling edge point of the scan signal is located between a rising edge point and a polling edge point of the gate signal.

And a rising edge of the scan signal is located between a rising edge and a falling edge of the gate signal.

The reference voltage having a value between a predetermined lower limit value and an upper limit value; The lower limit value is a value obtained by subtracting 15 [V] from the second drive voltage; And the upper limit value is a value obtained by subtracting 5 [V] from the second drive voltage.

The light emitting diode display device according to the present invention has the following effects.

According to the present invention, holes are accumulated in the light emitting diode due to the alternating application of the voltage according to the forward bias and the voltage according to the reverse bias to the light emitting diode for a proper time. As a result, the reversal field is reduced and the lifetime of the light emitting diode can be increased.

1 is a view illustrating a light emitting diode display device according to a first embodiment of the present invention;
2 is a diagram showing a circuit configuration of an n-th pixel according to an embodiment of the present invention;
3 is a diagram showing various signals supplied to the (n-1) th to (n + 1) th pixels connected in common to one mth data line and their timing diagrams in the display period
Figs. 4A to 4D are diagrams showing various signals supplied to the n-1th to (n + 1) -th pixels connected in common to one m-th data line and their timing diagrams in the non-
5 is a view for explaining a relationship between a period determination unit and peripheral components according to an embodiment of the present invention;
6 is a diagram for explaining a relationship between a drive time calculating unit and peripheral components according to an embodiment of the present invention;
7 is a view for explaining the operation of the n-th pixel in the display period
8 is a diagram for explaining the operation of the n-th pixel in the non-display period
9 is a view illustrating a light emitting diode display device according to a second embodiment of the present invention.
10 is a timing chart showing various signals supplied to the (n-1) th to (n + 1) th pixels connected in common to one mth data line and their signals
Figs. 11 and 12 are diagrams for explaining the operation of the n-th pixel
13 is a diagram showing the voltage of the gate electrode of the drive switching element and the voltage waveform of the anode electrode shown in Figs. 11 and 12
FIG. 14 is a view illustrating a result of a simulation experiment using a light emitting diode display device according to an embodiment of the present invention
15 is a view for explaining the effect of the present invention

1 is a view illustrating a light emitting diode display device according to a first embodiment of the present invention.

1, the LED display apparatus according to the first embodiment of the present invention includes a display unit DSP, a system SYS, a timing controller TC, a data driver DD, a scan driver SD, A gate driver GD, and a power supply PS.

The display unit DSP includes i * j pixels PX, i scan lines SL1 to SLi, i (i is a natural number greater than 1) gate lines and j Data lines DL1 to DLj, and a reference power supply line VRL. Here, first to i-th scan lines SL1 to SLi are applied with first to i-th scan signals, and first to i-th gate lines GL1 to GLi are applied with first to i- And the first to i-th recovery signals are applied to the first to j-th data lines DL1 to DLj and the reference voltage Vref is applied to the reference power line VRL, .

These pixels PX are arranged in a matrix on the display unit DSP. These pixels PX are divided into a red pixel R for displaying red, a green pixel G for displaying green, and a blue pixel B for displaying blue. At this time, the red pixels, the green pixels and the blue pixels R, G, B adjacent in the horizontal direction are unit pixels for displaying one unit image.

1, the display unit DSP further includes a first driving power supply line and a second driving power supply line. Here, the first driving voltage VDD is applied to the first driving power supply line, and the second driving voltage VSS is applied to the second driving power supply line.

The i * j pixels PX are connected in common to the first driving power supply line, the second driving power supply line and the reference power supply line VRL, respectively.

On the other hand, j pixels (hereinafter, the nth horizontal line pixels) arranged along the nth horizontal line (n is any one of 1 to i) are connected to the first to jth data lines DL1 to DLj Respectively. In addition, the n-th horizontal line pixels are commonly connected to the n-th scan line and the n-th gate line. Accordingly, the n-th horizontal line pixels receive the n-th scan signal, the n-th gate signal, the first driving voltage VDD and the second driving voltage VSS in common. That is, all the j pixels arranged on the same horizontal line are supplied with the same scan signal and gate signal, but the pixels located on different horizontal lines are supplied with different scan signals and gate signals. For example, both the red pixel R and the green pixel G located on the first horizontal line HL1 are supplied with the first scan signal and the first gate signal, while the red pixel R and the green pixel G located on the second horizontal line HL2, The pixel R and the green pixel G are supplied with the second scan signal and the second gate signal having different timings from those.

The i scan signals and i gate signals described above are actually the same type of pulses between signals of the same name, and differ only in output timing in terms of time.

The system SYS outputs a vertical synchronizing signal, a horizontal synchronizing signal, a clock signal, and image data through an interface circuit through a Low Voltage Differential Signaling (LVDS) transmitter of a graphic controller. The vertical / horizontal synchronizing signal and the clock signal output from the system SYS are supplied to the timing controller TC. In addition, the image data sequentially output from the system SYS is supplied to the timing controller TC.

The timing controller TC generates a data control signal DCS, a scan control signal SCS, a gate control signal GCS, and a recovery control signal RCS using a horizontal synchronizing signal, a vertical synchronizing signal, A data driver, a scan control signal SCS to a scan driver, a gate control signal SCS to a scan driver, a first power control signal PCS1 and a second power control signal PCS2, The recovery control signal RCS to the gate driver and the first and second power control signals PCS1 and PCS2 to the power supply PS. In this case, the operation of the LED display device according to the present invention is divided into an operation in a display period and an operation in a non-display period. The timing controller TC generates a data control signal DCS, A gate control signal GCS and a first power control signal PCS1 and supplies them to the scan driver SD, the gate driver GD and the power supply unit PS, respectively. On the other hand, the non-display outputs the data control signal DCS, the scan control signal SCS, the recovery control signal RCS and the second power control signal PCS2 between the scan driver SD and the gate driver GD And a power supply unit PS.

The non-display period may be a period of several frames after power is inputted to the light-emitting diode display device, a period during which the light-emitting diode display device is driven in the standby mode, a period during which the power of the LED display device is turned off, The period, and the period during which the channel is changed. On the other hand, the display period is a period excluding the non-display period, and can be defined as a general period in which an image is normally displayed on the display unit of the light emitting diode display. On the other hand, the above-described several frame periods can be set to a time of about three frames after the power source is inputted.

The data driver DD samples the image data (compensated image data) according to the data control signal DCS from the timing controller TC and then samples the data corresponding to one horizontal line every horizontal period Latches the sampled image data and supplies the latched image data to the data lines DL1 to DLj. That is, the data driver DD converts the video data from the timing controller TC into an analog signal (data voltage) by using the gamma voltage input from the power supply unit PS and supplies the converted video data to the data lines DL1 to DLj do.

The scan driver SD sequentially generates the first to i-th scan signals in accordance with the scan control signal SCS from the timing controller TC. The nth horizontal line pixels are controlled according to the nth scan signal.

The gate driver GD sequentially generates and outputs the first to i-th gate signals described above according to the gate control signal GCS from the timing controller TC. The gate driver GD outputs the above-described first to i-th recovery signals in accordance with the recovery control signal RCS from the timing controller TC. The first to i-th recovery signals may be sequentially output, simultaneously output, or may be output once per frame.

The first to i-th scan signals, the first to i-th gate signals, and the first to i-th recovery signals have an active state (high level voltage) ), It is possible to have a voltage of -5 [V].

The power supply unit PS supplies the first driving voltage VDD, the second driving voltage VSS and the reference voltage Vref having the first magnitude in accordance with the first power control signal PCS1 from the timing controller TC And supplies them to the corresponding power lines. On the other hand, the power supply PS supplies a first driving voltage VDD, a second driving voltage VSS and a reference voltage VSS having a second magnitude in accordance with the second power control signal PCS2 from the timing controller TC Vref) to the corresponding power supply lines.

The first driving voltage VDD and the second driving voltage VSS are 0 V and 0 V, respectively, as the first driving voltage VDD and the second driving voltage VSS, Lt; / RTI > On the other hand, the reference voltage Vref can change based on the second driving voltage VSS in conjunction with the gate signal and the recovery signal. That is, the reference voltage Vref is divided into a first driving voltage VSS of a first magnitude and a reference voltage Vref of a second magnitude. The first magnitude of the reference voltage Vref is The second driving voltage VSS has a value larger than the second driving voltage VSS and the second reference voltage Vref has a smaller value than the second driving voltage VSS. At this time, the second reference voltage Vref may have a value defined by the following equation (1).

[Equation 1]

VSS-15 [V] < Vref < VSS-5 [V]

Here, VSS denotes a second driving voltage VSS, and Vref denotes a reference voltage Vref having a second magnitude. For example, when the second driving voltage VSS is 0 [V] as described above, the reference voltage Vref of the first magnitude is 3 [V] and the reference voltage Vref of the second magnitude is -3 [V].

Meanwhile, according to the present invention, the second driving voltage VSS may change based on the reference voltage Vref in conjunction with the gate signal and the recovery signal. In other words, in the present invention, the reference voltage Vref may be fixed and the magnitude of the second driving voltage VSS may be varied based on the reference voltage Vref. That is, the second driving voltage VSS may be set to be smaller than the reference voltage Vref in the display period, and the second driving voltage VSS may be set to be larger than the reference voltage Vref in the non-display period. In such a case, the power supply unit PS sets the second driving voltage VSS to be smaller than the reference voltage Vref in response to the first power control signal PCS1, and sets the second power control signal PCS2, The second driving voltage VSS is set to be larger than the reference voltage Vref.

Each pixel is provided with a light emitting diode. During the display period, a first reference voltage Vref is applied to the anode electrode of the light emitting diode, and a second driving voltage VSS is applied to the cathode electrode of the light emitting diode do. On the other hand, in the non-display period, the reference voltage Vref of the second size is applied to the anode electrode of the light emitting diode, and the second driving voltage VSS is applied to the cathode electrode of the light emitting diode. Accordingly, in the display period, the light emitting diodes are biased in the forward direction, while in the non-display period, the light emitting diodes are biased in the reverse direction.

To this end, each of the pixels PX according to the present invention can have the following circuit configuration, and since the circuit configuration of all the pixels PX is the same, the circuit configuration for the above-mentioned n-th pixel will be exemplified .

2 is a diagram showing a circuit configuration of an n-th pixel according to an embodiment of the present invention.

The nth pixel PXn includes a driving switching element Tr_DR, a data switching element SW_data, a reference switching element SW_ref, a storage capacitor Cst and a light emitting diode OLED, as shown in FIG. do.

The driving switching element Tr_DR is controlled in accordance with a signal applied to its gate electrode and includes a first driving power supply line VDL for transmitting the first driving voltage VDD and an anode electrode An of the light emitting diode OLED . The driving switching element Tr_DR adjusts the amount (density) of driving current flowing from the first driving power supply line VDL to the second driving power supply line VSL according to the magnitude of a signal applied to its gate electrode .

The data switching element SW_data is controlled according to the n-th scan signal SSn from the n-th scan line SLn and is connected between the m-th data line DLm and the gate electrode of the drive switching element Tr_DR . In the n-th horizontal period included in the display period, this data switching element SW_data applies the data voltages from the m-th data line DLm to the gate electrode of the driving switching element Tr_DR. This data switching element SW_data is controlled according to the n-th scan signal SSn from the n-th scan line SLn, and the n-th scan signal SSn is applied to the And remains in the inactive state for the remaining period.

The reference switching element SW_ref is controlled in accordance with the n-th gate signal GSn and the n-th recovery signal RSn from the n-th gate line GLn, and transmits the anode voltage An and the reference voltage Vref And is connected between the reference power supply line VRL. In the n-th horizontal period included in the display period, the reference switching element SW_ref applies a reference voltage Vref having a first magnitude according to the n-th gate signal GSn from the n-th gate line GLn to the anode electrode (An). To this end, in this display period, the reference switching element SW_ref is controlled in accordance with the n-th gate signal GSn from the n-th gate line GLn, and the n-th gate signal GSn is an n-th horizontal Remains active for a period of time, and remains inactive for the remainder of the period. On the other hand, in the non-display period, the reference switching element SW_ref applies the reference voltage Vref having the second magnitude to the anode electrode in accordance with the n-th recovery signal RSn from the n-th gate line GLn. To this end, in this non-display period, the reference switching element SW_ref is controlled in accordance with the n-th recovery signal RSn from the n-th gate line GLn, and this n-th recovery signal RSn, Remains active for the whole or a part of the display period, and remains inactive for the remaining period.

The storage capacitor Cst is connected between the gate electrode of the drive switching element Tr_DR and the anode electrode An and stores a signal applied to the gate electrode of the drive switching element Tr_DR.

The light emitting diode OLED emits light according to the driving current supplied through the driving switching element Tr_DR, and emits light of different brightness depending on the magnitude of the driving current. The anode electrode An of the light emitting diode OLED is connected to the drain electrode (or the source electrode) of the driving switching element Tr_DR and its cathode electrode is connected to the second driving power supply line. The light emitting diode (OLED) in the present invention may be an organic light emitting diode (OLED).

3 is a diagram showing various signals supplied to the (n-1) th to (n + 1) th pixels connected in common to one m-th data line DLm and their timing diagrams in the display period.

As shown in FIG. 3, the n-th pixel PXn receives the n-th scan signal SSn, the n-th gate signal GSn, and the n-th data voltage Dn in the n-th horizontal period Hn. The n-th scan signal SSn is maintained in an active state (i.e., a high level voltage) for a part of the n-th horizontal period Hn and is maintained in an inactive state (i.e., a low level voltage) . On the other hand, the n-th gate signal GSn is maintained in an active state (i.e., a high level voltage) during the n-th horizontal period Hn, and is maintained in an inactive state (i.e., a low level voltage) for the remaining periods. The n-th scan signal SSn and the n-th gate signal GSn show pulse shapes shown in Fig. 3 for each display period T_DP of each frame.

1) th scan signal SSn-1, the (n-1) -th gate signal GSn-1, and the (n-1) th gate signal GSn-1 in the (n-1) -th horizontal period Hn- n-1 data voltage (Dn-1). The n-1 scan signal SSn-1 is maintained in an active state (i.e., a high level voltage) during a part of the (n-1) -th horizontal period Hn-1, , Low level voltage). On the other hand, the (n-1) th gate signal GSn-1 is maintained in an active state (i.e., a high level voltage) during the (n-1) -th horizontal period Hn- Level voltage). The (n-1) th scan signal SSn-1 and the (n-1) th gate signal GSn-1 exhibit pulse shapes shown in FIG. 3 for each display period T_DP of each frame.

1) th scan signal SSn + 1, the (n + 1) -th gate signal GSn + 1, and the (n + 1) th gate signal GSn + 1 in the (n + 1) -th horizontal period Hn + n + 1 data voltage (Dn + 1). The n + 1-th scan signal SSn + 1 is maintained in an active state (i.e., a high level voltage) for a part of the (n + 1) -th horizontal period Hn + 1, , Low level voltage). On the other hand, the (n + 1) -th gate signal GSn + 1 is maintained in an active state (i.e., a high level voltage) during the (n + 1) -th horizontal period Hn + 1, Level voltage). The (n + 1) th scan signal SSn + 1 and the (n + 1) th gate signal GSn + 1 exhibit the pulse shape shown in FIG. 3 for each display period T_DP of each frame.

In particular, during this display period T_DP, the reference voltage Vref has a first magnitude greater than the second driving voltage VSS. On the other hand, only a part of the display period T_DP is shown in Fig.

Figs. 4A to 4D are diagrams for explaining a case where the n-1th to (n + 1) th pixels PXn-1 to PXn + 1 commonly connected to one mth data line DLm are supplied to the non- Various signals and their timing diagrams. Here, the non-display period T_NDP in FIGS. 4A to 4D means the blank period BLK in the corresponding frame.

As shown in FIG. 4A, the n-th pixel PXn receives the n-th reset signal RSn in the blank period BLK of one frame. The n-th recovery signal RSn is maintained in an active state (i.e., a high level voltage) for a part of the blank period BLK and is maintained in an inactive state (i.e., a low level voltage) for the rest of the period. This n-th reset signal RSn represents the pulse form shown in Fig. 3 for each blank period (BLK) of every frame or kth frame (k is a natural number greater than 1). On the other hand, the n-th scan signal SSn and the n-th gate signal GSn are all kept inactive in the blank period BLK.

On the other hand, as shown in FIG. 4A, the (n-1) th pixel PXn-1 receives the (n-1) th recovery signal RSn-1 in the blank period BLK of one frame. The n-1-th recovery signal RSn-1 is maintained in an active state (i.e., a high level voltage) during a part of the blank period BLK and is maintained in an inactive state maintain. This n-1-th recovery signal RSn-1 represents the pulse shape shown in Fig. 3 for each blank period BLK of every frame or kth frame. On the other hand, the (n-1) th scan signal SSn-1 and the (n-1) th gate signal GSn-1 are kept inactive in the blank period BLK.

On the other hand, as shown in Fig. 4A, the (n + 1) th pixel PXn + 1 is supplied with the (n + 1) th recovery signal RSn + 1 in the blank period BLK of one frame. The n + 1-th recovery signal RSn + 1 is maintained in an active state (i.e., a high level voltage) during a part of the blank period BLK and is maintained in an inactive state maintain. This n + 1-th recovery signal RSn + 1 represents the pulse shape shown in Fig. 3 for each blank period BLK of every frame or k-th frame. On the other hand, the (n + 1) th scan signal SSn + 1 and the (n + 1) th gate signal GSn + 1 are kept inactive in the blank period BLK.

Here, the recovery signals supplied to the respective pixels in the blank period BLK can be supplied to the gate lines at the same timing at the same time. Also, each recovery signal may have the same pulse width. For example, as shown in Fig. 4A, the n-1 recovery signal RSn-1, the n-th recovery signal RSn and the n + 1 recovery signal RSn + 1 all have the same timing and pulse width Lt; / RTI &gt;

Particularly, during this blank period BLK, the reference voltage Vref has a second magnitude smaller than the second driving voltage VSS. On the other hand, only a part of the blank period BLK is shown in FIG. 4A.

Also, as shown in FIG. 4B, the n-th pixel PXn is supplied with the n-th reset signal RSn in the blank period BLK of one frame. The n-th recovery signal RSn is maintained in the active state for a part of the blank period BLK, and remains inactive for the rest of the period. This n-th reset signal RSn represents the pulse form shown in Fig. 3 for each blank period BLK of every frame or kth frame. On the other hand, the n-th scan signal SSn and the n-th gate signal GSn are all kept inactive in the blank period BLK.

On the other hand, as shown in FIG. 4B, the (n-1) th pixel PXn-1 receives the (n-1) th recovery signal RSn-1 in the blank period BLK of one frame. The n-1-th recovery signal RSn-1 is kept in an active state during a part of the blank period BLK, and remains inactive for the remaining periods. This n-1-th recovery signal RSn-1 represents the pulse shape shown in Fig. 3 for each blank period BLK of every frame or kth frame. On the other hand, the (n-1) th scan signal SSn-1 and the (n-1) th gate signal GSn-1 are kept inactive in the blank period BLK.

On the other hand, as shown in FIG. 4B, the (n + 1) th pixel PXn + 1 receives the (n + 1) th recovery signal RSn + 1 in the blank period BLK of one frame. The (n + 1) th recovery signal RSn + 1 is kept in the active state for a part of the blank period BLK, and remains inactive for the remaining period. This n + 1-th recovery signal RSn + 1 represents the pulse shape shown in Fig. 3 for each blank period BLK of every frame or k-th frame. On the other hand, the (n + 1) th scan signal SSn + 1 and the (n + 1) th gate signal GSn + 1 are kept inactive in the blank period BLK.

Here, the recovery signals supplied to the respective pixels PX in the blank period BLK may be sequentially supplied to the gate lines. For example, as shown in FIG. 4B, the (n-1) th recovery signal among the n-1 recovery signal RSn-1, the n-th recovery signal RSn, The signal RSn-1 may be output first in the blank period BLK and then the nth recovery signal RSn may be output and then the (n + 1) -th recovery signal RSn + 1 may be output . At this time, the pulse width of each recovery signal may be the same. On the other hand, the recovery signal may have a wider pulse width than the gate signal. For example, as shown in FIG. 4B, the n-th reset signal RSn may have a wider pulse width than the n-th gate signal GSn.

Also, as shown in FIG. 4C, only one specific pixel may be supplied with the recovery signal in the blank period BLK of one frame. For example, as shown in FIG. 4C, only the n-th pixel PXn among the n-1th to n-th pixels PXn-1 to PXn is supplied with a recovery signal in the blank period BLK of the frame . On the other hand, the remaining pixels can be supplied with a recovery signal in the blank period (BLK) of a frame other than the frame. For example, when the n-th pixel PXn is supplied with the n-th reset signal RSn in the blank period BLK of the k-th frame, the (n-1) 1 pixel PXn + 1 receives the (n + 1) -th recovery signal RSn-1 and the (n + 1) th pixel PXn + 1 in the blank period BLK of the (k + 1 recovery signal RSn + 1.

4D, not only the recovery signals RSn-1 to RSn + 1 but also the B-scan signals B-SSn-1 to B-SSn + 1 are output in the blank period BLK It is possible. That is, when a scan signal output in the display period T_DP is defined as an A-scan signal, the scan signal output in the non-display time can be defined as a B-scan signal. The B-scan signal is also applied to the pixel through the scan line. The B-scan signals B-SSn-1 to B-SSn + 1 may have a wider pulse width than the A-scan signals A-SSn-1 to A-SSn + The signal is outputted in correspondence with the recovery signal supplied to the corresponding pixel. For example, as shown in FIG. 4D, the (n-1) th scan signal B-SSn-1 supplied to the (n-1) th pixel PXn- 1), and the n-th B-scan signal (B-SSn) supplied to the n-th pixel PXn is positioned within the pulse width of the n-th reset signal RSn. Th scan signal B-SSn + 1 supplied to the (n + 1) th pixel PXn + 1 is determined as the pulse width of the (n + 1) th recovery signal RSn + The output timing thereof is determined.

4D, the scan driver SD outputs the A-scan signals A-SSn-1 to A-SSn + 1 in the display period T_DP and the non-display period T_NDP (B-SSn-1 to B-SSn + 1) to the scan line (e.g., the blank period BLK). The timing controller TC outputs the A-scan control signal, the gate control signal GCS and the first power control signal PCS1 in the display period T_DP and outputs them to the scan driver SD, Scan control signal, a recovery control signal RCS and a second power control signal PCS2 in the non-display period T_NDP and outputs them to the scan driver (GD) and the power supply unit PS, respectively, SD), the gate driver GD, and the power supply unit PS. At this time, the scan driver SD sequentially supplies the A-scan signals to the scan lines in accordance with the A-scan control signal, and sequentially supplies the B-scan signals to the scan lines according to the B-scan control signal.

On the other hand, at the timing when the B-scan signal is input to the corresponding pixel, a separate data voltage may be further input to the pixel. This data voltage may be a black gradation data voltage or a data voltage in the display period T_DP described above.

Meanwhile, the LED display device according to the present invention may further include a period determination unit, which will be described in detail with reference to FIG.

5 is a diagram for explaining a relationship between a period determination unit and peripheral components according to an embodiment of the present invention.

As shown in FIG. 5, the period determiner TD detects the state of the light emitting diode display in real time and determines whether the current period is the display period T_DP or the non-display period T_NDP. For example, the period determiner TD determines whether the current period is the display period T_DP or the blank period BLK corresponding to the non-display period T_NDP using the vertical synchronization signal and the horizontal synchronization signal . The period determiner TD determines whether the current period is the display period T_DP or the standby mode driving period corresponding to the non-display period T_NDP by determining the magnitude of the current consumed from the light emitting diode display device . The period determiner TD determines whether the current period is the display period T_DP or the power-on period T_NDP corresponding to the non-display period T_NDP by determining the magnitude of the power source voltage input to the LED display device The time when the light emitting diode display device is turned on). The period determiner TD determines whether the current period is the display period T_DP or the power-off period T_NDP corresponding to the non-display period T_NDP by determining the magnitude of the power source voltage input to the LED display device The time when the light-emitting diode display device is turned off). The period determiner TD determines whether the current period is the display period T_DP or the channel change period corresponding to the non-display period T_NDP based on the external channel change signal input to the light emitting diode display device .

The timing controller TC generates a scan control signal SCS, an A-scan control signal A-SCS, a B-scan control signal B-SCS gate control signal SCS based on a result of the period determiner TD. A recovery control signal RCS, a first power source control signal PCS1, and a second power source control signal PCS2.

Meanwhile, the LED display apparatus according to the present invention may further include a driving time calculating unit, which will be described in detail with reference to FIG.

6 is a diagram for explaining a relationship between a drive time calculating unit and peripheral components according to an embodiment of the present invention.

The driving time calculator DTC accumulates the image data corresponding to the data voltages supplied to the pixels PX to calculate the cumulative driving time for each pixel. That is, the driving time calculator DTC calculates the driving time of each of the pixels PX in accordance with the image data corresponding to each of the pixels PX so as to individually indicate the degree of deterioration of the light emitting diodes OLED provided in all the pixels PX. The driving time of each pixel PX is calculated. To this end, the drive time calculator DTC includes a memory therein, and the memory includes i * j memory cells in which data voltages of i * j pixels are accumulated and accumulated. The drive time calculator DTC stores one frame of image data (i.e., i * j number of image data) in each memory cell after the power supply voltage is applied to the light emitting diode OLED. At this time, the sum of the video data of the previous frames which have been already stored is summed with the video data of the current frame. For example, if previous frame image data (cumulative image data) corresponding to the n-th pixel PXn has been stored in the n-th memory cell, the driving time calculator DTC calculates The image data is summed up to calculate new cumulative image data, and the calculated new cumulative image data is stored in the nth memory cell. Then, new cumulative image data is stored in the nth memory cell. In this manner, the driving time calculating unit DTC calculates the cumulative driving time for all the pixels. Even if all the pixels are driven for the same time, the actual cumulative driving time may be different for each pixel depending on the gradation of the image data inputted thereto. Generally, it is judged that a pixel supplied with a large amount of image data of a high gradation level is driven for a longer time than a pixel not having a high gradation.

The timing controller TC adjusts the value of the recovery control signal RCS based on the largest value among the cumulative driving times calculated from the driving time calculating unit DTC (hereinafter referred to as the maximum cumulative driving time Tmax). That is, the timing controller adjusts the value of the recovery control signal RCS based on the pixel driven for the longest time. At this time, as the maximum cumulative drive time Tmax increases, the value of the recovery control signal RCS also increases.

At this time, the gate driver GD can adjust the magnitude of the pulse width of the recovery signal based on the value of the recovery control signal RCS. That is, the greater the value of the recovery signal, the larger the pulse width of the recovery signal can be. At this time, the pulse width of the recovery signal can be controlled so as not to exceed 20% of the maximum accumulated driving time.

Hereinafter, the operation of the n-th pixel PXn in the display period T_DP will be described with reference to FIG. 7 and FIG. 3 described above.

Fig. 7 is a diagram for explaining the operation of the n-th pixel PXn in the display period T_DP.

As shown in FIG. 3, an n-th scan signal SSn in an active state is applied to the n-th scan line SLn in the n-th horizontal period Hn, and an n-th gate signal The n th data voltage Dn is applied to the m th data line DLm and the reference voltage Vref H is applied to the reference power supply line VRL . Here, the first reference voltage Vref has a higher value than the second driving voltage VSS.

As the n-th scan signal SSn and the n-th gate signal GSn described above have an active state, the data switching element SW_data and the reference switching element SW_ref supplied thereto are turned on. Then, the n-th data voltage Dn is applied to the gate electrode of the driving switching element Tr_DR through the turn-on data switching element SW_data. At this time, the rising edge of the n-th gate signal GSn is faster than the rising edge of the n-th scan signal SSn and the falling edge of the n-th gate signal GSn is The reference switching element SW_ref is turned on earlier than the data switching element SW_data because the reference switching element SW_ref is slower than the polling edge point of the nth scan signal SSn, Is longer than the turn-on holding time of the data switching element (SW_data).

On the other hand, since the n-th data voltage Dn has a value larger than the reference voltage Vref, the driving switching element is turned on and the driving current I_oled is turned on through the turned- . The driving current I_oled is a current flowing from the first driving power supply line VDL toward the second driving power supply line VSL. The magnitude of the driving current I_oled depends on the magnitude of the n-th data voltage Dn applied to the gate electrode of the driving switching element Tr_DR. At this time, since the voltage of the anode electrode of the light emitting diode OLED (i.e., the reference voltage Vref of the first magnitude) is larger than the voltage of the cathode electrode (that is, the second driving voltage VSS) (I_oled) flows through the light emitting diode (OLED). Therefore, the light emitting diode OLED emits light. On the other hand, the n-th data voltage Dn supplied to the gate electrode of the driving switching element Tr_DR is stored by the storage capacitor Cst. The nth data voltage Dn stored by the storage capacitor Cst is maintained until a scan signal is generated in the next frame.

Hereinafter, the operation of the n-th pixel PXn in the non-display period T_DP will be described with reference to FIG. 8 and FIG. 4D described above.

8 is a diagram for explaining the operation of the n-th pixel PXn in the non-display period T_NDP.

As shown in FIG. 4D, an n-th B-scan signal (B-SSn) in an active state is applied to the n-th scan line SLn in the blank period BLK corresponding to the non-display period T_NDP, the n-th reset signal RSn in the active state is applied to the n-th gate line GLn and the reference voltage Vref (L) of the second magnitude is applied to the reference power supply line VRL. Here, the reference voltage Vref of the second size has a smaller value than the second driving voltage VSS. Although not shown in FIG. 4A, it is assumed that a further data voltage Dx is applied to the mth data line DLm in the blank period BLK. This data voltage Dx can be regarded as a data voltage applied at the time of channel change, for example, and this blank period BLK may be a part of the fact display period T_DP.

As the n-th B-scan signal (B-SSn) and the n-th recovery signal (RSn) described above have an active state, the data switching element SW_data and the reference switching element SW_ref, Is turned on. Then, the data voltage Dx is applied to the gate electrode of the drive switching element Tr_DR through the turn-on data switching element SW_data. When the rising edge of the n-th recovery signal RSn is earlier than the rising edge of the n-th B-scan signal B-SSn and the polling edge of the n-th reset signal RSn is the n-th B- The reference switching element SW_ref is turned on earlier than the data switching element and the turn-on holding time of the reference switching element SW_ref is relatively longer than the polling edge of the scan signal B- Is longer than the turn-on holding time of the data switching element (SW_data).

On the other hand, since the data voltage Dx has a value larger than the reference voltage Vref, the driving switching element Tr_DR is turned on. Since the voltage of the anode electrode An of the light emitting diode OLED (i.e., the reference voltage Vref of the second magnitude) is smaller than the voltage of the cathode electrode (that is, the second driving voltage VSS) The diode OLED is biased in the reverse direction so that the driving current I_oled is not generated. Therefore, the light emitting diode (OLED) remains off. On the other hand, the data voltage Dx supplied to the gate electrode of the driving switching element Tr_DR is stored by the storage capacitor Cst. The data voltage Dx stored by the storage capacitor Cst is maintained until a scan signal is generated in the next frame.

As described above, according to the present invention, the light emitting diode is biased in the forward direction while the light emitting diode is biased in the reverse direction in the non-display period, so that the light emitting diode can be prevented from being deteriorated.

9 is a view illustrating a light emitting diode display device according to a second embodiment of the present invention.

9 is a view illustrating a light emitting diode display device according to a second embodiment of the present invention.

9, the LED display device according to the second embodiment of the present invention includes a display unit DSP, a system SYS, a timing controller TC, a data driver DD, a scan driver SD, A gate driver GD, and a power supply PS.

The display unit DSP includes i * j pixels PX, i scan lines SL1 to SLi, i (i is a natural number greater than 1) gate lines and j Data lines DL1 to DLj, and a reference power supply line VRL. Here, first to i-th scan lines SL1 to SLi are applied with first to i-th scan signals, and first to i-th gate lines GL1 to GLi are applied with first to i- A data voltage is applied to each of the first to jth data lines DL1 to DLj and a reference voltage Vref is input to the reference power supply line VRL.

These pixels PX are arranged in a matrix on the display unit DSP. These pixels PX are divided into a red pixel R for displaying red, a green pixel G for displaying green, and a blue pixel B for displaying blue. At this time, the red pixels, the green pixels and the blue pixels R, G, B adjacent in the horizontal direction are unit pixels for displaying one unit image.

Although not shown in FIG. 2, the display unit DSP further includes a first driving power supply line and a second driving power supply line. Here, the first driving voltage VDD is applied to the first driving power supply line, and the second driving voltage VSS is applied to the second driving power supply line.

The i * j pixels PX are connected in common to the first driving power supply line, the second driving power supply line and the reference power supply line VRL, respectively.

On the other hand, j pixels (hereinafter, the nth horizontal line pixels) arranged along the nth horizontal line (n is any one of 1 to i) are connected to the first to jth data lines DL1 to DLj Respectively. In addition, the n-th horizontal line pixels are commonly connected to the n-th scan line and the n-th gate line. Accordingly, the n-th horizontal line pixels receive the n-th scan signal, the n-th gate signal, the first driving voltage VDD and the second driving voltage VSS in common. That is, all the j pixels arranged on the same horizontal line are supplied with the same scan signal and gate signal, but the pixels located on different horizontal lines are supplied with different scan signals and gate signals. For example, both the red pixel R and the green pixel G located on the first horizontal line HL1 are supplied with the first scan signal and the first gate signal, while the red pixel R and the green pixel G located on the second horizontal line HL2, The pixel R and the green pixel G are supplied with the second scan signal and the second gate signal having different timings from those.

The i scan signals and i gate signals described above are actually the same type of pulses between signals of the same name, and differ only in output timing in terms of time.

The system SYS outputs a vertical synchronizing signal, a horizontal synchronizing signal, a clock signal, and image data through an interface circuit through a Low Voltage Differential Signaling (LVDS) transmitter of a graphic controller. The vertical / horizontal synchronizing signal and the clock signal output from the system SYS are supplied to the timing controller TC. In addition, the image data sequentially output from the system SYS is supplied to the timing controller TC.

The timing controller TC generates a data control signal DCS, a scan control signal SCS and a gate control signal GCS by using a horizontal synchronizing signal, a vertical synchronizing signal and a clock signal input to the timing controller TC, Supplies the data control signal DCS to the data driver, the scan control signal SCS to the scan driver, and the gate control signal GCS to the gate driver.

The data driver DD samples the image data (compensated image data) according to the data control signal DCS from the timing controller TC and then samples the data corresponding to one horizontal line every horizontal period Latches the sampled image data and supplies the latched image data to the data lines DL1 to DLj. That is, the data driver DD converts the video data from the timing controller TC into an analog signal (data voltage) by using the gamma voltage input from the power supply unit PS and supplies the converted video data to the data lines DL1 to DLj do.

The scan driver SD sequentially generates the first to i-th scan signals in accordance with the scan control signal SCS from the timing controller TC. The nth horizontal line pixels are controlled according to the nth scan signal.

The gate driver GD sequentially generates and outputs the first to i-th gate signals described above according to the gate control signal GCS from the timing controller TC.

The first to i-th scan signals and the first to i-th gate signals have 20 [V] when they are active (high level voltage) and -5 [V] when they are inactive Voltage.

The power supply unit PS generates a first driving voltage VDD, a second driving voltage VSS, and a reference voltage Vref and supplies the generated voltages to corresponding power lines.

The first driving voltage VDD, the second driving voltage VSS and the reference voltage are both DC voltages. The first driving voltage VDD is 12 [V] and the second driving voltage VSS is 0 [V]. On the other hand, the reference voltage Vref is a DC voltage having a voltage smaller than the second driving voltage VSS. In other words, the reference voltage Vref in the second embodiment of the present invention is a DC voltage having a fixed value at all times without regard to the display period and the non-display period. This reference voltage Vref may have the value of the above-described equation (1). For example, this reference voltage may have a voltage of -3 [V].

Each pixel PX is provided with a light emitting diode, which is biased in a reverse direction when a reference voltage is applied, and biased in a forward direction when the supply of the reference voltage is cut off.

The circuit configuration of the pixel according to the second embodiment of the present invention is the same as that of the first embodiment described above, and therefore a description thereof will be made with reference to Fig.

The nth pixel PXn includes a driving switching element Tr_DR, a data switching element SW_data, a reference switching element SW_ref, a storage capacitor Cst and a light emitting diode OLED, as shown in FIG. do.

The driving switching element Tr_DR is controlled in accordance with a signal applied to its gate electrode and includes a first driving power supply line VDL for transmitting the first driving voltage VDD and an anode electrode An of the light emitting diode OLED . The driving switching element Tr_DR adjusts the amount (density) of driving current flowing from the first driving power supply line VDL to the second driving power supply line VSL according to the magnitude of a signal applied to its gate electrode .

The data switching element SW_data is controlled according to the n-th scan signal SSn from the n-th scan line SLn and is connected between the m-th data line DLm and the gate electrode of the drive switching element Tr_DR . In the n-th horizontal period, the data switching element SW_data applies data voltages from the m-th data line DLm to the gate electrode of the driving switching element Tr_DR. This data switching element SW_data is controlled according to the n-th scan signal SSn from the n-th scan line SLn, and the n-th scan signal SSn is applied to the And remains in the inactive state for the remaining period.

The reference switching element SW_ref is controlled according to the n-th gate signal GSn from the n-th gate line GLn and is connected between the anode electrode An and the reference power supply line VRL for transmitting the reference voltage Vref Respectively. In the n-th horizontal period, the reference switching element SW_ref applies the reference voltage Vref to the anode electrode An in accordance with the n-th gate signal GSn from the n-th gate line GLn. To this end, the reference switching element SW_ref is controlled according to the n-th gate signal GSn from the n-th gate line GLn, and the n-th gate signal GSn is in an active state during the n-th horizontal period And remains inactive for the remaining period. When the reference switching element SW_ref is turned on by the active gate signal GSn, the reference voltage Vref is supplied to the anode electrode An. At this time, And is kept smaller than the driving voltage VSS. Thus, at this time, the light emitting diode OLED is biased in the reverse direction, so that the light emitting diode OLED does not emit light. On the other hand, when the reference switching device SW_ref is turned off by the non-active gate signal GSn, the reference voltage Vref is no longer supplied to the anode electrode An. At this time, the voltage of the anode electrode An is increased to the driving current applied through the turn-on switching element Tr_DR, so that the voltage of the anode electrode An increases, (VSS). Thus, at this time, the light emitting diode OLED is biased in the forward direction, so that the light emitting diode OLED starts to emit light.

The storage capacitor Cst is connected between the gate electrode of the drive switching element Tr_DR and the anode electrode An and stores a signal applied to the gate electrode of the drive switching element Tr_DR.

The light emitting diode OLED emits light according to the driving current supplied through the driving switching element Tr_DR, and emits light of different brightness depending on the magnitude of the driving current. The anode electrode An of the light emitting diode OLED is connected to the drain electrode (or the source electrode) of the driving switching element Tr_DR and its cathode electrode is connected to the second driving power supply line VSL. The light emitting diode (OLED) in the present invention may be an organic light emitting diode (OLED).

10 is a diagram showing various signals supplied to the (n-1) th to (n + 1) th pixels connected in common to one mth data line DLm and a timing diagram thereof.

As shown in FIG. 10, the n-th pixel PXn receives the n-th scan signal SSn, the n-th gate signal GSn, and the n-th data voltage Dn in the n-th horizontal period Hn. The n-th scan signal SSn is maintained in an active state (i.e., a high level voltage) for a part of the n-th horizontal period Hn and is maintained in an inactive state (i.e., a low level voltage) . On the other hand, the n-th gate signal GSn is maintained in the active state (i.e., the high level voltage) during the n-th horizontal period Hn, and is maintained in the inactive state (i.e., the low level voltage) for the remaining period. The n-th scan signal SSn and the n-th gate signal GSn show pulse shapes shown in FIG. 10 every frame. Here, the polling edge point of the nth scan signal SSn is located between the rising edge point and the polling edge point of the nth gate signal GSn. The rising edge of the n-th scan signal SSn is located between the rising edge of the n-th gate signal GSn and the falling edge of the n-th gate signal GSn. The light emitting diode of the nth pixel PXn is biased in the reverse direction while the nth gate signal GSn is kept in the active state (high level voltage), and the nth gate signal GSn is in the inactive state Low level voltage), the light emitting diode is biased in the forward direction.

1) th scan signal SSn-1, the (n-1) -th gate signal GSn-1, and the (n-1) th gate signal GSn-1 in the (n-1) -th horizontal period Hn- n-1 data voltage (Dn-1). The n-1 scan signal SSn-1 is maintained in an active state (i.e., a high level voltage) during a part of the (n-1) -th horizontal period Hn-1, , Low level voltage). On the other hand, the (n-1) th gate signal GSn-1 is maintained in an active state (i.e., a high level voltage) during the (n-1) -th horizontal period Hn- Level voltage). The (n-1) th scan signal SSn-1 and the (n-1) th gate signal GSn-1 exhibit pulse shapes shown in FIG. 10 every frame. The polling edge point of the (n-1) th scan signal SSn-1 is located between the rising edge and the falling edge of the (n-1) th gate signal GSn-1. The rising edge of the (n-1) th scan signal SSn-1 is located between the rising edge and the falling edge of the (n-1) th gate signal GSn-1. The light emitting diode of the (n-1) th pixel PXn-1 is biased in the reverse direction while the (n-1) th gate signal GSn-1 is kept in the active state (high level voltage) 1) is changed from the active state to the inactive state (low level voltage), the light emitting diodes are forward biased.

1) th scan signal SSn + 1, the (n + 1) -th gate signal GSn + 1, and the (n + 1) th gate signal GSn + 1 in the (n + 1) -th horizontal period Hn + n + 1 data voltage (Dn + 1). The n + 1-th scan signal SSn + 1 is maintained in an active state (i.e., a high level voltage) for a part of the (n + 1) -th horizontal period Hn + 1, , Low level voltage). On the other hand, the (n + 1) -th gate signal GSn + 1 is maintained in an active state (i.e., a high level voltage) during the (n + 1) -th horizontal period Hn + 1, Level voltage). The (n + 1) -th scan signal SSn + 1 and the (n + 1) -th gate signal GSn + 1 represent pulse shapes shown in FIG. 10 every frame. The polling edge point of the (n + 1) th scan signal SSn + 1 is located between the rising edge and the falling edge of the (n + 1) th gate signal GSn + 1. The rising edge of the (n + 1) th scan signal SSn + 1 is located between the rising edge and the falling edge of the (n + 1) th gate signal GSn + 1. The light emitting diodes of the (n + 1) th pixel PXn + 1 are biased in the reverse direction while the (n + 1) th gate signal GSn + 1 is kept in the active state (high level voltage) GSn + 1) is changed from the active state to the inactive state (low level voltage), the light emitting diodes are forward biased.

10 shows horizontal periods included in a part of the display period, and the scan signal and the gate signal described above may not be outputted in the blank period.

Hereinafter, the operation of the n-th pixel PXn will be described with reference to FIGS. 11 and 12 and FIG. 10 described above.

11 and 12 are diagrams for explaining the operation of the n-th pixel PXn.

As shown in FIGS. 10 and 11, in the n-th horizontal period Hn, an n-th scan signal SSn in an active state is applied to the n-th scan line SLn, The n-th gate signal GSn is applied and the n-th data voltage Dn is applied to the m-th data line DLm and the reference voltage Vref is applied to the reference power supply line VRL. Here, the reference voltage Vref has a smaller value than the second driving voltage VSS.

As the n-th scan signal SSn and the n-th gate signal GSn described above have an active state, the data switching element SW_data and the reference switching element SW_ref supplied thereto are turned on. Then, the n-th data voltage Dn is applied to the gate electrode of the driving switching element Tr_DR through the turn-on data switching element SW_data. At this time, the rising edge of the n-th gate signal GSn is faster than the rising edge of the n-th scan signal SSn and the falling edge of the n-th gate signal GSn is The reference switching element SW_ref is turned on earlier than the data switching element SW_data because the reference switching element SW_ref is slower than the polling edge point of the nth scan signal SSn, Is longer than the turn-on holding time of the data switching element (SW_data).

On the other hand, since the nth data voltage Dn has a value larger than the reference voltage Vref, the driving switching element Tr_DR is turned on. However, during the n-th horizontal period Hn during which the n-th gate signal Gsn is kept in the active state, the anode voltage is supplied to the anode electrode An via the turned-on reference switching device SW_ref, Since the reference voltage Vref is continuously applied, the driving current can not be supplied to the light emitting diode OLED. That is, since the light emitting diode OLED is biased in the reverse direction during the nth horizontal period Hn, the driving current does not flow to the light emitting diode OLED. Accordingly, the light emitting diode (OLED) is off.

Next, as shown in FIGS. 10 and 12, an n-th scan signal SSn in an inactive state is applied to the n-th scan line SLn from the (n + 1) -th horizontal period Hn + 1, the n-th gate signal GSn is applied to the n-th gate line GLn and the n-th data voltage Dn is applied to the m-th data line DLm and the n-th gate signal GSn is applied to the reference power line VRL The reference voltage Vref is applied. Here, the reference voltage Vref has a smaller value than the second driving voltage VSS.

As the n-th scan signal SSn and the n-th gate signal GSn have the active state, the data switching element SW_data and the reference switching element SW_ref supplied thereto are turned off. Then, the reference voltage Vref is no longer supplied to the anode electrode An. At this time, the voltage of the anode electrode An is increased to the driving current I_oled applied through the turn-on drive switching device Tr_DR. Then, the voltage of the anode electrode An increases, 2 driving voltage VSS. Thus, at this time, the light emitting diode OLED is biased in the forward direction, so that the light emitting diode OLED starts to emit light. That is, the light emitting diode OLED is biased in the forward direction from the (n + 1) -th horizontal period Hn + 1, and the driving current I_oled begins to flow through it. The magnitude of the driving current I_oled depends on the magnitude of the n-th data voltage Dn applied to the gate electrode of the driving switching element Tr_DR. On the other hand, the n-th data voltage Dn supplied to the gate electrode of the driving switching element Tr_DR is stored by the storage capacitor Cst. The nth data voltage Dn stored by the storage capacitor Cst is maintained until a scan signal is generated in the next frame.

13 is a diagram showing the voltage of the gate electrode and the voltage waveform of the anode electrode of the driving switching element shown in Figs. 11 and 12. Fig.

13, when the gate signal GSn is active, the voltage Vg of the gate electrode rises by the data voltage Dn while the voltage Va of the anode electrode An rises by the reference voltage (Vref). However, the voltage Vg of the gate electrode and the voltage Va of the anode electrode begin to rise together starting from the time point when the gate signal GSn transits from the active state to the inactive state. Therefore, during a period in which the gate signal GSn is kept in the active state, the light emitting diode OLED is biased in the reverse direction, and the light emitting diode OLED is biased in the forward direction during the period in which the gate signal GSn is kept inactive. do.

FIG. 14 is a diagram illustrating a result of a simulation using a light emitting diode display device according to an embodiment of the present invention. Referring to FIG.

14, the first driving voltage VDD is set to 12 [V], the second driving voltage VSS is set to 0 [V], the first-size reference voltage Vref is set to 3 [V] The reference voltage Vref of the second size is -3 V, the voltage of the scan signal Scan in the active state is 20 V, and the voltage of the scan signal Scan in the inactive state is -5 [ V], the voltage of the recovery signal Recovery in the active state is set to 20 [V], and the voltage of the recovery signal Recovery in the inactive state is set to -5 [V]. The sustain time (i.e., the pulse width) of the scan signal Scan in the active state was set to 4.4 us and the sustain time (i.e., the pulse width) of the recovery signal Recovery in the active state was set to 6.4 us .

As a result of driving the LED display device according to the present invention by dividing it into the display period T_DP and the non-display period under such a setting, as shown in FIG. 14, in the display period T_DP, The voltage of the anode electrode An is maintained at 0 [V] when the recovery signal Recovery is active in the non-display period T_NDP, Respectively.

15 is a diagram for explaining the effect of the present invention.

As shown in FIG. 15, conventionally, a voltage according to the forward bias is continuously applied to the light emitting diode. Accordingly, a hole accumulation phenomenon occurs in the light emitting diode, thereby increasing the reversal field inside the light emitting diode. The increase of the reversal field causes the lifetime of the light emitting diode to shorten.

However, according to the present invention, since the voltage according to the forward bias and the voltage according to the reverse bias are alternately applied to the light emitting diode for a proper time, accumulation of holes in the light emitting diode is suppressed. As a result, the reversal field is reduced and the lifetime of the light emitting diode can be increased.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

DLm: mth data line VDD: first driving voltage
VSS: second driving voltage Vref: reference voltage
Cst: storage capacitor SW_data: data switching element
Tr_DR: drive switching element SW_ref: reference switching element
OLED: light emitting diode VDL: first driving power supply line
VSL: second driving power supply line VRL: reference power supply line
PXn: nth pixel SLn: nth scan line
GLn: nth gate line SSn: nth scan signal
RSn: nth recovery signal An: anode electrode
Dx: Data voltage

Claims (20)

A plurality of pixels formed with light emitting diodes;
Each pixel has,
A driving switching element connected between a first driving power supply line for transmitting a first driving voltage and an anode electrode of the light emitting diode, the driving switching element being controlled according to a signal applied to its gate electrode;
A data switching element controlled in accordance with a scan signal from the scan line and connected between the data line and the gate electrode of the drive switching element;
A reference switching element controlled in accordance with a gate signal and a recovery signal from a gate line and connected between the anode electrode and a reference power supply line for transmitting a reference voltage;
And a storage capacitor connected between the gate electrode of the drive switching element and the anode electrode;
A second driving power supply line for transmitting a second driving voltage is connected to a cathode electrode of the light emitting diode; And,
Wherein one of the reference voltage and the second driving voltage is changed based on the other one of the reference voltage and the second driving voltage interlocked with the gate signal and the recovery signal. The method according to claim 1,
A scan driver for outputting the scan signal in a display period and a non-display period;
A gate driver for outputting the gate signal in the display period and outputting the recovery signal in the non-display period;
A reference voltage having the first driving voltage, the second driving voltage, and the first magnitude is generated in the display period, and the reference voltage having the first driving voltage, the second driving voltage, A generating power supply unit; And
And a timing controller for controlling the scan driver, the gate driver, and the power supply unit;
Wherein the timing controller supplies a scan control signal, a gate control signal, and a first power control signal to the scan driver, the gate driver, and the power supply unit during the display period, And outputs the recovery control signal and the second power control signal to the scan driver, the gate driver, and the power supply unit;
Wherein the scan driver sequentially supplies scan signals to the scan lines according to the scan control signal;
Wherein the gate driver sequentially supplies gate signals to gate lines in accordance with the gate control signal and simultaneously supplies a recovery signal to the gate lines in accordance with the recovery control signal; And,
Wherein the power supply unit generates a reference voltage having a first driving voltage, a second driving voltage, and a first magnitude according to the first power supply control signal and supplies the reference voltage to corresponding power supply lines, And generates a reference voltage having a first driving voltage, a second driving voltage, and a second magnitude, and supplies the reference voltage to the corresponding power supply lines. 3. The method of claim 2,
The reference voltage having the first magnitude has a larger value than the second driving voltage; And,
And the reference voltage having the second magnitude has a value smaller than or equal to the second driving voltage. The method of claim 3,
The reference voltage having the second magnitude has a value between a predetermined lower limit value and an upper limit value;
The lower limit value is a value obtained by subtracting 15 [V] from the second drive voltage;
Wherein the upper limit value is a value obtained by subtracting 5 [V] from the second drive voltage. 3. The method of claim 2,
The non-display period includes a period of several frames after the power is inputted to the LED display device, a period during which the LED display device is driven in the standby mode, a period during which the power of the LED display device is turned off, A blank period of the light emitting diode, and a period during which the channel is changed. The method according to claim 1,
Wherein a pulse width of the gate signal and a pulse width of a recovery signal are different from each other. The method according to claim 6,
Wherein a pulse width of the recovery signal is larger than a pulse width of the gate signal. 3. The method of claim 2,
Further comprising: a period determiner for sensing the state of the LED display device in real time and determining whether the current period is the display period or the non-display period; And,
Wherein the timing controller outputs the scan control signal, the gate control signal, the recovery control signal, the first power supply control signal, and the second power supply control signal based on a result of the period determination unit. Display device. 3. The method of claim 2,
Further comprising: a driving time calculating unit for accumulating image data corresponding to a data voltage supplied to each of the pixels to calculate an accumulated driving time for each pixel;
Wherein the timing controller adjusts a value of the recovery control signal based on a largest value among cumulative driving times calculated from the driving time calculating unit; And,
Wherein the gate driver adjusts a magnitude of a pulse width of a recovery signal according to a value of the recovery control signal. The method according to claim 1,
A scan driver for outputting the scan signal in a display period and a non-display period;
A gate driver for outputting the gate signal in the display period and outputting the recovery signal in the non-display period;
A reference voltage having the first driving voltage, the second driving voltage, and the first magnitude is generated in the display period, and the reference voltage having the first driving voltage, the second driving voltage, A generating power supply unit; And
And a timing controller for controlling the scan driver, the gate driver, and the power supply unit;
Wherein the timing controller supplies a scan control signal, a gate control signal, and a first power control signal to the scan driver, the gate driver, and the power supply unit during the display period, And outputs the recovery control signal and the second power control signal to the scan driver, the gate driver, and the power supply unit;
Wherein the scan driver sequentially supplies scan signals to the scan lines according to the scan control signal;
Wherein the gate driver sequentially supplies gate signals to gate lines in accordance with the gate control signal and sequentially supplies recovery signals to the gate lines in accordance with the recovery control signal; And,
Wherein the power supply unit generates a reference voltage having a first driving voltage, a second driving voltage, and a first magnitude according to the first power supply control signal and supplies the reference voltage to corresponding power supply lines, And generates a reference voltage having a first driving voltage, a second driving voltage, and a second magnitude, and supplies the reference voltage to the corresponding power supply lines. A plurality of pixels formed with light emitting diodes;
Each pixel has,
A driving switching element connected between a first driving power supply line for transmitting a first driving voltage and an anode electrode of the light emitting diode, the driving switching element being controlled according to a signal applied to its gate electrode;
A data switching element which is controlled according to an A-scan signal or a B-scan signal from a scan line and is connected between a data line and a gate electrode of the drive switching element;
A reference switching element controlled in accordance with a gate signal and a recovery signal from a gate line and connected between the anode electrode and a reference power supply line for transmitting a reference voltage;
And a storage capacitor connected between the gate electrode of the drive switching element and the anode electrode;
A second driving power supply line for transmitting a second driving voltage is connected to a cathode electrode of the light emitting diode; And,
Wherein one of the reference voltage and the second driving voltage is changed based on the other one of the reference voltage and the second driving voltage interlocked with the gate signal and the recovery signal. 12. The method of claim 11,
A scan driver for outputting the A-scan signal in a display period and outputting the B-scan signal in the non-display period;
A gate driver for outputting the gate signal in the display period and outputting the recovery signal in the non-display period;
A reference voltage having the first driving voltage, the second driving voltage, and the first magnitude is generated in the display period, and the reference voltage having the first driving voltage, the second driving voltage, A generating power supply unit; And
And a timing controller for controlling the scan driver, the gate driver, and the power supply unit;
Wherein the timing controller outputs the A-scan control signal, the gate control signal, and the first power control signal to the scan driver, the gate driver, and the power supply unit during the display period, And outputs a scan control signal, a recovery control signal, and a second power control signal to the scan driver, the gate driver, and the power supply unit;
The scan driver sequentially supplies A-scan signals to the scan lines according to the A-scan control signal and sequentially supplies B-scan signals to the scan lines according to the B-scan control signal.
Wherein the gate driver sequentially supplies gate signals to gate lines in accordance with the gate control signal and sequentially supplies recovery signals to the gate lines in accordance with the recovery control signal; And,
Wherein the power supply unit generates a reference voltage having a first driving voltage, a second driving voltage, and a first magnitude according to the first power supply control signal and supplies the reference voltage to corresponding power supply lines, And generates a reference voltage having a first driving voltage, a second driving voltage, and a second magnitude, and supplies the reference voltage to the corresponding power supply lines. 12. The method of claim 11,
The pulse width of the A-scan signal is different from the pulse width of the B-scan signal; And,
Wherein a pulse width of the gate signal and a pulse width of a recovery signal are different from each other. 14. The method of claim 13,
The pulse width of the B-scan signal is larger than the pulse width of the A-scan signal; And,
Wherein a pulse width of the recovery signal is larger than a pulse width of the gate signal. 13. The method of claim 12,
Further comprising: a period determiner for sensing the state of the LED display device in real time and determining whether the current period is the display period or the non-display period; And,
Wherein the timing controller controls the timing of the A-scan control signal, the B-scan control signal, the gate control signal, the recovery control signal, the first power control signal, and the second power control signal And an output box. 12. The method of claim 11,
A scan driver for outputting the A-scan signal in a display period and outputting the B-scan signal in the non-display period;
A gate driver for outputting the gate signal in the display period and outputting the recovery signal in the non-display period;
A reference voltage having the first driving voltage, the second driving voltage, and the first magnitude is generated in the display period, and the reference voltage having the first driving voltage, the second driving voltage, A generating power supply unit; And
And a timing controller for controlling the scan driver, the gate driver, and the power supply unit;
Wherein the timing controller outputs the A-scan control signal, the gate control signal, and the first power control signal to the scan driver, the gate driver, and the power supply unit during the display period, And outputs a scan control signal, a recovery control signal, and a second power control signal to the scan driver, the gate driver, and the power supply unit;
The scan driver sequentially supplies A-scan signals to the scan lines according to the A-scan control signal and sequentially supplies B-scan signals to the scan lines according to the B-scan control signal.
Wherein the gate driver sequentially supplies gate signals to gate lines in accordance with the gate control signal and simultaneously supplies a recovery signal to the gate lines in accordance with the recovery control signal; And,
Wherein the power supply unit generates a reference voltage having a first driving voltage, a second driving voltage, and a first magnitude according to the first power supply control signal and supplies the reference voltage to corresponding power supply lines, And generates a reference voltage having a first driving voltage, a second driving voltage, and a second magnitude, and supplies the reference voltage to the corresponding power supply lines. A plurality of pixels formed with light emitting diodes;
Each pixel has,
A driving switching element connected between a first driving power supply line for transmitting a first driving voltage and an anode electrode of the light emitting diode, the driving switching element being controlled according to a signal applied to its gate electrode;
A data switching element controlled in accordance with a scan signal from the scan line and connected between the data line and the gate electrode of the drive switching element;
A reference switching element which is controlled according to a gate signal from a gate line and is connected between the anode electrode and a reference power supply line for transmitting a reference voltage;
And a storage capacitor connected between the gate electrode of the drive switching element and the anode electrode;
A second driving power supply line for transmitting a second driving voltage is connected to a cathode electrode of the light emitting diode; And,
Wherein the reference voltage is smaller than the second driving voltage. 18. The method of claim 17,
Wherein a falling edge of the scan signal is located between a rising edge and a falling edge of the gate signal. 19. The method of claim 18,
Wherein a rising edge of the scan signal is located between a rising edge and a falling edge of the gate signal. 18. The method of claim 17,
The reference voltage having a value between a predetermined lower limit value and an upper limit value;
The lower limit value is a value obtained by subtracting 15 [V] from the second drive voltage;
Wherein the upper limit value is a value obtained by subtracting 5 [V] from the second drive voltage.

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