WO2021117640A1

WO2021117640A1 - Timing controller, display system, and automobile

Info

Publication number: WO2021117640A1
Application number: PCT/JP2020/045305
Authority: WO
Inventors: 洋志松村
Original assignee: ローム株式会社
Priority date: 2019-12-12
Filing date: 2020-12-04
Publication date: 2021-06-17
Also published as: JP2023027419A

Abstract

A timing controller IC 200 receives image data from a graphic controller 132 and controls a display unit 110 via a differential serial-type main channel 152. The timing controller IC 200 generates, on the basis of the image data, a first control signal for controlling a source driver IC 300, a second control signal for controlling a gate driver 114, and a third control signal for controlling a power management (PM) IC 120, and transmits the first and the third control signals to the source driver IC 300 via the main channel 152. The source driver IC 300 controls the PM IC 120 on the basis of the third control signal.

Description

Timing controller and display system, automobile

This disclosure relates to a timing controller and a display system.

FIG. 1 is a diagram showing a conventional display system. The display system 1T of FIG. 1 includes a graphic controller 2, a timing controller 4, a source driver 6, a gate driver 8, a display panel 10, and a power management circuit (PMIC: Power Management IC) 30.

The graphic controller 2 generates image data to be displayed on the display panel 10, and sets the RGB value of each pixel of the image data together with control signals such as a pixel clock, a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal to the timing controller 4. Serial transmission to.

The timing controller 4 controls the source driver 6 and the gate driver 8 based on the received image data and the control signal, and displays the image on the display panel 10.

Japanese Unexamined Patent Publication No. 2018-031926

(Problem 1) In the system of FIG. 1, the interface between the timing controller 4 and the display unit 5 includes three control channels. One is a transmission channel CH1 between the timing controller 4 and the source driver 6, and image data and timing signals are transmitted to the source driver 6 via the transmission channel CH1. The other is a transmission channel CH2 between the timing controller 4 and the gate driver 8, and a timing signal to the gate driver 8 is transmitted via the transmission channel CH2. The other is the transmission channel CH3 between the timing controller 4 and the PMIC 30.

The source driver 6, the gate driver 8, the display panel 10, and the PMIC 30 constitute the display unit 5. In a system in which the distance between the timing controller 4 and the display unit 5 is as long as several meters, it is necessary to provide a serializer / deserializer for long-distance transmission for each transmission channel, which causes system complexity and cost increase. Become.

(Problem 2) In the communication standard of the timing controller 4 and the source driver 6 which is generally used at present, in order to monitor whether the communication between the timing controller 4 and the source driver 6 is normal, a single line or one direction Communication is used. Specifically, in the PtoP (Point to Point) format as shown in FIG. 1, the source driver 6 and the timing controller 4 are connected via a return line 18, and the source driver 6 for which communication has been established is a return line. It is configured to return the lock signal Lock to the timing controller 4 via 18. By monitoring the lock signal Lock, the timing controller 4 can detect whether or not the source driver 6 and the transmission channel CH1 are functioning normally.

In the system of FIG. 1, the timing controller 4 can detect an abnormality of the transmission channel CH1 with the source driver 6, but cannot detect other abnormalities. In recent years, LCDs for in-vehicle display systems have been promoted, but for in-vehicle applications, a strong fail-safe system is required from the viewpoint of safety, and it is necessary to detect an abnormality in PMIC30 or a circuit block (not shown). .. In this case, it is necessary to add an MCU (MicroControlUnit) that controls functional safety to the display unit 5, and further add a communication channel between the timing controller 4 and the MCU, which complicates the system.

This disclosure has been made in view of the above issues, and one of the exemplary purposes of the embodiment is to provide a display system with a simplified configuration.

One aspect of this disclosure relates to a display system. The display system is a display panel, a source driver and a gate driver that drives the display panel, a display unit having peripheral circuits, a graphic controller that generates image data, and a main differential serial format that receives image data from the graphic controller. It includes a timing controller that controls the source driver via a channel. The timing controller generates a first control signal that controls the source driver based on image data, a second control signal that controls the gate driver, and a third control signal that controls peripheral circuits, and feeds the source driver via the main channel. , The first control signal and the third control signal can be transmitted, and the source driver can control peripheral circuits based on the third control signal.

Another aspect of the present disclosure relates to a timing controller for a display system having a display unit. The display unit includes a display panel, a source driver and a gate driver for driving the display panel, and peripheral circuits. The timing controller generates an interface circuit that receives image data from the graphic controller, a first control signal for controlling the source driver, and a second control signal for controlling the gate driver based on the image data. A signal processing unit that generates a third control signal for controlling peripheral circuits, a serializer that converts image data, a first control signal, a second control signal, and a third control signal into serial data, and an output of the serializer. It includes a differential transmitter that transmits to the source driver via the main channel in differential serial format.

It should be noted that an arbitrary combination of the above components or a conversion of the expression between methods, devices, etc. is also effective as an aspect of the present invention.

According to a certain aspect of the present disclosure, the configuration of the display system can be simplified.

It is a figure which shows the conventional display system. It is a block diagram of the display system 100 which concerns on Embodiment 1. FIG. It is a figure explaining the frame data transmitted through a main channel. It is a sequence diagram explaining startup and termination of the display system of FIG. It is a block diagram of the display system which concerns on Embodiment 2. FIG. It is a block diagram of the timing controller IC which concerns on one Example. It is a block diagram of the source driver IC which concerns on one Example. It is a block diagram of the display system which concerns on Embodiment 3. FIG. It is a figure explaining the composite image data. It is a block diagram of the timing controller IC which concerns on Embodiment 3. FIG. It is a figure which shows the passenger compartment of the automobile equipped with a display system.

(Outline of Embodiment)
Some exemplary embodiments of the present disclosure will be outlined. This overview simplifies and describes some concepts of one or more embodiments for the purpose of basic understanding of the embodiments as a prelude to the detailed description described below, and is an invention or disclosure. It does not limit the size. Also, this overview is not a comprehensive overview of all possible embodiments and does not limit the essential components of the embodiments. For convenience, "one embodiment" may be used to refer to one embodiment (examples or modifications) or a plurality of embodiments (examples or modifications) disclosed herein.

The display system according to one embodiment receives image data from a display panel, a source driver and a gate driver for driving the display panel, a display unit having peripheral circuits, a graphic controller for generating image data, and a graphic controller, and makes a difference. It is equipped with a timing controller that controls the source driver via the main channel in the dynamic serial format. The timing controller generates a first control signal that controls the source driver based on image data, a second control signal that controls the gate driver, and a third control signal that controls peripheral circuits, and feeds the source driver via the main channel. , The first control signal and the third control signal can be transmitted, and the source driver can control peripheral circuits based on the third control signal.

According to this configuration, the peripheral circuit can be controlled via the transmission channel between the source driver and the peripheral circuit, so that the transmission channel between the peripheral circuit and the timing controller becomes unnecessary, and the system can be simplified.

In one embodiment, the timing controller is configured to be able to transmit a second control signal to the source driver via the main channel, and the source driver is configured to be able to control the gate driver based on the second control signal. Good.

According to this configuration, since the gate driver can be controlled via the transmission channel between the source driver and the source driver, the transmission channel between the gate driver and the timing controller becomes unnecessary, and the system can be simplified.

In one embodiment, the timing controller may be configured to be communicable with the source driver via a bidirectional serial auxiliary channel. The timing controller issues a request command to the source driver to acquire the status information of the peripheral circuit, and the source driver responds to the request command to acquire the status information of the peripheral circuit and replies including the status information. The command may be sent to the timing controller.

According to this configuration, by adding a bidirectional serial auxiliary channel to the panel interface between the timing controller and the source driver in addition to the main channel for images, the timing controller provides a detailed state of the panel driver. Can be obtained. The logical layer of communication via the auxiliary channel, I 2 ^{C (Inter} IC) compatible protocol may be utilized.

Storage In one embodiment, the source driver and the peripheral circuit are connected by the I 2 ^{C (Inter} IC) interface, a source driver, in response to the request command, the register of the peripheral circuit via the I 2 ^C interface The status information to be generated may be read, and a reply command including the status information may be sent to the timing controller.

In one embodiment, the peripheral circuit may be a power management circuit. The third control signal may instruct the start and stop of the power supply management circuit.

In one embodiment, the source driver and the power supply management circuit are connected by a control line, and the start and stop of the power supply management circuit may be controlled by using the control line.

The timing controller according to one embodiment is for a display system having a display unit. The display unit includes a display panel, a source driver and a gate driver for driving the display panel, and peripheral circuits. The timing controller generates an interface circuit that receives image data from the graphic controller, a first control signal for controlling the source driver, and a second control signal for controlling the gate driver based on the image data. A signal processing unit that generates a third control signal for controlling peripheral circuits, a serializer that converts image data, a first control signal, a second control signal, and a third control signal into serial data, and an output of the serializer. It includes a differential transmitter that transmits to the source driver via the main channel in differential serial format.

According to this configuration, peripheral circuits can be controlled via the transmission channel between the source driver and the peripheral circuit, eliminating the need for a transmission channel between the peripheral circuit and the timing controller and a transmission channel between the gate driver and the timing controller. Can be simplified.

In one embodiment, the timing controller may further include an auxiliary interface circuit capable of communicating with the source driver via a bidirectional serial auxiliary channel. The auxiliary interface circuit issues a request command to the source driver to acquire the status information of the peripheral circuit, and in response to the request command, issues a reply command containing the status information of the peripheral circuit acquired by the source driver to the auxiliary interface circuit. May be receivable by.

According to this configuration, by adding a bidirectional serial auxiliary channel to the panel interface between the timing controller and the source driver in addition to the main channel for images, the timing controller provides a detailed state of the panel driver. Can be obtained. The logical layer of communication via the auxiliary channel, protocol similar to the I 2 ^{C (Inter} IC) may be utilized. Physical layer of the auxiliary channel differential transmission that is suitable for long-distance transmission is employed than I 2 ^C.

(Embodiment)
Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and redundant description will be omitted as appropriate. Further, the embodiment is not limited to the invention but is an example, and all the features and combinations thereof described in the embodiment are not necessarily essential to the invention.

In the present specification, the "state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected to each other. It also includes the case of being indirectly connected via other members, which does not substantially affect the connection state or does not impair the functions and effects performed by the combination thereof.

Similarly, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, and their electricity. It also includes the case of being indirectly connected via other members, which does not substantially affect the connection state, or does not impair the functions and effects produced by the combination thereof.

(Embodiment 1)
FIG. 2 is a block diagram of the display system 100 according to the first embodiment. The display system 100 includes a display unit 110 and a control unit 130. The display unit 110 includes a display panel 112, a gate driver IC 114, and a source driver IC 300. The display panel 112 is typically a liquid crystal (LCD) panel, but may be an organic EL panel or a micro LED panel.

The display unit 110 is provided with a PMIC 120, a level shifter 122, a backlight (not shown), a drive circuit thereof, an EEPROM (Electrically Erasable Programmable Read-Only Memory), and the like (hereinafter collectively referred to as peripheral circuits).

The source driver IC 300 is connected to the source line (data line) SL of the display panel 112 and drives the source line SL. Further, the gate driver IC 114 is connected to the gate line (scan line) GL of the display panel 112 and drives the gate line GL. The number of source driver ICs 300 and gate drivers 114 is determined based on the size (resolution) of the display panel 112.

The control unit 130 includes a graphic controller 132, a microcontroller 134, and a timing controller IC 200. The graphic controller 132 is an SOC (System On Chip) including a graphic processor, and generates image data IMG to be displayed on the display panel 112. Then, the graphic controller 132 transfers the RGB value of each pixel of the image data IMG from its output port to the timing controller IC200 together with control signals such as pixel clock CLK, vertical synchronization signal Vsync, horizontal synchronization signal Hsync, and data enable signal DE. Send.

The timing controller IC 200 receives the image data IMG from the graphic controller 132, and generates a driver control signal (timing signal) for controlling the display unit 110 with respect to the image data IMG. This driver control signal mainly includes a first control signal CNTh for controlling the source driver IC 300 and a second control signal CNTv for controlling the gate driver 114. The generation of the driver control signal CNT in the timing controller IC200 is the same as the known technique, and thus the description thereof will be omitted. The driver control signal CNT includes a plurality of timing signals. Those skilled in the art will understand that the names and symbols of each driver control signal may vary from manufacturer to manufacturer.

1. 1. Driver control signal for the source driver (first control signal CNT)
1.1 Start pulse (STH)
Depending on the panel size (resolution) of the display panel, a plurality of source drivers or gate drivers may be cascaded. The image data and the driver control signal output from the timing controller pass through a plurality of source drivers in order. The plurality of source drivers postpone the start pulse STH in order like a shift register. The source driver to which the start pulse STH is input captures the image data.

1.2 Latch pulse (LOAD)
The latch pulse LOAD is asserted for each scan line. When the latch pulse LOAD is asserted, the source driver captures image data for one scanning line segment.

1.3 AC signal (POL)
The source driver drives the display panel with alternating polarities. The polarity of the source driver is determined by the AC signal POL.

2. Driver control signal for gate driver (second control signal CNTv)
2.1 Vertical shift direction input / output signal (STV)
Used when multiple gate drivers are cascaded. The vertical shift direction input / output signal STV is sequentially shifted by a plurality of gate drivers.

2.2 Vertical transfer clock (CPV)
Each gate driver captures the input vertical shift direction input / output signal STV at the timing of the positive edge of the vertical transfer clock CPV.

2.3 Output enable (OE)
This is the data that controls the state of the output terminal of the gate driver. When the output enable OE is asserted, a drive voltage is applied to the scanning line SL, and when negated, the potential of the scanning line SL is fixed.

The type and number of driver control signal CNTs and those exemplified here are not limited.

The timing controller IC 200 transmits the image data IMG together with the driver control signal CNT to the display unit 110.

The display unit 110 and the control unit 130 are arranged at a distance of about 1 m to 10 m, and the display unit 110 and the control unit 130 are connected via a panel interface 150 capable of long-distance transmission. The panel interface 150 is physically composed of differential wiring formed on an FPC (Flexible Printed Circuit) substrate or housed in a cable.

The timing controller IC 200 generates a third control signal CNTp for controlling the peripheral circuit of the display unit 110 in addition to the first control signal CNTh and the second control signal CNTv. For example, as the third control signal CNTp, an enable signal PMIC_EN that controls ON / OFF of the PMIC 120 is exemplified.

In the present embodiment, the panel interface 150 includes a main channel 152 for image transmission.

In the present embodiment, the image data IMG and the driver control signal (first control signal CNTh and second control signal CNTv) are transmitted to the source driver IC 300 via the main channel 152. The source driver IC 300 drives the source line of the display panel 112 based on the received first control signal CNTh.

The PMIC 120 receives a power supply voltage (denoted as VDD3.3) from the control unit 130 and generates a plurality of power supply voltages required by the display unit 110. Specifically, the PMIC 120 is a multi-channel power supply circuit including a step-up / step-down switching regulator and a linear regulator. The PMIC 120 supplies the source driver IC 300 with a power supply voltage (A VDD) for the analog block of the source driver IC 300 and a power supply voltage (DVDD) for the digital block of the source driver IC 300. The PMIC 120 also supplies the level shifter 122 with low-level and high-level voltages VGL and VGH.

The first feature of this embodiment will be described. In the present embodiment, the PMIC 120, which is one of the peripheral circuits, and the timing controller IC 200 are not directly connected, but are indirectly connected via the source driver IC 300.

The enable signal PMIC_EN for the PMIC 120 is transmitted from the timing controller IC 200 to the source driver IC 300 via the main channel 152.
The source driver IC 300 receives the enable signal PMIC_EN via the main channel 152 and controls the PMIC 120 based on the enable signal PMIC_EN. For example, the source driver IC 300 and the PMIC 120 are connected via one control line 124. The source driver IC 300 generates a standby signal PWR_STB corresponding to the enable signal PMIC_EN. The PWR_STB signal is input to the PMIC 120 via the control line 124, and the start and stop of the PMIC 120 are controlled according to the PWR_STB signal.

The second feature of this embodiment will be described. In the present embodiment, the gate driver IC 114 and the timing controller IC 200 are not directly connected, but are indirectly connected via the source driver IC 300. The source driver IC 300 receives the second control signal CNTv via the main channel 152 and controls the gate driver 114. A level shifter 122 is provided between the source driver IC 300 and the gate driver 114. The level shifter 122 shifts the output of the source driver IC 300 to an appropriate voltage level (VGH, VGL) and supplies it to the gate driver 114.

FIG. 3 is a diagram illustrating frame data 600 transmitted via the main channel 152. As described above, the frame data 600 includes image data, a first control signal CNT for controlling the source driver IC 300 and the gate driver 114, a second control signal CNTv, and an enable signal PMIC_EN for the PMIC 120.

The frame data 600 includes a plurality of line data 602. A blanking pattern HBP is arranged at the beginning of each line data 602, and an EOL (End Of Line) symbol is arranged at the end. The blanking pattern HBP is followed by a non-blanking pattern, that is, a SOL (Start Of Line) symbol indicating the start of valid data. Following the SOL symbol, the line configuration data CFG for the source driver IC is placed. A special symbol is assigned to the CFG data (FSTR = 1) on the first line, and the line counter of the source driver is reset by using this symbol as a trigger.

In the vertically effective area, RGB data of a plurality of pixels constituting the line data is arranged after the CFG data, and then the data for inspection is arranged. Known inspection data can be used, for example, (i) information generated by cyclic redundancy check (CRC) (remainder of polynomial division), (ii) number of packets transmitted by the timing controller IC200, and (iii) parity. , (Iv) May include at least one checksum. The source driver IC 300 that has received the frame data 600 can detect a transmission error by using the inspection data for each line data.

In the vertical invalid area, frame configuration data FCFG and blank data are arranged instead of RGB data.

Also, a pattern for clock training is embedded in the last few lines.

The enable signal PMIC_EN for the PMIC 120 can be mapped to the frame configuration data FCFG. The frame configuration data FCFG can include control data for peripheral circuits other than the PMIC 120.

The above is the configuration of the display system 100. Next, the advantages will be described. FIG. 4 is a sequence diagram illustrating startup and termination of the display system 100 of FIG. First, the operation at startup will be explained. The power supply voltage VDD3.3 is supplied to the timing controller IC200, PMIC120 and the power supply circuit 136. The power supply circuit 136 generates the power supply voltage VDD1.2 and supplies it to the timing controller IC200. Further, the power supply voltage VDD1.8 is supplied to the source driver IC300. At this stage, the timing controller IC 200 and the source driver IC 300 are activated, and data transmission via the main channel 152 becomes possible.

Then, the timing controller IC 200 asserts the enable signal PMIC_EN for the PMIC 120, embeds it in the frame configuration data, and transmits it to the source driver IC 300. The source driver IC 300 asserts the PWR_STB signal and activates the PMIC 120. As a result, the PMIC 120 generates the power supply voltages VGH and VGL and supplies them to the level shifter 122. As a result, the image can be displayed on the display panel 112.

The timing controller IC 200 transmits the frame data including the image data IMG received from the graphic controller 132 to the source driver IC 300 via the main channel 152. As a result, the display panel 112 is driven, and the image data IMG is displayed on the panel driver 12.

Next, the operation at the end will be explained. The timing controller IC 200 negates the enable signal PMIC_EN for the PMIC 120, embeds it in the frame configuration data, and transmits it to the source driver IC 300. The source driver IC 300 negates the PWR_STB signal and stops the PMIC 120. As a result, the PMIC 120 stops the power supply voltages VGH and VGL. After that, the power supply voltage VDD3.3 is cut off, VDD1.8 and VDD1.2 are cut off, and the system is stopped. The above is the operation of the display system 100. Subsequently, the advantages of the display system 100 will be described.

According to the display system 100 according to the present embodiment, the transmission channel between the timing controller IC 200 and the peripheral circuit PMIC 120 becomes unnecessary, so that the system can be simplified.

Further, according to the display system 100, the transmission channel between the gate driver 114 and the timing controller IC 200 becomes unnecessary, so that the system can be further simplified.

(Embodiment 2)
FIG. 5 is a block diagram of the display system 100A according to the second embodiment. In the present embodiment, the panel interface 150 between the timing controller IC 200 and the source driver IC 300 includes a bidirectional serial type auxiliary channel 154 in addition to the main channel 152, and the timing controller IC 200 and the source driver IC 300 are bidirectional. It is possible to communicate with.

The auxiliary channel 154 is a channel added to the timing controller IC 200 to collect the status information of the display unit 110, specifically, the error information of the plurality of source driver ICs 300 or the gate driver IC 114.

As for the communication protocol via the auxiliary channel 154, the timing controller IC200 is the master and the plurality of source driver ICs 300 are the slaves. ^{For example, a register access type protocol similar to I 2} C (Inter IC) can be used for communication via the auxiliary channel 154 ^{, which is called I 2} C over Aux.

The microcontroller 134 is provided for functional safety. The microcontroller 134 and the timing controller IC 200 are connected by an interface such as ^{I 2 C (Inter IC).} The status information of the display unit 110 is collected in the timing controller IC 200 via the auxiliary channel 154 and written to the register in the timing controller IC 200.

The microprocessor 134 can know the status information of each IC of the display unit 110 by accessing the register in the timing controller IC 200.

The status information that can be acquired by the timing controller IC200 will be described.
(1) Transmission error of main channel 152 The serial data (frame data) transmitted from the timing controller IC 200 to each source driver IC 300 includes inspection data in addition to the image data and the driver control signal as described above. be able to.

Each source driver IC300 uses the inspection data to detect a transmission error on the main channel 152. Then, the detected error is transmitted to the timing controller IC 200 as status information via the auxiliary channel 154.

(2) Abnormality of peripheral circuits other than the source driver IC 300 In addition to the source driver IC 300, a gate driver IC 114, a display panel 112, a PMIC 120, and the like are mounted on the display unit 110. The source driver IC 300 may operate as a host device in the display unit 110, collect status information of peripheral circuits, and transmit them to the timing controller IC 200 via the auxiliary channel 154.

The above is the configuration of the display system 100. According to the display system 100, the timing controller IC 200 is provided by adding a bidirectional serial type auxiliary channel 154 to the panel interface 150 between the timing controller IC 200 and the panel driver 300 in addition to the main channel 152 for images. , The detailed state of the panel driver 300 can be acquired.

The source driver IC 300 may acquire information on peripheral circuits such as the PMIC 120 in response to a request from the timing controller IC 200, and may transmit the acquired result to the timing controller IC 200.

In the second embodiment, the timing controller IC 200 issues a request command RQ to acquire the status information of the peripheral circuit (for example, PMIC 120) to the source driver IC 300 via the auxiliary channel 154.

The source driver IC 300 acquires the status information of the peripheral circuit in response to the request command RQ, and transmits the reply command RPLY including the status information to the timing controller IC 200.

More specifically, during the source driver IC300 and PMIC120, the source driver IC300 master, are connected through the ^{I 2} C interface 126 to slave the PMIC120, source driver IC300 is capable access registers of PMIC120 ..

The source driver IC300 is in response to a request command from the timing controller IC200, reads the status information stored in the register of PMIC120 via the ^{I 2} C interface 126, a reply command containing the status information to the timing controller IC200 Send.

The above is the configuration of the display system 100A.

(Configuration of timing controller IC)
Subsequently, the configuration of the timing controller IC200 will be described. FIG. 6 is a block diagram of the timing controller IC200 according to the embodiment. A plurality of (two in this embodiment) source driver ICs 300 can be connected to the timing controller IC200. The two source drivers 300 may drive one common panel or two panels.

The timing controller IC 200 includes an image input interface circuit 202, an MPU interface circuit 204, a register 206, an AUX interface circuit 208, a signal processing unit 210, a plurality of serializers 220, and a plurality of drivers (transmitters) 230. The serializer 220, the transmitter 230 and the AUX interface circuit 208 together with the main channel 152 and the auxiliary channel 154 form a part of the panel interface 150.

The image input interface circuit 202 receives image data IMG from the graphic controller 132 together with control signals such as pixel clock CLK, vertical synchronization signal Vsync, horizontal synchronization signal Hsync, and data enable signal DE. Known techniques can be used for the type of interface between the image input interface circuit 202 and the graphic controller 132. For example, LVDS (Low Voltage Differential Signaling) is used as the physical layer.

The signal processing unit 210 generates a driver control signal CNT for controlling the source driver IC 300 and the gate driver IC 114 based on the image data IMG. The processing of the signal processing unit 210 is the same as the processing of the conventional timing controller.

The plurality of serializers 220 and the plurality of transmitters 230 are provided corresponding to the plurality of source driver ICs 300. Each serializer 220 converts the pixel value of the region of the image data IMG to be transmitted to the corresponding source driver IC 300 and the frame data including the driver control signal CNT into serial data. The conversion to serial data is not particularly limited, but for example, 8b10b encoding or 9b10b encoding proposed by the applicant in Japanese Patent Application No. 2019-066764 can be adopted.

The serializer 220 also adds inspection data to the frame data in order to detect a transmission error on the main channel 152.

The transmitter (also referred to as a driver) 230 differentially serially transmits the output of the corresponding serializer 220 to the corresponding source driver IC 300. The configuration of the transmitter 230 is not particularly limited, but for example, mini-LVDS, RSDS (Reduced Swing Differential Signaling), or the like can be adopted. The transmitter 230 and the corresponding source driver IC 300 may be connected by a plurality of lanes, and the number of lanes may be determined according to the size of the image data to be transmitted.

The AUX interface circuit 208 is connected to a plurality of source driver ICs 300 via the auxiliary channel 154. The AUX interface circuit 208 operates as a master, and the plurality of source driver ICs 300 operate as slaves.

When a plurality of source driver ICs 300 are connected to the timing controller IC200, a multi-drop format may be adopted for the auxiliary channel 154. The AUX interface circuit 208 outputs the device ID of the access destination source driver IC300. Then, when the acknowledgement from the access destination source driver IC 300 is received, a request command is issued, a reply command from the source driver IC 300 is received, and the status information included in the reply command is stored in the register 206.

MPU interface circuit 204, for example, ^{I 2} C interface is connected to the microcontroller 134. The status information collected from the display unit 110 (source driver IC 300) to the timing controller IC 200 is stored in the register 206 of the timing controller IC 200. The microcontroller 134 can obtain the status information of the display unit 110 by accessing the register 206 via the MPU interface circuit 204.

The above is the configuration of the timing controller IC200.

(Configuration of source driver IC)
FIG. 7 is a block diagram of the source driver IC 300 according to the embodiment. The source driver IC 300 includes a receiver 310, a deserializer 320, a drive unit 330, an AUX interface circuit 340, a register 350, a logic circuit 360, and a peripheral interface circuit 370. The receiver 310 receives a differential serial signal including a part of the image data IMG and the driver control signal CNT from the timing controller IC 200. The deserializer 320 converts (deserializes) the differential serial signal received by the receiver 310 into parallel data.

The drive unit 330 is connected to a plurality of source line SLs of the display panel 112, and applies a drive signal according to the pixel value to each source line SL according to the output of the deserializer 320.

Further, the logic circuit 360 extracts a control signal for the gate driver IC 302 from the frame data received by the deserializer 320, and controls the gate driver IC 302 via the level shifter 122.

Further, the logic circuit 360 monitors the PMIC_EN signal included in the frame data received by the deserializer 320, and generates a PWR_STB signal for the PMIC 120.

The deserializer 320 performs an error check process, detects the presence or absence of a transmission error on the main channel 152, and writes the result to the register 350.

The AUX interface circuit 340 is connected to the AUX interface circuit 208 of the timing controller IC200 via the auxiliary channel 154. When the AUX interface circuit 340 receives a read instruction from the AUX interface circuit 208, the AUX interface circuit 340 transmits the value of the specified address of the register 350 to the AUX interface circuit 208.

When the AUX interface circuit 340 receives a request command from the timing controller IC 200, the logic circuit 360 accesses the PMIC 120 by using the peripheral interface circuit 370 and reads out the status information of the PMIC 120. Then, the logic circuit 360 transmits a reply command including the read status information to the timing controller IC 200 via the AUX interface circuit 208. The above is the configuration of the source driver IC300.

(Embodiment 3)
FIG. 8 is a block diagram of the display system 100B according to the third embodiment. The display system 100B includes a plurality of N (N = 3 in this example) display units 110_1 to 110_N. Each display unit 110 includes a display panel 112, a gate driver 114, a source driver IC 300, and other peripheral circuits (PMIC 120, etc.).

The timing controller IC200B is configured to be able to control a plurality of N display units 110_1 to 110_3. The timing controller IC 200B is an extension of the timing controller IC 200 for one panel, which has already been described, for three displays.

The panel interface 150 includes a plurality of main channels 152 and a plurality of auxiliary channels 154. A P2P (Point to Point) format is adopted for the main channel 152, and a multi-drop format is adopted for the auxiliary channel 154.

The graphic controller 132 generates individual image data IMG1 to IMG3 to be displayed on a plurality of display panels 112_1 to 112_3. The graphic controller 132 combines a plurality of individual image data IMG1 to IMG3 to generate one composite image data IMGc. Then, the graphic controller 132 transfers the RGB value of each pixel of the composite image data IMGc from its output port to the timing controller IC200 together with control signals such as pixel clock CLK, vertical synchronization signal Vsync, horizontal synchronization signal Hsync, and data enable signal DE. And send.

FIG. 9 is a diagram illustrating composite image data IMGc. In this example, the plurality of individual image data IMG1 to IMG3 are connected in the horizontal direction. The horizontal resolution x _c of the composite image data IMGc is larger than the sum _{of the horizontal resolutions x 1} , x ₂ , and x ₃ of the plurality of individual image data IMG 1 to IMG 3. Further, the vertical resolution y _c of the composite image data IMG c is larger than the maximum value (y _{1 in} _{this example) of the vertical resolutions y 1} , y ₂ , and y ₃ of the plurality of individual image data IMG 1 to IMG 3. The composite image data IMGc can include a blank area (blank period), and the blank area may be used to transmit a control signal other than the image data. In FIG. 9, a plurality of individual image data IMG1 to IMG3 are adjacent to each other without a gap, but a blank section may be inserted between them.

Return to Fig. 8. The timing controller IC 200B receives the composite image data IMGc from the graphic controller 132. The timing controller IC200B divides the composite image data IMGc into a plurality of individual image data IMG1 to IMG3.

The timing controller IC200B generates a driver control signal (timing signal) CNTi for controlling the corresponding display unit 110_i for each individual image data IMGi.

FIG. 10 is a block diagram of the timing controller IC200B according to the third embodiment.

The image input interface circuit 202 converts one composite image data IMGc, which is a combination of a plurality of individual image data IMG1 to IMG3, from the graphic controller 132 into a pixel clock CLK, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Received together with control signals such as.

MPU interface circuit 204, for example, ^{I 2} C interface is connected to the microcontroller 134. The status information collected in the timing controller IC 200 from the plurality of display units 110_1 to 110_3 is stored in the register 206 of the timing controller IC 200. The microcontroller 134 can obtain the states of the plurality of display units 110_1 to 110_3 by accessing the register 206 via the MPU interface circuit 204.

The signal processing unit 210 divides the composite image data IMGc into a plurality of individual image data IMG1 to IMG3. Then, for each of the plurality of individual image data IMG1 to IMG3, driver control signals CNT1 to CNT3 for controlling the plurality of panel drivers 114_1 to 114_3 are generated.

The signal processing unit 210 includes a division processing unit (division processing function) 212 and a timing control unit (timing control function) 214_1 to 214_3. The division processing unit 212 divides the composite image data IMGc into a plurality of individual image data IMG1 to IMG3. The method of division processing is not limited, but for example, the graphic controller 132 transmits a synchronization signal indicating a break of individual image data together with a horizontal synchronization signal and a vertical synchronization signal to the timing controller IC200, and this synchronization signal is used. Therefore, it may be divided into a plurality of individual image data IMG1 to IMG3. Alternatively, the signal processing unit 210 has information regarding the configuration (pixel layout) of the composite image data IMGc of FIG. 3, and may be divided into a plurality of individual image data IMG1 to IMG3 based on this information.

The timing control unit 214_i generates the driver control signal CNTi associated therewith based on the corresponding individual image data IMGi. The processing of the timing control unit 214_i is the same as the processing of the conventional timing controller.

The plurality of serializers 220_1 to 220_3 and the plurality of transmitters 230_1 to 230_3 are provided corresponding to the plurality of panel drivers ICs 300_1 to 300_3. The serializer 220_i converts the pixel value of the individual image data IMGc and the driver control signal CNTi into serial data.

The transmitter (also referred to as a driver) 230_i transmits the output of the corresponding serializer 220_i to the corresponding display unit 110 in a differential serial manner.

The embodiment has been described above. This embodiment is an example, and it will be understood by those skilled in the art that various modifications are possible for each of these components and combinations of each processing process, and that such modifications are also within the scope of the present invention. is there. Hereinafter, such a modification will be described.

(Modification example 1)
In the second embodiment, a request command is transmitted from the timing controller IC 200 to the source driver IC 300, and the source driver IC 300 collects the status information of the peripheral circuit by using the request command as a trigger, but this is not the case. The source driver IC 300 may collect the status information of the peripheral circuit at predetermined time intervals and hold it in an internal register. The timing controller IC 200 may access the register of the source driver IC 300 by a read command and collect the status information of the peripheral circuit.

(Modification 2)
In the above description, the peripheral circuit controlled by the timing controller IC 200 is assumed to be the PMIC 120, but this is not the case. For example, the driver circuit of the backlight of the display panel 112 may be controlled via the main channel 152 and the source driver IC 300. For example, the overall brightness of the backlight or the local brightness may be controlled. Further, the timing controller IC 200 may acquire the status information of the driver circuit of the backlight via the auxiliary channel 154.

(Modification example 3)
In FIG. 2, the gate driver IC 114 is configured as a chip different from the source driver IC 300, but this is not the case. The gate driver IC 114 may be integrated on the same chip as the source driver IC 300.

(Modification example 4)
In the embodiment, the communication protocol of the auxiliary channel 154, it is assumed the I 2 ^C compatible not limited to such. If wiring for chip selection can be added between the timing controller IC 200 and the plurality of source driver ICs 300, an SPI (Serial Peripheral Interface) compatible communication protocol may be adopted.

(Modification 5)
In the embodiment, the second control signal for the gate driver 114 is transmitted to the source driver IC 300 via the main channel 152, and the source driver IC 300 controls the gate driver 114. A dedicated channel for transmitting the second control signal CNTv may be added.

(Use)
Finally, the use of the display system 100 will be described. FIG. 11 is a diagram showing an interior of an automobile 500 equipped with a display system 100. The automobile 500 includes a cluster panel 502, a center information display 504, an electronic rearview mirror 506, side mirrors 508L, 508R, and the like. According to the display system 100 according to the embodiment, these plurality of display panels can be collectively controlled by a control unit (display ECU (Electronic Control Unit) 130).

The application of the display system 100 is not limited to in-vehicle use, but can also be applied to applications that require high reliability such as industrial machines.

The embodiment merely shows the principle and application of the present invention, and the embodiment includes many modifications and arrangement changes within a range that does not deviate from the idea of the present invention defined in the claims. Is recognized.

The present invention relates to a timing controller and a display system.

100 Display system 110 Display unit 112 Display panel 114 Gate driver 120 PMIC
122 Level shifter 130 Control unit 132 Graphic controller 134 Microcontroller 150 Panel interface 152 Main channel 154 Auxiliary channel 200 Timing controller IC
202 Image input interface circuit 204 MPU interface circuit 206 Register 208 AUX interface circuit 210 Signal processing unit 220 Serializer 230 Transmitter 300 Source driver IC
302 Gate driver IC
310 Receiver 320 Deserializer 330 Drive unit 340 AUX interface circuit 350 Register 360 Logic circuit 370 Peripheral interface circuit 600 Frame data 602 Line data

Claims

A display panel, a source driver and a gate driver for driving the display panel, a display unit having peripheral circuits, and
A graphic controller that generates image data and
A timing controller that receives the image data from the graphic controller and controls the source driver via the main channel of the differential serial format.
With
The timing controller generates a first control signal for controlling the source driver, a second control signal for controlling the gate driver, and a third control signal for controlling the peripheral circuit based on the image data, and generates the main channel. The first control signal and the third control signal can be transmitted to the source driver via the above.
The source driver is a display system characterized in that the peripheral circuit can be controlled based on the third control signal.
The timing controller is configured to be capable of transmitting the second control signal to the source driver via the main channel.
The display system according to claim 1, wherein the source driver is configured to be able to control the gate driver based on the second control signal.
The timing controller is configured to be able to communicate with the source driver via a bidirectional serial auxiliary channel.
The timing controller issues a request command to the source driver to acquire the status information of the peripheral circuit.
The first or second claim, wherein the source driver acquires the status information of the peripheral circuit in response to the request command and transmits a reply command including the status information to the timing controller. Display system.
The display system according to claim 3, wherein a register access type protocol is used for the logical layer of communication via the auxiliary channel.
The source driver and the peripheral circuit is connected with I 2 C (Inter IC) interface,
The source driver in response to the request command, the I read the status information stored in the register of the peripheral circuit via 2 C interface, transmits a reply command containing the status information to the timing controller The display system according to claim 3 or 4.
The peripheral circuit is a power supply management circuit.
The display system according to any one of claims 1 to 5, wherein the third control signal instructs the start and stop of the power supply management circuit.
The display according to claim 6, wherein the source driver and the power supply management circuit are connected by a control line, and the start and stop of the power supply management circuit are controlled by using the control line. system.
An automobile comprising the display system according to any one of claims 1 to 7.
A timing controller for a display system that has a display unit.
The display unit includes a display panel, a source driver and a gate driver for driving the display panel, and peripheral circuits.
The timing controller
An interface circuit that receives image data from the graphic controller,
Based on the image data, a first control signal for controlling the source driver and a second control signal for controlling the gate driver are generated, and a third control signal for controlling the peripheral circuit is generated. The signal processing unit to generate and
A serializer that converts the image data, the first control signal, the second control signal, and the third control signal into serial data.
A differential transmitter that transmits the output of the serializer to the source driver via the main channel of the differential serial format.
A timing controller characterized by being equipped with.
Further provided with an auxiliary interface circuit capable of communicating with the source driver via a bidirectional serial auxiliary channel.
The auxiliary interface circuit issues a request command to the source driver to acquire the status information of the peripheral circuit.
The timing controller according to claim 9, wherein a reply command including the status information of the peripheral circuit acquired by the source driver in response to the request command can be received by the auxiliary interface circuit.