JP2021128257A - Display device - Google Patents

Abstract

To enable a viewer to become aware of a fault when the fault detection function of display function of a display device becomes faulty, and, to this end, display an alert to the viewer or use a non-faulty healthy part to continue with display.SOLUTION: A display device 10 comprises image signal line drive circuits 61, 62 for driving the image signal line SL of a display panel 1, and power supply circuit units 1001, 1002 for supplying electric power to the display panel and the image signal line drive circuits. The display device 10 further includes fault detection circuits 2041, 2042 for detecting abnormality of the power supply circuits and monitoring circuits 2051, 2052 for monitoring a fault of the fault detection circuits.SELECTED DRAWING: Figure 3

Description

This disclosure relates to a display device, and can be suitably adopted for a display device having a function of detecting an operation abnormality.

Nowadays, display devices are used not only in applications such as TVs, PC displays, and mobile phones, but also in in-vehicle devices and industrial devices. Furthermore, in addition to conventional navigation devices as in-vehicle devices, liquid crystal displays are used in applications such as instrument panels that are instrument panels such as speedometers and warning lamps that are attached to dashboards, and back monitors that display images of the rear of the vehicle. The use of the device is expanding. Therefore, when the driver drives the vehicle, the information displayed on the mounted display device is becoming more important.

Generally, the display device includes a display panel, a circuit board, and a flexible printed circuit board (flexible printed circuit board, that is, FPC) that connects the display panel and the circuit board. The display panel includes a pixel area, a gate driver IC (hereinafter referred to as G-IC) on the vertical axis of the outer peripheral area of the pixel area, and a source driver IC (hereinafter referred to as S-IC) on the horizontal axis of the outer peripheral area of the pixel area. (Referred to as). The G-IC controls ON / OFF of a thin film transistor (hereinafter referred to as a “pixel TFT”) that drives a pixel electrode.
The circuit board includes a timing controller IC (hereinafter referred to as "TCON-IC"), a ROM for storing set values, an interface connector, a power supply circuit, and a gradation reference voltage generation circuit. In TCON, the received image data may be corrected for the image such as contrast adjustment, brightness adjustment, and gamma adjustment, and the corrected data may be output to the source driver.

Safety standards such as ISO 26262 and IEC 61508 have been established for in-vehicle devices and industrial devices that are well known as external devices for display devices, and when display devices are used in these products, safety requirements also arise for the display devices. .. For example, in a mirror substitute application of an in-vehicle device, it is necessary to avoid leaving an afterimage on the display panel that causes an accident, and as a display device, S-IC, G-IC, and TCON that drive the display panel have no problem. You need to monitor if it is working.

International Publication No. 2010/03857

Even if a part of the display function of the display device fails, the display is displayed on a black screen, or an external device connected to the display device notifies the failure and the backlight is turned off to display the black screen. In addition to the black screen display, an external device connected to the display device lights a warning light and a warning sound to notify the viewer of the display device that the failure has occurred.

Further, even if there is a display device having a failure detection function of the display function, when the failure detection function fails, there is a possibility that the display at the time of failure will continue to be displayed even if the display device fails.

In the present disclosure, when the display function of the display device fails and the failure detection function fails, a warning is displayed to the display device viewer or the failure occurs in order to make the display device viewer aware that the display device itself has a failure. The purpose is to keep displaying the parts that are not.

The display device according to the present disclosure includes a display panel, a plurality of image signal line drive units for driving the image signal lines of the display panel, and a plurality of power supply circuits for supplying power to the display panel and the image signal line drive unit. It is characterized by including a unit, a failure detection circuit for detecting a failure of the power supply circuit unit, and a monitoring circuit for monitoring the failure of the failure detection circuit.

In another aspect of the display device according to the present disclosure, the display panel, a plurality of scanning signal line driving circuits for driving the scanning signal lines of the display panel, and a plurality of generating control signals to the scanning signal line driving circuits. It is characterized by including a timing controller, a failure detection circuit for detecting a failure of the timing controller or the scanning signal line drive circuit, and a monitoring circuit for monitoring the failure of the failure detection circuit.

According to the present disclosure, when a failure occurs in the display device, the display device alone can notify the viewer of the failure. In addition, it is possible to monitor the failure of the failure detection function built into the display device.

It is the schematic of the display device which concerns on Embodiment 1. FIG. It is the schematic of the display device which adopted COF technology for the driver IC shown in FIG. It is a schematic block diagram which shows the circuit structure of the display device which concerns on Embodiment 1. FIG. FIG. 3 is a schematic view showing a configuration of a power supply circuit inside the source driver IC described in FIG. FIG. 5 is a schematic diagram showing a configuration when the power supply circuit of the master-side source driver IC described in FIG. 4 fails. This is a display example when the power supply circuit inside the master-side source driver IC of the display device shown in FIG. 3 fails. It is a modification of the display example of FIG. This is a display example when the power supply circuit inside the master-side source driver IC of the display device according to the first modification of the first embodiment fails. FIG. 5 is a schematic view of a timing controller and a source wiring drive unit inside a source driver IC used in the display device according to the second embodiment. It is a schematic diagram at the time of failure inside the source driver IC of FIG. This is a display example when the slave-side source driver IC of the display device according to the second embodiment fails. It is a modification of the display example of FIG. This is a display example when the slave-side source driver IC of the display device according to the second modification of the second embodiment fails. It is the schematic of the failure detection circuit built in the gate driver IC of the display device which concerns on Embodiment 3. FIG. This is a display example when a failure of one of the gate driver ICs of the display device shown in FIG. 12 is detected. This is a display example when a failure of the other gate driver IC of the display device shown in FIG. 12 is detected. It is a schematic block diagram which shows the source driver IC circuit configuration of the display device which concerns on Embodiment 4. FIG. This is a display example when an abnormality occurs in various inputs and power supplies of the display device according to the fourth embodiment. It is the schematic of the display device which concerns on the modification 3 of Embodiment 4.

Hereinafter, embodiments in the present disclosure will be described with reference to the drawings. It should be noted that the drawings are shown schematically, and for convenience of explanation, the configuration is omitted or the configuration is simplified as appropriate. Further, the interrelationship between the sizes and positions of the configurations and the like shown in different drawings is not always accurately described and can be changed as appropriate.

Further, in the description shown below, similar components are illustrated with the same reference numerals, and their names and functions are also the same. Therefore, detailed description of them may be omitted to avoid duplication.

Embodiment 1.
FIG. 1 is a schematic block diagram showing a configuration of a display device according to the present disclosure, and shows a configuration of a liquid crystal display device 10 that employs a liquid crystal display panel 1 as a typical example of the display device. As shown in FIG. 1, the display device refers to a flexible printed circuit board (Flexible printed circuit board, hereinafter referred to as "flexible printed circuit board") for connecting the liquid crystal display panel 1, the circuit board 2, the liquid crystal display panel 1, and the circuit board 2. 31 (referred to as FPC) and FPC 32. The circuit board 2 may be composed of FPC, that is, the circuit board 2, FPC31, and FPC32 may be one FPC.

In the liquid crystal display panel 1, n gate wirings (corresponding to scanning signal lines) GL and m × 3 source wirings (corresponding to image signal lines) intersect in a matrix, and pixel electrodes 8 are formed at the intersections. And, in order to drive it, pixel TFTs 9 in which the drain electrode is connected to the pixel electrode 8 are arranged vertically n and horizontally m × 3 (for R, G, B) (here, one set as a representative). Only the pixel electrode and TFT are shown).

Further, it drives G-IC51 and G-IC52, which are connected to n gate wiring GLs connected to the gate electrode of the pixel TFT 9, and m × 3 source wiring SL connected to the source electrode of the pixel TFT 9. The S-IC61 and the S-IC62 are arranged around the pixel area 4 of the liquid crystal display panel 1. Further, as shown in FIG. 1, the G-IC 51 and the G-IC 52 are vertically arranged in the outer peripheral region of the pixel region 4, and the S-IC 61 and the S-IC 62 are arranged in the lateral direction of the outer peripheral region of the pixel region 4. Have been placed. Further, the S-IC is generally referred to as an image signal line drive circuit, and the G-IC is generally referred to as a scanning signal line drive circuit.

The S-IC61 and S-IC62 are ICs that integrate a source wiring drive function and a timing controller (hereinafter referred to as "TCON") function. The S-IC61 and S-IC62 also have a built-in power supply circuit and memory, and both are the same IC having the same function. The G-IC 51 and the G-IC 52 control ON / OFF of the pixel TFT 9.

The FPC 31 and FPC 32 are mounted at positions corresponding to the S-IC 61 and the S-IC 62, and connect the liquid crystal display panel 1 and the circuit board 2.

The circuit board 2 includes an interface connector 7 for inputting various signals and power supplies from an external device. In addition to the interface connector 7, electronic components such as capacitors, coils, transistors, and diodes (not shown) are mounted on the circuit board 2. The circuit board 2 receives various signals such as video signals V-SIGNAL and timing signals and power supplies from the interface connector 7 from the connected external device, and via the FPC31 and the FPC32, the circuit board 2 receives the S-IC61 and S- Connect the signal to the IC 62. Further, the signals output from the S-IC61 and the S-IC62 are output to the external device connected to the interface connector 7.

In FIG. 1, two FPC 31s and FPC 32s are mounted in parallel, and each of them connects the liquid crystal display panel 1 and the circuit board 2.

The number of S-ICs, the number of FPCs, and the number of G-ICs are not limited to those exemplified in FIG. For example, there may be a configuration in which there are four S-ICs, the circuit board and the S-ICs are connected by four FPCs, and there are three G-ICs.

Further, as shown in FIG. 2, the S-IC61, S-IC62, G-IC51 and G-IC52 may be arranged on the FPC by adopting the COF (Chip on Film) technology. The S-IC61 is arranged on the FPC31, the S-IC62 is arranged on the FPC32, the G-IC51 is arranged on the FPC33, and the G-IC52 is arranged on the FPC34. The FPC 33 and the FPC 34 are connected to the circuit board 23. On the circuit board 23, there is an interface connector 73 with the outside.

FIG. 3 is a schematic block diagram showing a circuit configuration of the display device illustrated in FIG. The circuit diagram shown in FIG. 3 is just an example, and the numbers of S-IC, FPC, and G-IC may be different. As illustrated in FIG. 3, the power supply circuit unit 1001 and the power supply circuit unit 1002 are built in the S-IC61 and the S-IC62, respectively, and the power supply used inside and outside the S-IC61 and the S-IC62 (common power supply). VCOM, analog reference power supply VSD, gradation power supply VREF) is generated. The common power supply VCOM and the analog reference power supply VSD are connected to the S-IC61 and S-IC62 again via the circuit board 2. The common power supply VCOM is used as a common power supply for the counter electrode of the liquid crystal display panel 1. The analog reference power supply VSD is a voltage for the source wiring drive unit 1011 and the source wiring drive unit 1012 to use as an output drive power supply. The gradation power supply VREF is a voltage referred to when converting video data from a digital voltage to an analog voltage, and has a plurality of voltage levels.

Although only one type of analog reference power supply VSD is shown in FIG. 3, two types of positive electrode and negative electrode may be generated.

Further, the power supply circuit unit 1001 generates a gade drive power supply VGH / VEE which is a power supply for the G-IC 51 and the G-IC 52. The gade drive power supply has a positive voltage VGH and a negative voltage VEE. The positive voltage VGH is a voltage indicating a high level voltage when the pixel TFT 9 is in the ON state. Further, the negative voltage VEE is a voltage indicating a Low level voltage when the pixel TFT 9 is in the OFF state.

Further, in FIG. 3, the power supply circuit unit is shown only in the S-IC61 and S-IC62, but components necessary for power generation such as a coil and a capacitor may be provided on the circuit board 2.

Further, in FIG. 3, the gade drive power supply VGH / VEE is generated only by the power supply circuit unit 1001 in the S-IC61 and supplied to the G-IC51 and the G-IC52, but the power supply circuit unit 1002 in the S-IC62. May be supplied from. Further, it may be supplied to the G-IC 51 and the G-IC 52 via an FPC different from the circuit board 2.

The video signal V-SIGNAL is input to TCON1021 and TCON1022. The same video signal V-SIGNAL is input to TCON1021 and TCON1022. TCON1021 and TCON1022 output the horizontal start pulse STH to the source wiring drive unit 1011 and the source wiring drive unit 1012, respectively. Further, the TCON 1021 outputs a vertical start pulse STV signal (hereinafter, abbreviated as “STV signal”) to the G-IC 51. In this example, since the S-IC61 operates in the master mode and the S-IC62 operates in the slave mode, the STV signal is output from the TCON 1021 in the master S-IC61 to the G-IC51, and the G-IC51 is cascaded. It is connected to G-IC52. Further, the control signal CONT may be input to TCON1021 and TCON1022 to switch the format of the SCAN direction and the video signal V-DATA.

Further, the TCON 1021 outputs a shift clock signal (CLKV) of the G-IC 51 and the G-IC 52, an output control signal (Output Enable, OE) signal, and a vertical scan switching logic signal (UD).

Further, TCON1021 and TCON1022 are synchronized with the synchronization signal SYNC, and in addition to the video data, the horizontal scan switching logic signal (LR), the display panel applied polarity switching signal (POL), the internal latch of the source driver function, and , A signal (LP) for controlling the output timing is output to the source wiring drive unit 1011 and the source wiring drive unit 1012, respectively.

The synchronization signal SYNC between S-IC61 and S-IC62 is, for example, a signal for operating synchronously between the source wiring drive unit 1011 and the source wiring drive unit 1012, and is HSYNC, VSYNC, polarity reversal control POL, and synchronous CLK. May include. The synchronization signal SYNC for timing the output to the liquid crystal display panel 1 between the S-IC61 and the S-IC62 passes through the FPC31, the FPC32, and the circuit board 2, but may be directly connected on the liquid crystal display panel 1. ..

Further, the S-IC61 and S-IC62 have a function of detecting abnormalities of various signals and power supplies and failures of each circuit, and detects that various signals, various power supplies and each circuit are not operating normally. , Abnormality detection signal / ALERT_a, and abnormality detection signal / ALERT_b are output. Here, the abnormality detection signal / ALERT_a notifies the external device connected to the display device of the abnormality or failure of the S-IC62, and the abnormality detection signal / ALERT_b is connected to the display device of the abnormality or failure of the S-IC61. It is a signal to be notified to an external device, and thereafter, both signals show examples of negative logic signals (normal "High" level, abnormal "Low" level). However, the abnormality detection signal may change depending on the display device and the system, and is not limited to this. The abnormality detection signal / ALERT_a and the abnormality detection signal / ALERT_b may be output from the interface connector 7 as one signal in the circuit on the circuit board 2.

Here, the meaning of the above-mentioned "failure" is "a situation that hinders things from being done. An obstacle, a touch", and is not limited to a damaged state. For example, "failure" may include temporary malfunction due to latch-up of circuit parts due to discharge of static electricity. Hereinafter, the word "failure" is used in this sense.

FIG. 4 is a schematic view for explaining in detail the configurations of the power supply circuit unit 1001 and the power supply circuit unit 1002 in the display devices illustrated in FIGS. 1 and 3. Hereinafter, the configuration of the power supply circuit unit shown in FIG. 4 will be described in detail.

In FIG. 4, the power supply circuit unit 1001 in the S-IC61 on the master side controls the common power supply circuit unit 2001 that supplies the common power supply VCOM to the liquid crystal display panel 1 and the analog reference power supply generation circuit 206 that is the source of the gradation voltage. Analog reference power supply control circuit 2011, gradation power supply circuit 2021 that outputs gradation voltage, gate wiring drive power supply circuit 2031 that outputs power supply that drives the gate wiring of the liquid crystal display panel 1, and detects abnormalities in each power supply output. It is composed of a failure detection circuit 2041 and a monitoring circuit 2051 that monitors the operation of the failure detection circuit 2041. Similarly, the power supply circuit unit 1002 in the S-IC62 on the slave side also has a common power supply circuit unit 2002, an analog reference power supply control circuit 2012, a gradation power supply circuit 2022, a gate wiring drive power supply circuit 2032, a failure detection circuit 2042, and a monitoring circuit. It is composed of 2052. The signal line shown by the broken line in FIG. 4 indicates that the signal is in an inactive state.

The common power supply VCOM is output from the common power supply circuit 2001 and is supplied to the liquid crystal display panel 1 via the FPC31, FPC32, and circuit board 2, and the failure detection circuit 2042 in the power supply circuit unit 1002 in the slave side S-IC62. Detects an abnormality in the common power supply VCOM.

Next, FIG. 5 shows a schematic diagram showing a configuration when the power supply circuit portion of the S-IC61 on the master side fails. As shown in FIG. 5, when the failure detection circuit 2042 on the slave side detects an abnormality in the common power supply VCOM, the pause signal OFF output from the failure detection circuit 2042 shown by the broken line in FIG. 4 is activated (FIG. 5). (Indicated by a solid line in 5), as a result, the operation of the S-IC61 is stopped, the S-IC62 is switched from the slave side to the master side, and the common power supply VCOM is switched to output from the common power supply circuit 2002. In addition, when the S-IC 62 is switched from the slave side to the master side, the output of the control signal to the G-IC 51 and the G-IC 52 (not shown) is also switched from the S-IC 61 to the S-IC 62. At that time, the output of the wiring shared with the S-IC62 that switches to the master at the output of the S-IC61 (not shown) is switched to high impedance.

The analog reference power supply VSD is output from the analog reference power supply generation circuit 206 controlled by the analog reference power supply control circuit 2011, is supplied to the S-IC61 and S-IC62, and detects a failure in the power supply circuit unit 1002 on the slave side. The circuit 2042 detects an abnormality in the analog reference power supply VSD. As shown in FIG. 5, when an abnormality of the analog reference power supply VSD is detected, the operation of the S-IC61 is stopped, the S-IC62 is switched from the slave side to the master side, and the analog reference power supply control circuit 2012 uses the analog reference power supply. The generation circuit 206 is controlled to generate an analog reference power supply VSD. Even if the control is switched to the analog reference power supply control circuit 2012, if the failure detection circuit 2042 detects an abnormality in the analog reference power supply VSD, the analog reference power supply generation circuit 206 has failed, so the S-IC 62 also stops.

The gradation power supply VREF is output by the gradation power supply circuit 2021 and supplied to the S-IC61 and S-IC62, and an abnormality of the gradation power supply VREF is detected by the failure detection circuit 2042 in the power supply circuit unit 1002 on the slave side. do. As shown in FIG. 5, when an abnormality of the gradation power supply VREF is detected, the S-IC62 is switched from the slave side to the master side, the operation of the S-IC61 is stopped, and the gradation power supply VREF is the gradation power supply circuit 2022. Switch to output from.

The power supply for driving the gate wiring is output by the power supply circuit 2031 for driving the gate wiring and supplied to the G-IC 51 and the G-IC 52 via the FPC 31 and the circuit board 2. The failure detection circuit 2042 connected to the wiring connected to the FPC 32 and the circuit board 2 detects an abnormality in the power supply circuit for driving the gate wiring. As shown in FIG. 5, when an abnormality in the gate wiring drive power supply is detected, the S-IC62 is switched from the slave side to the master side, the operation of the S-IC61 is stopped by turning off the pause signal, and the gate wiring drive power supply is stopped. Switches to output from the gate wiring drive power supply circuit 2032.

Further, the failure detection circuit 2042 that detects the abnormality of each power supply notifies the external device connected by the abnormality detection signal / ALERT_b of the abnormality or the failure of the S-IC61, and also detects the failure of the S-IC61 as shown in FIG. The display area controlled on the side is set as a non-display area, and only the display area controlled on the S-IC62 side is displayed. As a method of the non-display area, the power of the S-IC that controls the non-display area is turned off (at this time, the output of the S-IC is high impedance), the backlight of the non-display area is turned off, and the like.

The content to be displayed in the display area controlled by the S-IC62 side is arbitrary, and is important among the display that notifies the viewer of the display device of a failure or abnormality of the display device and the content displayed on the display device. Is displayed, and the resolution is automatically adjusted according to the abnormality detection signal output from the display device. When adjusting the resolution, the slave side S-IC62 holds the resolution information at the time of the master side S-IC61 failure in the ROM in the S-IC in advance, and switches the master side S-IC61 at the time of failure or connects to the display device. It is conceivable that the external device rewrites the ROM using serial communication and adjusts the resolution of the video signal V-SIGNAL itself transmitted from the external device according to the abnormality detection signal notified to the external device.

For example, as shown in FIG. 7A, only the display area connected to S-IC62 and G-IC52 is set as the effective area, or as shown in FIG. 7B, S-IC62 and G. -Only the display area connected to the IC 51 may be used as the effective area.

Further, the full screen may be continuously displayed only when the failure or abnormality of the S-IC 61 does not affect other circuits in the display device.

The monitoring circuit 2051 and the monitoring circuit 2052 monitor the abnormality or failure of the failure detection circuit 2041 and the failure detection circuit 2042. When the failure detection circuit 2041 determines that the failure detection circuit 2041 is abnormal or faulty, the monitoring circuit 2051 notifies the external device connected by the abnormality detection signal / ALERT_b of the abnormality or failure of the S-IC61 via the failure detection circuit 2052. When the failure detection circuit 2042 determines that the failure detection circuit 2042 is abnormal or faulty, the monitoring circuit 2052 notifies the external device connected by the abnormality detection signal / ALERT_a of the abnormality or failure of the S-IC 62 via the failure detection circuit 2051.

As a simple monitoring circuit configuration, the failure detection circuit and the monitoring circuit are composed only of circuits that operate with the power supply (here, VDD / VSS) that is directly input from the external device, and the display device operates under the control of the external device. A method is adopted in which the monitoring circuit detects / determines whether the failure detection circuit outputs an abnormality determination due to a delay in the rise of the power supply voltage of the power supply circuit unit for a certain period of time at the start. Since the output voltages VSD, VGH, and VEE of the power supply circuit section are generated from the input voltage VDD, the rise is always delayed for a certain period of time as compared with the rise of VDD. If the failure detection circuit is normal during the delay period, it will be detected as a failure of the power supply circuit section. This delay period is measured by the monitoring circuit, and if it is within a certain range, the failure detection circuit is normal, and if the failure detection period is less than or equal to a predetermined period, it can be determined that the failure detection circuit has failed.

As another monitoring method, there is a method of confirming the operation of the failure detection circuit at the start of operation of the display device. Since the S-ICs 61 and 62 are TCONs and S-ICs with a built-in power supply circuit, when the display device is started, the power supply voltage that the failure detection circuit determines to be abnormal by the control of the TCON before starting the normal display is determined from the power supply circuit section. Temporarily output to the failure detection circuit, and check with each other's monitoring circuits whether the failure detection circuit normally determines that it is abnormal and outputs an abnormality. If both monitoring circuits output abnormally, it is possible to adopt a mechanism that starts normal display assuming that the failure detection circuit operates normally.

As yet another method, when the display device is started, the abnormality detection signal / ALERT_a and / ALERT_b signals are set to "Low", and all the failure detection circuits are operated so that the circuit operation is normal. After confirmation, a method is also conceivable in which the abnormality detection signal / ALERT_a and / ALERT_b are set to "High" to enable transmission of an image from an external device.

As another means for constant monitoring, although not shown, the failure detection circuit 2041 and the failure detection circuit 2042 acquire the power supply voltage, convert the voltage value into A / D, and connect the external device via a serial signal. It is conceivable to make it readable and compare the voltage value with the abnormality detection signal to periodically check whether the failure detection circuit is operating normally.

<Modification example 1>
Further, as shown in FIG. 8, the G-IC53 and the G-IC54 are arranged on the liquid crystal display panel 1, and the G-IC51 and the G-IC53, and the G-IC52 and the G-IC54 share the same gate wiring to switch the display area. At this time, the power supply for driving the gate wiring and the output control signal OE of the G-IC may be switched, the G-IC51 and the G-IC52 to be controlled may be turned off, and the G-IC53 and the G-IC54 may be switched. The gate wiring outputs of the G-IC 51 and G-IC 52 that are turned off at this time have high impedance.

Although the failure detection circuit 2041 and the failure detection circuit 2042 are shown in FIGS. 4 and 5 as if each power supply is detected by a single circuit, they may be independent as the failure detection circuit of each power supply. .. Further, although the failure detection circuit 2041 and the failure detection circuit 2042 are shown in the power supply circuit unit 1001 and the power supply circuit unit 1002, they are not necessarily arranged in the power supply circuit unit.

In FIG. 4, the analog reference power supply control circuit 2011 on the master side controls the analog reference power supply generation circuit 206, but the analog reference power supply control circuit 2012 on the slave side may control the analog reference power supply generation circuit 206. FIG. 4 shows an example in which only the positive electrode power supply is used. The analog reference power supply generation circuit 206 has both polarities, and the analog reference power supply control circuit 2011 on the master side has the analog reference power supply control circuit 2012 on the positive side and the slave side. Separated from the negative side, the abnormality of the analog reference power supply VSD is detected by the failure detection circuit 2042 on the positive side and the failure detection circuit 2041 on the negative side, respectively. Alternatively, positive / negative control and failure detection may be reversed on the master side and the slave side.

Although the signals between S-IC61 and S-IC62 are wired on the liquid crystal display panel 1 in FIGS. 4 and 5, communication may be performed via the FPC 31, FPC 32, and the circuit board 2.

Embodiment 2.
FIG. 9 is a diagram schematically illustrating the configuration of the TCON, the source wiring drive unit, and the G-IC in the S-IC in the display devices illustrated in FIGS. 1 and 3. In addition to TCON1021, TCON1022, source wiring drive unit 1011 and source wiring drive unit 1012, STH signal and LP, LR, POL signal, synchronization signal SYNC, CLKV signal, OE signal, and UD signal output abnormality output by TCON1021 and TCON1022. It is composed of a failure detection circuit 3001 for detecting the above, a failure detection circuit 3002, a monitoring circuit 3011 for monitoring an abnormality in the failure detection circuit, and a monitoring circuit 3012. The signal line shown by the broken line in FIG. 9 indicates that the signal is in an inactive state.

<Case 1>
As shown in FIG. 10, when the failure detection circuit 3001 detects an abnormality in the STH and LP / LR / POL signals output from the TCON 1021 to the source wiring drive unit 1011 and a failure signal TRBL of the source wiring drive unit 1011, S- The S-IC62 is switched from the slave to the master by the switching signal SLCT between the IC61 and the S-IC62, the pause signal OFF is transmitted from the failure detection circuit 3002 (the pause signal OFF is activated), and the operation of the S-IC61 is stopped. , The abnormality detection signal / ALERT_b notifies the external device connected to the display device of the abnormality or failure of the S-IC61. At that time, the TCON 1021 of the S-IC61 stops operating, and the output of the wiring shared with the S-IC62 that switches to the master (CLKV / OE / UD signal and STV signal) becomes high impedance at the output of the S-IC61. Switch.

<Case 2>
On the other hand, when the failure detection circuit 3002 detects an abnormality in the STH and LP / LR / POL signals output from the TCON 1022 in the S-IC 62 to the source wiring drive unit 1012, and a failure signal TRBL in the source wiring drive unit 1012, The abnormality or failure of the S-IC 62 is notified to the S-IC 61 via the switching signal SLCT between the S-IC 61 and the S-IC 62, and the failure detection circuit 3001 in the S-IC 61 is sent to the failure detection circuit 3002 in the S-IC 62. The pause signal OFF is transmitted (the pause signal OFF is activated), and the operation of the S-IC 62 is stopped. Further, the failure detection circuit 3001 in the S-IC61 notifies the external device connected to the display device of the abnormality or failure of the S-IC62 by the abnormality detection signal / ALERT_a.

If the abnormality detection signal / ALERT_b is a signal for notifying the abnormality or failure of the S-IC62, the abnormality detection signal / ALERT_b may be transmitted to the connected external device without going through the S-IC61.

<Case 3>
Further, when the failure detection circuit 3002 detects an abnormality in the synchronization signal SYNC input from the TCON 1021 of the S-IC 61 to the S-IC 62, the failure detection circuit 3002 switches the S-IC 62 from the slave to the master by the switching signal SLCT. A pause signal OFF is transmitted to the S-IC61 (to the failure detection circuit 3001) to stop the operation of the S-IC61, the TCON1021 stops the operation, and the S- is sent to the external device connected to the display device by the abnormality detection signal / ALERT_b. Notify the abnormality or failure of IC61.

<Case 4>
Further, the CLKV / OE / UD signals and STV signals supplied from the S-IC61 to the G-IC51 and the G-IC52 are connected to the failure detection circuit 3002 in the slave side S-IC62 via the FPC31, the FPC32, and the circuit board 2. Then, the failure detection circuit 3002 detects an abnormality in the CLKV / OE / UD signal and the STV signal. When an abnormality is detected by the failure detection circuit 3002, the switching signal SLCT switches the S-IC62 from the slave to the master, and the failure detection circuit 3002 transmits a pause signal OFF (to the failure detection circuit 3001) to the S-IC61. -The operation of the IC61 is stopped, the operation of the TCON 1021 is stopped, and the CLKV / OE / UD signal and the STV signal are supplied from the TCON 1022 of the S-IC 62 to the G-IC 51 and the G-IC 52.

<Display area when failure is detected>
When the failure detection circuit 3001 detects an abnormality in the master side S-IC61 and notifies the external device connected to the display device by the abnormality detection signal / ALERT_b via the failure detection circuit 3002 (the above <case). 1>) and when the failure detection circuit 3002 detects an abnormality in the master side S-IC61 and notifies the external device connected to the display device of the failure of the S-IC61 by the abnormality detection signal / ALERT_b (above <Case 3). >, <Case 4>), the display area controlled by the S-IC61 side where the failure was detected as shown in FIG. 6 is set as a non-display area, and only the display area controlled by the S-IC62 side is displayed.

Similarly, on the slave side S-IC62, the failure detection circuit 3002 detects an abnormality in the STH and LP / LR / POL signals output from the TCON 1022 to the source wiring drive unit 1012, and a failure signal TRBL in the source wiring drive unit 1012. At the time (<Case 2> above), the abnormality or failure of the S-IC 62 is notified to the external device connected to the display device by the abnormality detection signal / ALERT_a via the failure detection circuit 3001 in the S-IC 61, and FIG. As shown above, the display area controlled by the S-IC62 side that has detected a failure is set as a non-display area, and only the display area controlled by the S-IC61 side is displayed.

The content to be displayed in the display area is arbitrary, and a display that notifies the viewer of the display device of an abnormality or failure of the display device, an important content displayed on the display device is displayed, and an abnormality detection signal is automatically used. It is conceivable that the display is adjusted in resolution. The resolution adjustment method may be the same as that of a power supply abnormality or failure.

For example, as shown in FIG. 12 (a), only the display area connected to S-IC61 and G-IC52 is set as the effective area, or as shown in FIG. 12 (b), S-IC61 and G. -Only the display area connected to the IC 51 may be used as the effective area.

Further, the full screen may be continuously displayed only when the failure or abnormality of the S-IC 62 does not affect other circuits in the display device.

The failure detection circuit 3001 and the failure detection circuit 3002 are shown in FIGS. 9 and 10 so that each signal abnormality and the source wiring drive unit failure are detected by a single failure circuit. It may be independent as.

<Case 5>
The monitoring circuit 3011 and the monitoring circuit 3012 monitor an abnormality or a failure of the failure detection circuit 3001 and the failure detection circuit 3002. When the failure detection circuit 3001 determines that the failure detection circuit 3001 is abnormal or faulty, the monitoring circuit 3011 notifies the external device connected by the abnormality detection signal / ALERT_b of the abnormality or failure of the S-IC61 via the failure detection circuit 3002. When the failure detection circuit 3002 determines that the failure detection circuit 3002 is abnormal or faulty, the monitoring circuit 3012 notifies the external device connected by the abnormality detection signal / ALERT_a of the abnormality or failure of the S-IC 62 via the failure detection circuit 3001.

As a monitoring method, there is a method of confirming the operation of the failure detection circuit at the start of operation of the display device. Since S-ICs 61 and 62 are S-ICs with a built-in TCON, control signals (STH, LP / LR /) that the failure detection circuit should determine to be abnormal by TCON control before starting normal display when the display device is started. POL, CLKV / OE / UD, etc.) are temporarily output to the failure detection circuit, and each other's monitoring circuits check whether the failure detection circuit normally determines that it is abnormal and outputs it abnormally. If both monitoring circuits output abnormally, it is possible to adopt a mechanism that starts normal display assuming that the failure detection circuit operates normally.

In FIGS. 9 and 10, the signal between the S-IC 61 and the S-IC 62 is wired on the liquid crystal display panel 1, but communication may be performed via the FPC 31, FPC 32, and the circuit board 2.

<Modification 2>
Further, as shown in FIG. 13, G-IC53 and G-IC54 are arranged on the liquid crystal display panel 1, and the same gate wiring is shared by G-IC51 and G-IC53, and G-IC52 and G-IC54 for each display area. The power supply for driving the gate wiring, the CLKV / OE / UD signal, and the STV signal may be switched, and the control may also be switched.

Embodiment 3.
FIG. 14 is a schematic view focusing on the configurations of TCON and G-IC in the S-IC in the display devices illustrated in FIGS. 1 and 3. First, the TCON 1021 in the master side S-IC61 outputs an STV signal to the first stage G-IC51, and outputs an STV signal from the G-IC51 to the next stage G-IC52. Finally, the return of the STV signal is returned from the G-IC 52 to the S-IC 61. The G-IC 51 and the G-IC 52 have a failure detection circuit (not shown) inside, and the failure detection circuit 4001 outputs a pause signal OFF to the G-IC 51 and the G-IC 52 at the time of failure.

<Case 6>
When the failure detection circuit 4001 notifies the abnormality of the STV signal return between the G-IC 52 and the S-IC 61, and the G-IC 52 notifies the internal failure signal TRBL, the display is as shown in FIG. Therefore, the failure detection circuit 4001 transmits a stop signal OFF to the G-IC 52, a resolution switching signal RSLTN is transmitted to the TCON 1022 in the S-IC 62, and the display area controlled by the G-IC 52 is hidden. Only the display area controlled by the G-IC 51 is displayed.

<Case 7>
On the other hand, the failure detection circuit 4001 has an abnormality in the STV signal between TCON1021 and G-IC51 in the S-IC61, an abnormality in the STV signal between G-IC51 and G-IC52, and a failure signal TRBL inside the G-IC51. When the notification is sent, the operation stop signal OFF is sent to the S-IC62, and the abnormality or failure of the display device is notified to the external device to which the display device is connected by both the abnormality detection signal / ALERT_a and the abnormality detection signal / ALERT_b, and the display is stopped. ..
<Case 8>
Alternatively, although not shown in FIG. 14, the TCON 1021 has a separate route from the STV signal between the G-IC 51, a separate route for the STV signal from the TCON 1021 to the G-IC 52 is prepared, and the TCON 1021 switches the first-stage G-IC. In this case, it can be displayed as shown in FIG.

The contents to be displayed in the display areas of FIGS. 15 and 16 are arbitrary, and the display for notifying the viewer of the display device of an abnormality or failure of the display device and the important contents displayed on the display device are displayed. , A display in which the resolution is automatically adjusted by detecting an abnormality in the failure detection circuit 4001 can be considered. Although the failure detection circuit 4001 is shown in FIG. 14 as if each abnormality is detected by a single circuit, each failure detection circuit may be independent.

The monitoring circuit 4011 monitors the abnormality of the failure detection circuit 4001 and, when it is determined to be an abnormality or a failure, the abnormality of the S-IC61 or the abnormality of the S-IC61 or the external device connected to the display device by the abnormality detection signal / ALERT_b via the S-IC62. Notify the failure.

In FIG. 14, the signal between the S-IC 61 and the S-IC 62 is wired on the liquid crystal display panel 1, but communication may be performed via the FPC 31, FPC 32, and the circuit board 2.

Embodiment 4.
FIG. 17 is a diagram schematically illustrating the configuration of TCON and G-IC in the S-IC in the display devices illustrated in FIGS. 1 and 3. In the present embodiment, the failure detection circuit 5001 detects an abnormality in the input power supply VDD / VSS (GND), the control signal CONT, and the video signal V-SIGNAL input from an external device connected to the display device, and is shown in FIG. As described above, an image for notifying the viewer of the failure set in the S-IC61 and the S-IC62 is displayed. The content of the image for notifying the viewer of the failure is not limited to the content shown in FIG.

The video signal V-SIGNAL here detects whether the output and the input match, but whether the resolution and the clock set in the source line drive signal are excessive or too small.

Further, for example, if the number of data enable signals DENA, which is a part of the control signal CONT, and the total number of outputs of S-IC61 and S-IC62 (stored in the ROM of each S-IC) do not match, it is considered abnormal. to decide.

It is also possible to detect an abnormality in the input voltage VDD in the failure detection circuit 5001. It is possible to easily detect a voltage rise or a voltage drop in which the input voltage VDD is out of specification.

The monitoring circuit 5011 monitors the abnormality of the failure detection circuit 5001 and, when it is determined to be abnormal, causes the abnormality or failure of the S-IC61 to the external device connected to the display device by the abnormality detection signal / ALERT_b via the S-IC62. Notice.

In FIG. 17, the failure detection circuit 5001 is shown as if each abnormality is detected by a single circuit, but each failure detection circuit may be independent.

When an abnormality or failure of a failed circuit is detected by the monitoring circuits shown so far, it is displayed according to the abnormality or the location of the failure circuit as shown in FIGS. 6 to 8 and 11 to 13 as in other circuits. The area may be switched.

Although the failure detection circuit 5001 and the monitoring circuit 5011 of the S-IC61 on the master side are used in FIG. 17, since the S-IC62 is the same IC as the S-IC61, the failure detection circuit and the monitoring circuit of the S-IC62 May be used.

Although the signal between the S-IC 61 and the S-IC 62 is wired on the liquid crystal display panel 1 in FIG. 17, communication may be performed via the FPC 31, the FPC 32, and the circuit board 2.

<Modification example 3>
As shown in FIG. 19, the LED 601 is arranged on the FPC 33, and the LED 601 is turned on by the logical sum of the abnormality detection signal / ALERT_a and the abnormality detection signal ALERT_b. The position of the LED 601 is not limited to that shown in FIG. 19, and the LED 601 may be turned on in combination with the LED lighting when the display is switched, and the LED 601 may notify the viewer of the display device of the failure of the display device. Needless to say, the lighting for notifying the viewer of the failure of the display device is not limited to the LED.

In the above-described first and second embodiments, the case where the number of S-ICs mounted on the display panel is two has been described as an example, but it goes without saying that two or more S-ICs may be mounted. .. In this case, if the master S-IC fails, the order of the next master S-IC is determined in advance by the wiring feed order or the like. Further, the number of G-ICs mounted is not limited to two.

The gate driver IC adopted in the above-described first to fourth embodiments is an integrated circuit using a crystalline silicon transistor, but the gate wiring drive circuit used in the present disclosure includes a low-temperature polysilicon TFT and an amorphous silicon TFT. The shift register circuit that employs the above may be formed directly on the glass substrate.

Further, in the disclosure in the above-described first to fourth embodiments, in the pixel region 4 of the liquid crystal display panel 1 adopted in the display device, the pixel electrodes 8 and the pixel TFTs 9 are respectively n in the vertical direction and m × 3 in the horizontal direction (R, G, B minutes) are arranged in a matrix (color display panel), but a monochrome display panel of n vertical × m horizontal may be used.

On the other hand, in the above-mentioned disclosure according to the first to fourth embodiments, as an example of the display device, a liquid crystal display device in which a liquid crystal element is adopted as the pixel electrode 8 is described as an example of the display element. It can also be applied to a matrix display device that employs an electroluminescent (EL), an organic EL, a plasma display, an electronic paper, or the like as an electro-optical layer that converts the brightness into. Further, it can be widely applied to an electro-optical device such as an image pickup device (image sensor) that converts light intensity into an electric signal.

1 Liquid crystal display panel 4 Pixel areas 51, 52, 53, 54 G-IC (gate driver IC)
61, 62 S-IC (source driver IC)
601 LED
1001, 1002 Power supply circuit unit 1021, 1022 TCON
2001, 2002 Common power supply circuit 2011, 2012 Analog reference power supply control circuit 2021, 2022 Gradation power supply circuit 2031, 2032 Gate wiring drive power supply circuit 2041, 2042, 3001, 3002, 4001, 5001 Failure detection circuit 2051, 2052, 3011, 3012, 4011, 5011 Monitoring circuit OFF pause signal SLCT switching signal TRBL failure signal VCOM common power supply VSD analog reference power supply VGH gade drive power supply (plus voltage)
VEE Gade drive power supply (negative voltage)
VDD / VSS input power supply / ALERT_a, / ALERT_b Abnormality notification signal

The monitoring circuit 2051 and the monitoring circuit 2052 monitor the abnormality or failure of the failure detection circuit 2041 and the failure detection circuit 2042. When the failure detection circuit 2041 determines that the failure detection circuit 2041 is abnormal or faulty, the monitoring circuit 2051 notifies the external device connected by the abnormality detection signal / ALERT_b of the abnormality or failure of the S-IC61 via the failure detection circuit 2042. When the failure detection circuit 2042 determines that the failure detection circuit 2042 is abnormal or faulty, the monitoring circuit 2052 notifies the external device connected by the abnormality detection signal / ALERT_a of the abnormality or failure of the S-IC 62 via the failure detection circuit 2041.

1 Liquid crystal display panel 4 Pixel areas 51, 52, 53, 54 G-IC (gate driver IC)
61, 62 S-IC (source driver IC)
601 LED
1001, 1002 Power supply circuit unit 1021, 1022 TCON
2001, 2002 Common power supply circuit 2011, 2012 Analog reference power supply control circuit 2021, 2022 Gradation power supply circuit 2031, 2032 Gate wiring drive power supply circuit 2041, 2042, 3001, 3002, 4001, 5001 Failure detection circuit 2051, 2052, 3011, 3012, 4011, 5011 Monitoring circuit OFF pause signal SLCT switching signal TRBL failure signal VCOM common power supply VSD analog reference power supply VGH gade drive power supply (plus voltage)
VEE Gade drive power supply (negative voltage)
VDD / VSS input power supply / ALERT_a, / ALERT_b Anomaly detection signal

Claims (10)

Display panel and
A plurality of image signal line driving units for driving the image signal lines of the display panel, and
It is provided with a plurality of power supply circuit units that supply power to the display panel and the image signal line drive unit.
A failure detection circuit that detects a failure in the power supply circuit unit,
A display device including a monitoring circuit for monitoring a failure of the failure detection circuit. The display device according to claim 1, wherein the display area of the display panel is changed according to a failure detected by the failure detection circuit or the monitoring circuit. The display device according to claim 1 or 2, wherein the operation of the power supply circuit unit operating in the master mode is stopped in response to a failure detected by the failure detection circuit. Display panel and
A plurality of scanning signal line driving circuits for driving the scanning signal lines of the display panel, and
A plurality of timing controllers for generating a control signal to the scanning signal line drive circuit are provided.
A failure detection circuit that detects a failure of the timing controller or the scanning signal line drive circuit, and
A display device including a monitoring circuit for monitoring a failure of the failure detection circuit. The plurality of scanning signal line drive circuits are connected in series, the failure detection circuit detects a failure of the scanning signal line drive circuit, and the display area of the display panel connected to the failed scanning signal line drive circuit is displayed. The display device according to claim 4, wherein the display device is hidden. In a display panel that shares the scanning signal line and arranges the scanning signal line drive circuits so as to face each other.
When a failure of one of the scanning signal line drive circuits arranged opposite to each other is detected by the failure detection circuit, the other scanning signal line drive circuit arranged opposite to the failed scanning signal line drive circuit is detected. The display device according to claim 4, wherein the scanning signal line is driven by the above. The display device according to any one of claims 4 to 6, wherein the operation of the timing controller, which is operating in the master mode, is stopped in response to a failure detected by the failure detection circuit. The display device according to any one of claims 1 to 7, wherein the failure of the display device is notified to an external device as an abnormality detection signal according to the failure detected by the failure detection circuit. The display device according to any one of claims 1 to 7, wherein a failure of the failure detection circuit detected by the monitoring circuit is notified to an external device of the display device as an abnormality detection signal. The display device according to claim 8 or 9, wherein a failure display installed outside the display panel is turned on by the abnormality detection signal.

Images