KR102270600B1 - Display device - Google Patents

Abstract

A display device according to the present invention includes a display panel, a timing controller, and at least one source driver IC in order to reduce the number of transmission lines. Here, the timing controller transmits an EPI signal including an EPI clock, control data, and digital video data to the source driver IC through a shared data wire pair. In the display mode, the source driver IC restores an internal clock based on the EPI clock received through the shared data line pair, converts the digital video data into a video data voltage, and supplies it to the data lines of the display panel. In addition, the sensing data obtained from the display panel in the sensing mode is transmitted to the timing controller through the shared data line pair.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device capable of reducing signal transmission wiring.

An active matrix driving type display device displays a moving picture using a thin film transistor (hereinafter referred to as "TFT") as a switching element. The display device sequentially applies gate pulses (or scan pulses) to gate lines of a plurality of source drive integrated circuits (hereinafter, referred to as “ICs”) for supplying data voltages to data lines of a display panel and the display panel. A plurality of gate drive ICs for supplying to the IC, and a timing controller for controlling the drive ICs are provided.

The timing controller supplies digital video data, a clock for sampling digital video data, and a control signal for controlling the operation of the source drive ICs to the source drive ICs through an interface such as mini LVDS (Low Voltage Differential Signaling). . The source drive ICs convert digital video data input from the timing controller into analog data voltages and supply them to data lines.

When connecting the timing controller and source drive ICs in a multi-drop method through the mini LVDS (Low Voltage Differential Signaling) interface, R data transmission wiring, G data transmission wiring, B data transmission wiring, control wirings for controlling the output of the source drive ICs and the operation timing of the polarity change operation, and many wirings including clock transmission wirings are required. As an example of RGB data transmission in the mini-LVDS interface method, since each of RGB digital video data and clock is transmitted as a differential signal pair, the timing controller and source drive ICs are used to simultaneously transmit odd data and even data. Between them, at least 14 wires are needed for RGB data transmission. If RGB data is 10-bit data, 18 wires are needed. Accordingly, it is difficult to reduce the width of the source printed circuit board (PCB) mounted between the timing controller and the source drive ICs because many wires must be formed.

The applicant of the present application connects the timing controller and the source drive ICs in a point-to-point manner to minimize the number of wirings between the timing controller and the source drive ICs and a new signal transmission protocol (hereinafter referred to as "EPI") for stabilizing signal transmission. Interface protocol") in Korean Patent Application 10-2008-0127458 (2008-12-15), US Application 12/543,996 (2009-08-19), Korean Patent Application 10-2008-0127456 (2008-12-15) ), US Application 12/461,652 (2009-08-19), Korean Patent Application 10-2008-0132466 (2008-12-23), US Application 12/537,341 (2009-08-07), etc. have been proposed.

The EPI interface protocol satisfies the interface regulations of (1) to (3) below.

(1) Connect the transmitting end of the timing controller and the receiving end of the source drive ICs in a point-to-point manner via a pair of data lines without sharing wiring between the transmitting end of the timing controller and the receiving end of the source drive ICs.

(2) Do not connect a separate pair of clock wires between the timing controller and the source drive ICs. The timing controller transmits video data and control data along with a clock signal to the source drive ICs through a pair of data wires.

(3) Each of the source drive ICs has a built-in clock recovery circuit for CDR (Clok and Data Recovery). The timing controller transmits a clock training pattern (or preamble) signal to the source drive ICs so that the output phase and frequency of the clock recovery circuit can be locked. The clock recovery circuit built into the source drive ICs generates an internal clock when the clock training pattern signal and the clock signal input through the data line pair are input.

In the EPI interface protocol, as described above, the timing controller transmits a preamble signal to the source drive ICs before transmitting control data and video data of an input image. The clock recovery circuit of the source drive IC performs a clock training operation according to the preamble signal to stably fix the phase and frequency of the internal clock. When the phase and frequency of the internal clock are stably fixed, a data link through which the data of the input image is transmitted is established between the source drive IC and the timing controller. The timing controller starts transmitting control data and video data to the source drive ICs after the lock signal received from the last source drive IC is received.

When the output phase and frequency of the built-in clock recovery circuit of any one of the source drive ICs is unlocked, the lock signal is inverted to a low logic level, and the last source drive IC timing the inverted lock signal send to the controller. When the lock signal is inverted to a low logic level, the timing controller transmits a preamble signal to the source drive ICs to resume clock training of the source drive ICs.

Meanwhile, in the display device, in order to implement a touch UI (User Interface), touch sensors may be embedded in the pixel array in an in-cell type. When the touch sensors are embedded in the pixel array of the display device, the pixel driving period and the touch sensor driving period are time-divided in order to prevent interference between the touch sensors and the pixels. This is because the touch sensors and pixels are coupled through parasitic capacitance. The touch sensing data acquired during the touch sensor driving period is transmitted to the timing controller from the read-out IC or the source driver IC having the read-out IC built-in, and the timing controller analyzes the received touch sensing data to extract touch coordinates.

In addition, when the display device is implemented as an organic light emitting display device, deterioration compensation driving is applied based on sensing data through panel sensing. In the organic light emitting diode display, panel sensing is performed for a predetermined period excluding the pixel driving period, and deterioration of the driving TFT or organic light emitting diode (OLED) is sensed during the panel sensing period. The acquired deterioration sensing data is transmitted from the source driver IC to a timing controller, and the timing controller modulates the input digital video data to compensate for deterioration based on the received deterioration sensing data.

However, the conventional EPI interface protocol does not define a control method between a source driver IC and a timing controller for transmitting touch sensing data or deterioration sensing data as a unidirectional interface. In the conventional display device to which the EPI interface protocol is applied, additional signal wires are required in addition to the EPI signal wires to transmit sensing data.

For example, for sensing data transmission between each source driver IC (SDIC) and the timing controller (TCON), as shown in FIG. 1, there are 12 start signal transmission wires, 10 sensing data transmission wires, and one carry signal transmission wire. It should be further connected to the signal wires. In this case, as shown in FIG. 2 , the first transmitter 1a of the timing controller TCON transmits video data and control data along with a clock signal through the data wire pair 1c according to the EPI interface protocol to the first of each source drive IC. It is transmitted to the receiving unit 1b. In addition, the second transmitters 2a of the source drive ICs SDIC transmit clock and sensing data through the additional signal lines 2c as a Transistor Transistor Logic (TTL) signal irrespective of the EPI interface protocol as a timing controller TCON ) to the second receivers 2b.

Since the display device to which the conventional EPI interface protocol is applied needs to further include additional signal wires for sensing data transmission, the number of pins of each of the source driver IC (SDIC) and the timing controller (TCON) increases, and the control PCB (Printed Circuit) board) increases, and timing matching of sensing data between neighboring source driver ICs is difficult.

Accordingly, an object of the present invention is to provide a display device capable of reducing the number of transmission lines by further defining matters related to sensing data transmission in the EPI interface protocol.

In order to achieve the above object, a display device according to the present invention includes a display panel, a timing controller, and at least one source driver IC. Here, the timing controller transmits an EPI signal including an EPI clock, control data, and digital video data to the source driver IC through a shared data wire pair. In the display mode, the source driver IC restores an internal clock based on the EPI clock received through the shared data line pair, converts the digital video data into a video data voltage, and supplies it to the data lines of the display panel. In addition, the sensing data obtained from the display panel in the sensing mode is transmitted to the timing controller through the shared data line pair.

The timing controller and the source driver IC include a bi-directional EPI interface unit for exchanging the EPI signal and the sensing data through the shared data line pair.

The bidirectional EPI interface unit may include: a first transmitting end of the timing controller connected to the shared data line pair and outputting the EPI signal to the shared data line pair;

A first receiving end of the timing controller connected to the shared data wire pair to receive the sensing data from the shared data wire pair, and the shared data wire pair connected to the shared data wire pair to output the sensed data to the shared data wire pair a second transmitting end of the source driver IC; and a second receiving end of the source driver IC connected to the shared data line pair and receiving the EPI signal from the shared data line pair, wherein the first transmitting end and the second receiving end include Operation is activated under the display mode and operation is deactivated under the sensing mode, and the second transmitter and the first receiver are deactivated under the display mode and activated under the sensing mode.

A control line for transmitting a mode control signal is further provided between the timing controller and the source driver IC, wherein the timing controller transmits a mode control signal of a first logic level to the source driver IC under the display mode, and In the sensing mode, a mode control signal of a second logic level opposite to the first logic level is transmitted to the source driver IC.

In the display mode, one packet of data transmitted to each source driver IC includes 30-bit RGB digital video data, a 4-bit clock and a dummy signal, and one packet of data transmitted to the timing controller in the sensing mode includes 10-bit sensing data, 20-bit user data, and 4-bit clock and dummy signals.

In the display mode, one packet of data transmitted to each source driver IC includes 30-bit RGB digital video data, a 4-bit clock and a dummy signal, and one packet of data transmitted to the timing controller in the sensing mode includes 10-bit sensing data, 20-bit recovery sensing data, and 4-bit clock and dummy signals, and the recovery sensing data is implemented in the same way as the sensing data.

The present invention changes the EPI interface protocol to a bidirectional interface and transmits both video data and sensing data through a common signal line. Through this, the present invention can delete all conventional signal wires related to sensing data transmission, thereby greatly reducing the number of pins between the source driver IC and the timing controller and the design complexity of the control printed circuit board (PCB). In addition, the present invention can easily implement timing matching of sensing data between neighboring source driver ICs by using the EPI interface protocol for sensing data transmission.

1 and 2 are diagrams illustrating signal lines transmitting video data and signal lines transmitting sensing data separated in a display device to which an EPI interface protocol is applied;
3 is a block diagram illustrating a display device according to an embodiment of the present invention;
FIG. 4 is a view showing signal wirings between the timing controller shown in FIG. 3 and source drive ICs; FIG.
FIG. 5 is a view showing the internal configuration of the timing controller and the source drive IC shown in FIG. 3;
FIG. 6 is a waveform diagram showing an EPI protocol for signal transmission between the timing controller and the source drive ICs shown in FIG. 3;
FIG. 7 is a timing diagram showing the sensing section of FIG. 6 in detail;
8 is a diagram illustrating an example of time division driving for deterioration sensing;
9 is a diagram illustrating an example of time division driving for touch sensing.
Fig. 10 shows video data interfacing according to the present invention;
11A and 11B are diagrams illustrating sensing data interfacing according to the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

3 is a block diagram illustrating a display device according to an embodiment of the present invention.

Referring to FIG. 3 , the display device of the present invention includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting display device. (Organic Light Emitting Display, OLED) may be implemented as a flat panel display device.

A display device according to an embodiment of the present invention includes a display panel PNL, a timing controller TCON, source drive ICs SDIC#1 to SDIC#8, and gate drive ICs GDIC#1 to GDIC#4. It can be time-divisionally driven in a display mode for displaying an image and a sensing mode for sensing.

Pixels are formed in the display panel PNL. The display panel PNL includes m×n pixels arranged in a matrix form by an intersecting structure of m data lines and n gate lines. Each pixel may be one of an R sub-pixel corresponding to R digital video data, a G sub-pixel corresponding to G digital video data, and a B sub-pixel corresponding to B digital video data.

A pixel array including data lines, gate lines, and a pixel electrode is formed on the display panel PNL.

In this pixel array, touch sensors may be embedded in an in-cell type to implement a touch user interface (UI). Touch sensors may be implemented as capacitive touch sensors that sense a touch input based on a change in capacitance before and after a touch. The capacitive touch sensors may be divided into a mutual capacitive touch sensor and a self capacitive touch sensor. Mutual capacitance may be formed between two orthogonal conductor wirings, and self-capacitance may be formed along a single-layered conductor wiring formed in one direction. The touch sensing data acquired during the touch sensor driving period is transmitted to the timing controller from the read-out IC or the source driver IC having the read-out IC built-in, and the timing controller analyzes the received touch sensing data to extract touch coordinates. The touch sensor-embedded display device is described in detail in Korean Patent Application Laid-Open No. 10-2014-0077719 and Korean Patent Application Laid-Open No. 10-2014-0081470 previously filed by the applicant of the present application.

Meanwhile, when the display device is implemented as an organic light emitting display device, the pixel array of the present invention may include a light emitting element (OLED) and a driving TFT for each pixel. In such an organic light emitting display device, deterioration compensation driving is applied based on sensing data through panel sensing. In the organic light emitting diode display, panel sensing is performed for a predetermined period excluding the pixel driving period, and deterioration of the driving TFT or organic light emitting diode (OLED) may be sensed during the panel sensing period. The acquired deterioration sensing data is transmitted from the source driver IC to a timing controller, and the timing controller modulates the input digital video data to compensate for deterioration based on the received deterioration sensing data. The display device to which deterioration compensation is applied is the application number 10-2013-0134256 (2013/11/06), application number 10-2013-0141334 (2013/11/20), application number previously applied by the applicant of the present application. 10-2013-0166678 (2013/12/30), application number 10-2013-0149395 (2013/12/03), application number 10-2014-0079255 (2014/06/26), application No. 10-2014-0079587 (2014/06/27), Application No. 10-2014-0086901 (2014/07/10), Application No. 10-2014-0119357 (2014/09/05) described in detail.

The timing controller (TCON) receives external timing signals such as vertical/horizontal synchronization signals (Vsync, Hsync), external data enable signals (Data Enable, DE), and main clock (CLK) from an external host system and receives the source drive IC Timing control signals for controlling operation timings of the SDIC#1 to SDIC#8 and the gate drive ICs GDIC#1 to GDIC#4 are generated. The timing control signals are a gate timing control signal for controlling the operation timing of the gate drive ICs GDIC#1 to GDIC#4, and a gate timing control signal for controlling the operation timing of the source drive ICs SDIC#1 to SDIC#8. Includes a source timing control signal.

The timing controller TCON transmits a mode control signal of a first logic level (high logic level) to the source drive ICs SDIC#1 to SDIC#8 under the display mode, and is opposite to the first logic level under the sensing mode. The mode control signal of the second logic level (low logic level) may be transmitted to the source drive ICs SDIC#1 to SDIC#8.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP indicates a start timing at which the scan starts so that the first gate pulse is generated from the first gate drive IC GDIC#1. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The shift registers of the gate drive ICs GDIC#1 to GDIC#4 shift the gate start pulse GSP at the rising edge of the gate shift clock GSC. The gate drive ICs GDIC#1 to GDIC#4 receive the carry signal of the previous gate drive IC as a gate start pulse and start to operate. The gate output enable signal GOE controls output timing of the gate drive ICs GDIC#1 to GDIC#4. The gate timing control signal may be encoded in a control data packet and transmitted to the source drive ICs SDIC#1 to SDIC#8. The source drive ICs SDIC#1 to SDIC#8 may restore the gate timing control signal from the control data packet and transmit it to the gate drive ICs GDIC#1 to GDIC#4. When the gate timing control signal generated by the timing controller TCON is directly transmitted to the gate drive ICs GDIC#1 to GDIC#4, gate timing control information may be omitted from the control data packet.

The gate drive ICs GDIC#1 to GDIC#4 sequentially supply gate pulses synchronized with the data voltage to the gate lines in response to gate timing control signals.

The source timing control signal includes control information for controlling the operation of the source drive ICs SDIC#1 to SDIC#8. For example, the source timing control signal includes polarity control information and source output timing information. The source drive ICs SDIC#1 to SDIC#8 restore polarity control information to generate an internal polarity control signal POL to invert the polarity of the data voltage according to a logic value of the polarity control signal. The source drive ICs SDIC#1 to SDIC#8 generate an internal source output enable signal SOE by restoring source output timing information. The output timing of the data voltage output from the source drive ICs SDIC#1 to SDIC#8 is controlled according to the logic value of the internal source output enable signal SOE. The source timing control signal SOE may be encoded in a control data packet and transmitted to the source drive ICs SDIC#1 to SDIC#8.

A circuit for generating positive/negative gamma compensation voltages may be built in the source drive ICs SDIC#1 to SDIC#8. In this case, the source timing control signal transmitted to the source drive ICs SDIC#1 to SDIC#8 through the control data packet may include gamma compensation control information for controlling the gamma compensation voltage.

The source drive ICs SDIC#1 to SDIC#8 may restore the gate timing control signal from the control data packet and transmit it to the gate drive ICs GDIC#1 to GDIC#4.

The source drive ICs SDIC#1 to SDIC#8 receive a clock training pattern (or preamble) signal, a control data packet, and a video data packet from the timing controller TCON through a data line pair. The control data packet may include control information of the source timing control signal and control information of the gate timing control signal. In addition, the source drive ICs SDIC#1 to SDIC#8 receive a mode control signal from the timing controller TCON through a control line.

In the display mode according to the mode control signal, the source drive ICs SDIC#1 to SDIC#8 receive the clock training pattern signal and lock the output phase and frequency of the built-in clock recovery circuit. Subsequently, the source drive ICs SDIC#1 to SDIC#8 restore the internal clock signal by restoring the clock bit input to the bit stream through the data wire pair after the output phase and frequency of the clock recovery circuit are fixed. Subsequently, the source drive ICs SDIC#1 to SDIC#8 sample the bit stream of the control data packet according to the clock timing of the internal clock signal to restore control information received through the control data packet. Then, the source drive ICs SDIC#1 to SDIC#8 restore RGB digital video data by sampling the RGB bits of the video data packet received through the data wire pair according to the clock timing of the internal clock signal, and restore the restored RGB data. A data voltage is generated by converting RGB digital video data into a gamma compensation voltage. In addition, the source drive ICs SDIC#1 to SDIC#8 invert the polarity of the data voltage according to the internal polarity control signal POL restored from the control data packet, and the internal source output enable signal ( SOE) to output the data voltage.

Under the sensing mode according to the mode control signal, the source drive ICs SDIC#1 to SDIC#8 transmit the sensing data (touch sensing data or deterioration sensing data) obtained from the display panel PNL through the data line pair to the timing controller. (TCON). To this end, a bidirectional EPI interface protocol that shares a data wire pair is applied between the timing controller (TCON) and each source drive IC (SDIC#1 to SDIC#8).

In other words, the present invention changes the EPI interface protocol to a bidirectional interface and transmits both video data and sensing data through a common signal line. Through this, the present invention can delete all conventional signal wires related to sensing data transmission, so the number of pins between each source drive IC (SDIC#1 to SDIC#8) and the timing controller (TCON) and the design complexity of the control printed circuit board (PCB) can be greatly reduced. In addition, the present invention can easily implement timing matching of sensing data between neighboring source driver ICs by using the EPI interface protocol for sensing data transmission.

FIG. 4 shows signal lines between the timing controller TCON and the source drive ICs SDIC#1 to SDIC#8 shown in FIG. 3 .

Referring to FIG. 4 , between the timing controller (TCON) and each source drive IC (SDIC#1 to SDIC#8), a shared data wire pair 11 for a bidirectional EPI interface protocol, a mode control signal (DIS) for transmission Signal wires such as the control wire 12 and the lock check wire 13 for transmitting the lock check signal LCS are formed.

The shared data wire pair 11 serially connects the timing controller (TCON) to each source drive IC (SDIC#1 to SDIC#8) in a 1:1, that is, a point-to-point method. The timing controller TCON sequentially transmits a clock training pattern, a control data packet, and a video data packet to the source drive ICs SDIC#1 to SDIC#8 through the shared data wire pair 11 under the display mode. The control data packet may be composed of a bit stream including clock bits, control start bits, source and gate timing control information, and the like. The source and gate timing control information includes the aforementioned control information of the source timing control signal and control information of the gate timing control signal. A video data packet is a bit stream containing clock bits, internal data enable bits, RGB data bits, and the like. Each of the source drive ICs SDIC#1 to SDIC#8 restores an internal clock signal input through the shared data wire pair 11 . There is no need for wiring that transfers clock carry and RGB data between neighboring source drive ICs (SDIC#1 to SDIC#8).

The timing controller TCON transmits the clock training pattern signal to the source drive ICs SDIC#1 to SDIC#8, and an internal clock signal output from the clock recovery circuit of the source drive ICs SDIC#1 to SDIC#8. to stably fix the frequency and phase of The timing controller TCON sends a lock signal LOCK for checking whether the clock recovery circuit outputs of the source drive ICs SDIC#1 to SDIC#8 are stably fixed through the lock check wire LCS1 to the first source It can be transmitted to the drive IC (SDIC#1). The source drive ICs SDIC#1 to SDIC#8 may be connected in a cascade through a wire (dotted line in FIG. 2 ) for transmitting a lock signal. The first source drive IC (SDIC#1) receives the clock training pattern signal and when the frequency and phase of the clock recovery circuit output are fixed, the high logic lock signal (Lock) is transmitted to the second source drive IC (SDIC#2) and the second source drive IC (SDIC#2) receives the clock training pattern signal, fixes the frequency and phase of the clock recovery circuit output, and then applies a high logic lock signal (Lock) to the third source drive IC (SDIC#3) forward to After the frequency and phase of the clock recovery circuit output of all source drive ICs (SDIC#1 to SDIC#8) are fixed, when the frequency and phase of the clock recovery circuit output of the last source drive IC (SDIC#8) are fixed, the last source The drive IC (SDIC#8) transmits the high logic lock signal (Lock) to the timing controller (TCON) through the feedback lock check wire (LCS2). When the feedback input of the lock signal (Lock) is received from the last source drive IC (SDIC#8), the timing controller (TCON) transmits the bit stream of the control data packet and the video data packet to the source drive ICs (SDIC#1 to SDIC#8). ) to start sending. Accordingly, the timing controller TCON transmits the clock training pattern signal to the shared data wire pair 11 until the clock recovery circuit outputs of all the source drive ICs SDIC#1 to SDIC#8 are stably locked. The control data packet and video data packet are transmitted to the source drive ICs (SDIC#1 to SDIC#8) through start the transmission of

Each source drive IC (SDIC#1 to SDIC#8) restores the internal source output enable signal (SOE) from the control data packet received under the EPI protocol, and returns to the logic value of the internal source output enable signal (SOE). Output timing can be adjusted accordingly.

Each source drive IC (SDIC#1 to SDIC#8) transmits sensing data to the timing controller (TCON) through the shared data wire pair 11 under sensing mode.

FIG. 5 shows the internal configuration of the timing controller TCON and the source drive IC SDIC shown in FIG. 3 .

Referring to FIG. 5 , in the display mode, the timing controller TCON receives digital video data RGB of an input image from a host system through an LVDS interface or a TMDS interface. The timing controller TCON generates control data including source control data and gate control data based on an external timing signal input from a host system using an internal timing control signal generating circuit. The timing controller (TCON) rearranges the timing of the EPI clock and video data (RGB) input from the host system through the LVDS interface or the TMDS interface to match the timing of the gate driver IC of the source drive IC (SDIC), and also transmits the EPI For this purpose, by embedding an EPI clock between each video data (RGB) signal, it is converted into a difference signal pair. The timing controller TCON outputs the EPI signal including the EPI clock, control data, and digital video data to the shared data line pair 11 through the first transmitting terminal 21 . The EPI signal is sent to the source driver IC (SDIC) via a shared data wire pair 11 . The timing controller TCON transmits the mode control signal DIS to the source driver IC SDIC through the control wiring.

Under the display mode, the second receiving end 31 of the source drive IC (SDIC) is connected to the shared data wire pair 11 to receive the EPI signal from the shared data wire pair 11 . The clock recovery circuit 32 of the source drive IC (SDIC) recovers an internal clock from the received EPI clock, and the sampling circuit 33 of the source drive IC (SDIC) recovers control data and digital video data according to the recovered internal clock. Each (RGB) bit is sampled.

Under the sensing mode, the sensing unit 34 of the source drive IC (SDIC) obtains an analog sensed value from the display panel, and converts the sensed value to N bits (N is a natural number, for example, N is 10) ADC (analog-to-digital converter) is converted into sensed data through , and then output to the second transmitting terminal 35 of the source drive IC (SDIC). The second transmitting terminal 35 of the source drive IC (SDIC) is connected to the shared data line pair 11 to output sensing data to the shared data line pair 11 .

Under the sensing mode, the first receiving end 22 of the timing controller TCON is connected to the shared data line pair 11 to receive sensing data from the shared data line pair 11 . The data processing unit 23 of the timing controller TCON extracts touch coordinates by applying the sensing data input from the first receiving end 22 to a preset touch coordinate extraction algorithm, or applies a preset compensation algorithm to compensate for deterioration. A compensation value can be calculated for

In this way, the operation of the first transmitting terminal 21 of the timing controller TCON and the second receiving terminal 31 of the source driver IC (SDIC) is activated under the display mode and deactivated under the sensing mode, and the source driver IC (SDIC) The second transmitting end 35 of the and the first receiving end 22 of the timing controller (TCON) implement the EPI bidirectional interface protocol by inactivating the operation under the display mode and activating the operation under the sensing mode.

FIG. 6 is a waveform diagram illustrating an EPI protocol for signal transmission between the timing controller and the source drive ICs shown in FIG. 3 . And, FIG. 7 is a timing diagram showing the sensing section of FIG. 6 in detail.

Referring to FIG. 6 , the timing controller TCON time-divisions a display period in which a video data interface is implemented and a sensing period in which a sensing data interface is implemented by using the mode control signal DIS.

In the display period in which the mode control signal DIS is maintained at the low logic level L, the timing controller TCON sources the clock training pattern signal (or preamble signal) of a constant frequency during the first phase (Phase-I) period. When it is transmitted to the drive ICs SDIC#1 to SDIC#8 and a high logic level lock signal LOCK is input through the lock feedback signal line, the second phase (Phase-II) signal transmission is performed. Subsequently, the timing controller TCON transmits control data to the source drive ICs SDIC#1 to SDIC#8 during the second phase-II period, and when the lock signal LOCK maintains a high logic level, , transfers to the third step (Phase-III) signal transmission to transmit the video data (RGB Data) of the input image to the source drive ICs SDIC#1 to SDIC#8.

In FIG. 6 , “Tlock” is the output of the clock recovery circuit of the source drive ICs SDIC#1 to SDIC#8 after the clock training pattern signal is input to the source drive ICs SDIC#1 to SDIC#8. This is the time until the lock signal is inverted to a high logic level (H). This time (Tlock) is at least one horizontal period or more. One horizontal period is a time required to write video data to pixels arranged in one horizontal line of the display panel PNL.

In the sensing period in which the mode control signal DIS is maintained at the high logic level H, each source drive IC SDIC#1 to SDIC#8 operates for a predetermined period from the rising edge of the mode control signal DIS as shown in FIG. 7 . After the elapse of (T0), the data start signal may be output in the period T1, and then the sensing data may be sequentially output in the period T2. Each source drive IC (SDIC#1 to SDIC#8) can perform clock training during T0. In the sensing period, the timing controller (TCON) receives the data start signal, and receives a preset number (that is, the number that can be transmitted from one source driver IC (SDIC)) among the sensing data transmitted following the data start signal. It can be recognized by sensing data.

The timing controller TCON is the source when the low logic level (L) lock signal is input from the last source drive IC (SDIC#8) and the mode control signal DIS is inverted to the low logic level (L). In order to resume clock training of the drive ICs SDIC#1 to SDIC#8, the process proceeds to the first phase (Phase-I) and transmits the clock training pattern signal to the source drive ICs SDIC#1 to SDIC#8. do.

8 shows an example of time division driving for deterioration sensing. And, FIG. 9 shows an example of time division driving for touch sensing.

Deterioration sensing according to the present invention may be performed during a predetermined period of power-on as shown in FIG. 8, but is not limited thereto. The deterioration sensing of the present invention may be performed for a predetermined period (vertical blank period) during image display, and may also be performed for a predetermined period during power-off. During the sensing period, only the sensing data interface is turned on and the video data interface is turned off. Conversely, during the display period, only the video data interface is on and the sensing data interface is off.

As shown in FIG. 9 , touch sensing according to the present invention is performed during the remaining period excluding the display period in one frame period. The touch sensing of the present invention operates based on an internal data enable signal that is twice as fast as an input. During the sensing period, only the sensing data interface is turned on and the video data interface is turned off. Conversely, during the display period, only the video data interface is on and the sensing data interface is off.

10 shows video data interfacing according to the present invention. 11A and 11B show sensing data interfacing according to the present invention.

Referring to FIG. 10 , one packet of data transmitted to the source drive ICs SDIC#1 to SDIC#8 in the EPI protocol of the display period includes a plurality of data bits, clock bits allocated before and after the data bits. and dummy bits. Data bits are bits of control data or digital video data of an input image. 1 bit transmission time is 1 UI (Unit Interval) time and varies depending on the resolution of the liquid crystal display panel (PNL) or the number of data bits.

The clock bits and the dummy bits are allocated by 4 UI between the data bits of the neighboring packets, and the logical value may be allocated as “0 0 1 1 (or L L H H)”. When the number of data bits is 10 bits, one packet may include RGB data bits of 30 UIs, and clock bits and dummy bits of 4 UIs.

In order to prevent EPI protocol change as much as possible, the EPI protocol in the sensing period is determined based on the EPI protocol in the display period.

That is, as shown in FIG. 11A , one packet of data transmitted to the timing controller TCON in the sensing period may include a sensing data bit of 10 UI, a user data bit of 20 UI, and clock bits and dummy bits of 4 UI. The user data of the 20UI is a data bit stream that is pre-allocated to increase user convenience, and may correspond to a data number or the like.

In addition, 1 packet of data transmitted to the timing controller (TCON) in the sensing period as shown in FIG. 11b may include a sensing data bit of 10 UI, a sensing data bit for recovery of 20 UI, and clock bits and dummy bits of 4 UI. . Here, the sensing data bit for recovery of 20UI has substantially the same value as the sensing data of 10UI. The present invention can minimize the distortion of the sensed data generated in the transmission process through repeated transmission of the same data.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

TCON: Timing controller SDIC#1~SDIC#8: Source drive IC
GDIC#1~GDIC#4 : Gate Drive IC

Claims (6)

display panel;
a first transmitting end and a first receiving end connected to a shared transmission line, wherein the first transmitting end transmits an EPI signal including digital video data through the shared transmission line, and the first receiving end is the sensed data from the shared transmission line a timing controller to receive; and
a second transmitting end and a second receiving end connected to the shared transmission line, the second receiving end receiving the EPI signal output from the first transmitting end through the shared transmission line, and the second transmitting end receiving the EPI signal from the display panel and at least one source driver IC for transmitting the acquired sensed data to the first receiving terminal through the shared transmission line. delete The method of claim 1,
The first transmitting end and the second receiving end operate in a display mode for displaying an image based on the digital video data and are inactive in a sensing mode for acquiring the sensed data,
The second transmitter and the first receiver are inactive in the display mode and activated in the sensing mode. 4. The method of claim 3,
a control line for transmitting a mode control signal is further provided between the timing controller and the source driver IC;
The timing controller transmits the mode control signal of a first logic level to the source driver IC in the display mode, and transmits the mode control signal of a second logic level opposite to the first logic level to the source in the sensing mode A display device that transmits to a driver IC. 4. The method of claim 3,
In the display mode, one packet of the EPI signal transmitted to each source driver IC includes 30 bits of RGB digital video data and 4 bits of clock and dummy signals;
In the sensing mode, one packet of the sensed data transmitted to the timing controller includes 10-bit sensing data, 20-bit user data, and 4-bit clock and dummy signals. 4. The method of claim 3,
In the display mode, one packet of the EPI signal transmitted to each source driver IC includes 30 bits of RGB digital video data and 4 bits of clock and dummy signals;
In the sensing mode, one packet of the sensed data transmitted to the timing controller includes 10-bit sensing data, 20-bit recovery sensing data, and 4-bit clock and dummy signals;
The sensed data for recovery is the same as the sensed data.

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