KR102293371B1 - Display device - Google Patents

Abstract

A display device according to the present invention includes a first pair of wires connecting a timing controller and a plurality of source drive ICs, a second pair of wires connecting the timing controller and the source drive ICs, and a second pair of wires connecting the timing controller and the source drive ICs. a third wire pair connecting the timing controller to transmit data having a first clock embedded therein to the source drive ICs through the first wire pair, wherein the source drive ICs are analog-to-digital converter output data is transmitted to the timing controller through the second pair of wires, and the source drive ICs transmit the analog-to-digital converter clock to the timing controller through the third pair of wires.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device operating according to an EPI interface protocol.

The flat panel display device includes a liquid crystal display device (LCD), an organic light emitting diode display device (hereinafter referred to as “OLED display device”), a plasma display panel (PDP), and an electric field. and field emission displays (FEDs).

An active matrix driving type flat panel display uses a thin film transistor (hereinafter referred to as "TFT") as a switching element to display a moving picture. A display device includes a plurality of source drive ICs for supplying data voltages to data lines of a display panel, a plurality of gate drive ICs for sequentially supplying gate pulses (or scan pulses) to gate lines of the display panel, and and a timing controller or the like for controlling the drive ICs.

The timing controller supplies digital video data, a clock for sampling digital video data, and a control signal for controlling the operation of the source drive ICs to the source drive ICs through an interface such as mini LVDS (Low Voltage Differential Signaling). . The source drive ICs convert digital video data input from the timing controller into analog data voltages and supply them to data lines.

When connecting the timing controller and source drive ICs in a multi-drop method through the mini LVDS (Low Voltage Differential Signaling) interface, R data transmission wiring, G data transmission wiring, B data transmission wiring, control wirings for controlling the output of the source drive ICs and the operation timing of the polarity change operation, and many wirings including clock transmission wirings are required. As an example of RGB data transmission in the mini-LVDS interface method, since each of RGB digital video data and clock is transmitted as a differential signal pair, the timing controller and source drive ICs are used to simultaneously transmit odd data and even data. Between them, at least 14 wires are needed for RGB data transmission. If RGB data is 10-bit data, 18 wires are needed. Accordingly, it is difficult to reduce the width of the source printed circuit board (hereinafter referred to as "PCB") mounted between the timing controller and the source drive ICs because many wires must be formed.

The applicant of the present application connects the timing controller and the source drive ICs in a point-to-point manner to minimize the number of wirings between the timing controller and the source drive ICs and a new signal transmission protocol (hereinafter referred to as "EPI") for stabilizing signal transmission. Interface protocol") in Korean Patent Application 10-2008-0127458 (2008-12-15), US Application 12/543,996 (2009-08-19), Korean Patent Application 10-2008-0127456 (2008-12-15) ), US Application 12/461,652 (2009-08-19), Korean Patent Application 10-2008-0132466 (2008-12-23), US Application 12/537,341 (2009-08-07), etc. have been proposed.

The EPI interface protocol satisfies the interface regulations of (1) to (3) below.

(1) Connect the transmitting end of the timing controller and the receiving end of the source drive ICs in a point-to-point manner via a pair of data lines.

(2) Do not connect a separate pair of clock wires between the timing controller and the source drive ICs. The timing controller transmits video data and control data along with a clock signal to the source drive ICs through a pair of data wires.

(3) Each of the source drive ICs has a built-in clock recovery circuit for CDR (Clok and Data Recovery). The timing controller transmits a clock training pattern (or preamble) signal to the source drive ICs so that the output phase and frequency of the clock recovery circuit can be locked. The clock recovery circuit built into the source drive ICs generates an internal clock when the clock training pattern signal and the clock signal input through the data line pair are input.

In the EPI interface protocol, as described above, the timing controller transmits a preamble signal to the source drive ICs before transmitting control data and video data of an input image. The clock recovery circuit of the source drive IC performs a clock training (CT) operation according to the preamble signal to stably fix the phase and frequency of the internal clock. When the phase and frequency of the internal clock are stably fixed, a data link through which the data of the input image is transmitted is established between the source drive IC and the timing controller. The timing controller starts transmitting control data and video data to the source drive ICs after the lock signal received from the last source drive IC is received.

When the output phase and frequency of the built-in clock recovery circuit of any one of the source drive ICs is unlocked, the lock signal is inverted to a low logic level, and the last source drive IC timing the inverted lock signal send to the controller. When the lock signal is inverted to a low logic level, the timing controller transmits a preamble signal to the source drive ICs to resume clock training of the source drive ICs.

Pixels of an organic light emitting diode (OLED) display device include a driving TFT (Thin Film Transistor) that controls a driving current flowing through the OLED according to input image data. Device characteristics such as the threshold voltage of the OLED, the threshold voltage of the driving TFT, and the mobility of the driving TFT may vary depending on process deviation, driving time, driving environment, and the like. The change in device characteristics of these pixels degrades the image quality of the organic light emitting diode display and shortens the lifespan. Accordingly, a technology for compensating for changes in device characteristics of pixels by sensing changes in device characteristics of pixels and appropriately changing input data according to a sensing result is applied to an OLED display device.

The change in device characteristics of a pixel is converted into digital data through an analog-to-digital converter (hereinafter referred to as "ADC") and transmitted to a data compensation circuit. The ADC may be built into each of the source drive ICs, and the data compensation circuit may be built into the timing controller. Accordingly, in order to compensate for such device characteristic change, wirings for transmitting ADC data may be further provided between the timing controller and the source drive ICs.

In a conventional display device, the source drive IC (SIC) receives data from the timing controller (TCON) through the EPI line pair (DL) as shown in FIG. 1, and transmits ADC data through the ADC data line pair (SL) to the timing controller (TCON). ) is sent to To this end, the timing controller TCON and the source drive IC SIC are connected through the EPI line pair DL and also through the ADC data line pair SL.

A phase locked loop (PLL) of the timing controller (TCON) multiplies an LVDS (Low Voltage Differential Signaling) clock to generate a clock (Clock A) of the EPI interface transmission frequency, and an output clock (Clock A) of the PLL ) converts the embedded EPI data into a differential signal pair defined in the EPI interface protocol, and then supplies it to the EPI wiring pair DL through the transmitter Tx. The sampling & recovery unit of the source drive IC (SIC) generates an internal clock (Clock B) by extracting a clock from data received from the receiver (Rx) and recovering the clock. The ADC unit of the source drive IC (SIC) samples the sensing data regarding the device characteristic change input from the pixel according to the internal clock (Clock B) from the sampling & restoration unit, and sends the sampled ADC data to the ADC through the transmitter (Tx). It is supplied to the wiring pair SL. The parallel converter of the timing controller TCON samples and latches the ADC data from the receiver Rx according to the timing of the output clock (Clock A) of the PLL, then converts it into a parallel data system and supplies it to the data compensator.

The delay in the transmission section includes the EPI data delay from the timing controller (TCON) to the source drive IC (SIC) (hereinafter referred to as “delay 1”), and the ADC from the source drive IC (SIC) to the timing controller (TCON). There is a data delay (hereinafter referred to as "delay 2"). A delay deviation exists between the source drive ICs SIC having different transmission intervals with the timing controller TCON. Delay 1 and 2 are affected by the length and routing shape of the PCB (Printed Circuit Board) where the EPI wiring pair (DL) and the ADC wiring pair (SL) are formed. Delays 1 and 2 increase.

In the conventional display device, since the timing controller (TCON) receives only ADC data from the source drive IC (SIC), and samples and latches the ADC data using the output clock (Clock A) of the PLL, delay 1 of the transmission period, 2 causes a timing skew between the ADC data and the output clock (Clock A) of the PLL. If the skew increases, the ADC data timing margin becomes insufficient in a specific source drive IC (SIC) of the display device. As a result, the recognition error for ADC data increases. In order to reduce the recognition error of ADC data, it is necessary to adjust the output timing of ADC data. Since the transmission period to the timing controller (TCON) is different for each source drive IC (SIC), the ADC data output for each source drive IC (SIC) is different. There is trouble in having to adjust the timing.

Accordingly, it is an object of the present invention to provide a display device capable of improving the recognition error of ADC data without the hassle of individually adjusting the output timing of ADC data for each source drive IC.

In order to achieve the above object, a display device according to an embodiment of the present invention includes a first pair of wires connecting a timing controller and a plurality of source drive ICs, a second pair of wires connecting the timing controller and the source drive ICs; , a third pair of wires connecting the timing controller and the source drive ICs, wherein the timing controller transmits data including a first clock to the source drive ICs through the first pair of wires, The drive ICs transmit output data of the analog-to-digital converter to the timing controller through the second pair of wires, and the source drive ICs transmit the clock of the analog-to-digital converter to the timing controller through the third pair of wires .

The source drive ICs recover the first clock from the data received through the first pair of wires and divide the first clock to generate the analog-to-digital converter clock.

The timing controller receives the output data of the analog-to-digital converter and the clock of the analog-to-digital converter from the second wire pair and the third wire pair, respectively, at the same timing, and based on the clock of the analog-to-digital converter to sample and latch the output data of the analog-to-digital converter.

Each of the source drive ICs includes a clock recovery unit for recovering the first clock received through the first pair of wires, and a shift clock and data of the analog-to-digital converter by dividing the first clock from the clock recovery unit. It further includes: a divider for generating a transmission clock; and a sample & holder for sampling sensing data for a change in device characteristics input from a pixel of the display panel according to the shift clock and supplying the sample to the analog-to-digital converter.

The data transmission clock is transmitted to the timing controller through the third wire pair as the clock of the analog-to-digital converter, and output data of the analog-to-digital converter is transmitted through the second wire pair according to the data transmission clock. sent to the timing controller.

The first pair of wires is 1:1 connected between the timing controller and the source drive ICs, the second pair of wires is connected in parallel between the timing controller and the plurality of source drive ICs, and the third pair of wires is connected to the It is connected in parallel between a timing controller and the plurality of source drive ICs.

The present invention transmits the ADC clock together with the ADC data from the source drive IC to the timing controller at the same timing, and samples and latches the ADC data using the ADC clock from the timing controller. Therefore, according to the present invention, no skew occurs between ADC data and a clock sampling and latching the ADC data despite the delay time deviation along the transmission path. As a result, the present invention can effectively improve the recognition error of ADC data without the hassle of individually adjusting the output timing of ADC data for each source drive IC.

1 is a diagram schematically showing the internal configuration of a timing controller and a source drive IC of a conventional display device;
2 is a diagram schematically illustrating a topology between a timing controller and source drive ICs in a display device according to an embodiment of the present invention;
3 is a view showing that ADC data and ADC clock are simultaneously transmitted from a source drive IC to a timing controller according to the present invention;
4 is a diagram showing circuit configurations of a timing controller and a source drive IC according to an embodiment of the present invention;
5 is a diagram illustrating a data transmission delay time between a timing controller and source drive ICs;
6 is a diagram illustrating an example of a method of generating an ADC clock by dividing an EPI clock;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

2 schematically shows a topology between a timing controller and source drive ICs in a display device according to an embodiment of the present invention. 3 shows that ADC data and ADC clock are simultaneously transmitted from the source drive IC to the timing controller according to the present invention.

2 and 3, the display device of the present invention is a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic It may be implemented as a flat panel display such as an organic light emitting display (OLED).

A display device according to an embodiment of the present invention includes a display panel PNL, a timing controller TCON, source drive ICs SIC1 to SIC8 , and gate drive ICs GIC1 to GIC4 .

The display panel PNL includes a pixel array on which an input image is displayed. The pixel array includes pixels arranged in a matrix form by an intersecting structure of data lines and gate lines. Each of the pixels may include an R (red) sub-pixel, a G (green) sub-pixel, and a B (blue) sub-pixel, and may include a W (white) sub-pixel for color implementation.

The pixel array may include touch sensors to implement a touch user interface (UI). Touch sensors may be implemented as capacitive touch sensors that sense a touch input based on a change in capacitance before and after a touch. The capacitive touch sensors may be divided into a mutual capacitive touch sensor and a self capacitive touch sensor. Mutual capacitance may be formed between two orthogonal conductor wirings, and self-capacitance may be formed along a single-layered conductor wiring formed in one direction. The touch sensing data acquired during the touch sensor driving period is transmitted to the timing controller from the read-out IC or the source driver IC having the read-out IC built-in, and the timing controller analyzes the received touch sensing data to extract touch coordinates. The touch sensor-embedded display device is described in detail in Korean Patent Application Laid-Open No. 10-2014-0077719 and Korean Patent Application Laid-Open No. 10-2014-0081470 previously filed by the applicant of the present application.

In the case of an OLED display, the pixels may include a sensing circuit for sensing a characteristic change of the driving TFT. The device characteristic change is converted into digital data through the ADC and transmitted to the timing controller, and the timing controller compensates the device characteristic change of the pixels by modulating the data of the input image based on the device characteristic change data. The ADC may be built into the source drive ICs, and the data compensation circuit may be built into the timing controller. This compensation method includes application number 10-2013-0134256 (2013/11/06), application number 10-2013-0141334 (2013/11/20) previously filed by the applicant of the present application, application number 10- 2013-0166678 (2013/12/30), Application No. 10-2013-0149395 (2013/12/03), Application No. 10-2014-0079255 (2014/06/26), Application No. 10 -2014-0079587 (2014/06/27), application number 10-2014-0086901 (2014/07/10), application number 10-2014-0119357 (2014/09/05), etc. are described in detail have.

The timing controller (TCON) receives external timing signals such as vertical/horizontal synchronization signals (Vsync, Hsync), external data enable signals (Data Enable, DE), and main clock (CLK) from an external host system and receives the source drive IC Timing control signals for controlling operation timings of the SIC1 to SIC8 and the gate drive ICs GIC1 to GIC4 are generated. The timing control signals include a gate timing control signal for controlling the operation timing of the gate drive ICs GIC1 to GIC4 and a source timing control signal for controlling the operation timing of the source drive ICs SIC1 to SIC8 .

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP indicates a start timing at which the scan starts so that the first gate pulse is generated from the first gate drive IC GDIC#1. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The shift registers of the gate drive ICs GIC1 to GIC4 shift the gate start pulse GSP at the rising edge of the gate shift clock GSC. The gate drive ICs GIC1 to GIC4 start to operate by receiving the carry signal of the previous gate drive IC as a gate start pulse. The gate output enable signal GOE controls output timing of the gate drive ICs GIC1 to GIC4. The gate timing control signal may be encoded in a control data packet and transmitted to the source drive ICs SIC1 to SIC8. The source drive ICs SIC1 to SIC8 may restore the gate timing control signal from the control data packet and transmit it to the gate drive ICs GIC1 to GIC4 . When the gate timing control signal generated by the timing controller TCON is directly transmitted to the gate drive ICs GIC1 to GIC4, gate timing control information may be omitted from the control data packet.

The gate drive ICs GIC1 to GIC4 sequentially supply gate pulses synchronized with the data voltage to the gate lines in response to gate timing control signals.

The source timing control signal includes control information for controlling the operation of the source drive ICs SIC1 to SIC8. For example, the source timing control signal includes polarity control information and source output timing information. The source drive ICs SIC1 to SIC8 restore polarity control information to generate an internal polarity control signal POL to invert the polarity of the data voltage according to a logic value of the polarity control signal. The source drive ICs SIC1 to SIC8 generate an internal source output enable signal SOE by restoring source output timing information. The output timing of the data voltage output from the source drive ICs SIC1 to SIC8 is controlled according to the logic value of the internal source output enable signal SOE. The source timing control signal SOE may be encoded in a control data packet and transmitted to the source drive ICs SIC1 to SIC8.

Circuits for generating positive/negative gamma compensation voltages may be built in the source drive ICs SIC1 to SIC8. In this case, the source timing control signal transmitted to the source drive ICs SIC1 to SIC8 through the control data packet may include gamma compensation control information for controlling the gamma compensation voltage. The source drive ICs SIC1 to SIC8 may restore the gate timing control signal from the control data packet and transmit it to the gate drive ICs GIC1 to GIC4 .

The source drive ICs (SIC1 to SIC8) receive data from the timing controller (TCON) through the EPI interface, and transmit ADC data and ADC clock to the timing controller (TCON) through separate wiring pairs. To this end, the timing controller TCON and the source drive ICs SIC1 to SIC8 are connected through the EPI wiring pair DL, and also connected through the ADC data wiring pair SDL and the ADC clock wiring pair SCL. do. The EPI wiring pair DL connects the timing controller TCON and the source drive ICs SIC1 to SIC8 1:1 in a point-to-point form. The source drive ICs SIC1 to SIC8 receive a clock training pattern (or preamble) signal, a control data packet, and a video data packet from the timing controller TCON through the EPI wiring pair DL. The control data packet may include control information of the source timing control signal and control information of the gate timing control signal. The video data may be data modulated according to a preset compensation algorithm to compensate for a change in device characteristics.

The ADC data line pair SDL connects the timing controller TCON to the plurality of source drive ICs SIC1 to SIC8 in parallel. For example, the source drive ICs SIC1 to SIC4 connected to the first PCB PCB1 are connected to the timing controller TCON through the first ADC data line pair SDL. The source drive ICs SIC5 to SIC8 connected to the second PCB PCB2 are connected to the timing controller TCON through the second ADC data line pair SDL. The source drive ICs SIC1 to SIC8 transmit touch sensing data or sensing data related to changes in device characteristics of pixels to the timing controller TCON through the ADC data line pair SDL.

The ADC clock wire pair SCL connects the timing controller TCON to the plurality of source drive ICs SIC1 to SIC8 in parallel. For example, the source drive ICs SIC1 to SIC4 connected to the first PCB PCB1 are connected to the timing controller TCON through the first ADC clock wiring pair SCL. The source drive ICs SIC5 to SIC8 connected to the second PCB PCB2 are connected to the timing controller TCON through the second ADC clock wiring pair SCL. The source drive ICs SIC1 to SIC8 transmit the ADC clock to the timing controller TCON through the ADC clock line pair SCL.

ADC data and ADC clock are transmitted together through a transmission path of the same length from the source drive IC (SIC) to the timing controller (TCON) as shown in FIG. 3 . The timing controller (TCON) receives the ADC clock and ADC data from the ADC clock line pair (SCL) and the ADC data line pair (SDL) at the same timing, respectively, and samples and latches the ADC data based on the ADC clock. Therefore, if ADC data is transmitted according to the ADC clock without adjusting the output timing of ADC data for each source drive IC (SIC), it is possible to automatically prevent an ADC data recognition error.

4 shows a circuit configuration of a timing controller and a source drive IC according to an embodiment of the present invention. 5 shows a data transmission delay time between the timing controller and the source drive ICs. And, FIG. 6 shows an example of a method of generating an ADC clock by dividing the EPI clock.

Referring to FIG. 4 , the timing controller TCON includes a serializer 11 , a phase locked loop (hereinafter referred to as “PLL”) 12 , a transmitter 13 , first and second It includes receivers 14 and 15 , a de-serializer 16 , a compensator 17 , and the like.

The serial converter 11 samples and latches the data of the input image received from the host system through the LVDS interface according to the output clock of the PLL 12, and then converts the data into serial data. The PLL 12 multiplies the LVDS clock received from the host system to generate a clock of the EPI interface transmission frequency. The output clock of the PLL 12 is embedded in data output from the serial converter 11 in units of data packets. The transmitter 13 converts the EPI data with a built-in clock into a differential signal pair defined in the EPI interface protocol, and transmits it to the source drive ICs SIC1 to SIC8 through the EPI wiring pair DL.

The first receiver 14 receives ADC data from the source drive ICs SIC1 to SIC8 through the ADC data line pair SDL and supplies it to the parallel converter 16 . The second receiver 15 receives the ADC clock from the source drive ICs SIC1 to SIC8 through the ADC clock line pair SCL and supplies it to the parallel converter 16 . The parallel converter 16 samples and latches ADC data according to the ADC clock timing, then converts it into a parallel data system and supplies it to the compensator 17 . The compensator 17 modulates the data of the input image to compensate for the device characteristic change by estimating the device characteristic change of the pixels based on the received ADC data. Any known data modulation method for compensating for changes in device characteristics may be used.

Meanwhile, the parallel converter 16 may sample and latch the ADC data according to the ADC clock timing, then convert it into a parallel data system and supply it to the touch data processing unit (not shown). The touch data processing unit may analyze the ADC data using a preset touch recognition algorithm, determine the touch raw data equal to or greater than a predetermined threshold voltage as touch input data, and calculate the coordinate value of the touch input position.

Referring to FIG. 4 , the source drive ICs SIC1 to SIC8 include a receiver 21 , a parallel converter 22 , a clock recovery unit 23 , a divider 24 , and a sample and holder (S). /H) 25 , ADC 26 , serial conversion unit 27 , first and second transmitters 28 and 29 , and the like.

The parallel conversion unit 22 samples the EPI data received through the receiver 21 according to the internal clock timing restored by the clock recovery unit 23 and converts it into a parallel data system. The clock recovery unit 23 generates an internal clock by extracting a clock from the EPI data received from the receiver 21 and recovering the clock. The divider 26 divides the internal clock from the clock recovery unit 23 to generate an ADC sampling clock CLKS and an ADC data transmission clock CLKT. As shown in FIG. 6 , the ADC sampling clock CLKS may be generated by dividing the internal clock by 3, and the ADC data transmission clock CLKT may be generated by dividing the internal clock by 1, but is not limited thereto.

The sample & holder 25 samples sensing data (or touch sensing data) for a device characteristic change input from a pixel according to the ADC sampling clock CLK and supplies it to the ADC 26 . The ADC 26 supplies the sampled ADC data to the serial converter 27 according to the ADC data transmission clock CLKT. The serial converter 27 converts the ADC data into a serial data system and supplies it to the first transmitter 28 . The first transmitter 28 converts the ADC data into a differential signal pair and transmits it to the timing controller TCON through the ADC data wire pair SDL. The second transmitter 29 converts the ADC clock, that is, the ADC data transmission clock CLKT, into a differential signal pair and transmits the converted signal to the timing controller TCON through the ADC clock wire pair SCL.

As shown in FIG. 5 , skew varies for each IC due to a difference in wiring length between the timing controller TCON and the source drive ICs SIC1 to SIC8. The EPI data transmission delay time Td1 is different for each IC between the timing controller TCON and the source drive ICs SIC1 to SIC8, and the ADC data transmission delay time Td2 is also different for each IC. Conventionally, the optimal skew adjustment time for each IC was adjusted to match the delay times (Td1, Td2). However, in the present invention, since the ADC data is sampled and latched using the ADC data transmission clock CLKT in the timing controller TCON, there is no need to prepare a skew adjustment process despite the delay times Td1 and Td2. .

That is, the timing controller TCON receives the ADC data transmission clock CLKT together with the ADC data from the source drive IC SIC at the same timing, and samples and latches the ADC data using the ADC data transmission clock CLKT. . Therefore, despite the delay times Td1 and Td2, a skew does not occur between ADC data and a clock sampling and latching the ADC data. As a result, according to the present invention, the ADC data recognition error phenomenon caused by the conventional skew can be effectively prevented.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

TCON: Timing controller SIC1~SIC8: Source drive IC
11, 27: serial conversion unit 12: phase locked loop
13, 28,29: Transmitter 14,15,21: Receiver
16, 22: parallel conversion unit 17: compensation unit
23: clock recovery unit 24: divider
25: sample & holder 26: analog-digital converter

Claims (6)

a first pair of wires connecting the timing controller and the plurality of source drive ICs;
a second pair of wires connecting the timing controller and the source drive ICs; and
a third pair of wires connecting the timing controller and the source drive ICs;
The source drive ICs transmit output data of the analog-to-digital converter to the timing controller through the second pair of wires, and the source drive ICs transmit the clock of the analog-to-digital converter to the timing controller through the third pair of wires. send,
The timing controller receives the output data of the analog-to-digital converter and the clock of the analog-to-digital converter from the second wire pair and the third wire pair, respectively, at the same timing, and at the clock timing of the analog-to-digital converter A display device for sampling and latching the output data of the analog-to-digital converter in accordance with the above. The method of claim 1,
The source drive ICs generate a clock of the analog-to-digital converter by restoring a first clock from data received through the first pair of wires and dividing the first clock. delete The method of claim 1,
Each of the source drive ICs,
a clock recovery unit configured to recover a first clock received through the first pair of wires;
a divider for dividing the first clock from the clock recovery unit to generate a shift clock and a data transmission clock of the analog-to-digital converter; and
and a sample & holder for sampling sensing data on device characteristic change inputted from pixels of a display panel according to the shift clock and supplying the sampled data to the analog-to-digital converter. 5. The method of claim 4,
The data transmission clock is transmitted as a clock of the analog-to-digital converter to the timing controller through the third wire pair, and output data of the analog-to-digital converter is transmitted through the second wire pair according to the data transmission clock. Display sent to the timing controller. The method of claim 1,
the first pair of wires is 1:1 connected between the timing controller and the source drive ICs;
the second pair of wires is connected in parallel between the timing controller and the plurality of source drive ICs;
and the third wire pair is connected in parallel between the timing controller and the plurality of source drive ICs.

Images