KR102223496B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, and includes a first wiring pair connecting a timing controller and a plurality of source drive ICs, and a second wiring pair connecting the timing controller and the source drive ICs. The timing controller transmits data with a built-in clock to the source drive ICs through the first wiring pair. The source drive ICs transmit output data of the ADC to the timing controller through the second wiring pair. The source drive ICs generate a clock of the ADC by restoring the clock from data received through the first wiring pair and dividing the clock.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device having an automatic skew adjustment function between a timing controller and source drive integrated circuits (hereinafter referred to as “IC”).

Flat panel displays include Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (“OLED Display”), Plasma Display Panel (PDP), and electric field. Field Emission Display (FED) and the like.

A flat panel display device of an active matrix driving method displays a moving picture using a thin film transistor (hereinafter referred to as "TFT") as a switching element. The display device includes a plurality of source drive ICs for supplying data voltages to data lines of a display panel, a plurality of gate drive ICs for sequentially supplying gate pulses (or scan pulses) to gate lines of the display panel, and A timing controller or the like for controlling drive ICs is provided.

The timing controller supplies digital video data, a clock for sampling digital video data, and a control signal for controlling the operation of the source drive ICs to the source drive ICs through interfaces such as mini LVDS (Low Voltage Differential Signaling). . Source drive ICs convert digital video data input from a timing controller into analog data voltages and supply them to data lines.

In the case of connecting the timing controller and source drive ICs in a multi-drop method through the mini LVDS (Low Voltage Differential Signaling) interface, R data transmission wiring, G data transmission wiring, between the timing controller and source drive ICs, A number of wirings including B data transmission wiring, control wirings for controlling the output of the source drive ICs and the timing of operation of the polarity conversion operation, and clock transmission wirings are required. For example of RGB data transmission in the mini-LVDS interface method, the timing controller and source drive ICs are used when transmitting odd data and even data at the same time because each of the RGB digital video data and the clock is transmitted as a differential signal pair. Between them, at least 14 wires are required for RGB data transmission. If the RGB data is 10-bit data, 18 wires are required. Therefore, it is difficult to reduce the width of the source printed circuit board (Printed Circuit Board, hereinafter referred to as “PCB”) mounted between the timing controller and the source drive ICs because many wirings must be formed.

Applicant of the present application is a new signal transmission protocol (hereinafter referred to as "EPI" for stabilizing signal transmission and minimizing the number of wires between the timing controller and the source drive ICs by connecting the timing controller and the source drive ICs in a point-to-point method. "Interface Protocol"), Korean patent application 10-2008-0127458 (2008-12-15), US application 12/543,996 (2009-08-19), Korean patent application 10-2008-0127456 (2008-12-15) ), US application 12/461,652 (2009-08-19), Korean patent application 10-2008-0132466 (2008-12-23), and US application 12/537,341 (2009-08-07).

The EPI interface protocol satisfies the following interface specifications (1) to (3).

(1) Connect the transmitting end of the timing controller and the receiving end of the source drive ICs in a point-to-point manner via a data wire pair.

(2) Do not connect a separate clock wire pair between the timing controller and the source drive ICs. The timing controller transmits video data and control data along with a clock signal to the source drive ICs through a pair of data wires.

(3) A clock recovery circuit for CDR (Clok and Data Recovery) is built into each of the source drive ICs. The timing controller transmits a clock training pattern or preamble signal to the source drive ICs so that the output phase and frequency of the clock recovery circuit can be locked. The clock recovery circuit built into the source drive ICs generates an internal clock when a clock training pattern signal and a clock signal input through a pair of data lines are input.

In the EPI interface protocol, as described above, the timing controller transmits the preamble signal to the source drive ICs before transmitting the control data and video data of the input image. The clock recovery circuit of the source drive IC stably fixes the phase and frequency of the internal clock by performing a clock training (CT) operation according to the preamble signal. When the phase and frequency of the internal clock are stably fixed, a data link through which data of an input image is transmitted is established between the source drive IC and the timing controller. The timing controller starts transmitting control data and video data to the source drive ICs after the lock signal received from the last source drive IC is received.

When the output phase and frequency of the clock recovery circuit built in any of the source drive ICs are unlocked, the lock signal is inverted to a low logic level, and the last source drive IC timing the inverted lock signal. Send it to the controller. When the lock signal is inverted to a low logic level, the timing controller transmits a preamble signal to the source drive ICs to resume clock training of the source drive ICs.

Since the wiring lengths between the timing controller and the source drive ICs are different, the skew may be different for each source drive IC. When skew is optimal, transmission errors in data transferred between the timing controller and the source drive ICs are minimized. In order to optimize the skew of each of the source drive ICs, the skew adjustment time is lengthened because the operator must repeat the process of manually measuring and adjusting the skew. In addition, there may be variations in skew adjustment depending on the person.

The pixels of an OLED display device include a driving TFT (Thin Film Transistor) that controls a driving current flowing through the OLED according to the data of an input image. Device characteristics, such as a threshold voltage and mobility of the driving TFT, may change depending on process variations, driving time, driving environment, and the like. The change in device characteristics of these pixels degrades the image quality and shortens the lifespan of the OLED display. Accordingly, in the organic light emitting diode display, a technology for compensating for a change in device characteristics of pixels by sensing a change in device characteristics of a pixel and appropriately changing input data according to a sensing result is applied. The change in device characteristics of the pixel includes a change in characteristics of the driving TFT such as the threshold voltage and mobility of the driving TFT.

The change in device characteristics of the pixel is converted into digital data through an analog-to-digital converter (hereinafter referred to as “ADC”) and transmitted to a data compensation circuit. The ADC can be embedded in each of the source drive ICs, and the data compensation circuit can be embedded in the timing controller. Therefore, in order to compensate for this change in device characteristics, wiring for transmitting ADC data between the timing controller and the source drive IC, ADC clock wiring, and ADC control signal transmission wiring are required. The number of wires between them increases.

The present invention is to provide a display device that enables automatic skew adjustment between a timing controller and source drive ICs.

The display device of the present invention includes a first wiring pair connecting a timing controller and a plurality of source drive ICs, and a second wiring pair connecting the timing controller and the source drive ICs.

The timing controller transmits data with a built-in clock to the source drive ICs through the first wiring pair.

The source drive ICs transmit output data of the ADC to the timing controller through the second wiring pair.

The source drive ICs generate a clock of the ADC by restoring the clock from data received through the first wiring pair and dividing the clock.

The present invention transmits a delayed skew adjustment signal from the source drive ICs to a timing controller and determines the reception state of the skew adjustment signals received from the timing controller to determine the optimum skew timing for each IC. Therefore, the timing controller and source drive ICs not only can automatically adjust the skew, but also can adjust the optimal skew regardless of the display device or model.

Furthermore, the present invention generates an ADC clock based on a clock received from a timing controller (TCON), thereby minimizing the number of wires required for an ADC operation, and allowing the timing controller to sample ADC data at an optimal timing.

In addition, the present invention transmits timing information necessary for ADC driving, such as ADC operation period and sampling time, and transmits IC selection information for identifying each of the source drive ICs to the source drive ICs, so that a source drive without a carry signal when transmitting ADC data. Allows the ICs to sequentially transmit ADC data.

1 is a diagram schematically showing a topology between a timing controller and source drive ICs in a display device according to an embodiment of the present invention.
2 is a diagram showing a circuit configuration of a timing controller and a source drive IC.
3 is a diagram showing a data transmission delay time between a timing controller and source drive ICs.
4 is a block diagram of a skew adjustment including a skew generator.
5 is a waveform diagram showing a skew adjustment signal transmitted from a source drive IC to a timing controller and data sampling timing of the timing controller.
6 is a diagram illustrating an example of a method of determining an optimal skew timing.
7 is a diagram illustrating a process of searching for an optimal skew timing in a timing controller.
8 is a diagram showing various examples of a method for determining a skew.
9 is a diagram showing an example of a method of generating an ADC clock by dividing an EPI clock.
10 is a diagram showing a method of transmitting ADC data after a skew adjustment process.

The display device of the present invention may be implemented as a flat panel display device such as a liquid crystal display device (LCD), an OLED display device, a field emission display device (FED), and a plasma display panel (PPDP). In the following embodiments, an OLED display will be mainly described, but the present invention is not limited thereto.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, when it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

1 and 2, the display device of the present invention includes a display panel PNL, a timing controller TCON, and source drive ICs SIC1 to SIC12. In Fig. 1, the gate driving circuit (or the scan driving circuit) is omitted.

The display panel PNL includes a pixel array in which an input image is displayed. The pixel array includes pixels arranged in a matrix form by an intersection structure of data lines and gate lines. Each of the pixels may include an R (Red) sub-pixel, a G (Green) sub-pixel, and a B (Blue) sub-pixel, and may include a W (White) sub-pixel for color implementation. The pixel array may include touch sensors to implement a touch user interface (UI).

In the case of an OLED display, the pixels may include a sensing circuit for sensing a characteristic change of the driving TFT. The change in the dissipation characteristic is converted into digital data through the ADC and transmitted to the timing controller, and the timing controller compensates for the change in device characteristics of pixels by modulating the data of the input image based on the device characteristic change data. The ADC is built into the source drive ICs, and the data compensation circuit can be built into the timing controller. This compensation method is the application number 10-2013-0134256 (2013/11/06) previously filed by the applicant of the present application, application number 10-2013-0141334 (2013/11/20), application number 10- 2013-0166678 (2013/12/30), application number 10-2013-0149395 (2013/12/03), application number 10-2014-0079255 (2014/06/26), application number 10 -2014-0079587 (2014/06/27), application number 10-2014-0086901 (2014/07/10), application number 10-2014-0119357 (2014/09/05), etc. have.

The source drive ICs SIC1 to SIC12 receive data from the timing controller TCON through the EPI interface, and transmit ADC data to the timing controller TCON through a separate wire pair. To this end, the timing controller TCON and the source drive ICs SIC1 to SIC12 are connected through an EPI wiring pair DL and also connected through an ADC data wiring pair SL. The EPI wiring pair (DL) is connected in a point-to-point form by connecting the timing controller (TCON) and the source drive ICs (SIC1 to SIC12) 1:1. Timing controller (TCON) is a clock training pattern (clock training pattern or preamble), control data packet, and video data packet through an EPI wiring pair (DL) according to the EPI interface protocol in order to display the input image after setting the optimal skew timing. The clock is transmitted to the source drive ICs SIC1 to SIC12 together with data such as the. The control data packet contains control data for controlling the operation of the source drive ICs and the gate drive ICs. The video data may be data modulated according to a preset compensation algorithm in order to compensate for changes in device characteristics.

The ADC data wiring pair SL connects the timing controller TCON to a plurality of source drive ICs SIC1 to SIC12 in parallel. For example, the source drive ICs SIC1 to SIC6 connected to the first PCB PCB1 are connected to the timing controller TCON through the first ADC data line pair SL. The source drive ICs SIC7 to SIC12 connected to the second PCB (PCB2) are connected to the timing controller TCON through the second ADC data line pair SL. After setting the skew, the source drive ICs SIC1 to SIC12 transmit device characteristic change data of pixels to the timing controller TCON through the ADC data line pair SL.

The timing controller (TCON) includes a serializer (11), a phase locked loop (hereinafter referred to as "PLL") 12, a transmitter 13, a receiver 16, and a parallel converter (De- It includes a serializer, 15), a compensation unit 14, and the like. The serial converter 11 samples and latches the data of the input image received from the host system through the LVDS interface according to the output clock of the PLL, and then converts the data into serial data. The PLL 12 generates a clock of the EPI interface transmission frequency by multiplying the LVDS clock received from the host system. In the data output from the serial converter 11, the output clock of the PLL is embedded in units of data packets. The transmitter 13 converts the clock-embedded data into a differential signal pair defined in the EPI interface protocol and transmits it to the source drive ICs SIC1 to SIC12 through the EPI wiring pair DL.

The receiver 16 receives ADC data from the source drive ICs SIC1 to SIC12 through the ADC data wiring pair SL and supplies the ADC data to the parallel converter 15. The parallel conversion unit 15 samples and latches the ADC data according to the output clock timing of the PLL, converts it into a parallel data system, and supplies it to the compensation unit 14. The compensator 14 modulates the data of the input image to compensate for the device characteristic change by estimating the device characteristic change of the pixels based on the received ADC data. Any known data modulation method for compensating for changes in device characteristics is possible.

Source drive ICs (SIC1 to SIC12) include a receiver 21, a parallel converter 22, a clock recovery unit 23, a divider 24, and a sample & holder (S/H) 25 , ADC 26, serial converter 27, transmitter 28, and the like. The parallel conversion unit 22 samples the signal received through the receiver 21 according to the internal clock timing restored by the clock recovery unit 23 and converts it into a parallel data system. The clock recovery unit 23 generates an internal clock by extracting a clock from data received from the receiver 21 and restoring the clock. The divider 26 divides the internal clock from the clock recovery unit 23 to generate an ADC shift clock CLKS and an ADC data transfer clock CLKT. The sample & holder 25 samples device characteristic change data input from the pixel according to the ADC shift clock CLK and supplies it to the ADC 26. The ADC 26 supplies the sampled ADC data to the serial converter 27 according to the ADC data transmission clock CLKT. The serial converter 27 converts the ADC data into a serial data system and supplies it to the transmitter 28. The transmitter 28 converts the ADC data into a differential signal pair and transmits it to the timing controller TCON through the ADC data line pair DL.

Since the ADC-related clocks (CLKS, CLKT) are generated by dividing the clock synchronized with the clock received through the EPI interface, the timing controller (TCON) does not need to separately transmit the ADC-related clock. Since the ADC related clocks (CLKS, CLKT) are synchronized with the clock transmitted through the EPI interface, the ADC data, sampling, latch, and parallel system can be converted based on the clock of the PLL 12 received from the timing controller (TCON). . Accordingly, the source drive ICs SIC1 to SIC12 may process ADC data with the internal clock signal divided by the divider 26 without receiving the ADC related clock from the outside.

Due to the difference in wiring length between the timing controller TCON and the source drive ICs SIC1 to SIC12, the skew varies for each IC. The EPI data transmission delay time Td1 between the timing controller TCON and the source drive ICs SIC1 to SIC12 is different for each IC, and the ADC data transmission delay time Td21 is also different for each IC. The optimal skew adjustment time for each IC should be adjusted according to the delay times (Td1, Td2). The present invention provides a process of automatically adjusting skew between the timing controller TCON and the source drive ICs SIC1 to SIC12. The skew adjustment process may be prepared in a product development stage, a product production stage, or a power on sequence in which power of the display device is turned on.

The timing controller (TCON) transmits a skew adjustment signal to the source drive ICs (SIC1 to SIC12) during a preset skew adjustment time (SKEW_ON) and checks for errors in the skew adjustment signal received from the source drive ICs (SIC1 to SIC12). Thus, the optimal skew is determined for each IC, and the optimal skew timing set for each IC is set in its own register. The timing controller TCON transmits the optimal skew timing information for each IC to the source drive ICs SIC1 to SIC12 through the EPI wiring pair DL, so that the optimal skew timing is set in each IC.

The source drive ICs SIC1 to SIC12 include a skew generator 31 that is driven during a skew adjustment process as shown in FIG. 4.

4 and 5, each of the source drive ICs SIC1 to SIC12 includes a register 33, a skew generator 31, and a multiplexer (hereinafter, referred to as "MUX") 32. .

The timing controller TCON transmits the skew on signal SKEW_ON and the skew adjustment signal SKEW123 to the source drive ICs SIC1 to SIC12 through the EPI wiring pair DL. The data of the skew adjustment signal SKEW123 is data set in a register of the timing controller TCON. The skew on signal (SKEW_ON) defines the skew adjustment time. The source drive ICs SIC1 to SIC12 temporarily store in the register 33 the skew adjustment signal SKEW123 received during the skew-on signal SKEW_ON period received through the EPI wiring pair DL. The register 33 stores optimal skew timing information received from the timing controller TCON after the skew adjustment time.

The source drive ICs SIC1 to SIC12 timing the skew adjustment signal SKEW123 delayed in a predetermined time unit (3UI) according to the restored clock timing as shown in FIG. 5 through the ADC data wiring pair SL during the skew adjustment time. Transfer to the controller (TCON). The skew generator 31 continuously outputs the skew adjustment signal SKEW123 during the skew adjustment time while delaying the skew adjustment signal SKEW123 read from the register 33 according to the restored internal clock timing. In the example of FIG. 5, the skew adjustment signal SKEW123 includes eight signals LLL to HHH delayed in units of 3 UI during the skew on signal SKEW_ON. The skew generator 31 sequentially delays the skew adjustment signals SKEW123...n by a unit of UI (Unit Interval) or an integer multiple of UI according to the restored internal clock timing. One data packet of EPI data in the exemplary drawing is a case of 24 UI, and the UI is 1 bit transmission time. The MUX 32 transmits the skew adjustment signal SKEW123 received from the skew generator 31 during the skew adjustment time in response to the skew on signal SKEW_ON through the transmitter 28 and the ADC data wire pair SL. Transfer to (TCON).

Since the MUX 32 does not receive the skew-on signal SKEW_ON after the optimal skew timing for each IC is set, the ADC 26 is connected to the ADC data wire pair SL after the optimal skew timing is set. After the skew adjustment time, the ADC data is transmitted to the timing controller (TCON) through the ADC data wire pair (SL).

When the number of phase difference of the clock transmitted from the timing controller TCON is increased and combined with the number of delayed skew adjustment signals, the method of determining skew can be further diversified.

The timing controller (TCON) samples the skew adjustment signal (SKEW123) received from the source drive ICs (SIC1 to SIC12), compares the received data with pre-stored data, performs an error check, determines the data reception status, and determines the received data. It repeats for each of the skew adjustment signals SKEW123 that are continuously input after being delayed by a time difference. The timing controller TCON searches for an optimal skew adjustment signal SKEW123 with the smallest error as a result of the error check determination of each of the received skew adjustment signals SKEW123. The timing controller (TCON) stores the optimal skew adjustment signal (SKEW123) searched for each IC based on the determination result of the skew adjustment signal SKEW123 received from each of the source drive ICs SIC1 to SIC12 in its own register. After setting, the optimal skew timing information for each IC is transmitted to the source drive ICs SIC1 to SIC12 through the EPI wiring pair (DL). Each of the source drive ICs SIC1 to SIC12 stores an optimal skew adjustment signal code received from the timing controller TCON in a register 33 to set an optimal skew timing. When each of the source drive ICs SIC1 to SIC12 sets an optimal skew timing, it transmits ADC data to the timing controller TCON in accordance with a preset optimal skew timing after the skew adjustment time.

6 is a diagram illustrating an example of a method of determining an optimal skew timing.

Referring to FIG. 6, the timing controller TCON may determine a reception state of the skew adjustment signal SKEW123 in units of one data packet of EPI data. The timing controller (TCON) determines the signal with the worst reception condition among the skew adjustment signals (SKEW123) received from the source drive ICs (SIC1 to SIC12) and optimizes the delay time of the signal with the largest phase difference. It can be judged by the skew timing of.

The timing controller TCON may estimate an optimal skew timing based on a skew adjustment signal (Worst case) having the worst reception state as a result of the error check. For example, in the example of FIG. 6, if SKEW123 = 4 (HLL) is Worst, SKEW123 = 0 (LLL) having the largest phase difference therefrom may be selected as an optimal skew timing. When the skew adjustment signal (SKEW123) is generated as 8 signals with a predetermined time difference during the skew on time (SKWE_ON), the timing controller (TCON) receives 8 skew adjustment signals (SKEW123 = 0 ~ SKEW123) successively received by a 3-bit counter. =7) can be counted, and if 4 is added to the Worst count value, the skew adjustment signal of the best timing with the greatest difference between the worst timing and the phase can be estimated. The skew adjustment signal (SKEW123) is generated as 16 signals with a predetermined time difference during the skew on time (SKWE_ON). The skew adjustment signal of can be estimated.

If there are a number of signals in which errors are found in the skew adjustment signal (SKEW123) sequentially received from one source drive IC, the timing controller (TCON) takes an intermediate signal from among the multiple signals in which the error has occurred and is based on the intermediate signal. Estimate the optimal skew timing. The timing controller TCON selects the optimal skew timing of the IC as the same skew timing as the neighboring source drive IC when all the reception states of the skew adjustment signal SKEW123 received from a specific source drive IC are good and there is no Worst case.

7 is a diagram showing a process of searching for an optimal skew timing in a timing controller.

Referring to FIG. 7, the timing controller TCON checks errors for each of the skew adjustment signals SKEW123 received from each of the source drive ICs SIC1 to SIC12 during the skew adjustment time when the skew on signal SKEW_ON is generated. Thus, the optimal skew for each IC is determined. Subsequently, the timing controller TCON sets optimal skew timing information for each IC in its own register and transmits it to the source drive ICs SIC1 to SIC12. The optimal skew timing operation and register setting may be performed after the skew-on signal SKEW_OK is inverted to a low logic value.

8 is a diagram showing various examples of a method for determining a skew. In FIG. 8, NA is Not Available. TS (Transfer Start) is a header code of an ADC data packet. The timing controller (TCON) can read the TS and recognize the ADC data packet.

Referring to FIG. 8, a method of determining a skew is predetermined between the timing controller TCON and the source drive ICs SIC1 to SIC12. For example, the timing controller TCON may determine a skew state by checking an error of the skew adjustment signal SKEW123 by simply accumulating counts. As another embodiment, the timing controller TCON may determine a skew state by checking an error of the skew adjustment signal SKEW123 received in a pseudo-random bit sequence (PRBS) method. As another embodiment, the timing controller TCON stores the data or constant values previously promised with the source drive ICs SIC1 to SIC12 and checks an error by comparing it with the data of the received skew adjustment signal SKEW123. You can determine the skew state in a way.

9 is a diagram showing an example of a method of generating an ADC clock by dividing an EPI clock.

Referring to FIG. 9, in the present invention, an internal clock is generated by restoring an EPI clock received through an EPI wiring pair DL, and ADC clocks CLKS and CLKT are generated by dividing the internal clock. CLKT is an example that is synchronized with the restored internal clock PCLK and generated at the same frequency. CLKS is an example generated by dividing the EPI clock by three. CLKT and CLKS are not limited to FIG. 9.

10 is a diagram showing a method of transmitting ADC data after a skew adjustment process.

Referring to FIG. 10, the timing controller includes ADC sampling timing information (SAM) and ADC operation period (DIS) in a control packet (CTR) transmitted to source drive ICs (SIC1 to SIC12) through an EPI wiring pair (DL). ADC operation timing information can be encoded. The source drive ICs SIC1 to SIC12 decode the ADC control signal of the control packet, read the SAM and DIS, operate the ADC 26, and transmit the ADC data.

When the SAM is received, the ADC 26 of the source drive ICs SIC1 to SIC12 sequentially samples the ADC data, converts it into digital data, and stores the digital data in a register. ADC data starts to be sequentially transmitted from the first source drive IC SIC1. To distinguish the ADC data packet, the ADC data is transmitted following the TS code.

The timing controller (TCON) encodes the selection code (IC_SEL) set for each IC along with ADC control information such as SAM and DIS into the control packet (CTR) of EPI data and transmits it to the source drive ICs (SIC1 to SIC12). During ADC data transmission, the source drive ICs SIC1 to SIC12 do not need to generate a separate carry signal indicating the transmission timing of the next IC.

In FIG. 10, Hi-Z means a high impedance state in which the ADC data output channels of the source drive ICs SIC1 to SIC12 are opened.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Accordingly, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

TCON: Timing controller SIC1~SIC12: Source drive IC
11, 27: serializer 12: phase locked loop (PLL)
13, 28: transmitter 14: compensation unit
15, 22: parallel converter (De-serializer) 16, 21: receiver
23: clock recovery unit 24: divider
25: sample & holder (S/H) 26: analog-digital converter (ADC)
31: skew generator 32: multiplexer (MUX)
33: register

Claims (14)

A first wiring pair connecting the timing controller and the plurality of source drive ICs;
A second wiring pair connecting the timing controller and the source drive ICs,
The timing controller transmits a skew adjustment signal to the source drive ICs through the first wiring pair for a preset skew adjustment time, and based on the skew adjustment signals received from the source drive ICs through the second wiring pair. Determining an optimum skew timing in each of the source drive ICs, and transmitting data with a built-in clock to the source drive ICs through the first wiring pair after the skew adjustment time,
The timing controller determines a worst signal having the worst reception state among the skew adjustment signals received from the source drive ICs through the second wiring pair, and determines a delay time between the worst signal and the signal having the largest phase difference. Judging by the optimal skew timing,
The source drive ICs transmit output data of an analog-to-digital converter (ADC) to the timing controller through the second wiring pair after the skew adjustment time,
The source drive ICs restore the clock from data received through the first wiring pair and divide the clock to generate a clock of the analog-to-digital converter (ADC). The method of claim 1,
The timing controller transmits the skew adjustment signal to the source drive ICs together with a skew on signal indicating the skew adjustment time during the skew adjustment time,
The source drive ICs transmit a plurality of skew adjustment signals sequentially delayed in accordance with the restored clock timing during the skew-on signal period to the timing controller through the second wire pair. The method of claim 2,
The timing controller performs an error check on each of the skew adjustment signals received from the source drive ICs, sets the optimum skew timing information of each of the source drive ICs in a register based on the error check result, and sets the first wiring pair. Transmits to the source drive ICs through,
Each of the source drive ICs stores optimal skew timing information received from the timing controller in a register. The method of claim 3,
The source drive ICs transmit output data of an analog-to-digital converter (ADC) through the second wiring pair according to an optimal skew timing set in the register. The method of claim 3,
Each of the above source drive ICs
A clock recovery unit for restoring a clock received through the first wiring pair;
A divider for generating a shift clock and a data transmission clock of the analog-to-digital converter (ADC) by dividing the clock from the clock recovery unit; And
Further comprising a sample & holder for sampling device characteristic change data input from a pixel of the display panel according to the shift clock and supplying it to the analog-to-digital converter (ADC),
The output data of the analog-to-digital converter is transmitted to the timing controller through the second wire pair according to the data transmission clock after the skew adjustment time. The method of claim 5,
Each of the source drive ICs,
A skew generator for continuously generating the plurality of skew adjustment signals by delaying a plurality of skew adjustment signals according to the restored clock; And
The display device further comprises a multiplexer that supplies the output of the skew generator to the second wire pair during the skew adjustment time and supplies output data of the analog-to-digital converter to the second wire pair after the skew adjustment time. delete The method of claim 1,
The timing controller,
A display device for encoding operation timing information of the analog-to-digital converter and IC selection information identifying the source drive ICs into control data transmitted through the first wiring pair after the skew adjustment time. The method of claim 1,
The first wiring pair is connected 1:1 between the timing controller and the source drive ICs,
The second wiring pair is connected in parallel between the timing controller and the plurality of source drive ICs. A first wiring pair connecting the timing controller and the plurality of source drive ICs;
A second wiring pair connecting the timing controller and the source drive ICs,
The timing controller transmits a skew adjustment signal to the source drive ICs through the first wiring pair for a preset skew adjustment time, and based on the skew adjustment signals received from the source drive ICs through the second wiring pair. Determining an optimum skew timing in each of the source drive ICs, and transmitting data with a built-in clock to the source drive ICs through the first wiring pair after the skew adjustment time,
The source drive ICs transmit output data of an analog-to-digital converter (ADC) to the timing controller through the second wiring pair after the skew adjustment time,
The source drive ICs restore the clock from data received through the first wiring pair and divide the clock to generate a clock of the analog-to-digital converter (ADC). The method of claim 10,
The timing controller,
A display device comprising: a compensation unit for modulating data of an input image based on output data of the analog-to-digital converter (ADC) received through the second wire pair. The method of claim 10,
The timing controller,
When an error is detected in the skew adjustment signals sequentially received from one source drive IC, the display device determines an optimum skew timing based on an intermediate signal among the skew adjustment signals in which the error is detected. The method of claim 10,
The timing controller,
A display device for selecting an optimum skew timing of the specific source drive IC as the skew timing of another neighboring source drive IC when all the reception states of the skew adjustment signals received from a specific source drive IC are satisfactory. The method of claim 10,
The timing controller,
Skew adjustment signals received from the source drive ICs using any one of a count accumulation method, a pseudo-random bit sequence (PRBS) check method, and a method of comparing a preset data or constant value with the data of the received skew adjustment signal A display device that determines the skew state of the vehicle.

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