KR20200051226A - Image display device and method for driving the same - Google Patents

Abstract

The present invention relates to an image display device and a driving method thereof. According to an embodiment of the present invention, the image display device comprises: a timing controller outputting image data aligned to driving characteristics of an image display panel and a data signal in an LVDS interface method and outputting a gate control signal for gate line driving of the image display panel in a TTL interface method; a data driving circuit driving data lines of the image display panel according to the image data and the data control signal and generating and outputting a control clock signal for gate line driving; and a gate driving circuit driving a gate line using the gate control signal from the timing controller and the control clock signal from the data driving circuit. The effect of reducing the number of gate control signal transmissions of the image display device may be achieved.

Description

IMAGE DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

The present invention relates to an image display device and a driving method for reducing the number of gate control signals transmitted from the image display device.

Flat panel video display devices are used in various types of electronic products, including mobile phones, tablet PCs, and notebook computers. As a flat panel image display device, a liquid crystal display device, an organic light emitting diode display device, an electronic wet display device, and a field emission device are mainly applied.

A liquid crystal display device or an organic light emitting diode display device displays an image by adjusting a light transmittance or an emission amount of each pixel through an image display panel in which a plurality of pixels are arranged in a matrix form. To this end, panel driving circuits for driving the pixels of the image display panel are configured to be mounted or electrically connected to the image display panel.

For example, in the organic light emitting diode display panel, a plurality of gate lines and data lines are arranged to cross each other, and pixels including the organic light emitting diode are configured in each pixel area defined by the crossing of the gate lines and the data lines.

The panel driving circuit includes a gate driving circuit that sequentially drives the gate lines, a data driving circuit that supplies data voltages to the data lines, and a timing controller that supplies gates and data control signals to control driving timings of the gate and data driving circuits. It includes.

The gate driving circuit sequentially generates scan pulses using gate control signals transmitted from a timing controller. Then, by sequentially supplying scan pulses to respective gate lines, each pixel of the image display panel is sequentially driven by one line. Accordingly, the organic light emitting diode display panel displays an image by adjusting the emission amount of the organic light emitting diode according to the data voltage for each pixel.

Specifically, the timing controller may include a control clock signal that sets the output timing of the scan pulse, a scan control signal that sets the pulse width of the scan pulse, and an enable control signal that sets each frame period or data enable period. The gate control signal is generated. Then, the gate control signal is transmitted to the gate driving circuit every frame period.

The gate driving circuit is configured to sequentially output scan pulses to gate lines, and includes a level shifter and a shift register. Here, the level shifter sequentially generates a plurality of clock signals using a gate control signal from a timing controller, that is, a control clock signal, a scan control signal, and an enable control signal. The shift register sequentially changes the voltage level of the clock signals to generate scan pulses and supplies them to the gate lines.

The gate driving circuit is mounted on one side of the image display panel along a gate line arrangement direction or is electrically connected to the gate lines. Accordingly, when the gate driving circuit is applied to a high-resolution large-screen image display panel, the voltage of the gate control signals has to be increased so that the intensity of the gate control signals does not weaken as the number of gate lines increases.

However, as the voltage of the gate control signals increases, noise caused by electromagnetic interference (EMI) is also amplified during a period in which the phases of the gate control signals overlap, resulting in a defect in gate line driving.

In addition, a gate driving circuit may be provided on both sides of the image display panel in the high-resolution large-screen image display panel. In this case, there is a problem in that the number of input / output channels of the gate control signal and the design area of the transmission lines are increased according to the number of gate control signals transmitted by being divided into gate drive circuits on both sides of the timing controller.

The present invention is to solve the above problems, an image display device to reduce the number of gate control signals transmitted from the timing controller to the gate driving circuit to reduce the number of input / output channels and transmission lines of the gate control signal. And its purpose.

In addition, an object of the present invention is to provide an image display device and a driving method for reducing the number of gate control signals generated by a timing controller, a gate control signal output channel, and an arrangement area of a gate control signal transmission line. .

In addition, an object of the present invention is to provide an image display device and a driving method for reducing noise caused by transmission of a gate control signal by reducing the number of gate control signals transmitted from a timing controller to a gate driving circuit.

In addition, the present invention is an image display device and a method for driving the at least one gate control signal transmitted from a timing controller to a gate driving circuit and a control clock signal transmitted from a data driving circuit to the gate driving circuit are synchronized. The purpose is to provide.

In order to achieve the above object, the image display device according to an embodiment of the present invention outputs image data aligned with driving characteristics of the image display panel, and a data control signal using an LVDS interface, and gate lines of the image display panel. The gate control signal for driving is a timing controller that outputs in a TTL interface method, and a data driving assembly that drives data lines of an image display panel according to image data and data control signals and generates and outputs a control clock signal for driving the gate line. And a gate driving circuit for driving the gate line using the gate control signal from the timing controller and the control clock signal from the data driving circuit.

In addition, the driving method of the video display device according to an embodiment of the present invention for achieving the above object is the timing controller outputs the image data, and data control signals aligned with the driving characteristics of the video display panel in the LVDS interface method Outputting a gate control signal for driving a gate line of the image display panel in a TTL interface method, and generating and outputting a control clock signal for driving a gate line in a data driving circuit driving data lines of the image display panel And driving the gate line using the gate control signal from the timing controller and the control clock signal from the data driving circuit.

In the image display device and the driving method according to an embodiment of the present invention having various technical features as described above, the data driving circuit generates a control clock signal of one of the gate control signals and transmits it to the gate driving circuit. The number of gate control signals transmitted from the controller to the gate driving circuit can be reduced.

Accordingly, according to the present invention, the number of gate control signals generated by the timing controller, the gate control signal output channel, and the arrangement area of the gate control signal transmission line can be reduced. In this way, reducing the arrangement area of the gate control signal transmission line has an effect of minimizing the size of the non-display area of the image display panel, the printed circuit board on which the gate driving circuit is mounted, and the printed circuit film.

In addition, the image display device and the driving method of the present invention can reduce noise caused by the transmission of the gate control signal between the timing controller and the gate driving circuit by reducing the number of gate control signals transmitted from the timing controller to the gate driving circuit.

In addition, in the present invention, at least one gate control signal transmitted from the timing controller to the gate driving circuit and a control clock signal transmitted from the data driving circuit to the gate driving circuit are synchronized. Accordingly, according to the present invention, it is possible to maintain the same scan pulse output timing for each frame of the gate driving circuit and increase its reliability.

1 is a configuration diagram specifically showing an image display device according to an embodiment of the present invention.
FIG. 2 is a view showing an equivalent circuit of one sub-pixel shown in FIG. 1.
3 is a block diagram showing the configuration of the timing controller, data driving circuit, and level shifter shown in FIG. 1 according to the first embodiment.
4 is a waveform diagram illustrating a transmission timing error of a gate control signal transmitted from the timing controller shown in FIG. 3 to a level shifter.
5 is a waveform diagram specifically illustrating a gate control signal whose transmission timing is corrected according to the first embodiment.
6 is a block diagram showing the configuration of the timing controller, data driving circuit, and level shifter shown in FIG. 1 according to the second embodiment.
7 is a waveform diagram specifically showing a gate control signal whose transmission timing is corrected according to the second embodiment.
8 is a block diagram illustrating a configuration of a timing controller, a data driving circuit, and a level shifter shown in FIG. 1 according to a third embodiment.
9 is a waveform diagram specifically illustrating a gate control signal whose transmission timing is corrected according to a third embodiment.
10 is a block diagram showing a configuration of a timing controller, a data driving circuit, and a level shifter shown in FIG. 1 according to a fourth embodiment.
11 is a waveform diagram specifically illustrating a gate control signal whose transmission timing is corrected according to a fourth embodiment.

The above-described objects, features, and advantages will be described in detail below with reference to the accompanying drawings, and accordingly, a person skilled in the art to which the present invention pertains can easily implement the technical spirit of the present invention. In the description of the present invention, when it is determined that detailed descriptions of known technologies related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions will be omitted. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram specifically showing an image display device according to an embodiment of the present invention.

1 illustrates an example in which an organic light emitting diode display is applied as an image display device, in addition to an organic light emitting diode display, a liquid crystal display, an electroluminescent display, or an electronic wet display may be applied.

As shown in FIG. 1, the organic light emitting diode display device includes an image display panel PA, a timing controller 80, a data driving circuit 40, a level shifter 20, and a gate driving circuit 30.

The image display panel PA is divided into an image display area AD and an image non-display area ND, and a plurality of pixel areas P are defined in the image display area AD, and sub-pixels configured in each pixel area Display video through them. In addition, a plurality of data circuit films 60 are attached to the non-display area ND, or at least one gate driving circuit 30 is mounted.

Specifically, sub-pixels are formed in the pixel area P in a matrix form defined by the plurality of gate lines GL1 to GLn and the data lines DL1 to DLm in the image display area AD. Here, each sub-pixel includes at least one thin film transistor (TFT), an organic light emitting diode, and the like, thereby emitting light corresponding to the size of the data voltage.

FIG. 2 is a view showing an equivalent circuit of one sub-pixel shown in FIG. 1.

Referring to FIG. 2, each sub-pixel includes a pixel circuit connected to each gate line GL, data line DL, sensing voltage output line DV, and the like, and a pixel circuit and a low potential power signal VSS. And an organic light emitting diode (OLED), which is connected between and equivalently represented by a diode.

The pixel circuit may be configured as a source folloewr type compensation circuit structure, and the first and second switching elements T1 and T2, the first stabilization element C, and the driving switching element DT And the like.

Specifically, the first switching element T1 of the pixel circuit is switched by the gate-on signal from the gate line GL to drive the data voltage from the corresponding data line DL. The first node to which the switching element DT is connected (N1).

The second switching element T2 transmits the sensing voltage applied to the organic light emitting diode OLED to the sensing voltage output line DV in response to the gate-on signal or the sensing signal.

In the driving switching element DT, the first node N1 is connected to the gate terminal, the second node N2 is connected to the drain terminal, and the third node N3 is connected to the source terminal (or the driving voltage input terminal). It is configured to be electrically connected. Accordingly, the driving switching element DT is a data voltage input through the first node N1 and the first stabilization element C, and a compensation input through the second switching element T2 and the second node N2. The data voltage of the data line DL is transmitted to the organic light emitting diode OLED according to the voltage Vref.

The first stabilization element C is connected between the first node N1 and the second node N2 of the driving switching element DT to maintain the data voltage for one frame.

A second stabilization element C2 for stabilizing the output of the sensing voltage may be additionally configured in the sensing voltage output line DV.

The timing controller 80 receives synchronization signals (eg, vertical and horizontal synchronization signals, timing clocks, dot clocks, etc.) from the outside so that the gate lines GL1 to GLn of the image display panel PA can be driven. To generate a gate control signal. Here, the gate control signal is a scan control signal for setting a pulse width of a scan pulse output from the gate driving circuits 20 and 30, an enable control signal for setting a frame period or a data enable period, and a sensing voltage is detected. It includes a sensing clock signal to control as much as possible.

In addition, the timing controller 80 arranges digital image data input from an external graphic system or the like according to driving characteristics such as resolution and driving frequency of the image display panel PA. In addition, the timing controller 80 generates a data control signal using synchronization signals from the outside so that a data voltage can be supplied to the data lines DL1 to DLm of the image display panel PA. Here, the data control signal includes a timing control clock, a data enable signal, and a data shift clock signal.

The timing controller 80 transmits the data control signal to the data driving circuit 40 together with the aligned image data, and at the same time, transmits the gate control signal to the gate driving circuits 20 and 30. At this time, the timing controller 80 converts the aligned image data and data control signals to a format conforming to the EPI (Embedded Clock Point-Point Interface) protocol, and a data driving circuit using a low voltage differential signaling (LVDS) interface method. (40).

The LVDS interface method allows multiple channels to be connected between a transmitting device (eg, a timing controller 80 and a receiving device (eg, a data driving circuit 40)) and converts digital data or control signals into LVDS signal levels. The digital data or control signal converted to the LVDS signal level is transmitted through a plurality of preset channels, whereby the timing controller 80 sorts the image data and data control signals into a preset EPI protocol format. Converted to LVDS signal level and transmitted to the data driving circuit 40 through a preset multiple channel.

In addition, the timing controller 80 performs AVC (ADC Variation Compensation) deviation compensation to compensate for deviations between integrated circuits of the data driving circuit 40. To this end, the timing controller 80 receives respective sensing voltage values transmitted from the plurality of sensing voltage output lines DV through the data driving circuit 40. Then, the driving deviation of each organic light emitting diode (OLED) configured in the sub-pixels at a predetermined position is detected. Subsequently, the timing controller 80 generates compensation data to compensate for the driving deviation of the organic light emitting diode (OLED) of the sub-pixels, so that the gradation value of the image data input from the outside can be compensated according to the compensation data. The gradation value-compensated image data is aligned with driving characteristics such as resolution and driving frequency as described above, and transmitted to the data driving circuit 40.

As described above, the timing controller 80 generates gate control signals including a scan control signal, an enable control signal, and a sensing clock signal and transmits them to the gate driving circuits 20 and 30.

The data driving circuit 40 is mounted on the printed circuit film 60 between at least one side of the image display panel PA and the at least one source printed circuit board 100, so that the data lines DL1 to DLm are provided. It includes at least one integrated circuit for supplying a data voltage. The data driving circuit 40 restores the data control signal received through the LVDS interface method in a TTL (Transistor Transistor Logic) format. Then, the compensated image data is converted into an analog voltage, that is, a data voltage of each pixel, using the restored data control signal, and then supplied to the data lines DL1 to DLm.

In addition, the data driving circuit 40 is a control for controlling the gate driving circuits 20 and 30 using at least one clock or signal among data control signals (for example, a timing control clock and a data enable signal). Generate a clock signal. The data driving circuit 40 transmits the control clock signal to the gate driving circuits 20 and 30 in a TTL format.

The TTL interface method is a method in which at least one clock or digital signal is aligned with TTL (Transistor Transistor Logic) level serial data (hereinafter, TTL format conversion) and transmitted through TTL signal lines. Accordingly, TTL signal wires to transmit TTL signals are connected between the data driving circuit 40 and the gate driving circuits 20 and 30. Accordingly, the data driving circuit 40 generates a control clock signal in a TTL level signal state and transmits it to the gate driving circuits 20 and 30 through the TTL signal wiring.

In addition, the data driving circuit 40 converts the control clock signal into the LVDS format together with the sensing voltage values received through each sensing voltage output line DV. Then, the sensing voltage values converted into the LVDS format and the control clock signal are transmitted to the timing controller 80 every blank period during which no data voltage is output to the data lines DL1 to DLm.

Accordingly, the timing controller 80 generates compensation data using the sensing voltage value received during the blank period. Then, a gate control signal is generated and synchronized with the control clock signal from the data driving circuit 40 and transmitted to the gate driving circuits 20 and 30. Accordingly, the input timing of the control clock signal and the gate control signals input to the gate driving circuits 20 and 30 may be synchronized.

The gate driving circuits 20 and 30 are configured to sequentially output scan pulses to the gate lines GL1 to GLn, and include a level shifter 20 and a shift register 30.

The level shifter 20 controls the driving timing of the shift register 30 using a control clock signal received from the data driving circuit 40, a scan control signal received from the timing controller 80, and an enable control signal. can do. For example, the level shifter 20 generates at least one carry signal for controlling the scan pulse output timing of the shift register 30 according to the control clock signal, the scan control signal, and the enable control signal. 30).

In addition, the level shifter 20 sequentially generates a sensing control clock for controlling the sensing timing using the sensing clock signal among the gate control signals, and transmits the sensed control clock to the shift register 30.

The level shifter 20 may be mounted on the timing controller 80 and a separate main substrate 100, or may be mounted on the data driving circuit 40 and the printed circuit film 60. In addition, the level shifter 20 may be mounted on the printed circuit board 10 closest to the configuration position of the shift register 30, or may be configured to be included in the shift register 30.

Hereinafter, an example in which the level shifter 20 is mounted in a specific area of the printed circuit board 10 closest to the configuration position of the shift register 30 will be described. It is most advantageous that the level shifter 20 is configured in an area in which the interface distance of the shift register 30 and the TTL communication format is closest.

The shift register 30 includes a plurality of gate stages sequentially outputting scan pulses to the gate lines GL1 to GLn, and a plurality of sensing signal output stages sequentially transmitting sensing control clocks to the sensing signal line. Can be configured.

The shift register 30 configured as described above is enabled according to the enable control signal received from the level shifter 20, sequentially shifts the carry signals from the level shifter 20 during the enable period to sequentially scan pulses. To create. The scan pulses are sequentially supplied to each gate line GL1 to GLn. Also, the shift register 30 may sequentially generate a sensing signal and transmit the sensing signal to a sensing signal transmission line (not shown) even when a plurality of sensing control clocks having different phases are shifted.

3 is a block diagram showing the configuration of the timing controller, data driving circuit, and level shifter shown in FIG. 1 according to the first embodiment.

Referring to FIG. 3, the timing controller 80 includes a data alignment unit 81, a data compensation unit 82, an EPI control signal generation unit 83, a first LVDS transmission unit 84, and a first LVDS reception unit 85 ).

The first LVDS receiving unit 85 receives sensing voltage values of corresponding sub-pixels through integrated circuits of the data driving circuit 40 during every horizontal line driving period (hereinafter, a horizontal period) or a blank period of every frame period. In addition to the sensing voltage values, the control clock signal CLK (a) may be further received.

The data compensator 82 generates compensation data using the sensing voltage values received through the first LVDS receiver 85 and compensates for the gradation value of the image data according to the compensation data. Specifically, the data compensator 82 compares sensing voltage values received through the first LVDS receiver 85 to each other to compensate for AVC deviations between integrated circuits of the data driving circuit 40 to the sub-pixels. The driving deviation of each configured organic light emitting diode (OLED) is detected.

Subsequently, the data compensator 82 generates compensation data so that the driving deviation of the organic light emitting diode OLED can be compensated, and compensates the gradation value of the image data input from the outside using the compensation data. The gradation value of the image data input from the outside is adjusted according to the compensation data.

The data alignment unit 81 arranges image data whose grayscale values are compensated by the data compensation unit 82 according to driving characteristics such as resolution and driving frequency of the image display panel PA, and converts the converted LVDS format to the first LVDS. It transmits to the transmitter 84.

The EPI control signal generation unit 83 controls the scan driving signal GData, the enable control signal VD, and the sensing to control the gate driving circuits 20 and 30 according to the driving characteristics of the image display panel PA. Gate control signals including a clock signal are generated. Specifically, set values such as phase, period, amplitude, and pulse width for each signal are set so that the scan control signal GData, the enable control signal VD, and the sensed clock signals can be generated. In addition, the EPI control signal generation unit 83 generates gate control signals GData and VD according to the reception timing of the control clock signal CLK (a) received from the data driving circuit 40. ). That is, the EPI control signal generator 83 generates gate control signals GData to be synchronized with the transmission timing of the control clock signal CLK (a) transmitted from the data driving circuit 40 to the gate driving circuits 20 and 30. , VD) to the gate driving circuits 20 and 30.

In addition, the EPI control signal generator 83 includes a timing control clock, a data enable signal, and a data shift clock signal to control the data driving circuit 40 according to the driving characteristics of the image display panel PA. Generate data control signals. Then, the EPI control signal generation unit 83 converts the data control signal into the LVDS format and transmits it to the first LVDS transmission unit 84.

The first LVDS transmitting unit 84 transmits the data control signal converted to the LVDS format to the data driving circuit 40 during the control packet transmission period during at least one horizontal period. In addition, during at least one horizontal period, the compensated image data for at least one horizontal line converted to LVDS format is transmitted to the data driving circuit 40 during the data transmission period.

Referring to FIG. 3, the data driving circuit 40 includes a compensation data generator 41, a memory 42, a compensation controller 43, an LVDS control signal generator 44, a second LVDS receiver 45, and 2 LVDS transmission section 46, and a dividing circuit section 47.

The compensation data generation unit 41 converts the sensed voltage values received through the sensing voltage output lines DV of the image display panel PA into LVDS format under the control of the compensation control unit 43, and then transmits the second LVDS transmitter ( 84).

The LVDS control signal generating unit 44 restores the data control signal and the compensated and aligned image data received in at least one horizontal line through the second LVDS receiving unit 45 in the TTL format.

The compensation control unit 43 stores the sensed voltage values converted to the LVDS format by the compensation data generation unit 41 in the memory 42. Then, the sensing voltage values of the LVDS format and the control clock signal CLK (a) are controlled to be transmitted to the timing controller 80 in the LVDS interface method through the second LVDS transmitter 46. At this time, the compensation control unit 43 detects the LVDS format sensing voltage values and the control clock signal CLK (a) in the second LVDS transmitter 84 for each blank period during which no data voltage is output to the data lines DL1 to DLm. It is controlled to be transmitted to the timing controller 80.

The dividing circuit unit 47 divides at least one clock or signal (for example, a timing control clock and a data enable signal) from a data control signal received from the timing controller 80 at a predetermined period, thereby generating a gate driving circuit 20, 30) A control clock signal CLK (a) for controlling the driving timing is generated. Then, the division circuit unit 47 transmits the control clock signal CLK (a) to the memory 42 and the compensation control unit 43 so that the control clock signal CLK (a) is converted into the LVDS format. Accordingly, the compensation control unit 43 transmits the control clock signal CLK (a) to the timing controller 80 together with the sensed voltage values converted to the LVDS format. On the other hand, the division circuit unit 47 transmits the control clock signal CLK (a) to the gate driving circuits 20 and 30 in units of at least one horizontal period or frame period.

The level shifter 20 shown in FIG. 3 includes a gate control signal receiver 21, a TTL signal converter 22, and a shift control signal output 23.

The gate control signal receiving unit 21 receives the control clock signal CLK (a) from the frequency division circuit unit 47, and the scan control signal GData, enable control signal VD, and sensing from the timing controller 80. The clock signal is received. As described above, the timing controller 80 generates a scan control signal GData and an enable control signal VD to be synchronized with the control clock signal CLK (a) from the data driving circuit 40 to generate a level shifter. (20). Accordingly, the control clock signal CLK (a), the scan control signal GData, and the enable control signal VD are input to the gate control signal receiving unit 21 at the same timing.

The TTL signal conversion unit 22 TTL the at least one of the control clock signal CLK (a), the scan control signal GData, and the enable control signal VD received by the gate control signal receiving unit 21. It can be modulated in a communication format.

The shift control signal output unit 23 uses the control clock signal CLK (a), the scan control signal GData, and the enable control signal VD restored to the TTL communication format by the TTL signal conversion unit 22. Then, at least one carry signal GST, a plurality of clock pulses Gclk, and a plurality of sensing control clocks are sequentially generated and transmitted to the shift register 30.

4 is a waveform diagram illustrating a transmission timing error of a gate control signal transmitted from the timing controller shown in FIG. 3 to a level shifter.

The data driving circuit 40 transmits the control clock signal CLK only to the gate driving circuits 20 and 30, and the timing controller 80 separately transmits scan control signals and enable control signals to the gate driving circuits 20 and 30. 4, the transmission timings of the control clock signal CLK, the scan control signal GData, and the enable control signal VD may vary.

In the case of Case 1 (Case 1) of FIG. 4, the control clock signal CLK of the data driving circuit 40 is delayed for a predetermined period d1 compared to the enable control signal VD of the timing controller 80 and the level shifter ( 20).

On the other hand, in case 2 (Case 2) of FIG. 4, the control clock signal CLK of the data driving circuit 40 is compared to the enable control signal VD of the timing controller 80 for a certain period of time (d2), and the level shifter rapidly (20).

As shown in FIG. 4, when the input timings of the enable control signal VD and the control clock signal CLK input to the level shifter 20 are different, a carry signal GST output timing of the level shifter 20 and a plurality of clocks A problem occurs in that the pulse Gclk output timing becomes unstable.

5 is a waveform diagram specifically illustrating a gate control signal whose transmission timing is corrected according to the first embodiment.

The data driving circuit 40 according to the first embodiment of the present invention generates a control clock signal CLK (a) and transmits it to the timing controller 80 and the gate driving circuits 20 and 30. Accordingly, the timing controller 80 uses the scan control signal GData and the enable control signal VD to synchronize the control clock signal CLK (a) from the data driving circuit 40 to the gate driving circuit 20, 30).

Thus, as illustrated in FIG. 5, the input timing of the enable control signal VD and the control clock signal CLK (a) input to the level shifter 20 may be the same. That is, when the input timing of the control clock signal CLK (a) input from the data driving circuit 40 to the timing controller 80 is delayed, the timing controller 80 delays the control clock signal CLK (a). The enable control signal VD may be delayed and transmitted to the level shifter 20 to be synchronized with the period A1.

In addition, when the input timing of the control clock signal CLK (a) input from the data driving circuit 40 to the timing controller 80 is fast, the timing controller 80 rapidly controls the control clock signal CLK (a). The enable control signal VD may be transmitted to the level shifter 20 in synchronization with the input period A2.

6 is a block diagram showing the configuration of the timing controller, data driving circuit, and level shifter shown in FIG. 1 according to the second embodiment. 7 is a waveform diagram specifically showing a gate control signal whose transmission timing is corrected according to the second embodiment.

Referring to FIG. 6, the EPI control signal generator 83 of the timing controller 80 according to the second embodiment transmits the scan control signal GData and the enable control signal VD to the level shifter 20. do. At this time, the enable control signal VD is simultaneously transmitted to the data driving circuit 40.

The data driving circuit 40 compares the input timing of the enable control signal VD from the timing controller 80 and at least one clock or signal (eg, timing control clock, data enable signal) of the data control signal. Thus, a logic gate circuit unit 48 for outputting a comparison signal of a predetermined logic level at the same input timing is further included.

Accordingly, the division circuit unit 47 generates a control clock signal CLK (b) at the input timing of the comparison signal of the logic level and transmits it to the level shifter 20.

As illustrated in FIG. 7, the input timing of the enable control signal VD input to the level shifter 20 and the control clock signal CLK (b) may be the same. That is, the input of the enable control signal VD input from the timing controller 80 to the level shifter 20 and the control clock signal CLK (b) input from the data driving circuit 40 to the level shifter 20. The timing can be the same.

When the enable control signal VD input from the timing controller 80 to the level shifter 20 is delayed, the control clock of the data driving circuit 40 is synchronized with the delay period B1 of the enable control signal VD. The signal CLK (b) generation period may be delayed. On the other hand, when the enable control signal VD input from the timing controller 80 to the level shifter 20 is fast, the control clock signal of the data driving circuit 40 is synchronized with the input timing of the enable control signal VD. The production period of (CLK (b)) can also be accelerated.

8 is a block diagram illustrating a configuration of a timing controller, a data driving circuit, and a level shifter shown in FIG. 1 according to a third embodiment. 9 is a waveform diagram specifically showing a gate control signal whose transmission timing is corrected according to the third embodiment.

Referring to FIG. 8, the EPI control signal generation unit 83 of the timing controller 80 according to the third embodiment includes a scan control signal GData and an enable control signal VD as the first filter unit 86. Transfer to. Then, the first filter unit 86 delays the scan control signal GData and the enable control signal VD for a first preset delay period and transmits them to the level shifter 20 of the gate driving circuit.

The first filter unit 86 may be built in the timing controller 80 or the data driving circuit 40, or may be separately configured from the timing controller 80 and the like.

At this time, the division circuit part 47 of the data driving circuit 40 generates a control clock signal CLK (c) and transmits it to the second filter part 49. Then, the second filter unit 49 delays the control clock signal CLK (c) for a preset second delay period and transmits the delayed delay to the level shifter 20 of the gate driving circuit. The second filter unit 49 may also be embedded in the timing controller 80 or the data driving circuit 40, and may be separately configured from the data driving circuit 40 and the like.

The first filter unit 86 includes an RC circuit or an RLC circuit, and a scan control signal GData and an enable control signal VD are generated during a first delay period by device values of each RC circuit or RLC circuit. The delay is transmitted to the level shifter 20. The element value of each RC circuit or RLC circuit included in the first filter unit 86 and the first delay period are determined by the output timing of the scan control signal GData and the enable control signal VD of the timing controller 80. It can be preset accordingly.

The second filter unit 49 also includes an RC circuit or an RLC circuit, and the level shifter 20 by delaying the control clock signal CLK (c) during the second delay period by the element value of each RC circuit or RLC circuit. Will be sent to The element value and the second delay period of each RC circuit or RLC circuit included in the second filter unit 49 are the first delay period set in the first filter unit 86 and the control clock signal of the data driving circuit 40 (CLK (c)) may be set in advance according to the output timing. That is, the first delay period set in the first filter unit 86 and the second delay period set in the second filter unit 49 are control clock signals CLK (c) input to the level shifter 20. And scan control signals GData and enable control signals VD may be set to be the same.

Accordingly, as illustrated in FIG. 9, the input timing of the filtered enable control signal fVD and the control clock signal CLK (c) input to the level shifter 20 may be the same. That is, according to the filtering period F1 of the enable control signal fVD and the control clock signal CLK (c) from the timing controller 80, the enable control signal fVD input to the level shifter 20 and The input timing of the control clock signal CLK (c) may be the same.

10 is a block diagram showing a configuration of a timing controller, a data driving circuit, and a level shifter shown in FIG. 1 according to a fourth embodiment. 11 is a waveform diagram specifically illustrating a gate control signal whose transmission timing is corrected according to the fourth embodiment.

Referring to FIG. 10, the EPI control signal generation unit 83 of the timing controller 80 according to the fourth embodiment scan scan signal GData according to the delay period control value dData from the delay control memory 87. , And delay the enable control signal dVD to transmit to the level shifter 20 of the gate driving circuit.

At this time, the division circuit unit 47 of the data driving circuit 40 generates a control clock signal CLK (d) in units of at least one horizontal period or frame period and transmits it to the level shifter 20 of the gate driving circuit.

The delay period control value dData that is preset in the delay control memory 87 may be preset in accordance with the control clock signal CLK (d) output timing of the data driving circuit 40. That is, the delay period control value dData preset in the delay control memory 87 is a control clock signal CLK (c) input to the level shifter 20 and a delayed state input to the level shifter 20. The input timing of the enable control signal dVD may be set in advance.

Accordingly, as illustrated in FIG. 11, the input timings of the delayed enable control signal dVD and the control clock signal CLK (d) input to the level shifter 20 may be the same. That is, according to the delay period D1 of the enable control signal dVD from the timing controller 80, the enable control signal dVD input to the level shifter 20 and the control clock signal CLK (d) The input timing can be the same.

As described above, the image display device and the driving method according to an embodiment of the present invention having the above-described technical characteristics include control clock signals CLK (a), CLK (b), which are one of gate control signals in a data driving circuit, The number of gate control signals transmitted from the timing controller 80 to the gate driving circuits 20 and 30 is generated by generating and transmitting the CLK (c) and CLK (d) to the gate driving circuits 20 and 30. Can be reduced.

In addition, in the present invention, at least one gate control signal transmitted from the timing controller 30 to the gate driving circuits 20 and 30, and a control clock signal transmitted from the data driving circuit 40 to the gate driving circuits 20 and 30 The transmission timings of (CLK (a), CLK (b), CLK (c), and CLK (d)) are synchronized. Accordingly, according to the present invention, it is possible to maintain the same scan pulse output timing for each frame of the gate driving circuits 20 and 30 and increase its reliability.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical details of the present invention. It will be clear to those who have the knowledge of Therefore, the scope of the present invention is indicated by the following claims, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted to be included in the scope of the present invention.

10: Printed circuit board
20: level shifter
30: shift register
40: data driving circuit
60: printed circuit film
80: timing controller
100: main board

Claims (17)

A timing controller for outputting image data and data control signals aligned with driving characteristics of the image display panel using an LVDS interface, and outputting a gate control signal for driving a gate line of the image display panel using a TTL interface;
A data driving circuit which drives data lines of the image display panel according to the image data and the data control signal, and generates and outputs a control clock signal for driving the gate line; And
And a gate driving circuit for driving the gate line using a gate control signal from the timing controller and a control clock signal from the data driving circuit,
Video display device.
According to claim 1,
The data driving circuit
The control clock signal is generated by dividing at least one timing control clock or data enable signal among the data control signals at a preset period,
The control clock signal is transmitted to the timing controller in an LVDS interface method, and the gate driving circuit is transmitted in a TTL interface method.
Video display device.
According to claim 2,
The data driving circuit
The control clock signal is converted into an LVDS format along with sensing voltage values received through sensing voltage output lines of the image display panel, and sensing converted to the LVDS format every blank period during which no data voltage is output to the data lines. Transmitting voltage values and a control clock signal to the timing controller,
Video display device.
According to claim 2,
The timing controller
The gate control signal is transmitted to the gate driving circuit so as to be synchronized with the input timing of the control clock signal input from the data driving circuit.
Video display device.
According to claim 2,
The timing controller
A data compensator for generating compensation data using sensing voltage values received from the data driving circuit through a first LVDS receiver and compensating for a gradation value of the image data according to the compensation data;
A data alignment unit that aligns image data whose grayscale value is compensated in the data compensation unit according to driving characteristics of the image display panel and converts the image data into an LVDS format;
The gate control signal including the scan control signal, the enable control signal, and the sensing clock signal is generated, and the gate control signal is transmitted to the gate driving circuit in synchronization with the input timing of the control clock signal input from the data driving circuit. An EPI control signal generator;
And a first LVDS transmission unit transmitting the aligned image data of at least one horizontal line converted to the LVDS format to the data driving circuit,
Video display device.
The method of claim 5,
The data driving circuit
A compensation data generator configured to convert sensing voltage values received through sensing voltage output lines of the image display panel into an LVDS format;
An LVDS control signal generator configured to restore the data control signal received through the second LVDS receiver and the aligned image data in a TTL format;
A compensation control unit configured to control the sensing voltage values of the LVDS format and the control clock signal to be transmitted to the timing controller in a LVDS interface method through a second LVDS transmitter; And
The control clock signal is generated by dividing at least one timing control clock or data enable signal among the data control signals at a preset period, and transmitting the control clock signal to the compensation control unit and the second LVDS transmission unit. Including a divided circuit for transmitting to the gate driving circuit,
Video display device.
According to claim 1,
The data driving circuit
An enable control signal of one of the gate control signals output from the timing controller is received, and an input timing of the enable control signal and at least one control signal input timing of the data control signals are compared with an input timing to be preset in advance. A logic gate circuit unit outputting a logic level comparison signal; And
And a dividing circuit unit that generates the control clock signal at the logic level comparison signal input timing and transmits the control clock signal to the gate driving circuit.
Video display device.
According to claim 1,
A first filter unit delaying the scan control signal and the enable control signal among the gate control signals output from the timing controller for a first preset delay period and transmitting the delayed scan signal to the gate driving circuit; And
Further comprising a second filter unit for delaying the control clock signal output from the data driving circuit for a preset second delay period to transmit to the gate driving circuit at the same timing as the transmission timing of the scan control signal and the enable control signal. doing,
Video display device.
According to claim 1,
The timing controller
The scan control signal and the enable control signal among the gate control signals are delayed according to the delay period control value from the delay control memory and transmitted to the gate driving circuit.
The preset delay period control value is a preset value such that the input timing of the control clock signal input to the gate driving circuit and the enable control signal input to the gate driving circuit in the delayed state is the same. ,
Video display device.
Outputting image data aligned with driving characteristics of the image display panel and a data control signal from the timing controller using an LVDS interface method;
Outputting a gate control signal for driving a gate line of the image display panel in a TTL interface method;
Generating and outputting a control clock signal for driving the gate line in a data driving circuit driving data lines of the image display panel; And
And driving the gate line using a gate control signal from the timing controller and a control clock signal from the data driving circuit.
Method of driving a video display device.
The method of claim 10,
The step of generating and outputting the control clock signal is
Generating the control clock signal by dividing at least one timing control clock or data enable signal among the data control signals at a preset period; And
In addition to transmitting the control clock signal to the timing controller in an LVDS interface method, including the step of transmitting to the gate driving circuit in a TTL interface method,
Method of driving a video display device.
The method of claim 11,
The step of transmitting the control clock signal to the timing controller
Converting the control clock signal into an LVDS format along with sensing voltage values received through sensing voltage output lines of the video display panel; And
The method further includes transmitting sensing voltage values converted to the LVDS format and the control clock signal to the timing controller every blank period during which no data voltage is output to the data lines.
Method of driving a video display device.
The method of claim 11,
The step of outputting the gate control signal in a TTL interface method is
And transmitting the gate control signal to the gate driving circuit so as to be synchronized with an input timing of a control clock signal input from the data driving circuit.
Method of driving a video display device.
The method of claim 11,
The step of outputting the gate control signal in a TTL interface method is
Generating the gate control signal including a scan control signal, an enable control signal, and a sensing clock signal;
And transmitting the gate control signal to the gate driving circuit so as to be synchronized with an input timing of a control clock signal input from the data driving circuit.
Method of driving a video display device.
The method of claim 10,
The step of generating and outputting the control clock signal is
Logic gate circuit unit is used to compare the input timing of the enable control signal of one of the gate control signals output from the timing controller with the input timing of at least one of the data control signals, and a logic level set in advance at the same input timing. Allowing the comparison signal of the to be output;
And generating the control clock signal at the input timing of the comparison signal of the logic level and transmitting the control clock signal to the gate driving circuit.
Method of driving a video display device.
The method of claim 10,
The scan control signal and the enable control signal among the gate control signals output from the timing controller are delayed for a first preset delay period by using a first filter unit, and the delayed scan control signal and the enable control signal are applied to the gate driving circuit. Transmitting to; And
The control clock signal output from the data driving circuit is delayed for a preset second delay period by using a second filter unit, and the control clock signal is transmitted at the same timing as the transmission timing of the scan control signal and the enable control signal. Transmitting to the gate driving circuit,
Method of driving a video display device.
The method of claim 10,
The step of outputting the gate control signal in a TTL interface method is
And delaying the scan control signal and the enable control signal among the gate control signals according to the delay period control value from the delay control memory and transmitting the delayed scan control signal to the gate driving circuit.
The preset delay period control value is a preset value such that the input timing of the control clock signal input to the gate driving circuit and the enable control signal input to the gate driving circuit in the delayed state is the same. ,
Method of driving a video display device.

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