KR102555098B1 - Image display device and method for driving the same - Google Patents

Abstract

An image display device and its driving method are disclosed. An image display device according to an embodiment of the present invention includes a timing controller outputting image data and a gate control signal aligned according to driving characteristics of the image display panel through an LVDS interface method, and an image display panel according to image data received through the LVDS interface method. A data driving circuit that drives the data lines of and outputs the gate control signal in the LVDS interface method, and receives the gate control signal in the LVDS interface method through the data driving circuit and restores the gate control signal to the TTL communication format to the gate driving circuit. Since a level shifter is included, the number of gate control signal transmission pins or input/output channels from the timing controller to the level shifter can be minimized.

Description

Image display device and its driving method {IMAGE DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

The present invention is an image display device capable of reducing the number of transmission pins or input/output channels of gate control signals and minimizing the arrangement area of gate control signal transmission lines by improving an interface method for gate control signals of an image display device. and a driving method thereof.

Recently, flat-type image display devices such as liquid crystal displays, organic light emitting diode displays, electroluminescent displays, and field emission devices have been developed to realize large screens with high resolution in order to realize more satisfactory screens.

A flat-panel image display device displays an image by controlling light transmittance or light emission of each pixel through an image display panel in which a plurality of pixels are arranged in a matrix form. To this end, panel driving circuits such as gate and data control circuits and timing controllers are mounted or electrically connected to the image display panel.

As a communication method for transmitting and receiving image data or timing control signals between a timing controller and gate and data control circuits, a TTL (Transistor-Transistor Logic) signal interface method and a LVDS (Low Voltage Differential Signaling) interface method are used. . Here, the LVDS interface method is a method of converting and transmitting a TTL signal into an LVDS format using an EPI (Embedded Clock Point-Point Interface) protocol, and restoring the transmitted LVDS format data into a TTL signal.

Among them, the TTL signal interface method is a method in which the number of signal transmission lines inevitably increases according to the number of bits of data. On the other hand, the LVDS interface method can reduce the number of signal transmission wires, but requires complex modulation processes and circuits such as converting a TTL signal into an LVDS format and restoring it.

Accordingly, conventional flat panel image display devices are configured to selectively apply a TTL signal interface method or an LVDS interface method according to transmission targets of image data or timing control signals.

However, since the strengths and weaknesses of the TTL signal interface method and the LVDS interface method are clearly defined, even if the interface method is changed and applied, each of the disadvantages must be endured, so there is no choice but to increase the efficiency.

For example, when a flat panel type image display device is formed with a large screen and high resolution according to the trend, since the image data capacity and timing control signals increase, the number of signal wires and channels inevitably increases even more drastically. For this reason, the TTL signal interface method has no choice but to consider the increase in signal wiring, and the LVDS interface method also has no choice but to make the signal modulation process and circuit more complicated.

In this way, in the prior art, even if an interface method is selectively changed and set and applied to various types of image display devices, there is no choice but to increase interface efficiency.

The present invention is to solve the above problems, by improving an interface method for gate control signals, reducing the number of transmission pins or input/output channels of gate control signals, and minimizing the layout area of gate control signal transmission lines. An object of the present invention is to provide an image display device and a driving method thereof.

An image display device according to an embodiment of the present invention for achieving the above object is a timing controller that outputs image data and gate control signals aligned to the driving characteristics of an image display panel through an LVDS interface method, and receives them through an LVDS interface method. A data driving circuit that drives the data lines of the image display panel according to the image data to be generated and outputs the gate control signal through the LVDS interface method, and receives the gate control signal through the LVDS interface method through the data driving circuit and transmits the gate control signal through TTL communication. A level shifter for restoring the data into a format and transmitting the data to the gate driving circuit is included.

In addition, a method for driving a video display device according to an embodiment of the present invention for achieving the above object includes the steps of outputting image data and gate control signals aligned to the driving characteristics of an image display panel in an LVDS interface method, LVDS Driving the data lines of the image display panel according to the image data received through the interface method and transmitting the gate control signal through the LVDS interface method; and receiving the gate control signal through the LVDS interface method and converting the gate control signal to TTL through a level shifter. and restoring it to a communication format and transmitting it to a gate driving circuit.

An image display device and its driving method according to an embodiment of the present invention having various technical features as described above allow gate control signals of the image display device to be transmitted to a data driving circuit together with image data through an LVDS interface method using an EPI protocol. . In addition, the number of gate control signal transmission pins or input/output channels from the timing controller to the level shifter can be minimized by allowing the gate control signal to be transmitted between the data driving circuit and the level shifter of the gate driving circuit through the LVDS interface method.

In addition, by minimizing the arrangement area of the gate control signal transmission lines between the timing controller and the level shifter or the timing controller and the gate driving circuit, the non-display area of the image display panel, the printed circuit board and the printed circuit film on which the driving circuit is mounted, It has the effect of minimizing the size.

1 is a detailed configuration diagram of an image display device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating an equivalent circuit of any one sub-pixel shown in FIG. 1 .
FIG. 3 is a configuration diagram showing the timing controller, data driving circuit, and level shifter shown in FIG. 1 in detail.
FIG. 4 is a timing diagram specifically illustrating the structure of a data packet transmitted from the timing controller of FIG. 3 to a data driving circuit.
FIG. 5 is a timing diagram specifically illustrating a data packet transmitted to a level shifter in the data driving circuit of FIG. 3 and an output signal of the level shifter.
6 is a graph showing a change in noise due to electromagnetic interference between level shifters in a data driving circuit.

The above objects, features and advantages will be described later in detail with reference to the accompanying drawings, and accordingly, those skilled in the art to which the present invention belongs will be able to easily implement the technical spirit of the present invention. In describing the present invention, if it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a detailed configuration diagram of an image display device according to an embodiment of the present invention.

Although FIG. 1 shows an example in which an organic light emitting diode display is applied as an image display device, a liquid crystal display, an electroluminescent display, or an electrowetting display may be applied in addition to the organic light emitting diode display.

As shown in FIG. 1 , the organic light emitting diode display includes an image display panel (PA), a timing controller 80, a data driving circuit 40, a level shifter 20, and a gate driving circuit 30.

The image display panel (PA) is divided into an image display area (AD) and an image non-display area (ND), and a plurality of pixel areas (P) are defined in the image display area (AD), and sub-pixels are formed in each pixel area. display images through A plurality of data circuit films 60 are attached or at least one gate driving circuit 30 is mounted in the image non-display area ND.

Specifically, in the image display area AD, sub-pixels are formed in a matrix-shaped pixel area P defined by a plurality of gate lines GL1 to GLn and data lines DL1 to DLm. Here, each sub-pixel is configured to include at least one Thin Film Transistor (TFT) and an organic light emitting diode, thereby emitting light in response to the size of the data voltage.

FIG. 2 is a diagram illustrating an equivalent circuit of any one sub-pixel shown in FIG. 1 .

Referring to FIG. 2 , each sub-pixel includes a pixel circuit connected to each gate line GL, data line DL, sensing voltage output line DV, etc., and the pixel circuit and the low potential power signal VSS. It includes an organic light emitting diode (OLED) connected therebetween and equivalently represented by a diode.

The pixel circuit may be composed of a source follower-type compensation circuit structure, and includes first and second switching elements T1 and T2, a first stabilization element C1, and a driving switching element DT. It can be configured including, etc.

Specifically, the first switching element T1 of the pixel circuit is switched by a gate-on signal from the gate line GL to drive the data voltage from the corresponding data line DL to the first node to which the switching element DT is connected. Transfer to (N1).

The second switching element T2 transmits the sensing voltage applied to the organic light emitting diode OLED to the sensing voltage output line DV in response to the gate-on signal or the sensing signal.

In the driving switching element DT, a first node N1 is connected to a gate terminal, a second node N2 is connected to a drain terminal, and a third node N3 is connected to a source terminal (or a driving voltage input terminal). It is configured to be electrically connected. Accordingly, the driving switching element DT compensates for the data voltage input through the first node N1 and the first stabilization element C1 and the compensation input through the second switching element T2 and the second node N2. The data voltage of the data line DL is transmitted to the organic light emitting diode OLED according to the voltage Vref.

The first stabilization element C1 is connected between the first node N1 and the second node N2 of the driving switching element DT, and serves to maintain the data voltage for one frame.

A second stabilization element C2 for output stabilization of the sensing voltage may be additionally configured in the sensing voltage output line DV.

In order to drive the sub-pixels of the image display panel PA configured as described above, the timing controller 80 converts digital image data input through an external graphic system to the resolution and driving frequency of the image display panel PA. Align them according to driving characteristics.

In addition, the timing controller 80 receives synchronizing signals from the outside (for example, vertical and horizontal synchronizing signals, timing clocks, dot clocks, etc.) so that the gate lines GL1 to GLn of the image display panel PA can be driven. ) to generate a gate control signal. Here, the gate control signal includes a gate start signal, a gate reset signal, a carry clock signal, a carry main clock, a gate clock signal, a gate main clock, a sensing clock signal, a main sensing clock, and the like.

The timing controller 80 generates a data control signal using synchronization signals from the outside so that data voltages can be supplied to the data lines DL1 to DLm of the image display panel PA. Here, the data control signal includes a source enable signal, a data shift clock signal, and the like.

The timing controller 80 transmits gate and data control signals to the data driving circuit 40 together with the aligned image data. At this time, the timing controller 80 converts the format of the aligned image data and the gate and data control signals according to the EPI (Embedded Clock Point-Point Interface) protocol to form the data driving circuit 40 using the LVDS (Low Voltage Differential Signaling) interface method. send to

In addition, the timing controller 80 performs AVC (ADC Variation Compensation) deviation compensation to compensate for deviations between integrated circuits of the data driving circuit 40 . To this end, the timing controller 80 receives each of the sensing voltage values transmitted from the plurality of sensing voltage output lines DV through the data driving circuit 40 . In addition, a driving deviation of each organic light emitting diode (OLED) configured in sub-pixels at a preset position is detected. Next, the timing controller 80 generates compensation data to compensate for organic light emitting diode (OLED) driving deviations of sub-pixels so that grayscale values of image data input from the outside can be compensated according to the compensation data. As described above, the image data whose grayscale values are compensated is arranged according to driving characteristics such as resolution and driving frequency and transmitted to the data driving circuit 40 .

The timing controller 80 includes a gate clock signal and a main sensing signal in addition to the gate clock signal and the gate main clock so that the sensing voltage can be detected through at least one sub-pixel and the sensing voltage output line DV. A control signal is generated so that it can be transmitted to the data driving circuit 40 .

As described above, the gate control signal including the sensing clock signal and the main sensing signal is formatted according to the compensated image data and the EPI protocol and transmitted to the data driving circuit 40 through the LVDS interface.

The data driving circuit 40 is mounted on the printed circuit film 60 between at least one side of the image display panel PA and at least one source printed circuit board 100, and the data lines DL1 to DLm and at least one integrated circuit supplying a data voltage to The data driving circuit 40 restores the data control signal and compensated image data received in the LVDS interface method to a TTL format, and converts the compensated image data in the timing controller 80 to an analog voltage using the restored data control signal. That is, after converting the data voltage of each pixel, it is supplied to the data lines DL1 to DLm.

The integrated circuits of the data driving circuit 40 convert the sensing voltage values received through respective sensing voltage output lines DV and the gate control signal received from the timing controller 80 into an LVDS format. In addition, the sensing voltage values converted into LVDS format and the gate control signal are simultaneously transmitted to the timing controller 80 and the level shifter 20 during each blank period when data voltages are not output to the data lines DL1 to DLm.

Accordingly, the timing controller 80 generates compensation data by using the sensing voltage value received in the blank period.

On the other hand, the level shifter 20 restores the gate control signal received in the blank period to the TTL communication format.

The level shifter 20 generates at least one carry signal for controlling the driving timing of the gate driving circuit 30 using the carry clock signal and the carry main clock among the gate control signals restored in the TTL communication format, and generates at least one carry signal for controlling the driving timing of the gate driving circuit 30. to the furnace 30. A plurality of clock pulses are sequentially generated to control driving timings of the gate lines using the gate clock signal and the main clock signal among the restored gate control signals, and are transmitted to the gate driving circuit 30 .

In addition, the level shifter 20 sequentially generates a sensing control clock for controlling the sensing timing using a sensing clock signal and a sensing main clock among the gate control signals restored in the TTL communication format, and transmits the sensing control clock to the gate driving circuit 30. send.

The level shifter 20 may be mounted on a main board 100 separate from the timing controller 80, or may be mounted on the data driving circuit 40 and the printed circuit film 60. In addition, the level shifter 20 may be mounted on the printed circuit board 10 closest to the configuration position of the gate driving circuit 30, or may be included in the gate driving circuit 30.

Hereinafter, an example in which the level shifter 20 is mounted in a specific area of the printed circuit board 10 closest to the configuration position of the gate driving circuit 30 will be described. It is most advantageous that the level shifter 20 is configured in an area where the interface distance between the gate driving circuit 30 and the TTL communication format is closest.

When the level shifter 20 is configured separately from the gate driving circuit 30, the gate driving circuit 30 sequentially outputs a gate-on signal to the gate lines GL1 to GLn, and a plurality of gate stages and sensing signals. It may be configured to include a plurality of sensing signal output stages that sequentially transmit to sensing signal lines.

The gate driving circuit 30 configured as described above is enabled according to at least one carry signal input from the level shifter 20 in the TTL communication format, and receives a plurality of clock signals in the TTL communication method from the level shifter 20 during the enable period. Pulse and sensing control clock are sequentially received. Accordingly, the gate driving circuit 30 sequentially generates gate-on signals using a plurality of clock pulses whose phases are shifted differently from each other from the level shifter 20 and sequentially supplies them to the respective gate lines GL1 to GLn. In addition, sensing signals may be sequentially generated and transmitted through a sensing signal transmission line (not shown) even by using a plurality of sensing control clocks shifted in phases differently from each other.

FIG. 3 is a configuration diagram showing the timing controller, data driving circuit, and level shifter shown in FIG. 1 in detail.

Referring to FIG. 3 , the timing controller 80 includes a data aligning unit 81, a data compensating unit 82, an EPI control signal generating unit 83, a first LVDS transmitting unit 84, and a first LVDS receiving unit 85. ).

The first LVDS receiver 85 receives sensing voltage values of corresponding sub-pixels through the integrated circuits of the data driving circuit 40 during every horizontal line driving period (hereinafter referred to as a horizontal period) or during a blank period of every frame period.

The data compensator 82 generates compensation data using the sensing voltage values received from the data driving circuit 40 through the first LVDS receiver 85 and compensates the grayscale value of the image data according to the compensation data. Specifically, the data compensator 82 compares the sensing voltage values received through the first LVDS receiver 85 with each other to compensate for the AVC deviation between the integrated circuits of the data driving circuit 40 and determines the sub-pixels. A driving deviation of each configured organic light emitting diode (OLED) is detected.

Subsequently, the data compensator 82 generates compensation data to compensate for the organic light emitting diode (OLED) driving deviation, and compensates the gray level value of image data input from the outside according to the compensation data. Grayscale values of image data input from the outside are increased or subtracted according to compensation data.

The data aligning unit 81 aligns the image data for which grayscale values have been compensated by the data compensating unit 82 according to driving characteristics such as the resolution and driving frequency of the image display panel PA, and converts the LVDS format into a first LVDS format. It is transmitted to the transmitter 84.

The EPI control signal generation unit 83 includes a gate start signal, a gate reset signal, a carry clock signal, a carry main clock, and a gate start signal, a gate reset signal, a carry clock signal, a gate start signal, a carry main clock, A gate control signal is generated to include the gate clock signal, the gate main clock, the sensing clock signal, and the main sensing clock. Specifically, the phase, period, and phase of each clock signal so that the gate start signal, the gate reset signal, the carry clock signal, the carry main clock, the gate clock signal, the gate main clock, the sensing clock signal, and the main sensing clock can be generated. Set the setting values such as amplitude and pulse width. The EPI control signal generation unit 83 also generates a data control signal to include a source enable signal and a data shift clock signal. In this way, the EPI control signal generation unit 83 generates gate and data control signals suitable for driving characteristics such as resolution and driving frequency of the image display panel PA and converts them into LVDS format.

The first LVDS transmission unit 84 transmits the gate and data control signals converted to the LVDS format to the data driving circuit 40 during the control packet transmission section of at least one horizontal period. In the data transmission section of at least one horizontal period, the compensated image data of at least one horizontal line converted to the LVDS format is transmitted to the data driving circuit 40 .

Referring to FIG. 3 , the data driving circuit 40 includes a compensation data generator 41, a memory 42, a compensation controller 43, an LVDS control signal generator 44, and a second LVDS receiver 45. include

The compensation data generation unit 41 converts the sensing voltage values received through the sensing voltage output lines DV of the image display panel PA into an LVDS format under the control of the compensation control unit 43, so that the second LVDS transmission unit ( 84).

The LVDS control signal generation unit 44 restores the data control signal received in units of at least one horizontal line through the second LVDS receiver 45 and compensated and aligned image data in a TTL format.

The compensation controller 43 stores the gate control signal received in units of at least one horizontal line through the second LVDS receiver 45 in the memory 42 in LVDS format. The LVDS format sensing voltage values and gate control signals are simultaneously transmitted to the timing controller 80 and the level shifter 20 through the second LVDS transmitter 84 through the LVDS interface method. At this time, the compensation control unit 43 transmits the sensing voltage values of the LVDS format and the gate control signal to the timing controller 80 through the second LVDS transmission unit 84 in each blank period in which data voltages are not output to the data lines DL1 to DLm. and the level shifter 20 are controlled to be simultaneously transmitted.

Since the timing controller 80 and the level shifter 20 receive all of the LVDS format sensing voltage values and gate control signals during the blank period through the second LVDS transmitter 84, the timing controller 80 and the level shifter 20 ) should distinguish sensing voltage values and gate control signals. That is, the data compensator 82 of the timing controller 80 needs to separately receive sensing voltage values received during the blank period, and the level shifter 20 needs to separately receive gate control signals.

To this end, the compensation control unit 43 divides the blank periods in which data voltages are not output from the data driving circuit 40 to each data line into a sensing voltage value transmission period and a gate control signal transmission period, respectively. In the divided sensing voltage value transmission period, the second LVDS transmitter 84 is controlled so that the sensing voltage value transmission packet data and the sensing voltage value are simultaneously transmitted to the timing controller 80 and the level shifter 20 . Then, during the divided gate control signal transmission period, the second LVDS transmission unit 84 is controlled so that the gate control signal transmission packet data and the gate control signal are simultaneously transmitted to the timing controller 80 and the level shifter 20 .

The level shifter 20 shown in FIG. 3 includes a third LVDS receiver 21, a TTL signal converter 22, and a shift control signal output unit 23.

The third LVDS receiver 21 sequentially transmits gate control signals in the LVDS format during a period when the gate control signal transmission packet data is input from the second LVDS transmitter 84 or during a period after the gate control signal transmission packet data is input. receive with

According to the number of LVDS interface channels of the third LVDS receiver 21 and the second LVDS transmitter 84, the LVDS format gate control signal LVDS_Data is sequentially transmitted simultaneously during the period in which the gate control signal transmission packet data LVDS_CLK is input. may receive. On the other hand, when the number of channels is singular, gate control signals of the LVDS format may be sequentially received during a period after the gate control signal transmission packet data is input.

The TTL signal conversion unit 22 restores the gate control signal in the LVDS format received by the third LVDS receiver 21 to the TTL communication format and transmits it to the shift control signal output unit 23.

The shift control signal output unit 23 sequentially generates at least one carry signal, a plurality of clock pulses, and a plurality of sensing control clocks using the gate control signal restored in the TTL communication format by the TTL signal converter 22. It is sequentially transmitted to the gate driving circuit 30.

Specifically, the shift control signal output unit 23 controls the driving timing of the gate driving circuit 30 using the carry clock signal and the carry main clock among the gate control signals restored by the TTL signal converter 22. A carry signal of is generated and transmitted to the gate driving circuit 30. A plurality of clock pulses are sequentially generated to control driving timings of the gate lines using the gate clock signal and the main clock signal among the restored gate control signals, and are transmitted to the gate driving circuit 30 . In addition, the shift control signal output unit 23 may sequentially generate a sensing control clock for controlling the sensing timing using the sensing clock signal and the sensing main clock and transmit the sensing control clock to the gate driving circuit 30 .

FIG. 4 is a timing diagram specifically illustrating the structure of a data packet transmitted from the timing controller of FIG. 3 to a data driving circuit.

3 and 4, each horizontal period in which a gate and data control signal and video data are transmitted to the data driving circuit 40 includes a training period (Clock Training), a control packet transmission period (Control Data), and video data. It can be divided into transmission intervals (RGB Data).

The EPI control signal generating unit 83 of the timing controller 80 generates each gate control signal in the gate driving circuit 30 and converts it into an LVDS format. Here, the gate control signals include a gate start signal (GST), a gate reset signal (RST), a carry clock signal (Carry_Gclk), a carry main clock (Carry_Mclk), a gate clock signal (SCAN_Gclk), a gate main clock (SCAN_Mclk), and a sensing clock. It includes the signal SENSE_Gclk and the main sensing clock SENSE_Mclk.

Accordingly, the EPI control signal generator 83 includes a gate start signal (GST), a gate reset signal (RST), a carry clock signal (Carry_Gclk), a carry main clock (Carry_Mclk), a gate clock signal (SCAN_Gclk), a gate main clock ( SCAN_Mclk), sensing clock signal (SENSE_Gclk), and main sensing clock (SENSE_Mclk), the set values for amplitude, pulse width, phase (w), period, rising time (r), and polling time (po) are displayed in sequence. It is arranged to be included in the packets CTR1 to CTR6 and transmitted to the first LVDS transmission unit 84 so that it can be transmitted to the data driving circuit 40 in the control packet transmission period (Control Data) of every horizontal period.

The first LVDS transmission unit 84 transmits the gate control signal in the LVDS format to the data driving circuit 40 in the control packet transmission period (Control Data), and then transmits at least the LVDS format converted to the LVDS format in the image data transmission period (RGB Data). The compensated image data for one horizontal line is transmitted to the data driving circuit 40 .

Thereafter, the compensation control unit 43 of the data driving circuit 40 stores the gate control signal received in units of at least one horizontal line through the second LVDS receiving unit 45 in the memory 42 in LVDS format. The compensation control unit 43 simultaneously transmits the gate control signals along with the sensing voltage values in the LVDS format to the timing controller 80 and the level shifter 20 through the second LVDS transmission unit 84 through the LVDS interface method.

FIG. 5 is a timing diagram specifically illustrating a data packet transmitted to a level shifter in the data driving circuit of FIG. 3 and an output signal of the level shifter.

As described above with reference to FIG. 3 , the compensation control unit 43 transmits the sensing voltage values of the LVDS format and the gate control signal to the second LVDS transmitter ( 84) to be transmitted simultaneously to the timing controller 80 and the level shifter 20.

Accordingly, the timing controller 80 and the level shifter 20 must separately receive sensing voltage values and gate control signals in the LVDS format every blank period. To this end, the compensation controller 43 divides the blank period of each horizontal period into a sensing voltage value transmission period and a gate control signal transmission period.

[Table 1]

Referring to Table 1 above, the compensation controller 43 transmits the sensing voltage value transmission packet data (1111111111 or 0101010101) to the timing controller 80 and the level shifter 20 at the same time during the sensing voltage value transmission period. After controlling the LVDS transmitter 84, the second LVDS transmitter 84 is controlled so that the sensed voltage value (or AVC compensation value) is simultaneously transmitted to the timing controller 80 and the level shifter 20.

In this case, when sensing voltage transmission packet data (1111111111 or 0101010101) is received, the timing controller 80 receives and stores the sensing voltage value (or AVC compensation value) to use when generating compensation data. On the other hand, the level shifter 20 is disabled when sensing voltage value transmission packet data (1111111111 or 0101010101) is received.

Thereafter, as shown in FIG. 5, the compensation controller 43 transmits the gate control signal transmission packet data (0000000000 or 1010101010) and the gate control signal to the timing controller 80 and the level shifter 20 during the gate control signal transmission period. ) and controls the second LVDS transmission unit 84 to be simultaneously transmitted.

Accordingly, the level shifter 20 determines whether the gate control signal transmission packet data (0000000000 or 1010101010) is input from the second LVDS transmission unit 84 or the gate control signal transmission packet data (0000000000 or 1010101010) is input. During the subsequent period, gate control signals of the LVDS format are sequentially received.

When the gate control signal transmission packet data (0000000000 or 1010101010) is input, the level shifter 20 receives the LVDS format gate control signal and restores it to the TTL communication format. In addition, at least one carry signal, a plurality of clock pulses GCLK1, and a plurality of sensing control clocks are sequentially generated by using the gate control signal restored in the communication format, and are sequentially transmitted to the gate driving circuit 30 .

Specifically, the TTL signal converter 22 of the level shifter 20 converts the amplitude, pulse width, phase (w), period, and rising time of the gate start signal (GST) and gate reset signal (RST) among the gate control signals. A gate start signal (GST) and a gate reset signal (RST) of the TTL communication format are generated using set values for (r) and polling time (po), and transmitted to any one stage of the gate driving circuit 30. can

In addition, the TTL signal conversion unit 22 generates at least one carry signal for controlling the driving timing of the gate driving circuit 30 using set values of the carry clock signal Carry_Gclk and the carry main clock Carry_Mclk, This may be transmitted to the gate driving circuit 30 .

In addition, the TTL signal converter 22 generates a plurality of clock pulses GCLK1 for controlling driving timings of the gate lines GL1 to GLn using the restored gate clock signal SCAN_Gclk and set values of the gate main clock SCAN_Mclk. ) are sequentially generated and transmitted to the gate driving circuit 30. In addition, a sensing control clock for controlling the sensing timing is sequentially generated using the set values of the sensing clock signal SENSE_Gclk and the main sensing clock SENSE_Mclk among the restored gate control signals, and transmitted to the gate driving circuit 30. can

Accordingly, the gate driving circuit 30 is enabled according to at least one carry signal input from the level shifter 20 in the TTL communication format, and receives a plurality of clock pulses in the TTL communication format from the level shifter 20 during the enable period. and the sensing control clock are sequentially received.

The gate driving circuit 30 sequentially generates a gate-on signal using a plurality of clock pulses CLK1 whose phases are shifted differently from each other from the level shifter 20 and sequentially supplies the gate-on signals to the respective gate lines GL1 to GLn. In addition, even when using a plurality of sensing control clocks whose phases are shifted differently, sensing signals may be sequentially generated and transmitted through the sensing signal transmission line.

6 is a graph showing a change in noise due to electromagnetic interference between level shifters in a data driving circuit. And Table 2 below is a simulation result table when the gate control signals are transmitted to the data driving circuit 40 together with image data through the LVDS interface method using the EPI protocol.

[Table 2]

As shown in FIG. 6 and Table 1, when the gate control signals of the image display device are transmitted to the data driving circuit together with the image data by the LVDS interface method using the EPI protocol, the gate control signal is transmitted using only the LVDS interface line. Therefore, the number of gate control signal transmission pins or input/output channels can be reduced by more than 36%.

In addition, by reducing the arrangement area of the gate control signal transmission lines between the timing controller 80 and the level shifter 20 or between the timing controller 80 and the gate driving circuit 30 by about 20% to 30%, the image display panel The size of the non-display area ND of the PA, the printed circuit board 10 and the printed circuit film 60 on which the driving circuit is mounted can be minimized.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention belongs that various substitutions, modifications, and changes are possible without departing from the technical details of the present invention. It will be clear to those who have knowledge of Therefore, the scope of the present invention is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be construed as being included in the scope of the present invention.

10: printed circuit board
20: Level Shifter
30: gate driving circuit
40: data driving circuit
60: printed circuit film
100: main board

Claims (14)

a timing controller outputting image data and a gate control signal aligned according to driving characteristics of the image display panel through an LVDS interface method;
a data driving circuit which drives data lines of the image display panel according to the image data received through the LVDS interface and outputs the gate control signal through the LVDS interface; and
A level shifter receiving the gate control signal through the LVDS interface method through the data driving circuit and restoring the gate control signal to a TTL communication format and transmitting the restored gate control signal to the gate driving circuit;
The timing controller
a data compensator generating compensation data using sensing voltage values received from the data driving circuit through a first LVDS receiver and compensating grayscale values of the image data according to the compensation data;
a data aligning unit arranging the image data whose grayscale values are compensated by the data compensating unit according to driving characteristics of the image display panel and converting them into an LVDS format;
an EPI control signal generating unit generating the gate control signal to include a gate clock signal, a gate main clock signal, a sensing clock signal, and a main sensing clock, and converting the gate control signal into an LVDS format;
The gate control signal converted to the LVDS format is transmitted to the data driving circuit in a control packet transmission section of at least one horizontal period, and aligned image data of at least one horizontal line converted to the LVDS format is transmitted to the data driving circuit in the data transmission section. Including a first LVDS transmitter for transmitting to the data driving circuit,
video display device.
According to claim 1,
The level shifter
The timing controller and the main board may be mounted, the data driving circuit and the printed circuit film may be mounted, or the gate driving circuit may be mounted at any position of the printed circuit board closest to the position, or may be mounted on the gate driving circuit. configured to include
video display device.
delete According to claim 1,
The EPI control signal generator
Set values for the amplitude, pulse width, phase, and period of each of the gate start signal, gate reset signal, carry clock signal, carry main clock, gate clock signal, gate main clock, sensing clock signal, and main sensing clock. arranging data packets in this order and transmitting them to the first LVDS transmitter during a control packet transmission period of every horizontal period;
video display device.
According to claim 1,
The data driving circuit
a compensation data generating unit that converts sensing voltage values received through sensing voltage output lines of the image display panel into an LVDS format;
an LVDS control signal generator for restoring the image data aligned with the data control signal received through the second LVDS receiver into a TTL format; and
A compensation controller for storing the gate control signal in an LVDS format in a memory and controlling the sensing voltage values of the LVDS format and the gate control signal to be simultaneously transmitted to the timing controller and the level shifter through a second LVDS transmitter.
video display device.
According to claim 5,
The compensation control unit
In the data driving circuit, the blank periods in which data voltage is not output to each data line are divided into a sensing voltage value transmission period and a gate control signal transmission period, respectively;
Controlling a second LVDS transmitter so that the sensing voltage value transmission packet data and the sensing voltage value are simultaneously transmitted to the timing controller and the level shifter during the divided sensing voltage value transmission period;
Controlling the second LVDS transmission unit so that the gate control signal transmission packet data and the gate control signal are simultaneously transmitted to the timing controller and the level shifter during the divided gate control signal transmission period.
video display device.
According to claim 5,
The level shifter
a third LVDS receiving unit for sequentially receiving gate control signals in the LVDS format during a gate control signal transmission packet data input period;
a TTL signal converter for restoring the LVDS format gate control signal to the TTL communication format; and
A shift control signal output unit for sequentially generating at least one carry signal, a plurality of clock pulses, and a plurality of sensing control clocks using the gate control signal restored in the TTL communication format and sequentially transmitting them to the gate driving circuit,
video display device.
According to claim 7,
The TTL signal conversion unit
Among the gate control signals, the gate start signal and the gate reset signal of the TTL communication format are configured using a set value for at least one of the amplitude, pulse width, phase, period, rising time, and polling time of the gate start signal and the gate reset signal. create,
generating at least one carry signal for controlling a driving timing of the gate driving circuit by using a set value of a carry clock signal and a carry main clock;
sequentially generating a plurality of clock pulses for controlling driving timings of gate lines using set values of a gate clock signal and a gate main clock;
Using the sensing clock signal and the set value of the main sensing clock, a sensing control clock for controlling sensing timing is sequentially generated and transmitted to the gate driving circuit.
video display device.
outputting image data and a gate control signal aligned according to driving characteristics of the image display panel through an LVDS interface method;
driving data lines of the image display panel according to the image data received through the LVDS interface method and transmitting the gate control signal through the LVDS interface method; and
Receiving the gate control signal through the LVDS interface method and restoring the gate control signal into a TTL communication format through a level shifter and transmitting the same to a gate driving circuit;
The step of outputting the gate control signal and the aligned image data through the LVDS interface method
generating compensation data using sensing voltage values received through a first LVDS receiver, and compensating grayscale values of the image data according to the compensation data;
arranging the image data for which the grayscale value is compensated according to driving characteristics of the image display panel and converting the image data into an LVDS format;
generating and converting the gate control signal into an LVDS format to include a gate clock signal, a gate main clock signal, a sensing clock signal, and a main sensing clock;
During at least one horizontal period, the gate control signal converted to the LVDS format is transmitted to the data driving circuit in the control packet transmission period, and the aligned image data of at least one horizontal line converted to the LVDS format is transmitted to the data driving circuit during the data transmission period. Including the step of transmitting to
A method of driving an image display device.
delete According to claim 9,
Generating the gate control signal and converting it to LVDS format
Set values for the amplitude, pulse width, phase, and period of each of the gate start signal, gate reset signal, carry clock signal, carry main clock, gate clock signal, gate main clock, sensing clock signal, and main sensing clock. Arranged to be included in the data packet in this order and transmitted to the first LVDS transmitter during the control packet transmission period of every horizontal period.
A method of driving an image display device.
According to claim 9,
Transmitting the gate control signal through the LVDS interface;
converting sensing voltage values received through sensing voltage output lines of the image display panel into an LVDS format;
restoring the image data aligned with the data control signal into a TTL format; and
Storing the gate control signal in an LVDS format in a memory, and controlling the sensing voltage values and the gate control signal in the LVDS format to be simultaneously transmitted to a timing controller and a level shifter through a second LVDS transmitter.
A method of driving an image display device.
According to claim 12,
The step of simultaneously transmitting the sensing voltage values and the gate control signal in the LVDS format to a timing controller and a level shifter,
Dividing a blank period in which data voltage is not output to the data line into a sensing voltage value transmission period and a gate control signal transmission period, respectively;
Controlling a second LVDS transmitter so that the sensing voltage value transmission packet data and the sensing voltage value are simultaneously transmitted to the timing controller and the level shifter during the divided sensing voltage value transmission period; and
In the divided gate control signal transmission period, controlling the second LVDS transmission unit so that gate control signal transmission packet data and a gate control signal are simultaneously transmitted to the timing controller and the level shifter,
A method of driving an image display device.
According to claim 13,
The step of restoring the gate control signal transmitted through the LVDS interface method into a TTL communication format and transmitting it to the gate driving circuit
sequentially receiving LVDS format gate control signals during a gate control signal transmission packet data input period;
restoring the LVDS format gate control signal to a TTL communication format; and
Sequentially generating at least one carry signal, a plurality of clock pulses, and a plurality of sensing control clocks using the gate control signal restored in the TTL communication format and sequentially transmitting them to a gate driving circuit,
A method of driving an image display device.

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