KR102460112B1 - Display device - Google Patents

Abstract

The present invention relates to a display device, comprising a data driver including one or more source drive ICs, and a timing controller. The timing controller transmits image data to the data driver through a first wire, receives a start signal and a skew adjustment signal from the data driver through a second wire, selects a clock based on the skew adjustment signal, and selects the selected clock to sample the data received following the skew adjustment signal.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device having an automatic skew adjustment function between a timing controller and source drive integrated circuits (hereinafter, referred to as "IC").

The flat panel display device includes a liquid crystal display device (LCD), an organic light emitting diode display device (hereinafter referred to as “OLED display device”), a plasma display panel (PDP), and an electric field. and field emission displays (FEDs). The electroluminescent display is roughly divided into an inorganic light emitting display and an organic light emitting display according to the material of the light emitting layer. The active matrix type organic light emitting diode display includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has a fast response speed and high luminous efficiency, luminance and viewing angle. There are advantages.

An active matrix driving type flat panel display uses a thin film transistor (hereinafter referred to as "TFT") as a switching element to display a moving picture. A display device includes a data driver for supplying data voltages to data lines of a display panel, a gate driver for sequentially supplying gate pulses (or scan pulses) to gate lines of the display panel, and timing for controlling drive ICs A controller and the like are provided. The data driver may include a plurality of source drive integrated circuits (ICs).

The timing controller supplies digital video data, a clock for sampling digital video data, and a control signal for controlling the operation of the source drive ICs to the source drive ICs through an interface such as mini LVDS (Low Voltage Differential Signaling). . The source drive ICs convert digital video data input from the timing controller into analog data voltages and supply them to data lines.

When connecting the timing controller and source drive ICs in a multi-drop method through the mini LVDS (Low Voltage Differential Signaling) interface, R data transmission wiring, G data transmission wiring, Many wirings including B data transmission wiring, control wirings for controlling the output of the source drive ICs and the operation timing of the polarity change operation, and clock transmission wirings are required. As an example of RGB data transmission in the mini-LVDS interface method, since each of RGB digital video data and clock is transmitted as a differential signal pair, the timing controller and source drive ICs are used to simultaneously transmit odd data and even data. Between them, at least 14 wires are needed for RGB data transmission. If RGB data is 10-bit data, 18 wires are needed. Accordingly, it is difficult to reduce the width of the source printed circuit board (hereinafter referred to as "PCB") mounted between the timing controller and the source drive ICs because many wires must be formed.

The applicant of the present application connects the timing controller and the source drive ICs in a point-to-point manner to minimize the number of wirings between the timing controller and the source drive ICs and to stabilize the signal transmission EPI (Embedded clock point to point interface) ) has been proposed.

The EPI interface connects the transmitting end of the timing controller and the receiving end of the source drive ICs in a point-to-point manner via a data line pair. The EPI interface does not connect a separate pair of clock wires between the timing controller and the source drive ICs. Through the EPI interface, the timing controller transmits video data and control data along with a clock signal to the source drive ICs through a pair of data wires. Each of the source drive ICs has a built-in clock recovery circuit for CDR (Clok and Data Recovery). The timing controller transmits a clock training pattern (or preamble) signal to the source drive ICs so that the output phase and frequency of the clock recovery circuit can be locked. The clock recovery circuit built into the source drive ICs generates an internal clock when the clock training pattern signal and the clock signal input through the data line pair are input.

In the EPI interface, since the wiring length between the timing controller and the source drive ICs is different, skew may be different between the timing controller and the source drive IC. When skew is optimal, transmission errors in data transferred between the timing controller and the source drive ICs are minimized. In order to optimize the skew of each of the source drive ICs, the process of manually measuring and adjusting the skew has to be repeated by an operator, so the skew adjustment time is lengthened.

Manually adjusting the skew in the timing controller and the source drive IC requires manual work for each display panel, increasing the work time.

The skew can be adjusted by transmitting data from the source drive IC to the timing controller together with the clock (Clock, CLK). However, this method generates an additional cost because a clock is generated from the source drive IC and a separate clock line must be added between the timing controller and the source drive IC.

The prior art auto skew method takes about 8H or more to adjust the optimal skew before transmitting ADC data, and cannot cope with environmental changes such as temperature or voltage.

Accordingly, an object of the present invention is to provide a display device capable of automatically adjusting skew between a timing controller and a data driver without clock wiring or a skew adjustment time delay.

The light emitting display device of the present invention includes a data driver including one or more source driver ICs, and a timing controller. The timing controller transmits image data to the data driver through a first wire, receives a start signal and a skew adjustment signal from the data driver through a second wire, selects a clock based on the skew adjustment signal, and selects the selected clock to sample the data received following the skew adjustment signal.

The present invention can automatically adjust the skew without increasing the tact time compared to the manual skew adjustment method.

According to the present invention, since the skew is automatically adjusted in the timing controller whenever a data packet is transmitted from the data driver to the timing controller, it is possible to prevent transmission errors due to changes over time in the transmission wiring.

Furthermore, according to the present invention, skew can be automatically adjusted without delay in clock wiring and skew adjustment time, and skew can be optimally adjusted in real time without being affected by environmental changes such as temperature or voltage.

1 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention.
2 is a circuit diagram illustrating a pixel circuit and a sensing path connected to the pixel circuit.
3 is a diagram illustrating a power-on sequence, a display driving period, and a power-off sequence.
4 is a diagram illustrating in detail an active section and a vertical blank section.
5 is a diagram specifically illustrating a wiring connection between a timing controller and source drive ICs.
6 is a diagram showing the circuit configuration of a timing controller and a source drive IC.
7 is a diagram illustrating a signal format for real-time automatic skew.
8 is a diagram illustrating an example of a clock selected as an optimal skew timing.
9 is a diagram showing EPI data, ADC data, and clocks.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and those of ordinary skill in the art to which the present invention pertains It is provided to fully understand the scope of the invention, and the invention is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiment of the present invention are exemplary, the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When "includes", "includes", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, it may be interpreted as the plural unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship between the two components is described as 'on One or more other elements may be interposed between those elements in which 'directly' or 'directly' are not used.

The first, second, etc. may be used to distinguish the components, but the functions or structures of these components are not limited to the ordinal number or component name attached to the front of the component.

The following embodiments can be partially or wholly combined or combined with each other, and technically various interlocking and driving are possible. Each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship.

The present invention can be applied to any display device requiring skew adjustment between a timing controller and a data driver.

A compensation circuit for compensating for a characteristic change of a driving device for driving pixels in an organic light emitting diode display may be applied. The compensation circuit may be divided into an internal compensation circuit and an external compensation circuit. The internal compensation circuit samples the threshold voltage of the driving device by using an internal compensation circuit disposed in each of the pixels to drive the pixels by adding the threshold voltage to the data voltage of the pixel data to compensate for the threshold voltage deviation between the driving devices in the pixel circuit. automatically compensate. The external compensation circuit senses electrical characteristics of the driving elements, and compensates for changes in driving characteristics of each of the pixels by modulating pixel data of an input image based on the sensing result.

The external compensation circuit converts the device characteristics of the pixel into digital data through an analog-to-digital converter (hereinafter referred to as "ADC") and is transmitted to the data compensation circuit. The ADC may be built into each of the source drive ICs, and the data compensation circuit may be built into the timing controller.

The present invention is mainly described in the following embodiments, but is not limited to an organic electroluminescent display to which an external compensation circuit is applied.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the electroluminescent display will be mainly described with respect to the organic light emitting display including the organic light emitting material. The technical spirit of the present invention is not limited to an organic light emitting display device, and may be applied to an inorganic light emitting display device including an inorganic light emitting material.

1 is a block diagram illustrating a display device according to an embodiment of the present invention. 2 is a circuit diagram illustrating a sensing path connected to a pixel circuit.

1 and 2 , a display device according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit.

The screen of the display panel 100 includes an active area AA for displaying an input image. A pixel array is disposed in the active area AA. The pixel array includes a plurality of data lines 102 , a plurality of gate lines 104 intersecting the data lines 102 , and pixels arranged in a matrix form.

Each of the pixels may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement color. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels 101 includes a pixel circuit as shown in FIG. 2 .

Touch sensors may be disposed on the display panel 100 . The touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors may be implemented as in-cell type touch sensors disposed on the screen of a display panel or embedded in a pixel array as on-cell type or add-on type. can

The display panel driving circuits 110 , 112 , and 120 include a data driving unit 110 and a gate driving unit 120 . A demultiplexer 112 disposed between the data driver 110 and the data lines 102 may be disposed.

The display panel driving circuits 110 , 112 , and 120 write the pixel data of the input image to the pixels of the display panel 100 under the control of a timing controller (TCON) 130 during the display driving period to be displayed on the screen. Display the input image. The display panel driving circuit may further include a touch sensor driver for driving the touch sensors. The touch sensor driver is omitted from FIG. 1 . In a mobile device or a wearable device, the data driver 110 , the timing controller 130 , and the power circuit may be integrated into one drive IC (Integrated Circuit, DIC).

As shown in FIG. 2 , the data driver 110 uses a digital-to-analog converter (hereinafter, referred to as a DAC) for pixel data (digital) of an input image received from the timing controller 130 every frame period. data) into a gamma compensation voltage to output a data voltage. A data voltage is applied to the pixels through a demultiplexer 112 and a data line 102 . The demultiplexer 112 is disposed between the data driver 110 and the data lines 102 using a plurality of switch elements to distribute the data voltage output from the data driver 110 to the data lines 102 . The data driver 110 may include one or more source drive integrated circuits (ICs) as shown in FIG. 5 .

Since one channel of the data driver 110 is time-divisionally connected to a plurality of data lines by the demultiplexer 112 , the number of data lines 102 may be reduced. The demultiplexer 112 may be omitted.

The gate driver 120 may be implemented as a gate in panel (GIP) circuit that is directly formed on a bezel region of the display panel 100 together with a transistor array in the active region. The gate driver 120 outputs a gate signal to the gate lines 104 under the control of the timing controller 130 . The gate driver 120 may sequentially supply the gate signals to the gate lines 104 by shifting the gate signals using a shift register. The gate signal may be divided into first and second scan signals SCAN1 and SCAN2 as shown in FIG. 2 . The first scan signal SCAN1 selects pixels to which the data voltage is applied in synchronization with the data voltage. The second scan signal SCAN2 may be synchronized with the first scan signal SCAN1 . The second scan signal SCAN2 selects pixels in which electrical characteristics of the driving elements DT formed in the pixels are sensed in the external compensation method. Electrical characteristics of the driving device include mobility (μ) and a threshold voltage (Vth).

The external compensation circuit may generate a pulse of the second scan signal SCAN2 and connect the pixel circuit to the sensing line 103 to sense the threshold voltage Vth or mobility μ of the driving device. The sensing method is divided into before product shipment and after product shipment. After the threshold voltage of the driving element DT is sensed in each of the sub-pixels through a sensing path connected to the pixels before product shipment, the threshold voltage deviation in all sub-pixels is compensated based on the sensing result. In addition, the mobility of the driving element DT is sensed in each of the sub-pixels to compensate for the mobility deviation.

After the product is shipped, the sensing method is performed in a power-on sequence (ON), a vertical blank (VB) section, and a power-off sequence as shown in FIG. 3 . In the power-off sequence OFF, the display panel driving circuit and the sensing path are further driven for a preset delay time after receiving the power-off signal to sense the threshold voltage Vth of the driving device in each of the sub-pixels.

The timing controller 130 receives pixel data of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The host system may be any one of a television (Television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

The vertical synchronization signal Vsync defines one frame period. The horizontal synchronization signal Hsync defines one horizontal time period. The data enable signal DE is synchronized with pixel data to be displayed in the pixel array of the display panel 100 to define an effective pixel data period. One pulse period of the data enable signal DE is one horizontal period, and a high logic period of the data enable signal DE represents a pixel data input period of one pixel line. One horizontal period (1H) is a time required to write data to pixels of one pixel line in the display panel 100 . The pixel line includes pixels arranged along the gate line direction and connected to the same gate line. Pixels of one pixel line share a gate line to which a scan signal is applied, and are simultaneously addressed according to a scan signal from the gate line to receive a data voltage of pixel data.

The timing controller 130 controls the operation timing of the demultiplexer 112 and a data timing control signal for controlling the operation timing of the data driver 110 based on the timing signals Vsync, Hsync, DE received from the host system. The operation timing of the display panel driving circuits 110 , 112 , and 120 is controlled by generating a switch control signal for controlling a switch control signal for a sensing path, a switch element control signal for a sensing path, and a gate timing control signal for controlling an operation timing of the gate driver 120 . The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate-on voltage and a gate-off voltage through a level shifter (not shown) and supplied to the gate driver 120 . The level shifter converts a low level voltage of the gate timing control signal into a gate low voltage VGL, and converts a high level voltage of the gate timing control signal into a gate high voltage VGH. .

The sensing path includes a sensing line 103, an analog-to-digital converter (hereinafter referred to as “ADC”), and first and second switch elements M1 and M2, as shown in FIG. 2 . can do. The sensing path may sense the source voltage of the driving element DT to sense electrical characteristics of the driving element. The first switch element M1 initializes the source voltage of the driving element DT to the reference voltage Vref by supplying a predetermined reference voltage Vref to the sensing line 103 . The second switch element M2 is turned on after the first switch element M1 is turned off to supply the source voltage of the driving element DT to the ADC. The ADC converts the analog sensing voltage into digital sensing data and transmits it to the compensator 131 . The source voltage of the driving element DT may represent a threshold voltage or mobility of the driving element DT according to a sensing method. A method of sensing the threshold voltage of the driving element DT through the sensing path or a method of sensing the mobility of the driving element DT through the sensing path may use a known sensing method. The ADC may be applied to each of the source drive integrated circuits (ICs) of the data driver 110 together with the DAC.

The compensation unit 131 stores compensation values for compensating for the threshold voltage Vth and the mobility μ of the driving element in each of the sub-pixels. The compensator 131 selects a preset compensation value according to the ADC data (digital data) received from the ADC and compensates the pixel data by adding or multiplying the compensation value to the pixel data (digital data) of the input image. The compensated pixel data is transmitted to the data driver 110 , converted into a data voltage Vdata by the DAC of the data driver 110 , and supplied to the data line 102 . The driving element DT of the pixel circuit is driven by the data voltage Vdata supplied through the data line 102 to generate a current. A current flowing through the driving element DT to the OLED, which is the light emitting element, is determined according to the gate-source voltage Vgs of the driving element DT. The compensator 131 may be implemented as an arithmetic circuit in the timing controller 130 .

3 is a view showing a power ON sequence, a display driving period, and a power OFF sequence. FIG. 4 shows an active period AT and a vertical blank period VB in detail drawing is given.

3 and 4 , the power-on sequence (ON) is started after the display power is turned on. In the power-on sequence 0N, a driving voltage of the display panel driving circuit and the display panel 100 is generated, and the display panel driving circuit is initialized. The mobility of the driving element DT is sensed in the vertical blank section VB of the power-on sequence 0N and the display driving period, and the mobility deviation of the driving element DT is determined by a mobility compensation value selected according to the sensed value. can be compensated. A mobility compensation value may be updated based on a result of sensing the mobility of the driving element DT. During the display driving period, pixel data written to the pixels is updated every frame period to display an image on the screen.

The power-off sequence OFF is started after a display power-off signal is received. In the power-off sequence OFF, the threshold voltage Vth of the driving element may be sensed in each of the sub-pixels during a delay time during which the display panel driving circuit and the sensing path are additionally driven. A threshold voltage compensation value is selected according to the threshold voltage Vth of the driving device sensed in the power-off sequence OFF, so that a threshold voltage deviation of the driving device DT in each of the sub-pixels may be compensated.

The timing controller 130 receives the data enable signal DE and the data of the input image during the vertical active period AT. There is no data enable signal DE and no pixel data of the input image in the vertical blank period VB. During the active period AT, data corresponding to one frame to be written in all pixels is received by the timing controller 130 . One frame period is the sum of the active periods AT and the vertical blank period VB.

As can be seen from the data enable signal DE, input data is not received by the display device during the vertical blank period VB. The vertical blank section VB includes a vertical sync time (VS), a vertical front porch (FP), and a vertical back porch (BP). The vertical sync time (VS) is a time from a falling edge of Vsync to a rising edge, and represents the start (or end) timing of one screen. The vertical front porch FP is the time from the falling edge of the last DE indicating the last line data timing of one frame data to the start of the vertical blank period VB. The vertical back porch BP is the time from the end of the vertical blank period VB to the rising edge of the first DE indicating the first line data timing of one frame data.

An example of a pixel circuit is shown in FIG. 2 . As shown in FIG. 2 , the pixel circuit includes an OLED which is a light emitting device, a driving device DT connected to the OLED, first and second switch devices S1 and S2 , and a capacitor Cst. The driving element and the switch element of the pixel circuit may be implemented as a transistor having a metal oxide semiconductor field effect transistor (MOSFET) structure. The driving element DT and the switch elements S1 and S2 are illustrated as n-type transistors in FIG. 2 , but are not limited thereto.

The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the OLED is connected to the driving element DT through the second node n2, and the cathode of the OLED is connected to the VSS electrode to which the low potential voltage VSS is applied.

The driving device DT drives the OLED by controlling the current of the OLED according to the gate-source voltage Vgs. The driving element DT includes a gate connected to the first node n1, a first electrode (or drain) to which the high potential voltage VDD is supplied, and a second electrode connected to the anode of the OLED through the second node n2. (or source). The capacitor Cst is connected between the gate and the source of the driving device DT through the first and second nodes n1 and n2.

The first switch device S1 is turned on according to the first scan signal SCAN1 to supply the data voltage Vdata to the gate of the driving device DT connected to the first node n1. . The first switch element S1 includes a gate connected to the first gate line 1041 to which the first scan signal SCAN1 is applied, a first electrode connected to the data line 102 , and a first node connected to the first node n1 . Includes 2 electrodes.

The second switch element S2 is turned on according to the second scan signal SCAN2 to supply the reference voltage Vref to the second node n2 . The voltage difference between the reference voltage Vref and the low potential voltage VSS is lower than the threshold voltage of the OLED. Therefore, when the reference voltage Vref is applied to the anode of the OLED, the OLED does not emit light because no current flows through the OLED. The second switch element S2 includes a gate connected to the second gate line 1042 to which the second scan signal SCAN2 is applied, a first electrode connected to the sensing line 103 to which the reference voltage Vref is applied, and a first electrode connected to the second switch element S2 . A second electrode connected to the second node n2 is included.

The high potential voltage VDD is applied to the anode of the OLED through the driving element DT. A low potential voltage (VSS) is applied to the cathode of the OLED. Accordingly, the high potential voltage VDD is supplied to the anode of the OLED through the driving element DT.

5 and 6 , the source drive ICs SIC1 to SIC12 receive data from the timing controller TCON through the EPI interface and transmit ADC data to the timing controller TCON through the LVDS interface. . To this end, the timing controller TCON and the source drive ICs SIC1 to SIC12 are connected through the EPI line DL and also through the LVDS line SL. The EPI wiring DL connects the timing controller TCON and the source drive ICs SIC1 to SIC12 1:1 in a point-to-point form. Timing controller (TCON) transmits the clock along with data such as clock training pattern (or preamble), control data packet, and video data packet through the EPI wiring (DL) according to the EPI interface protocol to display the input image. It is transmitted to the drive ICs (SIC1 to SIC12). The control data packet includes control data for controlling the operation of the display panel driving circuit including the source drive ICs. The video data may be data modulated according to a preset external compensation algorithm to compensate for device characteristic change. 5 and 6 , “EPI data” is data transmitted from the timing controller TCON to the source drive IC SIC. One data packet of EPI data transmitted from the controller TCON to the source drive IC SIC may be 24 Unit Intervals (UI). 1 UI may be a unit time required for 1 bit transmission.

The LVDS line SL connects the timing controller TCON to the plurality of source drive ICs SIC1 to SIC12. The source drive ICs SIC1 to SIC6 connected to the first PCB PCB1 are connected to the timing controller TCON through the first LVDS line SL. The source drive ICs SIC7 to SIC12 connected to the second PCB PCB2 are connected to the timing controller TCON through the second LVDS wiring SL. The source drive ICs SIC1 to SIC12 transmit ADC data indicating a change in device characteristics of pixels to the timing controller TCON through the LVDS line SL.

The timing controller (TCON) includes a transmitter (Tx, 13), a receiver (Rx, 16), a serializer (11), a phase locked loop (hereinafter referred to as "PLL") 12, clock generation It includes a unit 17 , an optimal clock selection unit 18 , a skew check unit 19 , a de-serializer 15 , a compensator 14 , and the like.

The host system inputs the pixel data of the input image to the data modulator 14a through the LVDS interface. The data modulator 14a modulates pixel data with the compensation value received from the compensator 14 and outputs it to the serial converter 11 . The serial converter 11 samples and latches pixel data according to an output clock of the PLL 12 , and then converts the pixel data into serial data. The PLL 12 multiplies the LVDS clock received from the host system to generate a clock of the EPI interface transmission frequency. The output clock of the PLL is embedded in data output from the serial converter 11 in units of data packets. The transmitter 13 converts the clock-embedded data into a differential signal pair defined in the EPI interface protocol and transmits the data to the source drive ICs SIC1 to SIC12 through the EPI line DL.

The receiver 16 receives ADC data from the source drive ICs SIC1 to SIC12 through the LVDS line SL and supplies it to the parallel converter 15 . The parallel converter 15 samples the ADC data according to the clock input from the optimal clock selector 18 , converts it into a parallel data system, and supplies it to the compensator 14 .

The ADC data received from the source drive IC (SIC) is sampled and latched according to the clock timing of the clock received from the optimum clock selector 18 , and then converted into a parallel data system and supplied to the compensator 14 . The compensator 14 selects a compensation value of the pixel data according to the received ADC data as described above and provides it to the data modulator 14a.

The clock generation unit 17, the optimum clock selection unit 18, and the skew check unit 19 are the timing controller (TCON) without clock wiring or skew adjustment time delay, and without being affected by environmental changes such as temperature or voltage. and source drive IC (SIC) skew in real time to be optimally adjusted automatically.

The clock generator 17 receives the reference clock from the PLL 12 and shifts the phase of the reference clock CLK0 by a predetermined time unit to generate a plurality of clocks CLK1 to CLK24. The predetermined time may be 1 UI.

The optimal clock selection unit 18 selects any one of the clocks received from the clock generator 17 according to the setup signal received from the skew check unit 19 .

The skew check unit 19 receives the start signal and the skew adjustment signal from the source drive IC (SIC) and compares the clocks CLK1 to CLK24 input from the clock generator 17 with the skew adjustment signal during the skew adjustment period. Based on the result, a skew error is checked to find a clock that satisfies the optimal skew timing, and a setup signal indicating a clock with the optimal skew timing is generated. During the skew adjustment period, the skew check unit 19 may output the setup signal one or more times. The optimal clock selection unit 18 may select a clock indicated by the final setup signal last received from the skew check unit 19 during the skew adjustment period. In another embodiment, the optimal clock selection unit 18 may select a clock for each setup signal received from the skew check unit 19 during the skew adjustment period, and select the most selected clock as the final clock.

The source drive ICs (SIC1 to SIC12) include a receiver 21 , a parallel converter 22 , a clock recovery unit 23 , a divider 24 , a sample and holder (S/H) 25 . , ADC 26 , serial conversion unit 27 , transmitter 28 , and the like. The parallel conversion unit 22 samples the EPI data received through the receiver 21 according to the internal clock timing restored by the clock recovery unit 23 and converts it into a parallel data system. The clock recovery unit 23 generates an internal clock by recovering a clock from the EPI data received from the receiver 21 . The divider 24 divides the internal clock from the clock recovery unit 23 to generate an ADC shift clock CLKS and an ADC data transmission clock CLKT. The sample & holder 25 samples device characteristic change data input from the pixel according to the ADC shift clock CLK and supplies it to the ADC 26 . The ADC 26 supplies the sampled ADC data to the serial converter 27 according to the ADC data transmission clock CLKT. The serial converter 27 converts the ADC data into a serial data system and supplies it to the transmitter 28 . The transmitter 28 converts the ADC data into differential signal pairs and transmits them to the timing controller TCON through the LVDS wiring DL.

ADC related clocks (CLKS, CLKT) can be generated by the source drive ICs (SIC1 to SIC12) by dividing the clock synchronized with the clock received through the EPI interface. Therefore, there is no need for the timing controller (TCON) to separately generate an ADC-related clock and transmit it to the source drive IC (SIC).

7 is a diagram illustrating a signal format for real-time automatic skew. The data shown in FIG. 7 is data transmitted from the source drive IC (SIC) to the timing controller (TCON). 8 is a diagram illustrating an example of a clock selected as an optimal skew timing.

7 and 8 , the source drive IC SIC may transmit a start signal 3FFH and a skew adjustment signal 155H to the timing controller TCON prior to ADC data. In FIG. 7, CH1 to CH192 denote ADC data. Hi-Z means a high impedance state in which the ADC data output channels of the source drive ICs SIC1 to SIC12 are opened.

The timing controller TCON determines a skew start period RTskew Start, a skew adjustment period RTskew Adjust, and a skew hold period from a signal received from the source drive IC SIC.

The start signal 3FFH defines a real-time skew start period. The skew adjustment signal 155H informs the real-time skew adjustment section to the skew check unit 19 of the timing controller TCON. When 1 (=High: H) is continuously received 8 or more times in data received through the ADC wiring SL, the skew check unit 19 determines it as a start signal and generates a skew setup start signal (RTS_Start). Subsequently, the skew check unit 19 searches for an optimal skew timing during the skew adjustment period.

The skew adjustment signal 155H may define a skew adjustment section by repeating 0 (Low: L) and 1 (H) for a preset number of times, for example, 5 times. The skew check unit 19 generates an enable signal RTS_ADJEN defining a section of the skew adjustment signal 155H received following the start signal 3FFH. Whenever the skew adjustment signal 155H is 0, an optimal skew timing is found and a setup signal indicating a clock to be generated at this skew timing is generated. When the skew adjustment signal 155H is generated as “LH LH LH LH LH” as shown in FIG. 7 , the setup signal RTS_ADJ is output at every five rising edges in the skew adjustment signal 155H. The optimal clock selector 18 selects clocks CLK1 to CLK24 indicated by the setup signal RTS_ADJ whenever the setup signal RTS_ADJ is received during the skew adjustment period RTskew Adjust.

The skew hold period is a period in which an ADC data packet including actual ADC data output from the ADC is received by the timing controller (TCON). During the skew hold period, the timing controller (TCON) samples the ADC data with the previously selected clock without performing real-time skew adjustment.

The optimal skew timing between the timing controller TCON and the source drive ICs SIC1 to SIC12 varies depending on the wiring length or circuit delay time. For example, when the optimal skew timing of the timing controller TCON and the sixth source drive IC SIC6 is the twelfth clock CLK12, the optimal skew timing of the timing controller TCON and the first source drive IC SIC1 is This may be the first clock CLK12. Therefore, whenever every ADC data packet is received, the timing controller TCON finds an optimal skew timing using a signal received prior to the ADC data packet and selects a clock. This real-time skew adjustment is performed for all source drive ICs SIC1 to SIC12.

In FIG. 8, “B-LVDS” is data received from the source drive ICs (SIC1 to SIC12) through the ADC wiring (SL) to the timing controller (TCON), and “EPI” is the timing controller ( TCON) to the source drive ICs (SIC1 to SIC12).

As shown in Fig. 8, 24 bits are allocated in one EPI data packet. During the skew adjustment period, 1 bit in the length of 1 EPI data packet is received from the source drive ICs (SIC1 to SIC12) to the timing controller (TCON). The rising timing of the reference clock CLK0 is synchronized to the center of each of the 24 bits of one EPI data packet. 24 bits of one EPI data packet are sampled at each rising timing of the reference clock CLK0 and transmitted to the source drive ICs SIC1 to SIC24.

The clock generator 17 shifts the phase of the reference clock CLK0 by one bit of the EPI data, that is, by one clock of the reference clock CLK0 during the skew adjustment period to shift the first to 24th clocks CLK1 to CLK24) is output. The first clock CLK1 is in phase with the reference clock CLK0.

The skew check unit 19 determines that when the skew adjustment signal received from the source drive ICs SIC1 to SIC12 is “0(=L)” during the skew adjustment period, the duty among the clocks CLK1 to CLK24 is about 50 A clock of :50, that is, having a duty ratio of 50%, is selected as the optimal clock and selected as the sampling clock of the ADC data received during the skew hold period.

During the skew adjustment section, when the skew adjustment signal received from the source drive IC (SIC1~SIC12) is “0(=L)”, the clock with a duty of about 50:50 is the reference clock (CLK0) and the clock generator ( 17) may be detected based on a result of an AND operation on the clocks CLK1 to CLK24. As a result of the AND operation of the reference clock (CLK0) and the clocks (CLK1 to CLK24), when the skew adjustment signal is “0(=L)”, the duty of 11 consecutive clocks with “1(-H)” is “0(=L)” It can be determined that the clock is about 50:50. 8 and 9 show examples in which the twelfth clock CLK12 is selected.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

17: clock generation unit 18: optimum clock selection unit
19: skew check unit 100: display panel
110: data driver 120: gate driver
130: timing controller 131, 14: compensation unit

Claims (12)

a data driver including one or more source drive ICs for outputting data after outputting a start signal and a skew adjustment signal; and
The data driver transmits image data through a first wire, receives the start signal and the skew adjustment signal from the data driver through a second wire, selects a clock based on the skew adjustment signal, and selects the clock as the selected clock. a timing controller for sampling data received following the skew adjustment signal;
the timing controller
a reference clock generator for generating a reference clock;
a clock generator receiving the reference clock and shifting a phase of the reference clock by a predetermined time to generate a plurality of clocks;
Setup for receiving the start signal and the skew adjustment signal prior to the data from the data driver, selecting a clock based on a comparison result between the skew adjustment signal and the clocks generated by the clock generator, and instructing the selected clock a skew check unit that generates a signal more than once; and
and an optimal clock selector for selecting a clock indicated by the setup signal from among the clocks input from the clock generator. The method of claim 1,
In the start signal, the bits of a specific logical value are continuous for a predetermined number of times,
A display device in which the skew adjustment signal repeats a first logic value and a second logic value. delete The method of claim 1,
wherein the timing controller samples data received following the skew adjustment signal with a clock selected by the optimal clock selector. The method of claim 1,
The clock generator
A display device for generating a plurality of clocks whose phases are sequentially shifted by shifting the reference clock by one clock of the reference clock. 6. The method of claim 5,
A display device in which clocks are generated from the clock generator by the number of bits in one data packet transmitted to the data driver. 3. The method of claim 2,
The skew check unit selects one of the clocks from the first logical value, and generates the setup signal at a rising edge that is inverted from the first logical value to the second logical value. 8. The method of claim 7,
The optimal clock selector selects a clock indicated by a last setup signal from among a plurality of setup signals received from the skew checker during a period in which the skew adjustment signal is received. 8. The method of claim 7,
The optimal clock selector selects a clock for each setup signal received from the skew checker during a period in which the skew adjustment signal is received, and selects the most selected clock as a final clock. The method of claim 1,
The skew check unit selects a clock having a duty ratio of 50% from among the clocks generated by the clock generator when the skew adjustment signal has a specific logic value. 11. The method of claim 10,
The skew check unit determines when the skew adjustment signal is a specific logic value.
A display device for selecting the clock based on an AND operation between the reference clock and the clocks generated by the clock generator. 12. The method of any one of claims 1, 2, and 4 to 11,
The data received subsequent to the skew adjustment signal includes information on a sensing result of an electrical characteristic of a pixel.

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