KR102063350B1 - Timing controller and display device using the same - Google Patents

Abstract

The present invention relates to a timing controller and a display device using the same, the timing controller comprising: an interface receiving circuit including an error counter for counting an error of received data; A signal processor for aligning data received through the interface receiving circuit and generating timing control signals; An interface transmission circuit for transmitting the data arranged by the signal processor to the outside; And an initialization control unit for initializing at least one of the interface receiving circuit, the signal processing unit, and the interface transmitting circuit if the error count value from the error counter is greater than a predetermined threshold.

Description

TIMING CONTROLLER AND DISPLAY DEVICE USING THE SAME}

The present invention relates to a timing controller and a display device using the same.

Flat display devices include Liquid Crystal Display Device (LCD), Organic Light Emitting Display Device (OLED Display), Electrophoretic Display Device (EPD), Plasma Display Panel : PDP).

As an interface method for data transmission in a liquid crystal display, a low-voltage differential signaling (LVDS) interface has been mainly used. The LVDS interface could not adequately cope with the increased data amount due to the high resolution of the liquid crystal display, the color depth expansion, and the 2x or 4x driving to improve the response speed. In Full HD (1920 x 1080), a 120Hz panel with 10-bit color depth requires 48 pairs of 24 pairs to adopt the LVDS interface. In the LVDS interface, the clock signal is transmitted along with the data. Therefore, in the LVDS interface, as the amount of data increases, the clock frequency also increases, requiring electromagnetic interference (EMI) control.

The LVDS interface specification requires a signal that varies around 1.2V at ground (GND). The implementation of the large scale integration (LSI) miniaturization process has placed a significant limitation on the LSI design due to the signal voltage specification required at the LVDS interface. In this situation, interfaces such as DVI (Digital Video Interface), HDMI (High Definition Multimedia Interface), and DisplayPort have been put to practical use.

DVI and HDMI have skew adjustment, and HDMI has built-in high-bandwidth digital content protection (HDCP) as a content protection feature, which has many advantages in transmitting video signals between devices, but requires license fees and Internal video signal transmission has the disadvantage of excessive function and high power consumption.

The DisplayPort interface is standardized as a replacement for LVDS by the Video Electronics Standards Association (VESA). The DisplayPort interface consists of three independent but interconnected standards. The DisplayPort interface is divided into an external DisplayPort interface, an embedded DisplayPort (eDP) for mobile PCs, and an internal DisplayPort (iDP) for digital TVs. The external DisplayPort interface primarily connects the PC to the monitor. Introduced in 2008, eDP is designed to replace LVDS inside mobile PCs and all-in-one desktop PCs.

Display devices are rapidly developing thin, light and high resolution. In accordance with this trend, applications of high-speed data interfaces such as a DisplayPort interface are expanding as an interface of a display device. High-speed data interface integrated circuit chips (ICs) employ low power processes to reduce power consumption, but they are more vulnerable to electrostatic discharge (ESD) problems due to low power processing.

The driving circuit of the display device may include a data driver for outputting a data voltage, a gate driver (or scan driver) for outputting a gate pulse (or scan pulse) in synchronization with the data voltage, and controlling operation timing of the data driver and the gate driver. Timing controller (TCON), and the like. The timing controller receives digital video data of an input image from an external host system through a standard high-speed data interface such as DisplayPort, and aligns the data to the data driver. The timing controller receives a timing signal synchronized with the input image data from the host system and controls an operation timing of the data driver and the gate driver based on the timing signal.

When the high-speed data interface receiving circuit is incorporated in the timing controller, it is vulnerable to electrostatic discharge (ESD). For example, when electrostatic discharge (ESD) is applied to the timing controller, the digital logic circuit in the timing controller malfunctions and this malfunction appears to be noise in the display image.

The present invention provides a timing controller and a display device using the same to reduce the malfunction caused by static electricity.

The timing controller of the present invention includes an interface receiving circuit having an error counter for counting an error of received data; A signal processor for aligning data received through the interface receiving circuit and generating timing control signals; An interface transmission circuit for transmitting the data arranged by the signal processor to the outside; And an initialization control unit for initializing at least one of the interface receiving circuit, the signal processing unit, and the interface transmitting circuit if the error count value from the error counter is greater than a predetermined threshold.

According to an exemplary embodiment of the present invention, a display device includes: a display panel driver which writes data into pixels of a display panel; And a timing controller configured to transmit data of an input image to the display panel driver and to control an operation timing of the display panel driver.

The timing controller includes the interface receiving circuit, the signal processor, the interface transmitting circuit, and the initialization controller.

The present invention can minimize the malfunction of the timing controller caused by static electricity by initializing the internal circuit of the timing controller when the count value of the data received by the timing controller is greater than the predetermined threshold value.

1 is a block diagram illustrating a timing controller according to an embodiment of the present invention.
2 is a flowchart illustrating an interface procedure of a timing controller according to an embodiment of the present invention.
3 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The display device of the present invention can be implemented as any flat panel display device including a display panel, a driving circuit of the display panel, and a timing controller for controlling the operation timing of the driving circuit. For example, the display device of the present invention may be implemented as a flat panel display device such as a liquid crystal display (LCD), an organic light emitting display (OLED display), an electrophoretic display (EPD), a plasma display panel (PDP).

1 and 2, a timing controller 100 according to an exemplary embodiment of the present invention may include an interface receiving circuit (Rx (DP)) 102, an error counter 101, a signal processor 104, and an initialization controller ( 108, and an interface transmission circuit (Tx (TCON)) 110.

The timing controller 100 rearranges the digital video data of the input image input from the external host system and transmits the digital video data to the data driver. In addition, the timing controller 100 receives an input timing signal synchronized with the data of the input image from the host system and based on the input timing signal and predetermined waveform information, the data driver (FIGS. 3 and 12) and the gate driver (FIG. 3). , And generate timing control signals for controlling the operation timing. The input timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable, DE, and a main clock CLK. The input timing signal configuration may vary according to the type of the high speed data interface between the timing controller 100 and the host system.

The present invention periodically counts the number of errors of data during data transmission and reception between the timing controller 100 and the host system, and initializes the signal processing unit 104 of the timing controller 100 when the number of errors exceeds a preset threshold. To this end, an error check circuit may be added to the high speed data interface between the timing controller 100 and the host system, but a high speed data interface standard having an error check function, for example, a display port ( DisplayPort) interface is preferably embedded in the timing controller 100.

The interface receiving circuit 102 is embedded in the timing controller 100 and connected to the interface transmitting circuit of the host system to receive data. The interface receiving circuit 102 may incorporate a Clok and Data Recovery (CDR) circuit. The CDR circuit recovers the clock received from the host system to generate an internal clock. The timing controller 100 samples data in accordance with the internal clock timing.

The interface transmitting circuit of the host system and the interface receiving circuit 102 of the timing controller 100 transmit and receive data according to a protocol of a high speed data interface standard having an error checking function. The error counter 101 of the interface receiving circuit 02 receives an error count of data received when data is received after link training on a main link between the host system and the timing controller 100. Is counted and the result is supplied to the initialization control unit 108.

The signal processing unit 104 includes a data processing logic circuit for aligning digital video data received through the interface receiving circuit 102, a register for storing timing information from an electrically erasable programmable read-only memory (EEPROM) 106, and A timing signal generation circuit for generating timing control signals for controlling the operation timing of the data driver 12 and the gate driver 14 based on the input timing signal and the timing information.

The timing information stored in the EEPROM 106 includes pulse rising timing, pulse duration, pulse polling timing information of timing control signals for controlling the operation timings of the data driver 12 and the gate driver 14. When the display device is turned on, the timing information of the EEPROM 106 is supplied to a register of the signal processor 104 and stored in the register.

A data interface is applied to transmit and receive data between the timing controller 100 and the data driver. This data interface can be selected with mini Low Voltage Differential Signaling (LVDS). In addition, the data interface between the timing controller 100 and the data driver is the applicant of the Republic of Korea Patent Application 10-2008-0127458 (2008-12-15), US Application 12 / 543,996 (2009-08-19), Republic of Korea Patent Application 10 -2008-0127456 (2008-12-15), US application 12 / 461,652 (2009-08-19), Korean patent application 10-2008-0132466 (2008-12-23), US application 12 / 537,341 (2009-08 -07) can be applied to the interface proposed in the. In order to implement an interface between the timing controller 100 and the data driver, the timing controller 100 includes an interface transmission circuit 110 and the data driver 12 includes an interface receiving circuit.

The initialization control unit 108 compares the error count value from the interface receiving circuit 102 with a preset threshold. The initialization controller 108 initializes one or more of the interface receiving circuit 102, the signal processing unit 104, and the interface transmitting circuit 110 when the error count value is greater than the threshold value.

When electrostatic discharge (EPD) is applied to the timing controller 100, the number of errors of data received by the timing controller 100 increases rapidly. At this time, the initialization control unit 108 monitors the error count value and initializes the signal processing unit 104. The present invention initializes one or more of the interface receiving circuit 102, the signal processing unit 104, and the interface transmitting circuit 110 when static electricity is applied to the timing controller 100, thereby preventing malfunction of the timing controller 100 and causing abnormality. (abnormal) Minimize the image display.

2 is a flowchart illustrating an interface procedure of the timing controller 100.

Referring to FIG. 2, when the power of the display device is turned on, the interface between the timing controller 100 and the host system starts to be driven.

First, the interface transmitting circuit transmits a predetermined link training pattern signal to the interface receiving circuit 102 to drive the CDR circuit of the interface receiving circuit 102. (S1) If the link training is not completed, the interface is delayed by a predetermined time. After the link training is resumed (S7).

After the link training, the interface transmitting circuit shifts to the normal display mode and starts transmitting data to the interface receiving circuit 102. (S2 and S3) In the normal display mode, the interface receiving circuit 102 The error counter counts an error amount of the received data in a preset time unit and transmits the count value to the initialization control unit 108 (S4).

The initialization control unit 108 compares the error count value with a preset threshold. The initialization control unit 108 initializes one or more of the interface receiving circuit 102, the signal processing unit 104, and the interface transmitting circuit 110 when the error count value is larger than the threshold value (S5 and S6). If the error count value is less than or equal to the threshold value, the controller 101 resumes the error count after being delayed by a predetermined time under the control of the initialization control unit 108 (S5 and S8).

3 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the display device of the present invention includes a display panel 10, a display panel driver, a timing controller 100, and a host system 200.

The display panel 10 includes a pixel array in which an input image is displayed. The pixel array is defined by data lines 13 to which data voltages are supplied, gate lines 15 orthogonal to the data lines 13, and intersections of the data lines 13 and the gate lines 15. Pixels 11 arranged in a matrix form. Each of the pixels 11 may include one or more TFTs and a capacitor.

The display panel driver writes data of an input image to pixels of the display panel 10. The display panel driver includes a data driver 12 and a gate driver 14. The data driver 12 converts digital video data of an input image input from the timing controller 100 into an analog gamma compensation voltage to generate a data voltage, and supplies the data voltage to the data lines DL. The gate driver 102 generates a gate pulse synchronized with the data voltage, and sequentially supplies the gate pulse to the gate lines GL while shifting the gate pulse.

The timing controller 100 receives digital video data RGB and timing signals of an input image from the host system 200. The timing controller 100 generates timing control signals for controlling the operation timing of the data driver 12 and the gate driver 14 using the timing signals.

The timing controller 100 receives data of an input image from the host system 200 through a high-speed data interface having an error check function, checks an error of the data, and initializes internal circuits when an electrostatic discharge (ESD) is generated.

The host system is implemented as any one of a television system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system to receive an input image. The host system executes an application program associated with the touch input coordinates received from the touch controller 100.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

10: display panel 12: data driver
14: gate driver 100: timing controller (TCON)
200: host system

Claims (8)

An interface receiving circuit incorporating an error counter for counting an error of data received from the host system;
A signal processor for aligning data received through the interface receiving circuit and generating timing control signals;
An interface transmission circuit for transmitting the data arranged by the signal processor to a data driver; And
And an initialization control unit for initializing at least one of the interface receiving circuit, the signal processing unit, and the interface transmitting circuit if the error count value from the error counter is greater than a predetermined threshold value. The method of claim 1,
And the interface receiving circuit is a display port interface receiving circuit. A display panel driver which writes data to pixels of the display panel; And
A timing controller which transmits data of an input image input from a host system to the display panel driver and controls an operation timing of the display panel driver;
The timing controller,
An interface receiving circuit incorporating an error counter for counting an error of data received from the host system;
A signal processor for aligning data received through the interface receiving circuit and generating timing control signals;
An interface transmission circuit for transmitting the data arranged by the signal processor to the display panel driver; And
And an initialization control unit for initializing at least one of the interface receiving circuit, the signal processing unit, and the interface transmitting circuit if the error count value from the error counter is greater than a predetermined threshold value.
The method of claim 3, wherein
And the interface receiving circuit is a display port interface receiving circuit. The method of claim 3, wherein
The interface receiving circuit receives timing signals and digital video data RGB from the host system.
The signal processor may include a data processing logic circuit to align the digital video data received through the interface receiving circuit, a register to store prestored timing information, and the received timing signals and the stored timing information. And a timing signal generation circuit for generating timing control signals for controlling the operation timing of the display panel driver.
The method of claim 5,
The interface receiving circuit has a built-in CDR (Clok and Data Recovery) circuit for generating an internal clock based on the clock received from the host system,
And the signal processor samples the video data according to the internal clock generated by the CDR circuit.
The method of claim 3, wherein
The display panel driver,
And a data driver and a gate driver.
The method of claim 3, wherein
And the error counter resumes the error count after a delay for a predetermined time under the control of the initialization controller if the error count value is less than or equal to the threshold value.

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