JP2007286305A - Driving circuit, driving method, electrooptical device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving circuit and a driving method capable of suppressing the influence to an image quality to the minimum even when an error occurs in a receiving signal containing display data, to provide an electrooptical device comprising the driving circuit and to provide electronic equipment comprising the electrooptical device. <P>SOLUTION: The driving circuit for driving the electrooptical device based on the display data produced from a receiving signal obtained via an interface circuit which detects the error of the receiving signal comprises: an error processing part which counts the number of error detection and detects whether the number of the detection continues by a prescribed number or not; and a source line driving part for driving a source line of the electrooptical device based on the display data. The source line driving part performs a driving control of the electrooptical device so as to express an off display irrespective of the display data, provided it is detected by the error processing part that the number of the detection continues by the prescribed number. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a drive circuit, a drive method, an electro-optical device, and an electronic apparatus.

  In recent years, a display panel represented by a liquid crystal panel (an electro-optical device in a broad sense) has been increased in definition and screen size, and the data size of display data for one screen has been rapidly increased. In addition, although the number of display data bits per pixel also increases and the number of signal lines for transmitting display data tends to increase, there is a demand for downsizing electronic devices on which display panels are mounted. The increase in the number of lines has become a major issue in mounting display panels.

  Therefore, when supplying display data to a drive circuit for driving the display panel, the display data is converted into a low amplitude signal and transmitted at high speed, thereby increasing the data size of the display data and the number of signal lines. It corresponds to the increase.

For example, in Patent Document 1, a signal obtained by converting a high-amplitude parallel signal into a low-amplitude serial signal is transmitted between the display device and a display controller that drives the display device, and the high-amplitude parallel signal is transmitted on the display device side. An interface for converting to is disclosed.
JP-A-9-127908

  However, even the interface disclosed in Patent Document 1 is more susceptible to external noise as the frequency increases. As a result, the received signal may be different from the signal that should be received, which may cause image degradation on the display side. On the other hand, even if an error in the received signal is detected by accident, if the display is controlled so as not to affect the image quality, a stable image display can be obtained when using the interface as described above. It cannot be realized. Thus, how to deal with an error in the received signal becomes important.

  On the other hand, even if an error once occurs in the received signal, the error does not always continue to occur in the received signal thereafter. In such a case, a countermeasure that suppresses the influence on the image quality as much as possible is desired.

  The present invention has been made in view of the technical problems as described above, and an object thereof is to minimize the influence on image quality even if an error occurs in a reception signal including display data. It is an object to provide a driving circuit, a driving method, an electro-optical device, and an electronic apparatus.

In order to solve the above problems, the present invention
A driving circuit for driving the electro-optical device based on display data generated from a reception signal obtained through an interface circuit for detecting an error in the reception signal;
An error processing unit that counts the number of times the error has been detected and detects whether the number of times the detection has continued a given number of times;
A source line driving unit for driving a source line of the electro-optical device based on the display data,
The source line driver is
Related to a drive circuit that controls the driving of the electro-optical device so that the display is turned off regardless of the display data on the condition that the error processing unit detects that the number of times of detection continues for a given number of times. To do.

  In the present invention, the number of detected errors of the received signal is counted, and the off display is performed on the condition that it is detected that the number of detections continues for a given number of times. As a result, even if an error in the received signal is detected by chance, stable image display can be realized without immediately performing off display control in order to avoid an influence on the image quality.

In the driving circuit according to the present invention,
The error processing unit
Count the number of normal reception of the received signal, detect whether the number of normal reception is a given number of times,
The source line driver is
Drive control of the electro-optical device can be performed based on display data on the condition that the error processing unit detects that the normal reception count continues for a given number of times during the off-display period. .

  Further, in the present invention, the ON display is performed after confirming the stable normal reception without immediately controlling the ON display just because the normal reception of the received signal is detected by chance. As a result, it is possible to minimize degradation of image quality.

In the driving circuit according to the present invention,
The switching timing from the off display period to the on display period in which the drive control of the electro-optical device based on the display data is performed may be a start timing of one vertical scanning period.

In the driving circuit according to the present invention,
The off display is
It may be performed in synchronization with the start timing of one horizontal scanning period.

The present invention also provides
A driving circuit for driving the electro-optical device based on display data generated from a reception signal obtained through an interface circuit for detecting an error in the reception signal;
An error processing unit that counts the number of times of normal reception of the received signal and detects whether the number of times of normal reception continues for a given number of times;
A source line driving unit for driving a source line of the electro-optical device based on the display data,
The present invention relates to a drive circuit that performs drive control of the electro-optical device based on display data on the condition that the error processing unit detects that the given number of normal receptions continues for a given number of times during the off display period. To do.

  In the present invention, the number of times of normal reception of the received signal is counted, and ON display is performed on the condition that it is detected that the number of normal receptions continues for a given number of consecutive times. As a result, even if the normal reception of the received signal is detected by accident, the on display can be performed after confirming the stable normal reception without immediately controlling the on display, thereby minimizing image quality degradation. It becomes possible to limit to the limit.

In the driving circuit according to the present invention,
The switching timing from the off display period to the on display period in which the drive control of the electro-optical device based on the display data is performed may be a start timing of one vertical scanning period.

In the driving circuit according to the present invention,
The received signal is a serial signal;
The error processing unit
The number of detections or the number of normal receptions can be obtained by counting the presence or absence of errors for each pixel.

In the driving circuit according to the present invention,
The source line driver is
Each output buffer includes a plurality of output buffers for driving each source line of the plurality of source lines of the electro-optical device;
The output of each output buffer connected to each source line to which a given off signal is supplied during the off display period may be controlled to be in a high impedance state.

In the driving circuit according to the present invention,
The source line driver is
A given off signal can be supplied to a plurality of source lines of the electro-optical device during the off-display period.

In the driving circuit according to the present invention,
In the case where the electro-optical device includes a plurality of pixel electrodes that are specified by the gate lines of the plurality of gate lines and the source lines of the plurality of source lines,
The off display can be performed by controlling so that the voltage of the counter electrode facing each pixel electrode is applied to the pixel electrode.

  According to any one of the above-described inventions, it is possible to realize off-display drive control with a simple configuration.

The present invention also provides
A driving method for driving an electro-optical device based on display data,
Count the number of detection errors of the received signal for generating the display data,
Detect if the number of detections is a given number of times,
In a period in which it is not detected that the number of detections is a given number of times, the electro-optical device is driven based on display data obtained from the reception signal,
The present invention relates to a driving method for controlling the driving of the electro-optical device so that the display is turned off regardless of the display data on the condition that the number of times of detection is detected to be a given number of times.

In the driving method according to the present invention,
Count the number of normal reception of the received signal,
Detecting whether the number of normal receptions is a given number of times,
Drive control of the electro-optical device can be performed based on display data on the condition that it is detected that the number of normal receptions continues for a given number of times during the off-display period.

The present invention also provides
A driving method for driving an electro-optical device based on display data,
Count the number of normal reception of the reception signal for generating the display data,
Detecting whether the number of normal receptions is a given number of times,
In the period in which the normal reception count is not detected to be a given number of times during the off display period, the off display is continued regardless of the display data,
The present invention relates to a driving method for controlling the driving of the electro-optical device based on display data on the condition that the normal reception frequency is detected to be a given number of times during the off-display period.

The present invention also provides
Multiple gate lines,
Multiple source lines,
A plurality of pixels each pixel is specified by each gate line of the plurality of gate lines and each source line of the plurality of source lines;
The present invention relates to an electro-optical device that includes at least one of the plurality of gate lines and at least the plurality of source lines among the plurality of source lines.

  According to the present invention, it is possible to provide an electro-optical device capable of minimizing the influence on image quality even if an error occurs in a reception signal including display data.

The present invention also provides
The present invention relates to an electronic apparatus including the electro-optical device described above.

The present invention also provides
With the host,
A transmission side interface circuit connected to the host;
A receiving side interface circuit for receiving a serial signal from the transmitting side interface circuit;
The drive circuit according to any one of the above, wherein display data obtained from a reception signal of the reception-side interface circuit is supplied
The present invention relates to an electronic apparatus including an electro-optical device driven by the drive circuit based on the display data.

  According to the present invention, it is possible to provide an electronic apparatus including an electro-optical device that minimizes the influence on image quality even if an error occurs in a reception signal including display data.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. FIG. 1 shows an outline of the configuration of an active matrix liquid crystal display device according to this embodiment. In FIG. 1, a liquid crystal display device using an active matrix liquid crystal display panel as an electro-optical device will be described. However, a liquid crystal display device using a passive matrix liquid crystal display panel may be used. Further, the electro-optical device according to the present invention is not limited to the liquid crystal display panel.

  The liquid crystal display device 10 includes a liquid crystal display panel (display panel in a broad sense, electro-optical device in a broader sense) 20. The liquid crystal display panel 20 is formed on a glass substrate, for example. On this glass substrate, a plurality of gate lines (scanning lines) GL1 to GLM (M is an integer of 2 or more) arranged in the Y direction and extending in the X direction, and a source line arranged in the X direction and extending in the Y direction, respectively. (Data lines) SL1 to SLN (N is an integer of 2 or more) are arranged. The pixel region corresponds to the intersection position of the gate line GLm (1 ≦ m ≦ M, m is an integer, the same applies hereinafter) and the source line SLn (1 ≦ n ≦ N, n is an integer, the same applies hereinafter). (Pixel) is provided, and a thin film transistor (hereinafter abbreviated as TFT) 22 mn is disposed in the pixel region.

  The gate of the TFT 22mn is connected to the gate line GLn. The source of the TFT 22mn is connected to the source line SLn. The drain of the TFT 22mn is connected to the pixel electrode 26mn. Liquid crystal (electro-optical material in a broad sense) is sealed between the pixel electrode 26 mn and a counter electrode 28 mn facing the pixel electrode 26 mn, thereby forming a liquid crystal capacitor (liquid crystal element in a broad sense) 24 mn. The transmittance of the pixel changes according to the applied voltage between the pixel electrode 26mn and the counter electrode 28mn. The counter electrode voltage VCOM is supplied to the counter electrode 28mn.

  Such a liquid crystal display panel 20 includes, for example, a first substrate on which a pixel electrode and a TFT are formed and a second substrate on which a counter electrode is formed, and a liquid crystal as an electro-optical material between the two substrates. It is formed by enclosing.

  The liquid crystal display device 10 includes a display driver 40 (drive circuit in a broad sense). The display driver 40 drives the liquid crystal display panel 20. The display driver 40 includes a source driver (data driver) 30 and a gate driver (scan driver) 32. The source driver 30 drives the source lines SL1 to SLN of the liquid crystal display panel 20 based on display data (gradation data). The gate driver 32 sequentially drives (scans) the gate lines GL1 to GLM of the liquid crystal display panel 20 within one vertical scanning period.

  Further, the liquid crystal display device 10 can include a power supply circuit 100. The power supply circuit 100 generates voltages necessary for driving the source lines and supplies them to the source driver 30. The power supply circuit 100 generates a voltage necessary for scanning the gate line and supplies it to the gate driver 32.

  Furthermore, the power supply circuit 100 includes a common electrode voltage generation circuit, and the common electrode voltage generation circuit generates the common electrode voltage VCOM. That is, the power supply circuit 100 generates the common electrode voltage VCOM that periodically repeats the high potential side voltage VCOMH and the low potential side voltage VCOML in accordance with the timing of the polarity inversion signal POL generated by the source driver 30. Output to the counter electrode.

  The liquid crystal display device 10 can include a host 38. The host 38 includes a central processing unit (hereinafter abbreviated as “CPU”) and a memory (not shown) and a CPU that reads and executes a program stored in the memory, and each part of the display driver 40 and a power supply circuit. Processing for controlling 100 is realized. For example, the host 38 performs operation mode setting, polarity inversion driving setting, polarity inversion timing setting, supply of internally generated vertical synchronization signal and horizontal synchronization signal, and the like to the source driver 30 and the gate driver 32. The host 38 can be referred to as a processing unit in a broad sense.

  In FIG. 1, the liquid crystal display panel 20 includes switch circuits SW1 to SWN in which one end of each switch circuit is electrically connected to the counter electrode and the other end is electrically connected to one of the source lines SL1 to SLN. . The switch circuits SW1 to SWN are on / off controlled based on a switch control signal CP from the display driver 40 (more specifically, the source driver 30). When the switch circuit SWn is set in a conductive state by the switch control signal CP, the common electrode voltage VCOM (a given off signal in a broad sense) is supplied to the source line SLn. At this time, the source driver 30 does not drive the source line SLn, and the counter electrode voltage VCOM is supplied to the source line SLn set in the high impedance state.

  In FIG. 1, only the switch circuit connected to the source line SLn is shown, but the N switch circuits connected to the source lines SL1 to SLN are simultaneously turned on / off by the switch control signal CP. The

  In FIG. 1, the liquid crystal display device 10 includes the power supply circuit 100 or the host 38, but at least one of them may be provided outside the liquid crystal display device 10. .

  The source driver 30 may incorporate at least one of the gate driver 32 and the power supply circuit 100.

  Furthermore, some or all of the display driver 40, the host 38, and the power supply circuit 100 may be formed on the liquid crystal display panel 20. For example, in FIG. 2, a display driver 40 is formed on the liquid crystal display panel 20. As described above, the liquid crystal display panel 20 includes a plurality of gate lines, a plurality of source lines, a pixel (pixel electrode) specified by one of the plurality of gate lines and one of the plurality of source lines, and a plurality of gate lines. And a source driver for driving a plurality of source lines. A plurality of pixels are formed in the pixel formation region 78 of the liquid crystal display panel 20.

2. Interface Circuit In this embodiment, the host 38 and the display driver 40 are connected via a serial bus. The serial bus is composed of two sets of differential signal lines, and a transfer signal between the host 38 and the display driver 40 is converted into two sets of differential signals and transmitted. More specifically, three or more types of transmission signals from the host 38 are converted into two sets of differential signals by a transmission interface (Interface: hereinafter referred to as I / F) circuit and transferred via a serial bus. Is done. Then, the signal is converted into a plurality of original transmission signals by the reception I / F circuit connected to the serial bus and supplied to the display driver 40.

  FIG. 3 shows a block diagram of a configuration example between the host 38 and the display driver 40 in the present embodiment.

  In FIG. 3, the host 38 is provided with a transmission I / F circuit 50 that outputs five types of transmission signals, receives the transmission signals, and converts them into two sets of differential signals. The transmission I / F circuit 50 converts the transmission signal from the host 38 into two sets of differential signals whose maximum amplitude value is lower than that of the transmission signal, and the converted differential signal is a serial bus (differential signal line). Control to output to 52 is performed. That is, parallel transmission signals from the host 38 are parallel / serial converted and transmitted as serial differential signals. In FIG. 3, the transmission I / F circuit 50 is provided outside the host 38, but may be provided inside the host 38.

  A reception I / F circuit 54 is connected to the other end of the serial bus 52 to which the transmission I / F circuit 50 is connected. The reception I / F circuit 54 converts the reception signal received via the serial bus 52 into an original signal whose maximum amplitude value is higher than that of the reception signal, and supplies the signal to the drive unit 60 of the display driver 40. The drive unit 60 includes the source driver 30 and the gate driver 32 shown in FIG. In FIG. 3, the reception I / F circuit 54 is provided inside the host 38, but may be provided outside the host 38.

  In this embodiment, the reception I / F circuit 54 detects an error in the reception signal from the host 38 (more specifically, the transmission I / F circuit 50), and the detection result is used as an error detection signal CPO. 60 (more specifically, the source driver 30) is notified. The reception I / F circuit 54 can detect a parity error of the reception signal transmitted via the serial bus 52.

  Thereby, even when the data size of the display data for one screen for driving the liquid crystal display panel 20 is increased, the host 38 can supply the display data and the like to the display driver 40.

  As described above, a system (electronic device in a broad sense) in which the display driver 40 according to this embodiment is mounted includes a host 38, a transmission I / F circuit 50 (transmission-side interface circuit) connected to the host 38, and a transmission. A reception I / F circuit 54 (reception side interface circuit) that receives a serial signal from the I / F circuit 50, a display driver 40 to which display data obtained from the reception signal of the reception I / F circuit 54 is supplied, and a display And the liquid crystal display panel 20 driven by the display driver 40 based on the data.

  FIG. 4 shows an example of a transmission signal output from the host 38.

  The host 38 outputs display control signals (VS, HS, DE, PCLK) and display data DBUS. For example, when one pixel is composed of 3 dots, the display data DBUS includes, for example, 8-bit R component gradation data, 8-bit G component gradation data, and 8-bit B component gradation data. That is, the display data DBUS is 24-bit data. In this display data DBUS, 24-bit data for one pixel is sequentially transferred in synchronization with the pixel clock signal PCLK.

  Of the display control signals, the vertical synchronization signal VS is a signal that defines one vertical scanning period. For example, one vertical scanning period is defined by a falling edge of the vertical synchronization signal VS. The horizontal synchronization signal HS is a signal that defines one horizontal scanning period. For example, one horizontal scanning period is defined by the falling edge of the horizontal synchronization signal HS. The data enable signal DE is a signal indicating whether or not the display data DBUS is valid. The display data DBUS when the data enable signal DE is at the H level is valid, and the display data DBUS when the data enable signal DE is at the L level is invalid. The pixel clock signal PCLK is a synchronization signal for transferring the display data DBUS for each pixel.

  Thus, the host 38 outputs a 4-bit display control signal and 24-bit display data. The transmission I / F circuit 50 receives a total of 28-bit signals from the host 38, converts them into two sets of differential signals, and transmits the differential signals to the display driver 40 via the serial bus 52.

  FIG. 5 shows an example of a differential signal transmitted via the serial bus 52.

  The serial bus 52 includes a first differential signal line for data transfer and a second differential signal line for clock transfer. A data signal D and an inverted data signal DX whose phases are inverted from each other are output to the two signal lines constituting the first differential signal line. A clock signal CLK and an inverted clock signal CLKX whose phases are inverted from each other are output to the two signal lines constituting the second differential signal line. The clock signal CLK and the inverted clock signal CLKX serve as transfer reference timing for serial transfer via the serial bus 52. The data signal D and the inverted data signal DX change in order to transfer the display control signals (VS, HS, DE, PCLK) serially.

  Then, during a period when the clock signal CLK is at L level (period when the inverted clock signal CLKX is at H level), a data signal D and an inverted data signal DX having a predetermined number of R bits (R is an integer of 2 or more) are transmitted. The Similarly, the data signal D of R bits and the inverted data signal DX are transmitted during a period when the clock signal CLK is at the H level (a period when the inverted clock signal CLKX is at the L level).

  3 converts the display control signal and display data shown in FIG. 4 into the differential signal shown in FIG. On the other hand, the reception I / F circuit 54 of FIG. 3 converts the differential signal shown in FIG. 5 into the display control signal and display data shown in FIG. The presence / absence is detected and an error detection signal CPO is output. Then, the output signal of the reception I / F circuit 54 is supplied to the drive unit 60.

  FIG. 6 shows a block diagram of a configuration example of the reception I / F circuit 54 of FIG.

  The reception I / F circuit 54 includes first and second differential receivers Rx1 and Rx2, a serial / parallel conversion circuit 70, a PLL (Phase Lock Loop) circuit 72, a timing generation circuit 74, and a display control signal output circuit 76. .

  The second differential receiver Rx2 connected to the second differential signal line driven by the second differential transmitter Tx2 of the transmission I / F circuit 50 differentially amplifies the clock signal CLK and the inverted clock signal CLKX. As a result, a transfer reference timing for serial transfer via the serial bus 52 is generated. The PLL circuit 72 outputs to the timing generation circuit 74 a reference clock whose phase is synchronized with the output signal of the second differential receiver Rx2.

  The timing generation circuit 74 generates a reference timing signal for the serial / parallel conversion circuit 70 and the display control signal output circuit 76 based on the reference clock from the PLL circuit 72.

  The first differential receiver Rx1 connected to the first differential signal line driven by the first differential transmitter Tx1 of the transmission I / F circuit 50 differentially amplifies the data signal D and the inverted data signal DX. Thus, transfer data that is serially transferred via the serial bus 52 is generated. The serial / parallel conversion circuit 70 converts the serial signal differentially amplified by the first differential receiver Rx1 into a parallel signal in synchronization with the reference timing signal from the timing generation circuit 74. The display control signal output circuit 76 synchronizes with the reference timing signal from the timing generation circuit 74, and outputs the vertical synchronization signal VS, horizontal synchronization signal HS, data enable signal DE, pixel clock signal from the output signal of the serial / parallel conversion circuit 70. PCLK, display data DBUS (see FIG. 4), and error detection signal CPO are generated.

  The display driver 40 in the present embodiment determines whether or not an error has occurred in the signal from the host 38 based on the error detection signal CPO, and performs control to minimize the influence on the image quality.

3. Display Driver FIG. 7 shows an outline of the configuration of the display driver 40 in this embodiment.

  The display driver 40 can include the reception I / F circuit 54, the source driver 30, and the gate driver 32 described above. The signal received by the reception I / F circuit 54 is supplied to the source driver 30 or the gate driver 32.

  In FIG. 7, the configuration of the reception I / F circuit 54 is the same as that in FIG.

3.1 Gate Driver FIG. 8 shows a configuration example of the gate driver 32 of FIG.

  The gate driver 32 includes a shift register 80, a level shifter 82, and an output control circuit 84.

  The shift register 80 includes a plurality of flip-flops provided corresponding to the gate lines and sequentially connected. When the shift register 80 holds the start pulse signal VSP in the flip-flop in synchronization with the clock signal VCK, the shift register 80 sequentially shifts the start pulse signal VSP to the adjacent flip-flop in synchronization with the clock signal VCK. The clock signal VCK input here is a horizontal synchronizing signal, and the start pulse signal VSP is a vertical synchronizing signal.

  The level shifter 82 shifts the voltage level from the shift register 80 to a voltage level corresponding to the liquid crystal element of the liquid crystal display panel 20 and the transistor capability of the TFT. As this voltage level, for example, a high voltage level of 20 V to 50 V is required.

  The output control circuit 84 buffers the scanning voltage shifted by the level shifter 82, outputs the buffered voltage to the gate line, and drives the gate line. The output control circuit 84 includes an AND operation circuit provided for each gate line, and an AND operation result of the scanning voltage shifted by the level shifter 82 and the output enable signal VENB is output as a gate line selection signal. The Therefore, the gate line selection period can be adjusted by the output enable signal VENB.

3.2 Source Driver FIG. 9 shows a block diagram of a configuration example of the source driver 30 of FIG.

  The source driver 30 includes a data latch 120, a line latch 122, a level shifter 124, a reference voltage generation circuit 126, a DAC (Digital-to-Analog Converter) (voltage selection circuit in a broad sense) 128, and an output buffer 130.

  Further, the source driver 30 includes a parity error processing circuit (error processing unit) 132, a control register unit 134, a display timing generation circuit 136, and a level shifter 138.

  The data latch 120 receives the display data DBUS generated after differential amplification by the reception I / F circuit 54. The reception I / F circuit 54 supplies display data serially to the source driver 30 in units of one pixel, and the display data is sequentially taken into the data latch 120.

  The line latch 122 latches the display data fetched by the data latch 120 based on the horizontal synchronization signal HS.

  The level shifter 124 converts the voltage level of each bit signal read from the line latch 122.

  In the reference voltage generation circuit 126, each reference voltage generates a plurality of reference voltages corresponding to each display data. More specifically, the reference voltage generation circuit 126 generates a plurality of types of reference voltages obtained by resistance-dividing the voltage between the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH, and supplies the generated voltage to the DAC 128.

  The DAC 128 outputs a drive voltage (gray scale voltage) corresponding to the display data from the level shifter 124 for each source line from among a plurality of reference voltages in which each reference voltage corresponds to the display data. More specifically, the DAC 128 decodes display data for one dot from the level shifter 124 and selects one of a plurality of reference voltages based on the decoding result. The reference voltage selected by the DAC 128 is output to the output buffer 130 as a drive voltage.

  The output buffer 130 has a plurality of data output units in which each data output unit is provided corresponding to each source line. Each data output unit of the output buffer 130 drives the source line based on the drive voltage from the DAC 128. Each data output unit includes an operational amplifier connected in a voltage follower.

  The source driver 30 includes a plurality of output switches SWO1 to SWON provided between the output of the operational amplifier of the output buffer 130 and the source line, and each output switch is set to a non-conductive state. Each source line can be set to a high impedance state.

  In FIG. 9, the output lines SWO1 to SWON are provided to set the source lines SL1 to SLN connected to the output buffer 130 to a high impedance state, but the operating current of the operational amplifier of the output buffer 130 is stopped or limited. Thus, the source lines SL1 to SLN may be set to a high impedance state. In this case, the output switches SWO1 to SWON may be omitted.

  The parity error processing circuit 132 receives the error detection signal CPO and the pixel clock signal PCLK from the reception I / F circuit 54. Based on the error detection signal CPO, the parity error processing circuit 132 counts the number of parity errors detected in the reception signal of the reception I / F circuit 54, and the number of detections is Er (Er is an integer of 2 or more) times ( Whether or not a given number of times) continues is detected and output to the display timing generation circuit 136 as an error processing result signal flgCPErr.

  The parity error processing circuit 132 counts the number of normal receptions of the reception signal from the reception I / F circuit 54 based on the error detection signal CPO from the reception I / F circuit 54, and the normal reception number is Rc (Rc Is an integer greater than or equal to 2) (a given number of times), and can be detected and reflected in the error processing result signal flgCPErr and output to the display timing generation circuit 136.

  The control register unit 134 includes a plurality of control registers in which setting values for performing operation control of the source driver 30 are set. The set value of each control register is supplied from the host 38.

  The display timing generation circuit 136 generates a control signal for controlling the drive timing of the source line based on the vertical synchronization signal VS, the horizontal synchronization signal HS, the pixel clock signal PCLK, and the error processing result signal flgCPErr. The level shifter 138 converts the voltage level of each bit of the control signal generated by the display timing generation circuit 136. For example, the level shifter 138 outputs a clock signal VCK, a start pulse signal VSP, an output enable signal VENB, a switch control signal CP, and an inverting switch control signal XCP for controlling the display timing of the gate driver 32.

  The switch control signal CP is a control signal for on / off control of the switch circuits SW1 to SWN shown in FIG. The inverting switch control signal XCP is a control signal for on / off controlling the output switches SWO1 to SWON of the source driver 30. The inverting switch control signal XCP is a signal obtained by inverting the logic level of the switch control signal CP.

  As a result, when the parity error processing circuit 132 detects that the number of detected errors in the reception signal of the reception I / F circuit 54 has continued for a given number of times, the source driver 30 outputs an inversion switch control signal XCP. The switches SWO1 to SWON can be set to a non-conductive state, and the switch circuits SW1 to SWN of the liquid crystal display panel 20 can be set to a conductive state by a switch control signal CP.

  Accordingly, when it is detected by the parity error processing circuit 132 that the number of times of detection of errors in the reception signal of the reception I / F circuit 54 has continued Er times, the common electrode voltage VCOM is supplied to the source lines SL1 to SLN. it can. As a result, the voltages between the pixel electrode electrically connected to the source lines SL1 to SLN via the TFT and the counter electrode become substantially equal, and the display can be set to an off display state. That is, when it is detected by the parity error processing circuit 132 that the number of detected errors in the reception signal of the reception I / F circuit 54 is continuous Er times, the liquid crystal display panel 20 is turned off regardless of the display data. Can be controlled. As described above, the liquid crystal display panel 20 is opposed to each pixel electrode when each pixel electrode includes a plurality of pixel electrodes specified by each gate line of the plurality of gate lines and each source line of the plurality of source lines. The off-display is realized by controlling the counter electrode voltage VCOM to be applied to the pixel electrode. Here, the output buffer 130, the display timing generation circuit 136, and the level shifter 138 can realize the function as the source line driver described above.

  Further, when the parity error processing circuit 132 detects that the number of normal receptions of the reception signal of the reception I / F circuit 54 continues Rc times during the OFF display period, the source driver 30 detects the inverting switch control signal. The output switches SWO1 to SWON can be set to the conductive state by XCP, and the switch circuits SW1 to SWN of the liquid crystal display panel 20 can be set to the nonconductive state by the switch control signal CP.

  Therefore, when the parity error processing circuit 132 detects that the number of normal receptions of the reception signal of the reception I / F circuit 54 is Rc times, the source driver 30 sets the source lines SL1 to SLN based on the display data. Can be driven. That is, when it is detected by the parity error processing circuit 132 that the number of normal receptions of the reception signal of the reception I / F circuit 54 has continued Rc times, the liquid crystal display panel 20 is changed based on the display data from the off display period. It is possible to shift to a normal display period in which driving control is performed.

  Next, the parity error processing circuit 132 and the control register unit 134 will be described.

  FIG. 10 shows a configuration example of the control register unit 134 of FIG.

  The control register unit 134 includes an error count setting register 140 and a return count setting register 142.

  In the error count setting register 140, the parity error processing circuit 132 sets a set value corresponding to Er that is a threshold of the number of times of error detection of the received signal by the host 38. The setting value of the error count setting register 140 is output as the setting signal ErrREG.

  In the return count setting register 142, the parity error processing circuit 132 sets a set value corresponding to Rc, which is a threshold value of the normal reception count of the received signal, by the host 38. The set value of the return count setting register 142 is output as the setting signal RecREG.

  The setting signals ErrREG and RecREG are supplied to the parity error processing circuit 132 in FIG.

  FIG. 11 shows a circuit diagram of a configuration example of the parity error processing circuit 132.

  The parity error processing circuit 132 includes a first counter CNT1 for counting the number of times of error detection of the received signal, a second counter CNT2 for counting the number of times of normal reception of the received signal, and first and second comparators. CMP1, CMP2, first and second differentiating circuits DF1, DF2, and a set-reset flip-flop SRFF are included.

  The parity error processing circuit 132 receives the error detection signal CPO, the pixel clock signal PCLK, the initialization signal XRESET, and the setting signals ErrREG and RecREG. The initialization signal XRESET is a signal for initializing at least the parity error processing circuit 132 in the source driver 30, and is a signal that becomes active when it is at the L level.

  The reset terminal R of the first counter CNT1 receives a logical operation result signal of the error detection signal CPO and the initialization signal XRESET. A signal of a logical product operation result of the error detection signal CPO and the pixel clock signal PCLK is input to the clock terminal C of the first counter CNT1. Therefore, the first counter CNT1 is initialized when the error detection signal CPO or the initialization signal XRESET is at L level, and the count value becomes zero. The first counter CNT1 increments the count value in synchronization with the pixel clock signal PCLK when the error detection signal CPO is at the H level.

  The first comparator CMP1 compares the count value of the first counter CNT1 with the setting signal ErrREG, and outputs a pulse that becomes H level when they match. The first differentiating circuit DF1 detects the rising edge of the output signal of the first comparator CMP1, and outputs a pulse when the rising edge is detected. The output pulse of the first differentiation circuit DF1 is input to the set terminal S of the set / reset flip-flop SRFF.

  To the reset terminal R of the second counter CNT2, an inverted signal of the error detection signal CPO and a signal of a logical product operation result of the initialization signal XRESET are input. To the clock terminal C of the second counter CNT2, an inverted signal of the error detection signal CPO and a signal of a logical product operation result of the pixel clock signal PCLK are input. Accordingly, the second counter CNT2 is initialized when the inverted signal of the error detection signal CPO or the initialization signal XRESET is at L level, and the count value becomes zero. The second counter CNT2 increments the count value in synchronization with the pixel clock signal PCLK when the error detection signal CPO is at the L level.

  The second comparator CMP2 compares the count value of the second counter CNT2 with the setting signal RecREG, and outputs a pulse that becomes H level when they match. The second differentiating circuit DF2 detects the rising edge of the output signal of the second comparator CMP2, and outputs a pulse when the rising edge is detected. The output pulse of the second differentiation circuit DF2 is input to the reset terminal R of the set / reset flip-flop SRFF.

  The pixel clock signal PCLK is input to the clock terminal C of the set / reset flip-flop SRFF. The set-reset flip-flop SRFF changes the output signal from the output terminal Q to the H level when the set terminal S is at the H level in synchronization with the rise of the pixel clock signal PCLK, for example, and the reset terminal R is at the H level. At this time, the output signal is changed to L level.

  The output signal from the output terminal Q of the set / reset flip-flop SRFF becomes the error processing result signal flgCPErr. The error processing result signal flgCPErr is input to the display timing generation circuit 136.

  In this way, when the received signal is a serial signal, the parity error processing circuit 132 counts the presence / absence of a parity error for each pixel to obtain the number of times of detection of the received signal error or the number of times of normal reception of the received signal.

  FIG. 12 shows a timing chart of an operation example when an error is detected by the source driver 30 in the present embodiment.

  In FIG. 12, it is assumed that 10 is set in the error count setting register 140 of FIG. Therefore, the setting signal ErrREG is a signal corresponding to “10”.

  For example, it is assumed that the error detection signal CPO from the reception I / F circuit 54 of the display driver 40 changes from L level to H level at time TG1 within one vertical scanning period. That is, it is assumed that the reception I / F circuit 54 detects an error in the reception signal at time TG1. Therefore, at time TG1, the normal display period is switched to the previous data display period. The previous data display period is a period provided before switching from the normal display period to the off display period. The previous data indicates the last normal data before the error detection signal CPO changes to the H level.

  After time TG1, the count value of the first counter CNT1 is incremented in synchronization with the pixel clock signal PCLK. When the count value of the first counter CNT1 coincides with “10” indicated by the setting signal ErrREG, the first comparator CMP1 outputs a pulse that becomes H level. Receiving this, the first differentiating circuit DF1 detects the rising edge of the output signal of the first comparator CMP1, and outputs an output pulse to the set terminal S of the set / reset flip-flop. As a result, at time TG2, the error processing result signal flgCPErr changes to the H level.

  The display timing generation circuit 136 takes in the error processing result signal flgCPErr in synchronization with the horizontal synchronization signal HS and changes the switch control signal CP from L level to H level (time TG3). Accordingly, the output switches SWO1 to SWON are set to a non-conductive state, and the switch circuits SW1 to SWN are set to a conductive state. Thereby, the off display period is started. Thus, the off display is performed in synchronization with the start timing of one horizontal scanning period.

  FIG. 13 is an explanatory diagram of error handling measures in the present embodiment.

  FIG. 13 schematically shows a screen for one vertical scanning period. When one vertical scanning period is started, horizontal scanning is started, and the normal display period is started until time TG1 when the error detection signal CPO becomes H level (ND).

  Then, after the error detection signal CPO becomes H level, when it is detected that the error detection signal CPO is H level continuously 10 times in synchronization with the rising edge of the pixel clock signal PCLK, the error processing result signal flgCPErr is Change to H level. Then, the switch control signal CP changes to H level at the beginning of the horizontal scanning period next to the horizontal scanning period in which the error processing result signal flgCPErr has changed to H level. Therefore, the period from time TG1 to time TG3 is the previous data display period (BD). After time TG3, the display period is off (OD) as described above.

  As described above, paying attention to the screen in the vertical scanning period, the on display area is from the start timing of the vertical scanning period to the end timing of the previous data display period, and the off display area is in the off display period.

  As described above, according to the present embodiment, even if an error in a received signal is detected by chance, a stable image display can be realized without immediately controlling off-display in order to avoid an effect on image quality. To be able to.

  Further, in the present embodiment, the influence on the image quality can be suppressed as much as possible by returning from the off display period as described below.

  FIG. 14 shows a timing chart of an operation example at the time of error recovery of the source driver 30 in the present embodiment.

  In FIG. 14, it is assumed that 10 is set in the return number setting register 142 of FIG. Therefore, the setting signal RecREG is a signal corresponding to “10”.

  For example, at the start timing of the vertical scanning period, the error detection signal CPO is already at the H level (the switch control signal CP is also at the H level), and at time TG10 in the vertical scanning period, the error detection signal CPO is changed from the H level to the L level. It is assumed that In other words, at time TG10, it is assumed that the reception I / F circuit 50 that previously detected an error in the received signal has detected normal reception of the received signal.

  After time TG10, the count value of the second counter CNT2 is incremented in synchronization with the pixel clock signal PCLK. When the count value of the second counter CNT2 coincides with “10” indicated by the setting signal RecREG, the second comparator CMP2 outputs a pulse that becomes H level. Receiving this, the second differentiating circuit DF2 detects the rising edge of the output signal of the second comparator CMP2, and outputs an output pulse to the reset terminal R of the set / reset flip-flop. As a result, at time TG11, the error processing result signal flgCPErr changes from H level to L level.

  The display timing generation circuit 136 takes in the error processing result signal flgCPErr in synchronization with the vertical synchronization signal VS instead of the horizontal synchronization signal HS, and changes the switch control signal CP from H level to L level (time TG12). As a result, the output switches SWO1 to SWON are set to the conductive state, and the switch circuits SW1 to SWN are set to the nonconductive state, and the off display period ends. Thus, the switching timing from the off display period to the on display period (normal display period) in which the drive control of the liquid crystal display panel 20 based on the display data is performed can be the start timing of one vertical scanning period.

  As described above, according to the present embodiment, even if the normal reception of the received signal is detected by chance, the on display is performed after the stable normal reception is confirmed without immediately controlling the on display. As a result, image quality degradation can be minimized.

4). In this embodiment, the liquid crystal display panel 20 is provided with switch circuits SW1 to SWN, and the counter electrode voltage VCOM supplied to the counter electrode is supplied to the source lines SL1 to SLN during the off display period, so-called off. Although the display has been realized, the present invention is not limited to this. In the modification of this embodiment, the source driver supplies the common electrode voltage VCOM to the source lines SL1 to SLN, so that the liquid crystal display panel 20 can adopt a configuration in which the switch circuits SW1 to SWN are omitted.

  FIG. 15 shows a block diagram of a configuration example of a liquid crystal display device 200 according to a modification of the present embodiment. In FIG. 15, the same parts as those in FIG.

  The liquid crystal display panel 210 of the liquid crystal display device 200 of FIG. 15 differs from the liquid crystal display panel 20 of FIG. 1 in that the liquid crystal display panel 210 has a configuration in which the switch circuits SW1 to SWN of the liquid crystal display panel 20 are omitted. It is a point.

  The display driver 220 of FIG. 15 differs from the display driver 40 of FIG. 1 in that the display driver 220 is provided with a source driver 230 instead of the source driver 30 of the display driver 40.

  FIG. 16 shows a block diagram of another configuration example of the liquid crystal display device 200 of FIG. In FIG. 16, the same parts as those in FIG. 2 or FIG.

  FIG. 17 is a block diagram showing a configuration example of the source driver 230 shown in FIG. In FIG. 17, the same parts as those in FIG.

  A source driver 230 in FIG. 17 is different from the source driver 30 in FIG. 9 in that a display timing generation circuit 232 is provided instead of the display timing generation circuit 136. The second point is that a level shifter 234 is provided instead of the level shifter 138. The third point is that output switches SWP1 to SWPN are provided instead of the output switches SWO1 to SWON. A fourth point is that the counter electrode voltage VCOM is supplied to the source driver 230 in FIG.

  The display timing generation circuit 232 generates a control signal for controlling the drive timing of the source line based on the vertical synchronization signal VS, the horizontal synchronization signal HS, the pixel clock signal PCLK, and the error processing result signal flgCPErr. The level shifter 234 converts the voltage level of each bit of the control signal generated by the display timing generation circuit 232. For example, the level shifter 234 outputs a clock signal VCK, a start pulse signal VSP, an output enable signal VENB, and an inverting switch control signal XCP for controlling the display timing of the gate driver 32.

  Based on the inverting switch control signal XCP, the output switches SWP1 to SWPN switch between the state of supplying the output voltage of the operational amplifier of the output buffer 130 or the state of supplying the counter electrode voltage VCOM to the source lines SL1 to SLN.

  Accordingly, as in the present embodiment, the display timing generation circuit 232 captures the error processing result signal flgCPErr in synchronization with the horizontal synchronization signal HS when an error is detected in the reception signal, and when the reception signal is normally received, The error processing result signal flgCPErr is captured in synchronization with the vertical synchronization signal VS. Thereby, when the transition is made from the normal display period to the off display period, the transition can be made in the same manner as in FIG. 12, and when the transition from the off display period to the normal display period is made, the transition can be made as in FIG.

  The common electrode voltage VCOM supplied to the source driver 230 (display driver 220) is generated by the power supply circuit 100.

  FIG. 18 shows a block diagram of a configuration example of the power supply circuit 100 shown in FIG. 1, FIG. 2, FIG. 15, or FIG.

  The power supply circuit 100 includes a source voltage generation circuit 310, a gate voltage generation circuit 320, and a counter electrode voltage generation circuit 330. The source voltage generation circuit 310 generates the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH that are supplied to the reference voltage generation circuit 126 of FIG. 9 or FIG. The gate voltage generation circuit 320 generates the high potential side voltage VHH and the low potential side voltage VLL of the selection pulse output from the gate driver 32 to each gate line. The common electrode voltage generation circuit 330 generates a high potential side voltage VCOMH and a low potential side voltage VCOML of the common electrode voltage VCOM.

  Each of the source voltage generation circuit 310, the gate voltage generation circuit 320, and the counter electrode voltage generation circuit 330 is supplied with a system power supply voltage VDD and a system ground power supply voltage VSS, and adjusts the output potential with a boost circuit such as a charge pump circuit. The above-described voltages can be generated using a regulator.

  FIG. 19 shows an operation explanatory diagram of the source voltage generation circuit 310 of FIG.

  The source voltage generation circuit 310 generates a boosted voltage VOUT1 obtained by boosting the voltage between the system ground power supply voltage VSS and the system power supply voltage VDD twice in the positive direction on the basis of the system ground power supply voltage VSS. Then, the source voltage generation circuit 310 outputs the high potential side power supply voltage VDDH in which the potential of the boost voltage VOUT1 is adjusted by a regulator. The system ground power supply voltage VSS supplied to the source voltage generation circuit 310 is output as the low potential side power supply voltage VSSH.

  FIG. 20 is an operation explanatory diagram of the gate voltage generation circuit 320 and the counter electrode voltage generation circuit 330 of FIG.

  In the gate voltage generation circuit 320 or the counter electrode voltage generation circuit 330, a boosted voltage VDC obtained by adjusting the potential of the system power supply voltage VDD by a regulator is generated. The gate voltage generation circuit 320 or the counter electrode voltage generation circuit 330 boosts the voltage between the system ground power supply voltage VSS and the boosted voltage VDC twice in the positive direction based on the system ground power supply voltage VSS. VOUT2 is generated.

  The common electrode voltage generation circuit 330 generates a boosted voltage VOUTM obtained by boosting the voltage between the system ground power supply voltage VSS and the system power supply voltage VDD by a factor of 1 in the negative direction with reference to the system ground power supply voltage VSS. The counter electrode voltage generation circuit 330 generates a low potential side voltage VCOML in which the potential of the boosted voltage VOUTM is adjusted by a regulator. The counter electrode voltage generation circuit 330 generates a high potential side voltage VCOMH in which the potential of the boosted voltage VOUT2 is adjusted by a regulator.

  The gate voltage generation circuit 320 generates adjustment voltages VGON and VGOF in which the potential of the boost voltage VOUT2 is adjusted by a regulator. Thereafter, the gate voltage generation circuit 320 generates the high potential side voltage VHH obtained by boosting the voltage between the system ground power supply voltage VSS and the adjustment voltage VGON twice in the positive direction on the basis of the system ground power supply voltage VSS. Furthermore, the gate voltage generation circuit 320 generates a low-potential-side voltage VLL obtained by boosting the voltage between the system ground power supply voltage VSS and the adjustment voltage VGOF by a factor of 1 in the negative direction based on the system ground power supply voltage VSS.

  Among the voltages generated as described above, the counter electrode voltage VCOM is supplied to the counter electrode of the liquid crystal display panel 20 in the case of the present embodiment, and the counter electrode voltage VCOM is set in the case of the modification of the present embodiment. The counter electrode of the liquid crystal display panel 210 and the source driver 230 of the display driver 220 are supplied.

5). Electronic Device FIG. 21 is a block diagram showing a configuration example of an electronic device according to this embodiment. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device. In FIG. 21, the same parts as those in FIG. 1, FIG. 2, FIG. 15 or FIG.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera and supplies image data captured by the CCD camera to the host 38 in the YUV format.

  The mobile phone 900 includes the liquid crystal display panel 20 or the liquid crystal display panel 210. The liquid crystal display panel 20 or the liquid crystal display panel 210 is driven by the display driver 40 including the source driver 30 and the gate driver 32 or the display driver 220 including the source driver 230 and the gate driver 32. The liquid crystal display panel 20 or the liquid crystal display panel 210 includes a plurality of source lines, a plurality of gate lines, and a plurality of pixels. The source driver 30 or the source driver 230 performs drive control of the source line based on the display data.

  The host 38 is connected to the display driver 40 or the display driver 220 and supplies RGB format display data to the source driver 30 or the source driver 230.

  The power supply circuit 100 is connected to the display driver 40 or the display driver 220 and supplies a driving power supply voltage to each driver. The counter electrode voltage VCOM is supplied to the counter electrode of the liquid crystal display panel 20 or the liquid crystal display panel 210.

  Further, the host 38 can demodulate the display data received via the antenna 960 by the modem 950 and then supply the display data to the display driver 40 or the display driver 220. Based on the display data, the host 38 causes the display driver 40 or the display driver 220 to display on the liquid crystal display panel 20 or the liquid crystal display panel 210.

  The host 38 can instruct transmission to another communication device via the antenna 960 after modulating the display data generated by the camera module 910 by the modem 950.

  Based on the operation information from the operation input unit 970, the host 38 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the liquid crystal display panel 20 or the liquid crystal display panel 210.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the display driver according to the present embodiment multiplexes a plurality of types of drive voltages corresponding to display data for a plurality of dots on one output line, and distributes the drive voltages for each dot on the electro-optical device side to It can be applied to a driving circuit to be driven.

  Further, the host 38 may be notified of the error processing result signal flgCPErr from the parity error processing circuit 132. Further, based on the error processing result signal flgCPErr, at least the operation of the source driver among the display drivers may be stopped or initialized.

  Alternatively, when the number of error detections is detected 10 times continuously, the display is turned off, and when the number of continuous times serving as a threshold is large, for example, 30 times is detected continuously, the operation of the source driver (display driver) is stopped. The power may be turned off. Also, when performing off display, the number of error detections is counted in units of pixels, and when turning off the power, the number of error detections is counted in units of one vertical scanning period, depending on the type of error processing. Thus, the period for counting the number of error detections may be varied.

  In addition, for example, the present invention is not limited to the application to driving the above-described liquid crystal display panel, but can be applied to driving electroluminescence and plasma display devices.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

1 is a diagram illustrating an outline of a configuration of a liquid crystal display device according to an embodiment. The figure which shows the outline | summary of the other structure of the liquid crystal display device in this embodiment. The block diagram of the structural example between the host and display driver in this embodiment. The figure which shows the example of the transmission signal which the host in this embodiment outputs. The figure which shows the example of the differential signal transmitted via a serial bus. FIG. 4 is a block diagram of a configuration example of a reception I / F circuit in FIG. 3. FIG. 3 is a diagram showing an outline of a configuration of a display driver in the present embodiment. FIG. 8 is a diagram illustrating a configuration example of the gate driver in FIG. 7. FIG. 8 is a block diagram of a configuration example of the source driver in FIG. 7. The figure which shows the structural example of the control register part of FIG. The circuit diagram of the example of a structure of a parity error processing circuit. The timing diagram of the example of an operation | movement at the time of the error detection of the source driver in this embodiment. Explanatory drawing of the error processing countermeasure in this embodiment. The timing diagram of the example of operation at the time of error recovery of the source driver in this embodiment. The block diagram of the structural example of the liquid crystal display device in the modification of this embodiment. FIG. 16 is a block diagram of another configuration example of the liquid crystal display device of FIG. 15. FIG. 17 is a block diagram of a configuration example of the source driver in FIG. 15 or FIG. 16. FIG. 17 is a block diagram of a configuration example of the power supply circuit of FIG. 1, FIG. 2, FIG. 15 or FIG. FIG. 19 is an operation explanatory diagram of the source voltage generation circuit of FIG. 18. FIG. 19 is an operation explanatory diagram of the gate voltage generation circuit and the counter electrode voltage generation circuit of FIG. 18. 1 is a block diagram of a configuration example of an electronic device according to an embodiment.

Explanation of symbols

10, 200 liquid crystal display device, 20, 210 liquid crystal display panel,
30, 230 source drivers, 32 gate drivers, 38 hosts,
40, 220 display driver, 78 pixel formation region, 100 power supply circuit,
120 data latch, 122 line latch, 124 level shifter,
126 reference voltage generation circuit, 128 DAC, 130 output buffer,
132 parity error processing circuit, 134 control register unit,
136 display timing generation circuit, 138 level shifter,
flgCPErr error processing result signal, CP switch control signal,
CPO error detection signal, DBUS display data, GL1 to GLM gate line,
HS horizontal sync signal, PCLK pixel clock signal, POL polarity inversion signal,
SL1 to SLN source lines, SW1 to SWN switch circuits,
SWO1-SWON, SWP1-SWPN output switch,
VCOM counter electrode voltage, VS vertical sync signal, VSP start pulse signal,
VCK clock signal, VENB output enable signal,
XCP reverse switch control signal

Claims (16)

A driving circuit for driving the electro-optical device based on display data generated from a reception signal obtained through an interface circuit for detecting an error in the reception signal;
An error processing unit that counts the number of times the error has been detected and detects whether the number of times the detection has continued a given number of times;
A source line driving unit for driving a source line of the electro-optical device based on the display data,
The source line driver is
Drive control of the electro-optical device is performed so that the display is turned off regardless of the display data on the condition that the error processing unit detects that the number of detections continues for a given number of times. Drive circuit. In claim 1,
The error processing unit
Count the number of normal reception of the received signal, detect whether the number of normal reception is a given number of times,
The source line driver is
Drive control of the electro-optical device is performed based on display data on the condition that the error processing unit detects that the normal reception count continues for a given number of times during the off-display period. Drive circuit. In claim 2,
The drive circuit characterized in that the switching timing from the off display period to the on display period for controlling the driving of the electro-optical device based on the display data is the start timing of one vertical scanning period. In any one of Claims 1 thru | or 3,
The off display is
A driving circuit which is performed in synchronization with a start timing of one horizontal scanning period. A driving circuit for driving the electro-optical device based on display data generated from a reception signal obtained through an interface circuit for detecting an error in the reception signal;
An error processing unit that counts the number of times of normal reception of the received signal and detects whether the number of times of normal reception continues for a given number of times;
A source line driving unit for driving a source line of the electro-optical device based on the display data,
Drive control of the electro-optical device is performed based on display data on the condition that the error processing unit detects that the normal reception count continues for a given number of times during the off display period. Drive circuit. In claim 5,
The drive circuit characterized in that the switching timing from the off display period to the on display period for controlling the driving of the electro-optical device based on the display data is the start timing of one vertical scanning period. In any one of Claims 1 thru | or 6.
The received signal is a serial signal;
The error processing unit
A drive circuit characterized in that the number of detections or the number of normal receptions is obtained by counting the presence or absence of errors for each pixel. In any one of Claims 1 thru | or 7,
The source line driver is
Each output buffer includes a plurality of output buffers for driving each source line of the plurality of source lines of the electro-optical device;
A drive circuit, wherein an output of each output buffer connected to each source line to which a given off signal is supplied during the off display period is controlled to be in a high impedance state. In any one of Claims 1 thru | or 7,
The source line driver is
A driving circuit that supplies a given off signal to a plurality of source lines of the electro-optical device during the off-display period. In any one of Claims 1 thru | or 9,
In the case where the electro-optical device includes a plurality of pixel electrodes that are specified by the gate lines of the plurality of gate lines and the source lines of the plurality of source lines,
A drive circuit that performs the off display by controlling so that a voltage of a counter electrode facing each pixel electrode is applied to the pixel electrode. A driving method for driving an electro-optical device based on display data,
Count the number of detection errors of the received signal for generating the display data,
Detect if the number of detections is a given number of times,
In a period in which it is not detected that the number of detections is a given number of times, the electro-optical device is driven based on display data obtained from the reception signal,
A driving method comprising: controlling driving of the electro-optical device so that the display is turned off regardless of the display data on the condition that the number of times of detection is detected to be a given number of times. In claim 11,
Count the number of normal reception of the received signal,
Detecting whether the number of normal receptions is a given number of times,
A drive method characterized in that drive control of the electro-optical device is performed based on display data on condition that the normal reception count is detected to be a given number of times during the off-display period. A driving method for driving an electro-optical device based on display data,
Count the number of normal reception of the reception signal for generating the display data,
Detecting whether the number of normal receptions is a given number of times,
In the period in which the normal reception count is not detected to be a given number of times during the off display period, the off display is continued regardless of the display data,
A drive method characterized in that drive control of the electro-optical device is performed based on display data on condition that the normal reception count is detected to be a given number of times during the off-display period. Multiple gate lines,
Multiple source lines,
A plurality of pixels each pixel is specified by each gate line of the plurality of gate lines and each source line of the plurality of source lines;
11. An electro-optical device comprising: a drive circuit according to claim 1, which drives at least the plurality of source lines among the plurality of gate lines and the plurality of source lines.   An electronic apparatus comprising the electro-optical device according to claim 14. With the host,
A transmission side interface circuit connected to the host;
A receiving side interface circuit for receiving a serial signal from the transmitting side interface circuit;
The drive circuit according to any one of claims 1 to 10, wherein display data obtained from a reception signal of the reception-side interface circuit is supplied;
An electronic apparatus comprising: an electro-optical device driven by the drive circuit based on the display data.

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