JP2008152024A - Display driver, electro-optical device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display driver, a bridge circuit, an electro-optical device and electronic equipment capable of suppressing degradation in image quality to the minimum even when abnormality occurs in the display data itself. <P>SOLUTION: The display driver to drive an active matrix type electro-optical device includes an interface circuit to receive transmission data, an error detection circuit to perform an error detection process on the data received by the interface circuit, a display memory to store the image data received by the interface circuit, and a source line driving circuit to drive source lines of the electro-optical device based on the image data read from the display memory. The driver controls a gate line driving circuit to scan a plurality of gate lines of the electro-optical device while avoiding selecting a scan line including dots that display the image data where an error is detected, in the succeeding vertical scanning period to a vertical scanning period where the error is detected by the error detection circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display driver, an electro-optical device, and an electronic apparatus.

  In recent years, a display panel represented by a liquid crystal panel (an electro-optical device in a broad sense) has been increased in definition and screen size, and the data size of display data for one screen has been rapidly increased. Furthermore, in spite of the tendency for the number of bits of display data per pixel to increase, the number of signal lines is increased in mounting the display panel due to the demand for downsizing of electronic devices on which the display panel is mounted. It has become a big issue.

  Therefore, when display data is supplied to a display driver that drives the display panel, the display data is converted into a low amplitude signal and transmitted at high speed. Thereby, it is possible to cope with an increase in the data size of the display data and an increase in the number of signal lines.

However, even when display data or a display control signal is converted to a low amplitude signal and transmitted at high speed, an abnormal image may be displayed under the influence of noise or the like. Therefore, in Patent Document 1, even when a noise is mixed during transmission of a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal from the outside, an abnormality occurs internally, a horizontal synchronization signal, a vertical synchronization signal, and data A liquid crystal display device that generates an enable signal is disclosed. Thereby, in patent document 1, the display of an abnormal image is prevented.
JP 2003-167545 A

  However, in Patent Document 1, there is a problem that even if an abnormality occurs in the display data itself, an image is displayed as it is using the display data in which the abnormality has occurred. Some display drivers for driving liquid crystal display devices have a built-in display memory, and display data is temporarily stored in the display memory. The display driver repeatedly reads display data from the display memory and drives the liquid crystal display device. By doing so, it is possible to reduce power consumption associated with supplying display data from the outside.

  Even when the display memory is incorporated in this way, it is desirable to be able to prevent image quality deterioration due to display data in which an abnormality has occurred. This responds to market demands for image quality improvement with the recent increase in the number of pixels.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to minimize deterioration in image quality even when an abnormality occurs in the display data itself. It is an object of the present invention to provide a display driver, an electro-optical device, and an electronic apparatus that can perform the above.

In order to solve the above problems, the present invention
A display driver for driving an active matrix type electro-optical device,
An interface circuit for receiving image data;
An error detection circuit for performing error detection processing of image data received by the interface circuit;
A display memory for storing image data received by the interface circuit;
A source line driving circuit for driving a source line of the electro-optical device based on image data read from the display memory;
In the vertical scanning period next to the vertical scanning period in which the error is detected by the error detection circuit, the plurality of electro-optical devices of the electro-optical device can be selected without selecting a scanning line including a dot on which the image data in which the error is detected is displayed. The present invention relates to a display driver that controls a gate line driving circuit that scans the plurality of gate lines so as to scan the gate lines.

  In general, there is little difference between images in two consecutive vertical scanning periods (frames). If white display or black display is intentionally performed on a scanning line including pixels on which image data in which an error has been detected is displayed, the difference is concerned. Scan lines may be noticeable. On the other hand, according to the present invention, control is performed so that a plurality of gate lines are scanned without selecting a scan line including a dot on which error-detected image data is displayed. The same pixel display as before is performed. Therefore, in the next vertical scanning period, the image data can be read again from the display memory and immediately updated to the next image. Therefore, even if an error is detected in the image data itself, the influence on the image quality can be minimized. In particular, when an error is detected on a plurality of scanning lines for one screen, it is possible to greatly reduce the influence on image quality degradation as compared with the case where white display or black display is performed on each scanning line. It becomes like this.

The present invention also provides
A display driver for driving an active matrix type electro-optical device,
An interface circuit for receiving image data;
An error detection circuit for performing error detection processing of image data received by the interface circuit;
A display memory for storing image data received by the interface circuit;
A source line driving circuit for driving a source line of the electro-optical device based on image data read from the display memory;
Without writing the image data in which an error is detected by the error detection circuit to the display memory, the source based on the image data read from the display memory in the vertical scanning period next to the vertical scanning period in which the error is detected Related to display drivers that drive lines.

  According to the present invention, the image data in the vertical scanning period is replaced with the image data in the immediately preceding vertical scanning period by controlling not to write only the image data in which an error is detected to the display memory. Since only the dot corresponding to the image data in which the error is detected is displayed using the image data of the previous vertical scanning period, the image quality can be further prevented from being deteriorated as compared with the case where the scanning line is not selected. become.

In the display driver according to the present invention,
A gate line driving circuit for selecting a plurality of gate lines of the electro-optical device may be included.

In the display driver according to the present invention,
A retransmission request processing unit that makes a retransmission request of image data based on an error detection processing result of the error detection circuit to a transmission source of the image data received by the interface circuit;
When an error is detected by the error detection circuit,
The retransmission request processing unit makes a retransmission request for image data in the vertical scanning period to the transmission source, and the gate line driving circuit completes scanning in the vertical scanning period, and image data corresponding to the retransmission request Scanning in the next vertical scanning period can be started on the condition that the retransmission is started.

In the display driver according to the present invention,
A retransmission request processing unit that makes a retransmission request of image data based on an error detection processing result of the error detection circuit to a transmission source of the image data received by the interface circuit;
When an error is detected by the error detection circuit,
The retransmission request processing unit makes a retransmission request for the image data of the vertical scanning period to the transmission source, and the gate line driving circuit responds to the retransmission request without completing the scanning of the vertical scanning period. Scanning in the next vertical scanning period can be started on condition that retransmission of image data is started.

  According to any one of the above inventions, since the image data is already stored in the display memory, the display image can be periodically updated. Therefore, it is possible to prevent image quality degradation by requesting retransmission of image data in which an error is detected and performing display using only normal display data.

The present invention also provides
A display driver for driving an active matrix type electro-optical device,
An interface circuit for receiving image data;
An error detection circuit for performing error detection processing of image data received by the interface circuit;
A source line driving circuit for driving a source line of the electro-optical device based on image data received by the interface circuit;
A gate line driving circuit for scanning a plurality of gate lines of the electro-optical device;
A retransmission request processing unit that makes a retransmission request of image data based on an error detection processing result of the error detection circuit to a transmission source of the image data received by the interface circuit,
When an error is detected by the error detection circuit,
The retransmission request processing unit makes a retransmission request of the image data of the frame to the transmission source, and the gate line driving circuit completes scanning of the frame and starts retransmission of the image data corresponding to the retransmission request. This relates to the display driver that starts scanning the next frame on the condition.

The present invention also provides
A display driver for driving an active matrix type electro-optical device,
An interface circuit for receiving image data;
An error detection circuit for performing error detection processing of image data received by the interface circuit;
A source line driving circuit for driving a source line of the electro-optical device based on image data received by the interface circuit;
A gate line driving circuit for scanning a plurality of gate lines of the electro-optical device;
A retransmission request processing unit that makes a retransmission request of image data based on an error detection processing result of the error detection circuit to a transmission source of the image data received by the interface circuit,
When an error is detected by the error detection circuit,
The retransmission request processing unit makes a retransmission request for the image data of the vertical scanning period to the transmission source, and the gate line driving circuit responds to the retransmission request without completing the scanning of the vertical scanning period. The present invention relates to a display driver that starts scanning in the next vertical scanning period on condition that retransmission of image data is started.

The present invention also provides
Multiple gate lines,
Multiple source lines,
A plurality of pixels in which each pixel is specified by each gate line and each source line;
A gate driver that scans the plurality of gate lines;
The present invention relates to an electro-optical device including the display driver described above that drives the plurality of source lines based on data received by the interface circuit.

The present invention also provides
The present invention relates to an electro-optical device including any one of the display drivers described above.

  According to any one of the above-described inventions, it is possible to provide an electro-optical device capable of minimizing deterioration in image quality even when abnormality occurs in the image data itself.

The present invention also provides
With the host,
The present invention relates to an electronic device including any one of the display drivers described above that receives data from the host.

The present invention also provides
The present invention relates to an electronic apparatus including the electro-optical device described above.

  According to any one of the above-described inventions, it is possible to provide an electronic apparatus capable of minimizing degradation of image quality even when an abnormality occurs in the image data itself.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Liquid Crystal Display Device FIG. 1 shows an outline of the configuration of an active matrix liquid crystal display device according to this embodiment. 1 illustrates a liquid crystal display device in which an active matrix type liquid crystal display panel is employed as an electro-optical device, but embodiments described below are not limited to the liquid crystal display panel.

  The liquid crystal display device 10 includes a liquid crystal display panel (display panel in a broad sense, electro-optical device in a broader sense) 20. The liquid crystal display panel 20 is formed on a glass substrate, for example. On this glass substrate, a plurality of gate lines (scanning lines) GL1 to GLM (M is an integer of 2 or more) arranged in the Y direction and extending in the X direction, and a source line arranged in the X direction and extending in the Y direction, respectively. (Data lines) SL1 to SLN (N is an integer of 2 or more) are arranged. The pixel region corresponds to the intersection position of the gate line GLm (1 ≦ m ≦ M, m is an integer, the same applies hereinafter) and the source line SLn (1 ≦ n ≦ N, n is an integer, the same applies hereinafter). (Pixel) is provided, and a thin film transistor (hereinafter abbreviated as TFT) 22 mn is disposed in the pixel region.

  The gate of the TFT 22mn is connected to the gate line GLn. The source of the TFT 22mn is connected to the source line SLn. The drain of the TFT 22mn is connected to the pixel electrode 26mn. Liquid crystal (electro-optical material in a broad sense) is sealed between the pixel electrode 26 mn and a counter electrode 28 mn facing the pixel electrode 26 mn, thereby forming a liquid crystal capacitor (liquid crystal element in a broad sense) 24 mn. The transmittance of the pixel changes according to the applied voltage between the pixel electrode 26mn and the counter electrode 28mn. The counter electrode voltage VCOM is supplied to the counter electrode 28mn.

  Such a liquid crystal display panel 20 includes, for example, a first substrate on which a pixel electrode and a TFT are formed and a second substrate on which a counter electrode is formed, and a liquid crystal as an electro-optical material between the two substrates. It is formed by enclosing.

  The liquid crystal display device 10 includes a display driver 40. The display driver 40 drives the liquid crystal display panel 20. The display driver 40 includes a source driver (data driver) 30 and a gate driver (gate line driving circuit, scanning driver) 32. The source driver 30 drives the source lines SL1 to SLN of the liquid crystal display panel 20 based on display data (image data and gradation data). The gate driver 32 sequentially drives (scans) the gate lines GL1 to GLM of the liquid crystal display panel 20 within one vertical scanning period.

  Further, the liquid crystal display device 10 can include a power supply circuit 100. The power supply circuit 100 generates voltages necessary for driving the source lines and supplies them to the source driver 30. The power supply circuit 100 generates a voltage necessary for scanning the gate line and supplies it to the gate driver 32.

  Furthermore, the power supply circuit 100 includes a common electrode voltage generation circuit, and the common electrode voltage generation circuit generates the common electrode voltage VCOM. That is, the power supply circuit 100 generates the common electrode voltage VCOM that periodically repeats the high potential side voltage VCOMH and the low potential side voltage VCOML in accordance with the timing of the polarity inversion signal POL generated by the source driver 30. Output to the counter electrode.

  The liquid crystal display device 10 can include a host 38. The host 38 includes a central processing unit (hereinafter abbreviated as “CPU”) and a memory (not shown) and a CPU that reads and executes a program stored in the memory, and each part of the display driver 40 and a power supply circuit. Processing for controlling 100 is realized. For example, the host 38 performs operation mode setting, polarity inversion driving setting, polarity inversion timing setting, supply of internally generated vertical synchronization signal and horizontal synchronization signal, and the like to the source driver 30 and the gate driver 32.

  In FIG. 1, the liquid crystal display device 10 includes the power supply circuit 100 or the host 38, but at least one of them may be provided outside the liquid crystal display device 10. .

  The source driver 30 may incorporate at least one of the gate driver 32 and the power supply circuit 100.

  Furthermore, some or all of the display driver 40, the host 38, and the power supply circuit 100 may be formed on the liquid crystal display panel 20. For example, in FIG. 2, a display driver 40 is formed on the liquid crystal display panel 20. As described above, the liquid crystal display panel 20 includes a plurality of gate lines, a plurality of source lines, a pixel (pixel electrode) specified by one of the plurality of gate lines and one of the plurality of source lines, and a plurality of gate lines. And a source driver for driving a plurality of source lines. A plurality of pixels are formed in the pixel formation region 78 of the liquid crystal display panel 20.

  FIG. 3 shows a configuration example of the liquid crystal display device shown in FIG.

  In FIG. 3, a pixel formation region 92 in which a gate line and a source line are provided and a pixel is formed is provided on the panel substrate 90. The display driver 40 is mounted on the edge of the panel substrate 90. A flexible substrate 94 is connected to the panel substrate 90, and an EEPROM (Electronically Erasable and Programmable Read Only Memory) 96 that stores setting information of the display driver 40 is mounted on the flexible substrate 94. The flexible board 94 is provided with a serial bus 98 that functions as a data transfer bus. The display driver 40 and the EEPROM 96 are electrically connected via a given signal line. The display driver 40 and the host 38 exchange packet data via the serial bus 98.

2. Interface Circuit In this embodiment, the host 38 and the display driver 40 are connected via a serial bus. The serial bus is composed of two sets of differential signal lines, and a transfer signal between the host 38 and the display driver 40 is converted into two sets of differential signals and transmitted. More specifically, three or more types of transmission signals from the host 38 are converted into two sets of differential signals by a transmission interface (Interface: hereinafter referred to as I / F) circuit and transferred via a serial bus. Is done. Then, the signal is converted into a plurality of original transmission signals by the reception I / F circuit connected to the serial bus and supplied to the display driver 40.

  FIG. 4 shows a block diagram of a configuration example between the host 38 and the display driver 40 in the present embodiment.

  In FIG. 4, the host 38 is provided with a transmission I / F circuit 50 that outputs five types of transmission signals, receives the transmission signals, and converts them into two sets of differential signals. The transmission I / F circuit 50 converts the transmission signal from the host 38 into two sets of differential signals whose maximum amplitude value is lower than that of the transmission signal, and the converted differential signal is a serial bus (differential signal line). The control which outputs to 98 is performed. That is, parallel transmission signals from the host 38 are parallel / serial converted and transmitted as serial differential signals. In FIG. 4, the transmission I / F circuit 50 is provided outside the host 38, but may be provided inside the host 38.

  A reception I / F circuit 54 is connected to the other end of the serial bus 98 to which the transmission I / F circuit 50 is connected at one end. The reception I / F circuit 54 converts the reception signal received via the serial bus 98 into an original signal having a maximum amplitude value higher than the reception signal, and supplies the signal to the drive unit 60 of the display driver 40. The drive unit 60 includes the source driver 30 and the gate driver 32 shown in FIG. In FIG. 4, the reception I / F circuit 54 is provided inside the host 38, but may be provided outside the host 38.

  In this embodiment, the reception I / F circuit 54 detects an error in the received signal from the host 38 (more specifically, the transmission I / F circuit 50), and the detection result is used as an error detection flag FlgErr. 60 (more specifically, the source driver 30) is notified. The reception I / F circuit 54 can detect a parity error of the reception signal transmitted via the serial bus 98.

  FIG. 5 shows an example of a transmission signal output from the host 38.

  The host 38 outputs display control signals (VS, HS, DE, PCLK) (display timing signal) and display data DBUS. For example, when one pixel is composed of 3 dots, the display data DBUS includes, for example, 8-bit R component gradation data, 8-bit G component gradation data, and 8-bit B component gradation data. That is, the display data DBUS is 24-bit data. In this display data DBUS, 24-bit data for one pixel is sequentially transferred in synchronization with the pixel clock signal PCLK.

  Of the display control signals, the vertical synchronization signal VS is a signal that defines one vertical scanning period. For example, one vertical scanning period is defined by a falling edge of the vertical synchronization signal VS. The horizontal synchronization signal HS is a signal that defines one horizontal scanning period. For example, one horizontal scanning period is defined by the falling edge of the horizontal synchronization signal HS. The data enable signal DE is a signal indicating whether or not the display data DBUS is valid. The display data DBUS when the data enable signal DE is at the H level is valid, and the display data DBUS when the data enable signal DE is at the L level is invalid. The pixel clock signal PCLK is a synchronization signal for transferring the display data DBUS for each pixel.

  Thus, the host 38 outputs a 4-bit display control signal and 24-bit display data. The transmission I / F circuit 50 receives signals of a total of 28 bits from the host 38, converts them into two sets of differential signals, and transmits the differential signals to the display driver 40 via the serial bus 98.

  FIG. 6 shows an example of a differential signal transmitted via the serial bus 98.

  The serial bus 98 includes a first differential signal line for data transfer and a second differential signal line for clock transfer. A data signal D and an inverted data signal DX whose phases are inverted from each other are output to the two signal lines constituting the first differential signal line. A clock signal CLK and an inverted clock signal CLKX whose phases are inverted from each other are output to the two signal lines constituting the second differential signal line. The clock signal CLK and the inverted clock signal CLKX serve as transfer reference timings for serial transfer via the serial bus 98. The data signal D and the inverted data signal DX change in order to transfer the display control signals (VS, HS, DE, PCLK) serially.

  Then, during a period when the clock signal CLK is at L level (period when the inverted clock signal CLKX is at H level), a data signal D and an inverted data signal DX having a predetermined number of R bits (R is an integer of 2 or more) are transmitted. The Similarly, the data signal D of R bits and the inverted data signal DX are transmitted during a period when the clock signal CLK is at the H level (a period when the inverted clock signal CLKX is at the L level).

  As described above, the transmission I / F circuit 50 in FIG. 4 converts the display control signal and display data shown in FIG. 5 into the differential signal shown in FIG. On the other hand, the reception I / F circuit 54 shown in FIG. 4 converts the differential signal shown in FIG. 6 into the display control signal and display data shown in FIG. 5, and the parity error of the display control signal and display data. The presence / absence or the like is detected, and an error detection flag FlgErr is output. Then, the output signal of the reception I / F circuit 54 is supplied to the drive unit 60.

  7A and 7B are explanatory diagrams of packet data exchanged between the host 38 and the display driver 40. FIG.

  A packetized command or data shown in FIG. 7A or 7 B is exchanged between the host 38 and the display driver 40 via the serial bus 98. For example, the host 38 issues a command to the display driver 40 based on the packet data shown in FIG. Further, for example, the host 38 transmits display data to be displayed by the display driver 40 using the packet data shown in FIG.

  As shown in FIGS. 7A and 7B, the packet data has a packet header part PH, a data part DT, and a packet footer part PF. In the packet header part PH, in addition to the data identification code and data type, a packet length is set as necessary. Data for command issuance or data to be processed is set in the data portion DT. The command issuing data includes command data and parameter data, and the parameter data is specified based on the decoding result of the command data. Error detection data is set in the packet footer section PF. Here, the error detection data includes, for example, a parity code, CRC data, checksum data, ECC data, hash function data, and the like.

  As an example of the command, for the source driver 30 and the gate driver 32 of the display driver 40, operation mode setting, polarity inversion driving setting, polarity inversion timing setting, one screen size, vertical scanning period and horizontal scanning period There is something to set.

  Examples of data include display data such as still image data and moving image data, display control signals such as a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal.

  Such packet data has a short packet structure or a long packet structure.

  FIG. 8A shows an example of a short packet structure. FIG. 8B shows an example of a long packet structure.

  As shown in FIG. 8A, the packet data having the short packet structure has a packet header part PH, a data part DT, and a packet footer part PF. ECC (Error Correcting Code) data is set in the packet footer portion PF of the packet data having the short packet structure, and a 1-bit error of the packet data is corrected based on the ECC data, and a 2-bit error is detected.

  As shown in FIG. 8B, the packet data having a long packet structure has a packet header part PH, a data part DT, and a PF part. ECC data is set in the packet header PH of packet data having a long packet structure. Based on this ECC data, a 1-bit error in the packet header portion PH is corrected, and a 2-bit error is detected. Also, checksum data is set in the packet footer portion PF of packet data having a long packet structure. Based on this checksum data, an error of 1 bit or more in the data part DT is detected.

  8A and 8B illustrate an example in which ECC data or checksum data is employed as error detection data, the present invention is not limited to these data.

  FIG. 9 is an explanatory diagram of the exchange of display data for one horizontal scan using packet data.

  The host 38 transmits to the display driver 40 the SYNC packet in which the identifier indicating the horizontal synchronization start timing is set in the packet header part PH and the SYNC packet in which the identifier indicating the horizontal synchronization end timing is set in the packet header part PH. As a result, the horizontal synchronization signal HS can be generated in the display driver 40.

  After transmitting the SYNC packet, the host 38 transmits packet data in which display data for one line is packetized to the display driver 40. In this packet data, an identifier indicating that it is an image format or display data is set in the packet header portion PH, display data is set in the data portion DT, and error detection data is set in the packet footer portion PF.

  Thereafter, the host 38 transmits a SYNC packet to designate the next horizontal synchronization start timing and horizontal synchronization end timing.

  In FIG. 9, the change timing of the horizontal synchronization signal is specified by two SYNC packets. However, the active period of the horizontal synchronization signal is specified and the change timing of the horizontal synchronization signal is specified by one SYNC packet. It may be.

  FIG. 10 is an explanatory diagram of the exchange of display data for one vertical scan using packet data.

  The host 38 transmits the SYNC packet in which the identifier indicating the horizontal synchronization start timing is set in the packet header part PH to the display driver 40, whereby the vertical synchronization signal VS can be generated in the display driver 40. Similarly, the display driver 40 that has received the SYNC packet designating the horizontal synchronization start timing from the host 38 can generate the horizontal synchronization signal HS. Then, after transmitting the SYNC packet, the host 38 transmits to the display driver 40 packet data in which display data for one line is packetized. In this packet data, an identifier indicating that it is an image format or display data is set in the packet header portion PH, display data is set in the data portion DT, and error detection data is set in the packet footer portion PF.

  Thereafter, similar packets are transmitted and received in units of one horizontal scan.

3. Display Driver FIG. 11 shows an outline of the configuration of the display driver 40 in this embodiment.

  The display driver 40 can include the reception I / F circuit 54, the source driver 30, and the gate driver 32 described above. The signal received by the reception I / F circuit 54 is supplied to the source driver 30 or the gate driver 32.

3.1 First Embodiment FIG. 12 is a block diagram showing a configuration example of the reception I / F circuit 54 shown in FIG.

  The reception I / F circuit 54 includes a physical layer circuit 200, a reception processing circuit 210, and a timing generation circuit 220. The physical layer circuit 200 includes first and second differential receivers Rx1 and Rx2, a serial / parallel conversion circuit 70, and a PLL (Phase Lock Loop) circuit 72. The reception processing circuit 210 includes a packet processing unit 212, an error detection unit 214 (an error detection circuit in a broad sense), and a decoder 216.

  The second differential receiver Rx2 connected to the second differential signal line driven by the second differential transmitter Tx2 of the transmission I / F circuit 50 differentially amplifies the clock signal CLK and the inverted clock signal CLKX. As a result, a transfer reference timing for serial transfer via the serial bus 98 is generated. The PLL circuit 72 outputs a reference clock whose phase is synchronized with the output signal of the second differential receiver Rx2 to the timing generation circuit 220.

  The timing generation circuit 220 generates reference timing signals for the serial / parallel conversion circuit 70 and the reception processing circuit 210 based on the reference clock from the PLL circuit 72.

  The first differential receiver Rx1 connected to the first differential signal line driven by the first differential transmitter Tx1 of the transmission I / F circuit 50 differentially amplifies the data signal D and the inverted data signal DX. As a result, transfer data serially transferred via the serial bus 98 is generated. The serial / parallel conversion circuit 70 converts the serial signal differentially amplified by the first differential receiver Rx1 into a parallel signal in synchronization with the reference timing signal from the timing generation circuit 220.

  The reception processing circuit 210 synchronizes with the reference timing signal from the timing generation circuit 220 from the output signal of the serial / parallel conversion circuit 70 from the vertical synchronization signal VS, horizontal synchronization signal HS, data enable signal DE, pixel clock signal PCLK, Display data DBUS and error detection flag FlgErr are generated.

  More specifically, as a result of extracting data of each part of the packet data by the packet processing unit 212 and analyzing the SYNC packet and the data packet by the decoder 216, the reception processing circuit 210 receives the vertical synchronization signal VS and the horizontal synchronization signal HS. The data enable signal DE, the pixel clock signal PCLK, and the display data DBUS are generated. The error detection unit 214 determines whether or not an error has occurred by a known error detection process based on the error detection data of the packet data, and sets an error detection flag FlgErr when it is determined that an error has occurred. Activate.

  The display driver 40 drives the source line based on the display data by the source line driving unit 300 of the source driver 30 while scanning the gate line by the gate driver 32. The source driver 30 includes a display memory 120, and display data for at least one screen is stored in the display memory 120. The source driver 30 temporarily stores the display data extracted by the reception processing circuit 210 in the display memory 120, reads out the display data from the display memory 120 in synchronization with the display timing signal for display, and the liquid crystal display panel 20. The driving of a plurality of source lines is repeated. The display data stored in the display memory 120 in the first vertical scanning period is read from the display memory 120 in the second vertical scanning period that is the vertical scanning period next to the first vertical scanning period, and the liquid crystal display panel. 20 drive. Further, the display driver 40 determines whether or not an error has occurred in the signal from the host 38 based on the error detection flag FlgErr by the error processing unit 310 and performs control to minimize the influence on the image quality. .

  FIG. 13 is an explanatory diagram of a processing example of the error processing unit in the first embodiment.

  When the error detection unit 214 detects an error in the display data based on the error detection flag FlgErr, the error processing unit 310 selects a plurality of scan lines including a dot including a dot on which the display data in which the error is detected is displayed. Control is performed to scan the gate lines.

  As a result, as shown in FIG. 13, the gate line is not selected in the scanning line on which the display data in which the error detection flag FlgErr is activated is displayed. That is, a pixel connected to the gate line is not selected. Since the liquid crystal display panel 20 of FIG. 1 or FIG. 2 is an active matrix type, when a pixel is not selected, the voltage written last time is stored in the pixel.

  The source driver 30 reads the display data stored in the display memory 120 in synchronization with the display timing signal for display, and periodically drives the source lines of the liquid crystal display panel 20. In general, there is little difference between images in two consecutive vertical scanning periods (frames), and if white display or black display is intentionally performed on a scanning line including pixels on which display data in which an error is detected is displayed, The scan line may be noticeable. On the other hand, according to the first embodiment, the control is performed so that a plurality of gate lines are scanned without selecting a scanning line including a dot on which display data in which an error is detected is displayed. The same pixel display as the previous time is performed on the scanning line. Accordingly, the source driver 30 of the display driver 40 updates the next image immediately after the display data is read again from the display memory 120 in the next vertical scanning period. For this reason, even if an error is detected in the display data itself, the influence on the image quality can be minimized. In particular, when an error is detected on a plurality of scanning lines for one screen, it is possible to greatly reduce the influence on image quality degradation as compared with the case where white display or black display is performed on each scanning line. It becomes like this.

3.1.1 Gate Driver FIG. 14 shows a configuration example of the gate driver 32 of FIG.

  The gate driver 32 includes a shift register 80, a level shifter 82, and an output control circuit 84.

  The shift register 80 includes a plurality of flip-flops provided corresponding to the gate lines and sequentially connected. When the shift register 80 holds the start pulse signal VSP in the flip-flop in synchronization with the clock signal VCK, the shift register 80 sequentially shifts the start pulse signal VSP to the adjacent flip-flop in synchronization with the clock signal VCK. The clock signal VCK input here is a horizontal synchronizing signal, and the start pulse signal VSP is a vertical synchronizing signal.

  The level shifter 82 shifts the voltage level from the shift register 80 to a voltage level corresponding to the liquid crystal element of the liquid crystal display panel 20 and the transistor capability of the TFT. As this voltage level, for example, a high voltage level of 20 V to 50 V is required.

  The output control circuit 84 buffers the scanning voltage shifted by the level shifter 82, outputs the buffered voltage to the gate line, and drives the gate line. The output control circuit 84 includes an AND operation circuit provided for each gate line, and an AND operation result of the scanning voltage shifted by the level shifter 82 and the output enable signal VENB is output as a gate line selection signal. The Therefore, the gate line selection period can be controlled by the output enable signal VENB.

3.1.2 Source Driver FIG. 15 is a block diagram showing a configuration example of the source driver 30 shown in FIG.

  The source driver 30 includes a display memory 120, a line latch 122, a level shifter 124, a reference voltage generation circuit 126, a DAC (Digital-to-Analog Converter) (voltage selection circuit in a broad sense) 128, and an output buffer 130.

  Further, the source driver 30 includes an error processing unit 310 (error processing circuit), a display timing generation circuit 136, and a level shifter 138.

  The display memory 120 receives the display data DBUS generated after differential amplification by the reception I / F circuit 54. The reception I / F circuit 54 supplies display data serially to the source driver 30 in units of one pixel, and the display data is sequentially taken into the display memory 120. The source driver 30 has a memory control circuit (not shown), and the memory control circuit performs control to write display data into the display memory 120 while updating the write address of the display memory 120. The memory control circuit performs control to update the read address in synchronization with the display read timing and to read the display data stored in the read address.

  The line latch 122 latches the display data read from the display memory 120 based on the horizontal synchronization signal HS.

  The level shifter 124 converts the voltage level of each bit signal read from the line latch 122.

  In the reference voltage generation circuit 126, each reference voltage generates a plurality of reference voltages corresponding to each display data. More specifically, the reference voltage generation circuit 126 generates a plurality of types of reference voltages obtained by resistance-dividing the voltage between the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH, and supplies the generated voltage to the DAC 128.

  The DAC 128 outputs a drive voltage (gray scale voltage) corresponding to the display data from the level shifter 124 for each source line from among a plurality of reference voltages in which each reference voltage corresponds to the display data. More specifically, the DAC 128 decodes display data for one dot from the level shifter 124 and selects one of a plurality of reference voltages based on the decoding result. The reference voltage selected by the DAC 128 is output to the output buffer 130 as a drive voltage.

  The output buffer 130 has a plurality of data output units in which each data output unit is provided corresponding to each source line. Each data output unit of the output buffer 130 drives the source line based on the drive voltage from the DAC 128. Each data output unit includes an operational amplifier connected in a voltage follower.

  The error processing unit 310 receives the error detection flag FlgErr, the vertical synchronization signal VS, the horizontal synchronization signal HS, and the pixel clock signal PCLK from the reception I / F circuit 54. The error processing unit 310 detects an error in the reception signal of the reception I / F circuit 54 based on the error detection flag FlgErr, and outputs the error detection result to the display timing generation circuit 136.

  The display timing generation circuit 136 controls the gate line selection timing and the source line drive timing based on the vertical synchronization signal VS, the horizontal synchronization signal HS, the pixel clock signal PCLK, and the error detection result of the error processing unit 310. Generate a signal. The level shifter 138 converts the voltage level of each bit of the control signal generated by the display timing generation circuit 136. For example, the level shifter 138 outputs a clock signal VCK, a start pulse signal VSP, and an output enable signal VENB for controlling the display timing of the gate driver 32.

  Further, the source line driver 300 of the source driver 30 can include an oscillation circuit 380. The oscillation circuit 380 can generate an oscillation clock that is asynchronous with the display timing signal from the reception I / F circuit 54. This oscillation clock is supplied to the display timing generation circuit 136. The display timing generation circuit 136 can generate a display timing signal for display (horizontal synchronization signal, vertical synchronization signal) based on the oscillation clock, and can generate a display readout timing.

  FIG. 16 illustrates an example of a main configuration part of the display timing generation circuit 136.

  FIG. 16 shows only a block of a circuit portion that generates the output enable signal VENB in the display timing generation circuit 136. The display timing generation circuit 136 can include a flip-flop (FF) 350, a RAM address counter 352, a counter 354, and a gate output control unit 356.

  An error detection flag FlgErr and an interface clock (I / FCLK) are input to the FF 350. I / FCLK is a reference clock generated by the timing generation circuit 220 of the reception I / F circuit 54, for example. The RAM address counter 352 can generate a write address and a read address of the display memory 120 in synchronization with the I / FCLK. The FF 350 latches the write address of the display memory 120 when the error detection flag FlgErr becomes active in synchronization with I / FCLK. The write address latched in the FF 350 is supplied to the gate output control unit 356.

  The counter 354 receives the horizontal synchronization clock 1HCLK generated by the display timing generation circuit 136 based on the oscillation clock from the oscillation circuit 380. The counter 354 counts the number of horizontal synchronization clocks 1HCLK based on the start timing of one vertical scanning period, and supplies the count value to the gate output control unit 356.

  The write address of the display memory 120 latched in the FF 350 is associated with the scan line in the vertical scan period. The gate output control unit 356 includes a comparator 357 that compares the write address of the FF 350 and the count value of the counter 354, and determines whether the scan line in which the error detection flag FlgErr is active by the comparator 357 is an error line. It can be determined whether or not. The output of the comparator 357 becomes the output enable signal VENB.

  As described above, the display driver 40 can control the gate driver 32 so as not to select a scanning line including a dot on which display data in which an error is detected is displayed.

  FIG. 17 shows an example of control of the gate driver 32 in the first embodiment.

  In FIG. 17, the display enabled by the data enable signal DE for each horizontal scanning period defined by the horizontal synchronizing signal HS within one vertical scanning period started when the vertical synchronizing signal VS becomes L level. Data DBUS is supplied. When the display data DBUS is supplied, the gradation voltage corresponding to the display data DBUS is supplied to the source line of the liquid crystal display panel 20 in the next horizontal scanning period.

  In FIG. 17, when an error is detected in the display data of the third line (SQ1), the error detection flag FlgErr is changed to H level in the next horizontal scanning period (SQ2). In this horizontal scanning period, the output enable signal VENB remains at the L level based on the error detection flag FlgErr (SQ3), and the third gate line is not selected.

  When no error is detected in the display data on the fourth line, the error detection flag FlgErr changes to L level in the next horizontal scanning period, and the gate line on the fourth line is selected. As described above, in the horizontal scanning period next to the horizontal scanning period in which the error is detected by the error detection unit 214, the liquid crystal display panel can be selected without selecting a scanning line including dots on which the image data in which the error is detected is displayed. The gate driver 32 is controlled to scan the plurality of 20 gate lines.

  In FIG. 16 and FIG. 17, image quality degradation is suppressed by controlling not to select a scanning line including a dot on which display data in which an error is detected is displayed. It is not limited to this. For example, the display data in the vertical scanning period may be replaced with the display data in the immediately preceding vertical scanning period by controlling so that only display data in which an error is detected is not written in the display memory 120. In this way, only the dots corresponding to the display data in which an error is detected are displayed using the display data of the previous vertical scanning period, so that the image quality is further deteriorated compared with the case where the scanning line is not selected. Can be prevented. This can be easily realized by not writing only the display data in which an error is detected to the display memory 120 when the memory control circuit writes the display data to the display memory 120. In this case, the display driver 40 reads the display data in which the error is detected by the error detection unit 214 from the display memory 120 in the vertical scanning period next to the vertical scanning period in which the error is detected without writing the display data in the display memory 120. The source line is driven based on the obtained image data.

3.2 Second Embodiment In the first embodiment, when an error is detected in display data, the gate driver is controlled so as not to select a scanning line on which the display data is displayed. On the other hand, in the second embodiment, attention is paid to the fact that the source driver has a built-in display memory, and the display image can be periodically updated by reading the display data repeatedly from the display memory and driving the liquid crystal display panel. Then, a request for resending the display data in which an error is detected is made. That is, the same display image can be periodically updated by incorporating the display memory. Therefore, during this period, a request for retransmission of display data in which an error has been detected is made, and display is performed using only normal display data, thereby preventing image quality deterioration.

  FIG. 18 is an explanatory diagram of an example of error processing in the second embodiment.

  FIG. 18 shows a memory image and an image displayed on the liquid crystal display panel 20 corresponding to the display data stored in the display memory along the flow of time in the vertical axis direction. ing.

  It is assumed that an image is displayed on the liquid crystal display panel 20 in the vertical scanning period VT1 defined by the vertical synchronization signal VS. It is assumed that an error is detected in the display data during the writing period WRT1 of the display data to the display memory of the display driver in the vertical scanning period VT1.

  At this time, in the second embodiment, the error detection flag FlgErr is set to the H level, and a display data retransmission request is made to the host that is the transmission source of the display data. Then, the error detection flag FlgErr is returned to the L level on condition that no error is detected in the display data retransmitted from the host written in the display memory in the writing period WRT2. Then, the pulse of the vertical synchronization signal VS is shifted until the timing at which the error detection flag FlgErr returns to the L level.

  In this vertical scanning period VT1, the host is requested to retransmit the display data in the vertical scanning period, but the gate driver may complete the scanning in the vertical scanning period regardless of whether or not an error is detected. However, when an error is detected, scanning in the vertical scanning period may be interrupted (not necessarily completed). In any case, the gate driver starts scanning in the next vertical scanning period on the condition that retransmission of display data is started in response to a retransmission request to the host.

  Note that when scanning in the vertical scanning period is interrupted, for example, by generating a gate output control enable signal that is set on condition that an error has been detected and is reset at the start timing of the next vertical scanning period, This can be easily realized with the configuration of the first embodiment.

  Thereafter, whether or not the scanning of the vertical scanning period is completed or interrupted, in the vertical scanning period VT2 next to the vertical scanning period VT1 in which the error is detected, based on the display data written in the display memory in the writing period WRT2. To drive the liquid crystal display panel.

  As described above, according to the second embodiment, since the display data is already stored in the display memory, the display image can be periodically updated. Therefore, by making a retransmission request for display data in which an error is detected and performing display using only normal display data, it is possible to prevent image quality degradation as in the first embodiment. Become.

  Hereinafter, a configuration example of the display driver in the second embodiment will be described. In the following, a configuration example in which a request for resending display data in the vertical scanning period is made to the host and the gate driver completes scanning in the vertical scanning period regardless of whether or not an error has been detected will be described. . A configuration different from the display driver in the first embodiment among the configurations of the display driver in the second embodiment will be described.

  FIG. 19 shows a block diagram of a configuration example of the gate driver in the second embodiment. 19, the same parts as those in FIG. 14 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

  The gate driver 400 of FIG. 19 includes a shift register 80, a level shifter 82, and an output control circuit 85. The output control circuit 85 buffers the scanning voltage shifted by the level shifter 82, outputs the buffered voltage to the gate line, and drives the gate line. The output control circuit 85 includes an output buffer provided for each gate line, buffers the scanning voltage shifted by the level shifter 82, and outputs it as a gate line selection signal.

  FIG. 20 is an explanatory diagram of a configuration example of an interface between the host and the display driver in the second embodiment. However, in FIG. 20, the same parts as those in FIG.

  The display driver in the second embodiment includes a reception I / F circuit 500 of FIG. 20 instead of the reception I / F circuit 54 of FIG. The display driver includes a transmission I / F circuit 600. The host 38 includes a reception I / F circuit 700.

  The reception I / F circuit 500 is different from the reception I / F circuit 54 in that a packet processing unit 510 is provided instead of the packet processing unit 212. The packet processing unit 510 includes a retransmission request processing unit 512. The retransmission request processing unit 512 makes a display data retransmission request to the host 38 that is the transmission source of the display data received by the reception I / F circuit 54 based on the error detection processing result of the error detection unit 214. The retransmission request processing unit 512 makes a display data retransmission request to the host 38 using a retransmission request packet via the serial bus 98.

  The transmission I / F circuit 600 includes a physical layer circuit 610. The physical layer circuit 610 includes a third differential transmitter Tx3, a fourth differential transmitter Tx4, a parallel / serial conversion circuit 612, and a transmission clock generation circuit 614. The parallel / serial conversion circuit 612 converts the parallel data of the retransmission request packet data generated by the retransmission request processing unit 512 into serial data in synchronization with the reference timing signal generated by the timing generation circuit 220. The third differential transmitter Tx3 transfers the data serialized by the parallel / serial conversion circuit 612 via the serial bus 98 as the data signal D and the inverted data signal DX. The transmission clock generation circuit 614 generates a transmission clock signal. The fourth differential transmitter Tx4 transfers the clock signal generated by the transmission clock generation circuit 614 via the serial bus 98 as the clock signal CLK and the inverted clock signal CLKX.

  The reception I / F circuit 700 of the host 38 includes a third differential receiver Rx3 and a fourth differential receiver Rx4. The third differential receiver Rx3 generates transfer data serially transferred via the serial bus 98 by differentially amplifying the data signal D and the inverted data signal DX. The fourth differential receiver Rx4 differentially amplifies the clock signal CLK and the inverted clock signal CLKX to generate transfer reference timing for serial transfer via the serial bus 98.

  FIG. 21 shows an example of a packet transmission / reception sequence between the host and the display driver in the second embodiment.

  The display driver receives display data from the host 38 as a data packet (ST1), performs packet processing as described above, and determines whether or not there is an error in the display data. As a result, when it is determined that there is an error in the display data packetized from the host 38 (ST2), an error report indicating the type of the detected error is packetized and transmitted to the host 38 (ST3).

  The host 38 that has received the error report analyzes the error report (ST4) and identifies the type of error detected on the display driver side. For example, when an error in the display data is detected, the host 38 receives the error report. It is transmitted as a retransmission data packet of display data (ST5). The display driver that has received the retransmission data packet restarts the display driving process of the liquid crystal display panel when it is determined that there is no error in the display data retransmitted by the retransmission data packet (ST6).

  FIG. 22 shows a flowchart of an example of data packet retransmission processing by the host in the second embodiment. The host 38 can perform the process shown in FIG. 22 by reading a program stored in a memory (not shown) and executing a process corresponding to the program.

  First, when receiving a packet from the display driver (step S10: Y), the host 38 analyzes the content of the packet to determine whether it is an error report (step S11). When it is determined that the packet is an error report (step S11: Y), it is determined whether an error is detected on the display driver side (step S12). When it is determined that the error is an error in the display data received on the display driver side (step S13: Y), the display data in which the error is detected on the display driver side is packetized and displayed as a retransmission data packet. A process of resending to the driver is performed (step S14), and the process returns to step S10 (return).

  When no packet is received in step S10 (step S10: N), when it is determined in step S11 that the received packet does not include an error report (step S11: N), no error is detected in the error report in step S12. When it is indicated (step S12: N), or when it is determined that the error detected on the display driver side in step S13 is not display data (step S13: N), it is monitored whether or not it is a transmission timing. (Step S15: N).

  When it is determined in step S15 that the transmission timing is reached (step S15: Y), the transmission process of the SYNC packet obtained by packetizing the vertical synchronization signal or the horizontal synchronization signal (step S16) and the transmission of the data packet obtained by packetizing the display data The process (step S17) is performed, and the process returns to step S10 (return).

  The source driver in the second embodiment once completes scanning in the vertical scanning period in which an error is detected, and requests retransmission of display data in which an error is detected.

  FIG. 23 shows a block diagram of a configuration example of the source driver in the second embodiment.

  In FIG. 23, the same parts as those in FIG. 15 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The source driver 800 in FIG. 23 differs from the source driver 30 in FIG. 15 in that a display timing generation circuit 810 is provided instead of the display timing generation circuit 136. The display timing generation circuit 810 allows the source driver 800 to once complete scanning in the vertical scanning period in which an error is detected.

  FIG. 24 shows a configuration example of the display timing generation circuit 810 of FIG.

  The display timing generation circuit 810 can include a counter 812, a count-up value register 814, a comparator 816, and a mask circuit 818.

  The counter 812 receives the horizontal synchronization clock 1HCLK generated by the display timing generation circuit 810 based on the oscillation clock from the oscillation circuit 380. The counter 812 counts the number of horizontal synchronization clocks 1HCLK based on the start timing of one vertical scanning period, and supplies the count value to the comparator 816. A set value corresponding to the number of horizontal scanning periods within one vertical scanning period is set in advance in the count-up value register 814 from the host 38. The comparator 816 compares the count value of the counter 812 with the count-up value register 814, and outputs a coincidence detection pulse when they coincide.

  The mask circuit 818 masks the output of the comparator 816 with the error detection flag FlgErr. The output of the mask circuit 818 is output as the frame head flag endLn. When the frame head flag endLn becomes active, the count value of the counter 812 is initialized. Note that the counter 812 counts the number of clocks of the horizontal synchronization clock 1HCLK to a predetermined count value (for example, the set value of the count-up value register), and stops the count operation until the frame head flag endLn becomes active.

  When the frame head flag endLn generated in this way becomes active, a pulse of the display vertical synchronization signal VS is generated.

  25A and 25B are timing charts of an operation example of the display timing generation circuit 810 in FIG.

  FIG. 25A shows an operation example when the error detection flag FlgErr is at the L level and no error is detected in the display data or the like. When the line head flag end1H becomes active, a pulse of the display horizontal synchronization signal HS is generated. The counter 812 counts the number of horizontal synchronization clocks 1HCLK, and the count value cntLn is counted up. For example, when the count value cntLn is 328, the frame head flag endLn becomes active, and the count value cntLn of the counter 812 is initialized.

  FIG. 25B shows an operation example when the error detection flag FlgErr changes from the H level to the L level and changes from a state where an error is detected in display data or the like to a state where no error is detected. . Here, the error detection flag delay FlgErrd is a signal obtained by synchronizing the error detection flag FlgErr with the line head flag end1H. Also in this case, when the line head flag end1H becomes active, a pulse of the display horizontal synchronization signal HS is generated. The counter 812 counts the number of horizontal synchronization clocks 1HCLK, and the count value cntLn is counted up. For example, when the count value cntLn is 328, since the error detection flag FlgErr (error detection flag delay FlgErrd) is at the H level, the count operation of the counter 812 is stopped. Then, after the timing when the error detection flag delay FlgErrd changes from the H level to the L level, the frame head flag endLn becomes active at the timing when the next line head flag end1H becomes active. Thereby, the count value cntLn of the counter 812 is initialized and the next vertical scanning period is started.

  As described above, the source driver 800 can once complete scanning in the vertical scanning period in which an error such as display data is detected. Then, when the error is detected, a display data retransmission request is issued to the host, and scanning can be started again when the error detection flag FlgErr changes to the L level. Accordingly, scanning in the next vertical scanning period can be started on the condition that the display data retransmission corresponding to the retransmission request to the host 38 is started.

  FIG. 26 shows a timing diagram of a control example of the source driver 800 in the second embodiment.

  FIG. 26 shows an example of timing when the display driver shifts to the sleep-out state upon receiving a command packet from the host 38 in the sleep-in state.

  First, in the sleep-in state, it is assumed that an error is detected in the display data packetized in the data packet after the SYNC packet (SQ10). This error changes the error detection flag FlgErr from the L level to the H level, but the display driver does not request the host 38 to retransmit the display data.

  Next, the display driver that has received the command packet from the host 38 in the sleep-in state analyzes the command packet and shifts to the sleep-out state (SQ11). As a result, the control signal slpout in the display driver (source driver 800) changes from the L level to the H level.

  When shifting to the sleep-out state, the display driver starts a display driving process for the liquid crystal display panel 20. That is, a pulse of the vertical synchronizing signal VS is generated for display.

  It is assumed that an error is detected in the display data packetized by the data packet after the SYNC packet from the host 38 in the sleep-out state (SQ12). This error changes the error detection flag FlgErr from the L level to the H level. Then, the display driver makes a display driver retransmission request to the host 38 as described above. Receiving this retransmission request, the host 38 retransmits the display data with a data packet (SQ13). When the retransmitted data packet is analyzed and the display driver detects that there is no error in the display data, the error detection flag FlgErr is changed from H level to L level. As a result, the frame head flag endLn becomes active (SQ14). A pulse of the vertical synchronizing signal VS for display is generated by the activated frame head flag endLn (SQ15).

  As described above, in the second embodiment, when an error occurs in the display data, the host requests the host to retransmit the display data, extends the vertical scanning period, and receives normal display data. The next vertical scanning period is started.

4). Electronic Device FIG. 27 shows a block diagram of a configuration example of an electronic device in the present embodiment. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device. In FIG. 27, the same parts as those in FIG. 1 or FIG.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera and supplies image data captured by the CCD camera to the host 38 in the YUV format.

  The mobile phone 900 includes the liquid crystal display panel 20. The liquid crystal display panel 20 is driven by the display driver 40 including the source driver 30 and the gate driver 32 (or the display driver according to the second embodiment including the source driver 800 and the gate driver 400). The liquid crystal display panel 20 includes a plurality of source lines, a plurality of gate lines, and a plurality of pixels. The source driver 30 (or source driver 800; the same applies hereinafter) controls the drive of the source line based on the display data.

  The host 38 is connected to the display driver 40 (or the display driver in the second embodiment, the same applies hereinafter), and supplies RGB format display data to the source driver 30.

  The power supply circuit 100 is connected to the display driver 40 and supplies a driving power supply voltage to each driver. The counter electrode voltage VCOM is supplied to the counter electrode of the liquid crystal display panel 20.

  Further, the host 38 can supply the display data received via the antenna 960 to the display driver 40 after demodulating the display data by the modem unit 950. The host 38 displays the display data on the liquid crystal display panel 20 by the display driver 40 based on the display data.

  The host 38 can instruct transmission to another communication apparatus via the antenna 960 after the display data generated by the camera module 910 is modulated by the modem unit 950.

  The host 38 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the liquid crystal display panel 20 based on operation information from the operation input unit 970.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the above-described liquid crystal display panel, but can be applied to driving electroluminescence and plasma display devices.

  In the above-described embodiment, the case where the display memory is incorporated in the source driver of the display driver has been described as an example. However, the display driver may not include the display memory, and the display memory is provided outside the display driver. The same effect can be obtained.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention may be made dependent on another independent claim.

1 is a diagram illustrating an outline of a configuration of an active matrix liquid crystal display device according to an embodiment. The figure which shows the outline | summary of the other structure of the active matrix type liquid crystal display device in this embodiment. FIG. 3 is a diagram illustrating a configuration example of the liquid crystal display device of FIG. 1 or FIG. 2. The block diagram of the structural example between the host and display driver in this embodiment. The figure which shows the example of the transmission signal which a host outputs. The figure which shows the example of the differential signal transmitted via a serial bus. 7A and 7B are explanatory diagrams of packet data exchanged between the host and the display driver. FIG. 8A illustrates an example of a short packet structure. FIG. 8B shows an example of a long packet structure. Explanatory drawing of the exchange of the display data for 1 horizontal scanning by packet data. Explanatory drawing of the exchange of the display data for 1 vertical scanning by packet data. FIG. 3 is a diagram showing an outline of a configuration of a display driver in the present embodiment. FIG. 12 is a block diagram of a configuration example of a reception I / F circuit in FIG. 11. Explanatory drawing of the process example of the error process part in 1st embodiment. FIG. 12 is a block diagram of a configuration example of the gate driver in FIG. 11. FIG. 12 is a block diagram of a configuration example of the source driver in FIG. 11. The figure which shows an example of the principal part of the display timing generation circuit of 1st Embodiment. The figure which shows the example of control of the gate driver in 1st Embodiment. Explanatory drawing of the example of an error process in 2nd Embodiment. The block diagram of the structural example of the gate driver in 2nd Embodiment. Explanatory drawing of the structural example of the interface of the host and display driver in 2nd Embodiment. The figure which shows an example of the transmission / reception sequence of the packet between the host and display driver in 2nd Embodiment. FIG. 10 is a flowchart of an example of a data packet retransmission process by a host according to the second embodiment. The block diagram of the structural example of the source driver in 2nd Embodiment. FIG. 24 is a diagram illustrating a configuration example of a display timing generation circuit in FIG. 23. 25A and 25B are timing diagrams of an operation example of the display timing generation circuit in FIG. The timing diagram of the example of control of the source driver in 2nd Embodiment. 1 is a block diagram of a configuration example of an electronic device according to an embodiment.

Explanation of symbols

10 liquid crystal display device, 20 liquid crystal display panel, 30 source driver,
32 gate drivers, 38 hosts, 40 display drivers,
50 transmission I / F circuit, 54 reception I / F circuit, 60 drive unit,
70 serial / parallel conversion circuit, 72 PLL circuit, 98 serial bus,
120 display memory, 122 line latch, 124 level shifter,
126 reference voltage generation circuit, 128 DAC, 130 output buffer,
136 display timing generation circuit, 138 level shifter, 200 physical layer circuit,
210 reception processing circuit, 212 packet processing unit,
214 error detection unit, 216 decoder, 220 timing generation circuit,
300 source line drive unit, 310 error processing unit, 380 oscillation circuit,
DE data enable signal, FlgErr error detection flag,
HS horizontal sync signal, PCLK pixel clock signal, VS vertical sync signal

Claims (11)

A display driver for driving an active matrix type electro-optical device,
An interface circuit for receiving image data;
An error detection circuit for performing error detection processing of image data received by the interface circuit;
A display memory for storing image data received by the interface circuit;
A source line driving circuit for driving a source line of the electro-optical device based on image data read from the display memory;
In the vertical scanning period next to the vertical scanning period in which the error is detected by the error detection circuit, the plurality of electro-optical devices of the electro-optical device can be selected without selecting a scanning line including a dot on which the image data in which the error is detected is displayed. A display driver that controls a gate line driving circuit that scans the plurality of gate lines so as to scan the gate lines. A display driver for driving an active matrix type electro-optical device,
An interface circuit for receiving image data;
An error detection circuit for performing error detection processing of image data received by the interface circuit;
A display memory for storing image data received by the interface circuit;
A source line driving circuit for driving a source line of the electro-optical device based on image data read from the display memory;
Without writing the image data in which an error is detected by the error detection circuit to the display memory, the source based on the image data read from the display memory in the vertical scanning period next to the vertical scanning period in which the error is detected A display driver characterized by driving a line. In claim 1 or 2,
A display driver comprising a gate line driving circuit for selecting a plurality of gate lines of the electro-optical device. In any one of Claims 1 thru | or 3,
A retransmission request processing unit that makes a retransmission request of image data based on an error detection processing result of the error detection circuit to a transmission source of the image data received by the interface circuit;
When an error is detected by the error detection circuit,
The retransmission request processing unit makes a retransmission request for image data in the vertical scanning period to the transmission source, and the gate line driving circuit completes scanning in the vertical scanning period, and image data corresponding to the retransmission request A display driver characterized by starting scanning in the next vertical scanning period on the condition that the retransmission of the image is started. In any one of Claims 1 thru | or 3,
A retransmission request processing unit that makes a retransmission request of image data based on an error detection processing result of the error detection circuit to a transmission source of the image data received by the interface circuit;
When an error is detected by the error detection circuit,
The retransmission request processing unit makes a retransmission request for the image data of the vertical scanning period to the transmission source, and the gate line driving circuit responds to the retransmission request without completing the scanning of the vertical scanning period. A display driver characterized by starting scanning in the next vertical scanning period on condition that retransmission of image data is started. A display driver for driving an active matrix type electro-optical device,
An interface circuit for receiving image data;
An error detection circuit for performing error detection processing of image data received by the interface circuit;
A source line driving circuit for driving a source line of the electro-optical device based on image data received by the interface circuit;
A gate line driving circuit for scanning a plurality of gate lines of the electro-optical device;
A retransmission request processing unit that makes a retransmission request of image data based on an error detection processing result of the error detection circuit to a transmission source of the image data received by the interface circuit,
When an error is detected by the error detection circuit,
The retransmission request processing unit makes a retransmission request of the image data of the frame to the transmission source, and the gate line driving circuit completes scanning of the frame and starts retransmission of the image data corresponding to the retransmission request. A display driver characterized by starting scanning of the next frame on the condition of A display driver for driving an active matrix type electro-optical device,
An interface circuit for receiving image data;
An error detection circuit for performing error detection processing of image data received by the interface circuit;
A source line driving circuit for driving a source line of the electro-optical device based on image data received by the interface circuit;
A gate line driving circuit for scanning a plurality of gate lines of the electro-optical device;
A retransmission request processing unit that makes a retransmission request of image data based on an error detection processing result of the error detection circuit to a transmission source of the image data received by the interface circuit,
When an error is detected by the error detection circuit,
The retransmission request processing unit makes a retransmission request for the image data of the vertical scanning period to the transmission source, and the gate line driving circuit responds to the retransmission request without completing the scanning of the vertical scanning period. A display driver characterized by starting scanning in the next vertical scanning period on condition that retransmission of image data is started. Multiple gate lines,
Multiple source lines,
A plurality of pixels in which each pixel is specified by each gate line and each source line;
A gate driver that scans the plurality of gate lines;
An electro-optical device comprising: the display driver according to claim 1, wherein the display driver drives the plurality of source lines based on data received by the interface circuit.   An electro-optical device comprising the display driver according to claim 1. With the host,
An electronic device comprising: the display driver according to claim 1, which receives data from the host.   An electronic apparatus comprising the electro-optical device according to claim 8.

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