KR20100073739A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to reduce the noise of an electromagnetic-interference broadband by distributing the output time of source driver integrated circuits. CONSTITUTION: A liquid crystal display device includes a plurality of data lines and gate lines. The gate lines cross the data lines. A timing controller generates source-output enable signal and a chip identification code. Delay circuits(ΔD1 to ΔD3) are embedded in a plurality of source driver integrated circuits, and the source driver integrated circuits outputs a data voltage. The data voltage is applied to the data lines. The delay circuits delay the source-output enable signal.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device.

A liquid crystal display device of an active matrix driving type displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. The liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), which is applied to a display device in portable information equipment, office equipment, computer, etc., and is also rapidly replaced by a cathode ray tube.

A liquid crystal display device includes a plurality of source drive integrated circuits (“ICs”) for supplying data voltages to data lines of a liquid crystal display panel, and gate pulses (or scan pulses) to gate lines of the liquid crystal display panel. ) And a plurality of gate drive ICs for sequentially supplying the < RTI ID = 0.0 > In such a liquid crystal display, digital video data is input to a timing controller through an interface. The timing controller supplies digital video data, a clock signal for sampling digital video data, a control signal for controlling the operation of the source drive ICs, and the like through an interface such as mini LVDS (Low Voltage Differential Signaling). do. The source drive ICs convert digital video data input in series from a timing controller into a parallel scheme, and then convert an analog data voltage using a gamma compensation voltage to supply data lines.

The timing controller supplies signals required for the source drive ICs in a multi-drop method in which clock and digital video data are commonly applied to the source drive ICs. The source drive ICs are cascaded and sequentially output data voltages of one line after sampling the data sequentially. Such a data transmission method includes control wirings for controlling R data transfer wiring, G data transfer wiring, B data transfer wiring, operation timing of output and polarity conversion operation of the source drive IC, and the like between the timing controller and the source drive ICs; Many wirings, such as clock transmission wirings, are required. As an example of RGB data transmission in the mini-LVDS interface method, the mini-LVDS interface method transmits RGB digital video data and a clock as differential signal pairs that are out of phase with each other, thereby simultaneously transmitting odd and even data. In this case, at least 14 wires are required between the timing controller and the source drive ICs for RGB data transmission. Therefore, it is difficult to reduce the width of the printed circuit board (PCB) disposed between the timing controller and the source drive ICs because many wirings should be formed.

Recently, the liquid crystal display device processes a large amount of data at high speed according to the high resolution and large screen tendency of the liquid crystal display panel 10, and the data load for processing simultaneously increases. In this state of high data load, when the data voltages are simultaneously output from the source drive ICs, electromagnetic interference (EMI) broadband noise increases.

Accordingly, an object of the present invention is to provide a liquid crystal display device to reduce EMI broadband noise as an invention devised to solve the problems of the prior art.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention comprises a liquid crystal display panel including a plurality of data lines, the gate line crossing the data lines; A timing controller for generating a source output enable signal and a chip identification code; And a plurality of sources incorporating a delay circuit for delaying the source output enable signal according to the chip identification code to output data voltages to be supplied to the data lines in response to the source output enable signal delayed by the delay circuit. Drive ICs.

The liquid crystal display of the present invention can reduce EMI broadband noise by distributing the output time of the source drive ICs by individually controlling the delay time of the delay circuits embedded in the source drive ICs using chip identification codes.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 1 to 29.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention may include a liquid crystal display panel 10, a timing controller TCON, source drive ICs SDIC # 1 to SDIC # 8, and gate drive ICs. GDIC # 1 to GDIC # 4).

The liquid crystal layer is formed between the glass substrates of the liquid crystal display panel 10. The liquid crystal display panel 10 includes m × n liquid crystal cells Clc arranged in a matrix by a cross structure of m data lines DL and n gate lines GL.

A pixel array including data lines DL, gate lines GL, TFTs, and a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 10. The liquid crystal cells Clc are driven by an electric field between the pixel electrode 1 to which the data voltage is supplied through the TFT and the common electrode 2 to which the common voltage Vcom is supplied. The gate electrode of the TFT is connected to the gate line GL, and the source electrode thereof is connected to the data line DL. The drain electrode of the TFT is connected to the pixel electrode 1 of the liquid crystal cell. The TFT is turned on according to the gate pulse supplied through the gate line GL to supply the positive / negative analog video data voltage from the data line DL to the pixel electrode 1 of the liquid crystal cell Clc. .

A black matrix, a color filter, a common electrode 2, and the like are formed on the upper glass substrate of the liquid crystal display panel 10.

The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate.

A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed. A spacer for maintaining a cell gap of the liquid crystal cell Clc is formed between the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10.

The liquid crystal mode of the liquid crystal display panel applicable to the present invention may be implemented in any liquid crystal mode as well as in the TN mode, VA mode, IPS mode, FFS mode. In addition, the liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display.

The timing controller (TCON) is a vertical / horizontal synchronization signal (Vsync, Hsync), an external data enable signal (Data Enable, DE), and a dot clock (CLK) through an LVDS interface and a transition minimized differential signaling (TMDS) interface. The timing control signals for controlling the operation timing of the source drive ICs SDIC # 1 to SDIC # 8 and the gate drive ICs GDIC # 1 to GDIC # 4 are generated by receiving an external timing signal. The timing control signals include a gate timing control signal for controlling the operation timing of the gate drive ICs GDIC # 1 to GDIC # 4 and a timing control signal for controlling the operation timing of the source drive ICs SDIC # 1 to SDIC # 8. And a source timing control signal.

The timing controller TCON is connected to the source drive ICs SDIC # 1 to SDIC # 8 in a point-to-point manner described later. The timing controller TCON includes a preamble signal for initializing the source drive ICs SDIC # 1 to SDIC # 8, source control data including a source timing control signal, a clock, and RGB digital video data. The data is transferred to the source drive ICs SDIC # 1 to SDIC # 8 through a pair of data wires.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE1 to GOE3), and the like. The gate start pulse GSP is applied to the first gate drive IC GDIC # 1. The gate start pulse GSP indicates a start time at which a scan is started so that a first gate pulse is generated from the first gate drive IC GDIC # 1. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The shift register of the gate drive ICs GDIC # 1 to GDIC # 4 shifts the gate start pulse GSP at the rising edge of the gate shift clock GSC. The second to fourth gate drive ICs GDIC # 2 to GDIC # 4 start receiving the carry signal of the previous gate drive IC as a gate start pulse. The gate output enable signal GOE controls the output timing of the gate drive ICs GDIC # 1 to GDIC # 4. The gate drive ICs GDIC # 1 to GDIC # 4 output a gate pulse for a low logic period of the gate output enable signal GOE, that is, immediately after the polling time of the previous pulse to just before the rising time of the next pulse. do. One period of the gate output enable signal GOE is approximately one horizontal period.

The source timing control signal is transmitted to the source drive ICs SDIC # 1 to SDIC # 8 through a pair of data wires during the time between the preamble signal transmission time and the RGB data block transmission time. Output-related control data; The polarity control related control data includes control information for controlling a polarity control signal (POL) in the form of pulses generated in the source drive ICs SDIC # 1 to SDIC # 8. The digital-to-analog converter (hereinafter referred to as "DAC") of the source drive ICs (SDIC # 1 to SDIC # 8) converts RGB digital video data into positive analog video in response to a polarity control signal (POL). Convert to data voltage or negative analog video data voltage. The source output related control data includes control information for controlling a source output enable signal (SOE) in the form of pulses generated in the source drive ICs. The source output enable signal SOE controls timing of outputting the positive / negative analog video data voltages from the source drive ICs SDIC # 1 to SDIC # 8.

Each of the gate drive ICs GDIC # 1 to GDIC # 4 sequentially supplies gate pulses to the gate lines GL in response to gate timing control signals.

The source drive ICs SDIC # 1 to SDIC # 8 lock an output frequency and a phase of an integrated clock separation and data sampling unit according to a preamble signal supplied from a timing controller TCON through a data wire pair. Subsequently, the source drive ICs SDIC # 1 to SDIC # 8 receive a serial clock from a source control packet input to the digital bit stream through the data wire pair after the clock separation and the output frequency and phase of the data sampling unit are fixed. Restore and sample the control data related to the source output. The source drive ICs SDIC # 1 to SDIC # 8 output the polarity control signal POL and the source output enable signal SOE using control data.

The source drive ICs SDIC # 1 to SDIC # 8 recover a clock from a source control packet input to the digital bit stream through the data wire pair, thereby applying a polarity control signal POL and a source output enable signal SOE. After reconstruction, the clock is reconstructed from an RGB data packet input to the digital bit stream through the data line pair to generate a serial clock for data sampling, and sample the RGB digital video data input in serial according to the serial clock. The source drive ICs SDIC # 1 to SDIC # 8 convert sequentially sampled RGB digital video data into a parallel system and then convert the data into positive / negative analog video data in response to the polarity control signal POL. The voltage is converted into a voltage and supplied to the data lines DL in response to the source output enable signal SOE.

FIG. 2 is a diagram illustrating wirings between the timing controller TCON and the source drive ICs SDIC # 1 to SDIC # 8.

Referring to FIG. 2, a data wiring pair DATA & CLK, a control wiring pair SCL / SDA, a lock check wiring LCS, and the like are disposed between the timing controller TCON and the source drive ICs SDIC # 1 to SDIC # 8. Wirings are formed.

The timing controller TCON sequentially transmits the preamble signal, the source control packet, and the RGB data packet to the source drive ICs SDIC # 1 to SDIC # 8 through the data line pair DATA & CLK. The source control packet is a bit stream including clock bits, polarity control related control data bits, and source output related control data. The RGB data packet is a bit stream including clock bits, internal data enable bits, RGB data bits, and the like. The data line pair DATA & CLK connects the timing controller TCON to each of the source drive ICs SDIC # 1 to SDIC # 8 in a 1: 1, point-to-point manner. Each of the source drive ICs SDIC # 1 to SDIC # 8 restores clocks input through the data line pair DATA & CLK. Therefore, no wiring is required between the neighboring source drive ICs SDIC # 1 to SDIC # 8 to transfer the clock carry and the RGB data.

The timing controller TCON controls chip individual codes for controlling the functions of the chip identification codes CID of the source drive ICs SDIC # 1 to SDIC # 8 and the functions of the source drive ICs SDIC # 1 to SDIC # 8. The data is transferred to the source drive ICs SDIC # 1 to SDIC # 8 through the control wiring pair SCL / SDA. The control wiring pair SCL / SDA is commonly connected between the timing controller TCON and the source drive ICs SDIC # 1 to SDIC # 8. Detailed description of the chip individual control data will be described later. If the source drive ICs SDIC # 1 to SDIC # 8 are separated into two groups and connected to the two source PCBs PCB1 and PCB2 as shown in FIG. 8, the first control wiring pair SCL / SDA1 is a timing controller. A parallel connection between the TCON and the first to fourth source drive ICs SDIC # 1 to SDIC # 4, and the second control wiring pair SCL / SDA2 is connected to the timing controller TCON and the fifth to eighth. It is connected in parallel between the source drive ICs (SDIC # 5 to SDIC # 8).

The timing controller TCON supplies a lock signal LOCK for checking whether the clock separation of the source drive ICs SDIC # 1 to SDIC # 8 and the data sampling unit output are stably fixed. Supply to the first source drive IC (SDIC # 1) through. The source drive ICs SDIC # 1 to SDIC # 8 are connected in a cascade through a wiring for transmitting a lock signal LOCK. When the frequency and phase of the clock output for data sampling are fixed, the first source drive IC SDIC # 1 transmits a high logic lock signal to the second source drive IC SDIC # 2, and the second source. The drive IC SDIC # 2 transmits a high logic lock signal Lock to the third source drive IC SDIC # 3 after fixing the frequency and phase of the output clock. When the clock output frequency and the phase of the source drive ICs SDIC # 1 to SDIC # 8 are fixed, and the clock output frequency and the phase of the last source drive IC SDIC # 8 are fixed, the last source drive IC SDIC # 8) feedbacks the high logic lock signal Lock to the timing controller TCON through the feedback lock check line LCS2. The timing controller TCON transmits the source control packet and the RGB data packet to the source drive ICs SDIC # 1 to SDIC # 8 after receiving the feedback input of the lock signal Lock.

3 is a block diagram showing an internal configuration of the source drive ICs SDIC # 1 to SDIC # 8.

Referring to FIG. 3, each of the source drive ICs SDIC # 1 to SDIC # 8 has positive / negative analog video data in k (k is a positive integer less than m) data lines D1 to Dk. Supply the voltages. Each of the source drive ICs SDIC # 1 to SDIC # 8 includes a clock separation and data sampling unit 21, a DAC 22, an output circuit 23, and the like.

The clock separation and data sampling unit 21 fixes the phase and frequency of the output according to the preamble signal input at a low frequency through the data line pair DATA & CLK in the first step Phase1. Subsequently, the clock separation and data sampling unit 21 restores the reference clock from the source control packet input to the bit stream through the data line pair DATA & CLK in the second step Phase2, and separates the control data related to the polarity control. The polarity control signal POL is restored based on the polarity control related control data, the source output related control data is separated from the source control packet, and the source output enable signal SOE is restored based on the source output related data.

The clock separating and data sampling unit 21 separates the clock from the RGB data packet input through the data line pair DATA & CLK in the third step Phase3, restores the reference clock, and restores the RGB digital video data according to the reference clock. Generate serial clock signals for sampling each bit. To this end, the clock separation and data sampling unit 21 may output a clock with a stable phase and frequency (Phase locked loop, hereinafter referred to as "PLL"), and a delay locked loop (DLL). And the like. 7 and 9 illustrate an example in which the clock separation and data sampling unit 21 is implemented using a PLL. The clock separation and data sampling unit 21 is not limited to the PLL but may be implemented as the above-described DLL.

In addition, the clock separation and data sampling unit 21 samples and latches each of the bits of the RGB data serially inputted through the data line pair DATA & CLK according to the serial clock, and then simultaneously outputs the latched data to output the serial transmission data. Convert the scheme to a parallel transmission data scheme.

The DAC 22 converts the RGB digital video data from the clock separation and data sampling unit 21 into the positive gamma compensation voltage GH or the negative gamma compensation voltage GL in response to the polarity control signal POL. Convert to positive / negative analog video data voltage. To this end, the DAC 22 is a P-decoder (PDEC) 41 supplied with the positive gamma reference voltage GH and an N-decoder (NDEC) supplied with the negative gamma reference voltage GL as shown in FIG. 4. (42), a multiplexer 43 for selecting the output of the P-decoder 41 and the output of the N-decoder 42 in response to the polarity control signal POL. The P-decoder 41 decodes RGB digital video data input from the clock separation and data sampling unit 21, outputs a positive gamma compensation voltage GH corresponding to the gray level of the data, and outputs an N-decoder ( 42 decodes the RGB digital video data input from the clock separation and data sampling unit 21 and outputs a negative gamma compensation voltage GL corresponding to the gray scale value of the data. The multiplexer 43 alternately selects the positive gamma compensation voltage GH and the negative gamma compensation voltage GL in response to the polarity control signal POL, and selects the selected positive / negative gamma compensation voltage as positive / negative. Polarity Output as analog video data voltage.

The output circuit 23 supplies the charge share voltage or the common voltage Vcom to the data lines D1 to Dk through the output buffer during the high logic period of the source output enable signal SOE. In addition, the output circuit 23 supplies the positive / negative analog video day voltage to the data lines D1 to Dk through the output buffer during the low logic period of the source output enable signal SOE. The charge share voltage is generated when the data line to which the positive voltage is supplied and the data line to which the negative voltage is supplied are shorted, and have an average voltage level of the positive voltage and the negative voltage.

FIG. 5 is a block diagram illustrating an internal configuration of gate drive ICs GDIC # 1 to GDIC # 4.

Referring to FIG. 5, each of the gate drive ICs GDIC # 1 to GDIC # 4 may include a plurality of gate resistor ICs connected between the shift register 50, the level shifter 52, the shift register 50, and the level shifter 52. An AND gate (hereinafter referred to as an "AND gate") 51 and an inverter 53 for inverting the gate output enable signal GOE are provided.

The shift register 50 sequentially shifts the gate start pulse GSP according to the gate shift clock GSC using a plurality of D-flip flops connected in a cascade manner. Each of the AND gates 51 generates an output by ANDing the output signal of the shift register 50 and the inverted signal of the gate output enable signal GOE. The inverter 53 inverts the gate output enable signal GOE and supplies it to the AND gates 51. Therefore, the gate drive ICs GDIC # 1 to GDIC # 4 output gate pulses when the gate output enable signal GOE is in a low logic period.

The level shifter 52 shifts the output voltage swing width of the AND gate 51 to a swing width capable of operating TFTs formed in the pixel array of the liquid crystal display panel 10. The output signal of the level shifter 52 is sequentially supplied to the gate lines G1 to Gk.

The shift register 50 may be formed directly on the glass substrate of the liquid crystal display panel 10 together with the TFTs of the pixel array. In this case, the level shifter 52 may not be formed on the glass substrate but may be formed on the control board or the source PCB together with the timing controller TCON, the gamma voltage generation circuit, and the like.

6 is a flowchart illustrating a signal transmission process between the timing controller TCON and the source drive ICs SDIC # 1 to SDIC # 8.

Referring to FIG. 6, when power is applied to the liquid crystal display, the timing controller TCON transmits the first stage signals Phase 1 signals through the data line pair DATA & CLK to the source drive ICs SDIC # 1 to SDIC #. (S1 and S2) The first stage signals include a low frequency preamble signal and a lock signal Lock supplied to the first source drive IC SDIC # 1.

The clock separation and data sampling unit 21 of the first source drive ICs SDIC # 1 restores the preamble signal to the PLL reference clock, and locks a high logic when the phase of the PLL reference clock output and the PLL output are fixed. The signal Lock is transmitted to the second source drive ICs SDIC # 2. Subsequently, when the clock separation and the data sampling unit outputs of the second to eighth source drive ICs SDIC # 2 to SDIC # 8 are sequentially and stably fixed, the eighth source drive IC SDIC # 8 is a high logic lock. Feedback is inputted to the timing controller (TCON) (S3 to S7).

When the lock signal is input in high logic from the eighth source drive IC SDIC # 8, the timing controller TCON stabilizes clock separation and output of the data sampling part of all the source drive ICs SDIC # 1 to SDIC # 8. It is determined that it is locked so that the second stage signals (Phase 2 signals) are supplied to the source drive ICs SDIC # 1 to SDIC # 8 in a point-to-point manner through the data line pair DATA & CLK. Phase 2 signals include a plurality of source control packets including polarity control related control data bits and source output related control data bits.

The timing controller TCON supplies the phase drive signals Phase 3 signals to the source drive ICs SDIC # 1 to SDIC # 8 in a point-to-point manner after the phase 2 signals. The third phase signal includes a plurality of RGB data packets to be charged in liquid crystal cells of one line of the liquid crystal display panel for one horizontal period.

The clock separation of the source drive ICs SDIC # 1 to SDIC # 8 and the PLL output of the data sampling unit 21 are unlocked, that is, the phase of the PLL output during the second or third phase signal transmission process. The frequency may shake. In this case, when the logic of the feedback lock signal is inverted to low logic, the timing controller TCON determines that the PLL output of the source drive ICs SDIC # 1 to SDIC # 8 is unlocked, and thus the first stage signal is driven. After retransmitting the ICs SDIC # 1 to SDIC # 8 to lock the PLL outputs of the source drive ICs SDIC # 1 to SDIC # 8, the second and third phase signal transmissions are resumed. (S9 and S11 )

FIG. 7 is a block diagram illustrating in detail the clock separation and data sampling unit 21 of the source drive ICs SDIC # 1 to SDIC # 8.

Referring to FIG. 7, the clock separation and data sampling unit 21 includes an ODT (On die Terminator or less, “ODT”) 61, an analog delay replica or less (“ADR”) ( 62), Clock Separator (63), PLL (64), PLL Lock Detector (65), Tunable Analog Delay (66), Deserializer (67), Digital Filter (68), Phase Detector (69), Lock Detector (70), I ² C Controller (71), Power Reset (Power-On) Reset hereinafter, " POR "

The ODT unit 61 has a built-in termination resistor to remove signal mixed in the preamble signal, the source control packet, and the RGB data packet input through the data line pair DATA & CLK to improve signal integrity. In addition, the ODT unit 61 incorporates a reception buffer and an equalizer (RX Buffer & Equation) to amplify the input differential signal and convert it into digital data. The ADR 62 delays the RGB data and the clock from the ODT unit 61 by the delay value of the tunable analog delay 66 to equalize the delay value between the clock path and the data path. .

The clock separator 63 separates the clock bits inserted into the source control packet and the RGB data packet restored by the ODT unit 61 and restores them to the reference clock of the PLL 64. The clock bits include a clock, a dummy clock, internal data enable bits, and the like. PLL 64 generates clocks for sampling the data bits of the source control packet and the RGB data packet. If the RGB data packet contains 10 bits of RGB bits each and 4 bits of clock bits are allocated with the RGB bits in between, the PLL 64 outputs 34 clocks per 1 RGB data packet. The PLL lock detector 65 monitors the output phase and frequency of the PLL 64 in accordance with a predetermined input data rate and detects whether the PLL output clock is locked.

The tunable analog delay 66 is provided between the RGB data input from the ODT unit 61 and the feedback clocks fed back through the phase detector 69 and the digital filter 68 so that data can be sampled at the center of the clock. Compensate for minute phase differences. The serial-to-parallel converter 67 incorporates flip-flops to sample and latch bits of RGB digital video data input in series in accordance with the serial clocks output from the PLL 64, and simultaneously converts the bits of the RGB digital video data into parallel data.

The digital filter 68 and the phase detector 69 receive the sampled RGB digital video data and determine a delay value of the tunable analog delay 66. The lock detection unit 70 compares the RGB parallel data restored by the serial-to-parallel conversion unit 67 with the output PLL_LOCK of the PLL lock detection unit 65 to check the error amount of the data enable clock of the RGB parallel data. If the amount of errors in the clocks is above a certain level, the output of the PLL 64 is unlocked to operate the entire physical interface (PHY) circuit again. The lock detector 70 generates a low logic output when the PLL output is unlocked, while generating a high logic output when the PLL output is locked. The AND gate 73 is a lock signal input from the timing controller TCON or a lock signal transmitted from the front source drive ICs SDIC # 1 to SDIC # 7 and the lock detector 70. Outputs a high logic lock signal when both signals are high logic. The high logic lock signal is transmitted to the next source drive ICs (SDIC # 2 to SDIC # 8), and the last source drive IC (SDIC # 8) transmits a lock signal (Lock Out) to the timing controller (TCON). Enter your feedback.

The POR 72 generates a reset signal for resetting the clock separation and data sampling unit 21 according to a preset power sequence, generates a clock signal of approximately 50 MHz, and recalls the clock signal. Supply digital circuits, including one circuits.

The I ² C controller 71 controls the operation of each of the above circuit blocks by using the chip identification code CID and the chip individual control data inputted as serial data through the control wiring pair SCL / SDA. Chip identification code (CID) is a different logic value (HH) to the source drive ICs (SDIC # 1 ~ SDIC # 8) as shown in Figure 8 so that the source drive ICs (SDIC # 1 ~ SDIC # 8) can be individually controlled , LL). The I ² C controller 71 controls the PLL power down and the buffer power of the ODT unit 61 according to the chip individual control data inputted through the timing controller TCON and the serial data bus SDA of the control wiring pair. Down, EQ On / Off function of ODT section 61, charge bump current value adjustment of PLL 64, VCO range manual selection adjustment of PLL 64, I ² C PLL lock signal push through communication, analog delay control value adjustment, disable of lock detection unit 70, coefficient change of digital filter 68, digital filter coefficient change function, PHY (physical interface) through I ² C ) RESETB signal push, function to replace the lock signal of the leading source drive ICs (SDIC # 1 to SDIC # 7) with the reset signal of the current source drive ICs (SDIC # 1 to SDIC # 8), and the vertical resolution of the input image. You can control functions such as setting the (Vertical Resolution) value and saving the history of the data enable clock transition (DE transition) for analyzing the cause of PHY RESET occurrence.

The SOE & POL recovery unit 74 samples the polarity control-related control data included in the source control packet from the ODT unit 61 according to the PLL output clock to generate the polarity control signal POL as high logic (or low logic). i (i is a natural number) Reverses the logic in units of horizontal periods. The SOE & POL reconstruction unit 74 samples the source output related control data included in the source control packet from the ODT unit 61 according to the PLL output clock and then sources the source output related control data according to the source output related control data as shown in FIGS. 16 to 18C. Generate an output enable signal SOE and adjust the pulse width of its source output enable signal SOE.

9 is a block diagram showing the PLL 64 in detail.

Referring to FIG. 9, the PLL 64 may include a phase comparator 92, a charge pump 93, a loop filter 94, a pulse-to-voltage converter 95, and a voltage controlled oscillator (VCO) 96. And a digital controller 97.

The phase comparator 92 controls the reference edge refclk input from the clock separator 63 and the feedback edge clock fbclk from the clock separator replica (hereinafter referred to as "CSR") 91. Compare the phases. As a result of the comparison, the phase comparator 92 has a pulse width equal to the difference between the reference clock refclk and the feedback edge clock EG [0], and outputs a positive pulse when the reference clock is faster than the feedback edge clock. On the other hand, when the feedback edge clock is later than the reference clock, a negative pulse is output.

The charge pump 93 supplies the amount of charge supplied to the loop filter 94 differently according to the output pulse width and polarity of the phase comparator 92. The loop filter 94 accumulates or discharges the charges according to the charge amount of the charge pump 93 and removes high frequency noise including harmonic components from the clock input to the pulse-voltage converter 95.

The pulse-voltage converter 95 converts a pulse input from the loop filter 94 into a control voltage of the VCO 96 and according to the pulse width and the sign of the pulse input from the loop filter 94. Adjust the control voltage level (96). The VCO 96 generates 34 edge clocks and 34 center clocks per one source control data packet / RGB data packet when the bit stream of one RGB data packet includes 10 bits of RGB bits and four clock bits, respectively. The phase delay amount of the clocks is adjusted according to the control voltage from the pulse-voltage converter 95 and the control data from the digital controller 97.

The first edge clock EG [0] output from the VCO 96 is input to the clock separator replica 91 as a feedback edge clock. The feedback edge clock EG [0] is generated at a frequency divided by 1/34 of the output frequency of the VCO 96. The digital controller 97 receives the reference clock refclk and the feedback edge clock fbclk from the clock separator 63 and compares the phase difference between the clocks. The digital controller 97 also compares the phase difference with the 50 MHz clock signal from the POR 72. The phase difference of (clk_osc) is compared. The digital controller 97 selects the oscillation region of the VCO 96 by adjusting the output delay amount of the VCO 96 according to the comparison result of the phase difference of the clocks.

FIG. 10 is a waveform diagram illustrating first step signals generated from the timing controller TCON.

Referring to FIG. 10, the timing controller TCON generates a lock signal Lock and a low frequency preamble signal in a first step Phase1. A preamble signal is a signal in which a plurality of low logic bits are contiguous after a plurality of high logic bits are contiguous and has a low frequency. The frequency of the preamble signal is 1/34 of the PLL output clock frequency of the clock separation and data sampling section 21 when the bit stream of the 1 RGB data packet includes 10 bits of RGB bits and 4 clock bits, respectively. It is frequency divided by. The clock separator 63 of the clock separator and the data sampling unit 21 transitions the reference clock refclk to a high logic in synchronization with the high logic bit of the preamble signal, and provides a low logic of the preamble signal pre logic. The reference clock refclk is transitioned to a low logic bit.

The clock separation and data sampling unit 21 of each of the source drive ICs SDIC # 1 to SDIC # 8 outputs the phase of the feedback edge clock and the reference clock refclk generated according to the preamble signal. If the lock operation is repeated and the output is stably locked, the lock signal Lock is transmitted to the next source drive ICs SDIC # 1 to SDIC # 8.

In the initial power-on stage of the LCD, the timing controller TCON receives the lock signal input from the last source drive IC DIS # 8 to perform clock separation and output locking of the data sampling unit 21. After checking, the second stage signals are output within the blanking period of the vertical synchronization signal Vsync.

FIG. 11 is a waveform diagram illustrating second stage signals generated from the timing controller TCON.

Referring to FIG. 11, the timing controller TCON includes a plurality of front dummy source control packets Cf during a blanking period without data within one period (1 horizontal period) of the horizontal synchronization signal Hsync in a second step. The source control packets Cf, Cr, Cb, and Cl are sourced through the data line pair DATA & CLK in order of one or more real source control packets Cr and a plurality of back dummy source control packets Cb and Cl. It transfers to the drive ICs (SDIC # 1 to SDIC # 8).

The front dummy source control packets Cf are source drive ICs SDIC # 1 to SDIC # prior to the real source control packet Cr for the clock separation and the stable real source control packet reception operation of the data sampling unit 21. 8) are sent continuously. The real source control packet Cr includes polarity control-related control data bits and source output-related control data bits for controlling the polarity inversion operation and data output of the source drive ICs SDIC # 1 to SDIC # 8. The plurality of back dummy source control packets Cb and Cl may be configured to secure the real source control packet reception verification process of the clock separation and data sampling unit 21 and to perform stable reception of the third stage signal. After Cr), it is sequentially transmitted to the source drive ICs (SDIC # 1 to SDIC # 8). The last dummy source control packet Cl of the back dummy source control packets Cb and Cl is then assigned a bit value indicating that phase 3 signals are to be transmitted. Since the source drive ICs SDIC # 1 to SDIC # 8 read the bit value of the last dummy source control packet C1 and know in advance that the RGB data packet is input thereafter, the RGB data sampling operation can be stably performed. Can be.

The front dummy source control packets Cf, the real source control packet Cr, and the back dummy source control packets Cb and Cl may be divided into values of specific bits as shown in the table of FIG. 15. Accordingly, the SOE & POL recovery unit 74 of the clock separation and data sampling unit 21 divides the source control packets Cf, Cr, Cb, and Cl into bit values at specific positions, thereby polarizing the real source control packet Cr. Control-related control data and source output-related control data can be identified.

The clock separation and data sampling unit 21 of the source drive ICs SDIC # 1 to SDIC # 8 separates the clocks from the source control packet to restore the reference clock, and compares the phase of the reference clock with a high frequency output clock. Outputs serial clocks for sampling each bit of control data related to polarity control and control data related to source output. The clock separation and data sampling unit 21 generates the polarity control signal POL according to the sampled polarity control data and generates the source output enable signal SOE according to the source output control data.

As shown in FIG. 11, an RGB data packet may be transmitted following a plurality of source control packets Cf, Cr, Cb, and Cl within one horizontal period, and then a plurality of source control packets may be further transmitted after the RGB data packet. . Source control packets transmitted following the RGB data packet may include one or more real source control packets and a plurality of dummy source control packets, which affect the next horizontal period of RGB data packets.

12 and 13 are waveform diagrams illustrating third stage signals generated from the timing controller TCON.

12 and 13, the timing controller TCON includes a plurality of RGB data packets to be displayed on a third stage signal, that is, one line of the liquid crystal display, within one horizontal period following the second stage signal. The data is transferred to the source drive ICs SDIC # 1 to SDIC # 8 through (DATA & CLK).

The clock separation and data sampling unit 21 separates the clock CLK and the data enable clock CLK from the RGB data packet, restores the reference clock, and compares the phase of the reference clock with the high frequency output clocks. Output serial clocks for sampling each bit of video data. When the bit stream of one RGB data packet includes 10 bits of RGB bits and four clock bits, respectively, a low logic dummy clock bit (DUM) and a high logic clock bit ( CLK) is allocated, and after the head area, R1 to R10 and G1 to G5 bits corresponding to the first half of the RGB data are allocated, and then the logic of the low logic dummy data enable clock (DE DUM) and the high logic are inverted from each other. An internal data enable clock bit DE is assigned. After the internal data enable clock bit DE, bits G6 to G10 and B1 to G10 corresponding to the second half of the RGB data are allocated. The clock separation and data sampling unit 21 detects the clock CLK and the internal data enable clock DE, and then may determine the data serially input thereto as RGB digital video data, and determine the data to the sampling clock. Sampling accordingly.

The bit values of the dummy data enable clock and the data enable clock positions in the first and second stage signals are different from the dummy data enable clock DE DUM and the data enable clock DE allocated to the third stage signal. Therefore, the clock separation and data sampling unit 21 reads the bit values of the dummy data enable clock DE DUM and the data enable clock DE, and does not sample the RGB data from the first and second stage signals. Only RGB data packets of the step signal are sampled.

The clock separator 63 of the clock separator and the data sampling unit 21 generates a reference clock refclk in which a rising edge is synchronized with the clock CLK and the internal data enable clock DE. Since the reference clock refclk is transitioned once more from the internal data enable clock DE, the frequency is twice as high as that of the reference clock REF restored in the first and second stages. As the reference clock frequency of the clock separation and data sampling unit 21 increases, the number of stages in the VCO of the PLL 64 may be reduced, and thus the output of the PLL 64 may be further stabilized. In detail, when the PLL's reference clock frequency is doubled by transitioning the PLL's reference clock refclk at an intermediate point of the RGB data packet in the internal data enable signal DE, the number of VCO stages in the PLL 64 is increased. It can be reduced to 1/2. 34 VCO stages are required if the reference clock (refclk) is not used as the transition clock in the internal data enable clock (DE), while only 17 VCO stages are required when the internal data enable clock (DE) is used as the transition clock. Do. As the number of VCO stages in the PLL 64 increases, the effects on process, voltage, and temperature (PVT) variations are multiplied by the number of stages, increasing the likelihood that the PLL lock will be unlocked for these external variations. Accordingly, the present invention can increase the PLL locking reliability by increasing the frequency of the reference clock (refclk) of the PLL by using the internal data enable clock DE as a transition clock in addition to the clock CLK.

The RGB data packet and the source control packets Cf, Cr, Cb, and Cl may be distinguished by setting predetermined bits differently. FIG. 14 is a data mapping table of source control packets Cf, Cr, Cb, and Cl generated in a second step and RGB data packets generated in a third step. The data table of the RGB data packet and the source control packet is not limited to FIG. 14 but may be variously modified based on the data table of FIG. 14.

Referring to FIG. 14, if each of the RGB data is 10 bits of data, the RGB data packet includes a total of 34 bits. When describing the RGB data packet in detail, the RGB data packet includes a clock of 1 bit, R data [0: 9] of 10 bits, G data [0: 4] of 5 bits, and a dummy data enable of 1 bit (DE DUM). , 1 bit data enable (DE), 5 bits of G data [5: 9], and 10 bits of B data [0: 9]. The source control packets Cf, Cr, and Cb include the same data length, that is, 34 bits, as the RGB data packet. The source control packets Cf, Cr, and Cb will be described in detail. The first bit of 15 bits, the first half of the control data and the first bit of data, instead of the R data [0: 9] and G data [0: 4] Data enable (DE DUM), 1 bit of data enable (DE), G data [5: 9] and B data [0: 9], the latter half of 15 bits control data. The RGB data packet and the source control packets Cf, Cr, and Cb may be distinguished by different bit values of the dummy data enable DE DUM and the data enable DE.

The dummy source control packets Cf, Cb, and Cl and the real source control packet Cr may be divided into predetermined bits determined in the first half control data and the second half control data of FIG. 14. FIG. 15 is a data table example of source control packets, and is not limited thereto, and may be variously modified based on the data table of FIG. 15.

15 is a data mapping table of source control packets Cf, Cr, Cb, Cl.

Referring to FIG. 15, high logic (H), low logic (L), low logic (L), and low logic (L) are included in 4 bits of C0 to C3 in the dummy source control packets Cf, Cb, and Cl. Is assigned. In contrast, high logic (H), high logic (H), high logic (H), and low logic (L) are allocated to 4 bits of C0 to C3 in the real source control packet Cr. Accordingly, the dummy source control packets Cf, Cb, and Cl and the real source control packet Cr may be divided into bits of C1 and C2.

The last dummy source control packet Cl indicating the transmission of the RGB data packet among the dummy source control packets Cf, Cb, and Cl is 2 bits of C16 to C17 to be distinguished from other dummy source control packets Cf and Cb. Can be. The clock separation and data sampling unit 21 of the source drive ICs SDIC # 1 to SDIC # 8 reads C16 to C17 of the last dummy source control packet C1 to be input after the last dummy source control packet Cl. The reception of an RGB data packet can be predicted. In detail, each of the dummy source control packets Cf and Cb, the real source control packet Cr, and the last dummy source control packet Cl includes the first and second identification information C1 to C2, as described above. C16 to C17) are encoded. Logical values of the first identification information C1 to C2 encoded in the real source control packet Cr may include first identification information C1 of each of the dummy source control packets Cf and Cb and the last dummy source control packet Cl. It is set differently from the logical value of ~ C2). The logic value of the second identification information C16 to C17 encoded in the last dummy source control packet Cl is the logic of the second identification information of each of the dummy source control packets Cf and Cb and the real source control packet Cr. It is set differently from the value. Each of the source drive ICs SDIC # 1 to SDIC # 8 may determine the authenticity of the real source control packet Cr according to a logic value of the first identification information C1 to C2, and determine the second identification information ( The reception of the RGB data packet can be predicted according to the logic values of C16 to C17).

16 is a data mapping table of the real source control packet Cr. FIG. 17 is a waveform diagram illustrating a source output enable signal SOE controlled according to C1 to C2 bits and a polarity control signal POL controlled according to C13 to C14 in the real source control packet Cr as shown in FIG. 16. to be.

16 and 17, the real source control packet Cr includes 'SOE' of C1 to C2 bits and includes 'POL' of C13 to 14 bits.

The SOE & POL reconstruction unit 74 generates the source output enable signal SOE in high logic when the C1 to C2 bits of the real source control packet Cr are detected as the first logic value H / H, Maintain the logic of the source output enable signal SOE at high logic, and then read the C1 to C2 bits of another real source control packet Cr if the C1 to C2 bits are the second logic value (H / L). Inverts the output enable signal SOE to low logic. Therefore, the pulse width of the source output enable signal SOE may be automatically adjusted according to the logic values of C1 to C2 of the real source control packets Cr. The pulse width of the source output enable signal SOE may be adjusted in units of a source control packet length as shown in FIGS. 18A to 18C.

In the example of FIG. 18A, the first real source control packet Cr includes rising time information HH of the source output enable signal SOE in C1 to C2, and the fourth real source control packet Cr includes C1. C2 may include polling time information HL of the source output enable signal SOE. The SOE & POL recovery unit 74 generates the source output enable signal SOE in high logic from the first recovery clock SCLK # 1 and generates the source output enable signal SOE up to the fourth recovery clock SCLK # 4. After maintaining the high logic, the source output enable signal SOE is inverted to low logic when the polling time information HL is detected by the fourth recovery clock SCLK # 4. Accordingly, the SOE & POL reconstruction unit 74 can reconstruct the source output enable signal having a pulse width equal to the length of the 4x source control / RGB data packet.

In the example of FIG. 18B, the first real source control packet Cr includes rising time information HH of the source output enable signal SOE in C1 to C2, and the eighth real source control packet Cr includes C1. C2 may include polling time information HL of the source output enable signal SOE. The SOE & POL recovery unit 74 generates the source output enable signal SOE in high logic from the first recovery clock SCLK # 1 to generate the source output enable signal SOE up to the eighth recovery clock SCLK # 8. After maintaining the high logic, the source output enable signal SOE is inverted to low logic when the polling time information HL is detected by the eighth recovery clock SCLK # 8. Accordingly, the SOE & POL reconstruction unit 74 may reconstruct the source output enable signal having a pulse width equal to 8 × source control / RGB data packet length.

In the example of FIG. 18C, the first real source control packet Cr includes rising time information HH of the source output enable signal SOE in C1 to C2, and the first real source control packet Cr includes C1 in the twelfth real source control packet Cr. C2 may include polling time information HL of the source output enable signal SOE. The SOE & POL recovery unit 74 generates the source output enable signal SOE in high logic from the first recovery clock SCLK # 1 and generates the source output enable signal SOE up to the twelfth recovery clock SCLK # 12. After maintaining the high logic, the source output enable signal SOE is inverted to low logic when the polling time information HL is detected by the twelfth recovery clock SCLK # 12. Therefore, the SOE & POL reconstruction unit 74 can reconstruct the source output enable signal having a pulse width equal to 12 × source control / RGB data packet length.

The SOE & POL reconstruction unit 74 detects the C13 to C14 bits of the real source control packet Cr to generate the polarity control signal POL, and maintains the polarity control signal POL in the same logic for i horizontal periods and then inverts it. Let's do it. For example, the SOE & POL restoring unit 74 detects the C13 to C14 bits of the real source control packet Cr to generate the polarity control signal POL, and sets the polarity control signal POL high for one horizontal period or two horizontal periods. You can keep it in logic and then in low logic and invert the logic in units of one horizontal period or two horizontal periods.

19 is a waveform diagram showing the output of the clock separation and data sampling section 21 when each of the R data, the G data, and the B data is 10 bits of data.

The liquid crystal display and the driving method thereof according to an exemplary embodiment of the present invention are not limited to the source control / RGB data packet as shown in FIGS. 10 to 16, but control / RGB data according to the number of bits of the input image as shown in FIGS. 20A to 20D. The length of the packet can be different.

When each of the R data, the G data, and the B data is 10 bits of data, the timing controller TCON sets one control / RGB data packet to DUM, CLK, R1 to R10, G1 to G5, and DE for a time T as shown in FIG. 20A. Occurs as a bit stream containing DUM, DE, G6 to G10, and B1 to B10. The clock separation and data sampling unit 21 generates 34 edge clocks and 34 center clocks in one control / RGB data packet input from the timing controller TCON, and controls data / RGB data according to the center clocks. Sample the bits.

When each of the R data, the G data, and the B data is 8 bits of data, the timing controller TCON sets one control / RGB data packet to DUM, CLK, R1 to R8 for T × (28/34) time as shown in FIG. 20B. Occurs as a bit stream including G1 to G4, DE DUM, DE, G5 to G8, and B1 to B8. The clock separation and data sampling unit 21 generates 28 edge clocks and 28 center clocks in one control / RGB data packet input from the timing controller TCON, and controls data / RGB data according to the center clocks. Sample the bits.

When each of the R data, the G data, and the B data is 6 bits of data, the timing controller TCON sets one control / RGB data packet to DUM, CLK, R1 to R6 during T × (22/34) time as shown in FIG. 20C. Occurs as a bit stream containing G1 to G3, DE DUM, DE, G4 to G6, and B1 to B6. The clock separation and data sampling unit 21 generates 22 edge clocks and 22 center clocks in one control / RGB data packet input from the timing controller TCON, and controls data / RGB data according to the center clocks. Sample the bits.

When each of the R data, the G data, and the B data is 12 bits of data, the timing controller TCON sets one control / RGB data packet to DUM, CLK, R1 to R12 for T × (40/34) time as shown in FIG. 20D. Occurs as a bit stream including G1 to G6, DE DUM, DE, G7 to G12, and B1 to B12. The clock separation and data sampling unit 21 generates 40 edge clocks and 40 center clocks in one control / RGB data packet input from the timing controller TCON, and controls data / RGB data according to the center clocks. Sample the bits.

The timing controller TCON may automatically switch the length of the control / RGB data packet as shown in FIGS. 20A through 20D by determining the number of bits of the input data.

The liquid crystal display according to another exemplary embodiment of the present invention generates the first stage signals as a preamble signal including a plurality of pulse groups having different pulse widths and periods, thereby outputting the PLL of the clock separation and data sampling unit 21. The phase and frequency of the clock can be locked more reliably.

21 and 22 are waveform diagrams showing a first stage signal according to another embodiment of the present invention.

21 and 22, the first step signal includes a phase 1-1 signal and a phase 1-2 signal. The phase 1-1 signal is a signal whose one period is set to the same time as one control / RGB data packet, similarly to the above-described preamble signal. The phase 1-2 signal is higher in frequency than the phase 1-1 signal and is generated at a frequency less than 1/2 of the phase 1-1 signal. The phase 1-2 signal may be generated in the form of alternating two pulse groups P1 and P2 having different phases and frequencies. The first pulse group P1 is at least two times higher than the frequency of the pulse train generated by the phase 1-1 signal, and the second pulse group P2 is at least two times higher than the frequency of the first pulse group P1. The PLL 64 of the clock separation and data sampling unit 21 tracks pulses whose frequency is faster than the phases 1-1 and regularly change phases as shown in Figs. 21 and 22, while the low frequency regular preambles as shown in Fig. 10 are tracked. You can lock the phase and frequency of the output faster and more steadily than the signal.

The source drive ICs (SDIC # 1 to SDIC # 8) offer various options for the LCD module maker (consumer) to adjust the detailed operation as the needs of the LCD module maker diversify. To this end, in the prior art, a plurality of option pins are provided in the source drive ICs SDIC # 1 to SDIC # 8, and the LCD module maker may optionally select the options of the source drive ICs SDIC # 1 to SDIC # 8. The optional operation of the source drive ICs (SDIC # 1 to SDIC # 8) was controlled by connecting a pullup resistor or pulldown resistor to the pins and applying a power supply voltage (Vcc) or a ground voltage (GND). However, providing the option pins in the source drive ICs (SDIC # 1 to SDIC # 8) not only increases the chip size but also the PCB size due to the pull-up / pull-down resistors and wirings connected to the option pins. .

According to another exemplary embodiment of the present invention, a liquid crystal display (LCD) may add source control ICs (SDIC) by adding signals for controlling an operation option of the source drive ICs SDIC # 1 to SDIC # 8 to a portion of the second step. Chip size and PCB size of # 1 ~ SDIC # 8 can be further reduced. To this end, the liquid crystal display of the present invention generates control option information for controlling the source drive IC operation such as PWRC1 / 2, MODE, SOE_EN, PACK_EN, CHMODE, CID1 / 2, H_2DOT, as a separate source control packet. The source control packet including the control option information may be inserted in some sections of the second step and transmitted to the source drive ICs SDIC # 1 to SDIC # 8 through the data wire pair DATA & CLK.

PWRC1 / 2 selects the power capacity of the source drive ICs SDIC # 1 to SDIC # 8 by adjusting the output buffer amplification ratios of the source drive ICs SDIC # 1 to SDIC # 8 as shown in Table 1 below. Optional information.

PWRC1 / 2 = 11 (HH) High Power Mode PWRC1 / 2 = 10 (HL) Normal Power Mode PWRC1 / 2 = 01 (LH) Low power mode PWRC1 / 2 = 00 (LL) Ultra Low Power Mode

MODE is an option to decide whether to enable or disable the charge share voltage output during the high logic period of the source output enable signal SOE as shown in Table 2 below.

MODE = 1 (H) Hi_Z Mode Operation (charge share output disable) MODE = 0 (L) Charge-share mode operation (Charge share output enable

SOE_EN indicates whether the source drive ICs SDIC # 1 to SDIC # 8 are to receive the source output enable signal SOE in embedded form to the RGB digital video data as shown in Table 3 below. Option to decide whether to input through separate wiring.

PACK_EN = 0 (L) PACK_EN = 1 (H) SOE_EN = 0 (L) Forbidden Use internal SOE SOE_EN = 1 (H) Use external SOE

PACK_EN is a gate start pulse that causes the source drive ICs SDIC # 1 to SDIC # 8 to relay the polarity control signal POL and the gate drive ICs GDIC # 1 to GDIC # 4 as shown in Table 4 below. It is an option to decide whether to input GSP) in embedded form to RGB digital video data or through external wiring.

PACK_EN = 1 (H) Enable control packet PACK_EN = 0 (L) Disable control packet (Ignore the value of SOE_EN)

CHMODE is an option to select the number of output channels of the source drive ICs (SDIC # 1 to SDIC # 8) according to the resolution of the LCD as shown in Table 5 below.

CHMODE = 1 (H) 690 Ch. Outputs (691 ~ 720 Ch. Disable) CHMODE = 0 (L) 720 Ch. Outputs

CID1 / 2 is independent of the source drive ICs SDIC # 1 to SDIC # 8 by assigning a unique chip identification code (CID) to each of the source drive ICs SDIC # 1 to SDIC # 8 as shown in Table 6 below. This option allows you to control with. The number of bits of CID1 / 2 may be adjusted according to the number of source drive ICs SDIC # 1 to SDIC # 8. As described above, the source drive ICs SDIC # 1 to SDIC # 8 may be individually controlled through I2C communication through the timing controller TCON and the control wiring pair SCL / SDA. LCD makers may select a method of independently controlling the source drive ICs SDIC # 1 to SDIC # 8 among the two methods.

CID1 / 2 = 00 (LL) Specify SDIC # 1 CID1 / 2 = 01 (LH) Specify SDIC # 2 CID1 / 2 = 10 (HL) Specify SDIC # 3 CID1 / 2 = 11 (HH) Specify SDIC # 4

H_2DOT is an option to control the horizontal polarity period of positive / negative analog video data voltage output from source drive ICs (SDIC # 1 to SDIC # 8) as shown in Table 7 below. For example, when H_2DOT = H, the source drive ICs SDIC # 1 to SDIC # 8 control the polarity of the data voltage in a horizontal 2-dot inversion method. In the horizontal two-dot inversion method, the source drive ICs SDIC # 1 to SDIC # 8 output data voltages having the same polarity to two neighboring data lines, and invert the polarity of the data voltage every two data lines. The polarity of the voltage charged in horizontally neighboring liquid crystal cells is controlled as "-+ + -... +--+ (or +--+ ...-+ +-)". If H_2DOT = L, the source drive ICs SDIC # 1 to SDIC # 8 control the polarity of the data voltage in a horizontal 1-dot inversion manner. In the horizontal 1 dot inversion scheme, the source drive ICs SDIC # 1 to SDIC # 8 invert the polarities of the voltages supplied to the neighboring data lines to change the polarity of the voltage charged in the horizontally adjacent liquid crystal cells. -+-+ ... +-+-(or +-+ -...-+-+) ".

H_2DOT = 1 (H) Horizontal 2-Dot inversion Enable H_2DOT = 0 (L) Horizontal 2-Dot inversion Disable

In the above-described embodiments, the timing controller TCON transfers to the second step only after receiving the high logic feedback lock signal from the last source drive IC SDIC # 8. If none of the source drive ICs SDIC # 1 to SDIC # 8 is locked to the PLL, the timing controller TCON repeatedly generates only the preamble signal of the first phase and the source drive ICs SDIC #. 1 to SDIC # 8) do not output the data voltage. Therefore, when the feed lock lock signal is not input to the timing controller TCON, individual driving states of the source drive ICs SDIC # 1 to SDIC # 8 cannot be confirmed. However, it is necessary to check which source drive IC of the source drive ICs SDIC # 1 to SDIC # 8 is a bad chip and the driving state of each of the source drive ICs SDIC # 1 to SDIC # 8.

According to another exemplary embodiment of the present invention, in order to check the individual driving states of the source drive ICs SDIC # 1 to SDIC # 8 as described above, a liquid crystal display device includes a test mode and a timing controller in the test mode. The feedback lock signal is input to TCON to induce the data voltage output of the source drive ICs SDIC # 1 to SDIC # 8. To this end, the liquid crystal display of the present invention is provided with a selection unit SEL inside or outside the timing controller TCON as shown in FIG.

The first input terminal of the selection unit SEL is connected to the feedback lock check wiring LCS2, and the second input terminal is connected to the input terminal of the test mode enable signal TEST. The selector SEL may be implemented as an OR gate that outputs at least one of a feedback lock signal Lock Out and a test mode enable signal TEST. When the high logic test mode enable signal TEST is input, the selector SEL outputs the high logic test mode enable signal of the timing controller TCON even when the high logic feedback lock signal Lock Out is not input. Input to the data transfer module. Accordingly, even when the TCON is not receiving the real feedback signal in the test mode, the timing controller TCON moves to step S8 in FIG. 6 to transfer the second and third stage signals to the source drive ICs SDIC # 1 to SDIC #. 8) can be sent. At this time, the timing controller TCON codes the test data read from the internal memory in the test mode into RGB data packets of the third stage signal and transmits the test data to the source drive ICs SDIC # 1 to SDIC # 8. The operator may check the image of the test data displayed on the liquid crystal display panel in the test mode to check the individual driving state and defects of the source drive ICs SDIC # 1 to SDIC # 8.

The liquid crystal display is processing a large amount of data at high speed according to the high resolution and large screen tendency of the liquid crystal display panel 10, and the data load for processing simultaneously increases. In this state of high data load, when the data voltages are simultaneously output from the source drive ICs SDIC # 1 to SDIC # 8, electromagnetic interference (EMI) broadband noise increases.

The liquid crystal display according to another embodiment of the present invention controls the output timing between the source drive ICs SDIC # 1 to SDIC # 8 differently in order to reduce EMI broadband noise. To this end, the liquid crystal display of the present invention further comprises a delay circuit for delaying the source output enable signal SOE in the source drive ICs SDIC # 1 to SDIC # 8 as shown in FIG. Is controlled by the chip identification code (CID1 / 2) transmitted through the control wiring pair (SCL / SDA) shown in FIG. This embodiment will be described in detail with reference to FIGS. 24 to 29.

Referring to FIG. 24, when the gate drive ICs GDIC # 1 to GDIC # 4 are disposed outside one side of the liquid crystal display panel 10, the delay time of the gate pulse toward the other side of the liquid crystal display panel 10 is increased. ) Becomes large. In consideration of the delay time of the gate pulse, the data voltage charging amount of all liquid crystal cells in the screen may be uniform only when the output timing of the data voltages output from the source drive ICs SDIC # 1 to SDIC # 8 is properly delayed. To this end, the delay time of the source output enable signal SOE for controlling the output of the first source drive ICs SDIC # 1 is minimal and the output of the eighth source drive ICs SDIC # 8 is controlled. The delay time of the source output enable signal SOE must be relatively large. The delay time of the source output enable signal SOE should increase from the first source drive ICs SDIC # 8 to the eighth source drive ICs SDIC # 8.

The chip identification code CID1 / 2 may be generated as 2 bits data as in the example of FIG. 25. In this case, the chip identification codes CID1 / 2 of the first and second source drive ICs SDIC # 1 and SDIC # 8 are LL, and the third and fourth source drive ICs SDIC # 3. The chip identification code CID1 / 2 of the SDIC # 4 is 'LH', and the chip identification code CID1 / 2 of the fifth and sixth source drive ICs SDIC # 5 and SDIC # 6 is 'HL'. The chip identification codes CID1 / 2 of the seventh and eighth source drive ICs SDIC # 7 and SDIC # 8 may be set to 'LL', respectively. The chip identification code CID1 / 2 and its logical value are not limited to FIG. 25, but are set to different bit numbers and logic values from those of FIG. 25 to individually control the source drive ICs SDIC # 1 to SDIC # 8. Each can be set to a different logical value. For example, when the chip identification code CID1 / 2 is generated with 3 bits, the delay time of each of the source drive ICs SDIC # 1 to SDIC # 8 may be controlled differently.

FIG. 26 is a circuit diagram illustrating a delay circuit embedded in the source drive ICs SDIC # 1 to SDIC # 8.

Referring to FIG. 26, the source drive ICs SDIC # 1 to SDIC # 8 include a multiplexer 261, a plurality of delay circuits ΔD1 to ΔD3, and the like.

The multiplexer 261 includes an input terminal IN to which the source output enable signal SOE is input, a control terminal to which the chip identification code CID1 / 2 is input, and a plurality of output terminals OUT1 to OUT4. The source output enable signal SOE is connected from the timing controller TCON to the source drive ICs SDIC # 1 through the wiring formed separately between the timing controller TCON and the source drive ICs SDIC # 1 to SDIC # 8. Either the external source output enable signal input to SDIC # 8) or the internal source output enable signal recovered in the source drive ICs SDIC # 1 to SDIC # 8 as described above in the above embodiment. . The multiplexer 261 outputs the source output enable signal SOE through one of a plurality of output terminals according to the chip identification code CID1 / 2 as shown in FIG. 25.

The delay circuits ΔD1 to ΔD3 are the first delay circuit ΔD1 and the second output terminal of the multiplexer 261 connected between the first output terminal OUT1 and the second output terminal OUT2 of the multiplexer 261. A second delay circuit ΔD2 connected between OUT2 and a third output terminal OUT3, and a third connected between the third output terminal OUT3 and the fourth output terminal OUT4 of the multiplexer 261. A delay circuit ΔD3. Each of the delay circuits ΔD1 to ΔD3 delays the source output enable signal SOE by a predetermined time by using a delay circuit including a flip-flop or an RC delay circuit. The delay time of each of the delay circuits ΔD1 to ΔD3 may be adjusted to be the same or different. The second output terminal OUT2 of the multiplexer 261 is connected to the output terminal of the first delay circuit ΔD1 of the multiplexer 261 and the input terminal of the second delay circuit ΔD2 via the first node n1. do. The third output terminal OUT3 of the multiplexer 261 is connected to the output terminal of the second delay circuit ΔD2 of the multiplexer 261 and the input terminal of the third delay circuit ΔD3 via the second node n2. do. The fourth output terminal OUT4 of the multiplexer 261 is connected to the output terminal of the source output enable signal, and the source output enable signal SOE output through the output terminal is supplied to the output circuit 23 of FIG. 3. do.

When the chip identification code CID1 / 2 is shown in FIG. 25, the delay circuit of FIG. 26 operates as follows for each source drive IC.

The multiplexer 261 embedded in the first and second source drive ICs SDIC # 1 and SDIC # 2 generates a source output enable signal SOE in response to the chip identification code CID1 / 2 of the LL. The output is performed through the fourth output terminal OUT4. As a result, the source output enable signal SOE for controlling the output timing of the first and second source drive ICs SDIC # 1 and SDIC # 2 is hardly delayed.

The multiplexer 261 embedded in the third and fourth source drive ICs SDIC # 3 and SDIC # 4 generates a source output enable signal SOE in response to the chip identification code CID1 / 2 of 'LH'. Output through the third output terminal (OUT3). As a result, the source output enable signal SOE for controlling the output timing of the third and fourth source drive ICs SDIC # 3 and SDIC # 4 is delayed by ΔD3.

The multiplexer 261 embedded in the fifth and sixth source drive ICs SDIC # 5 and SDIC # 6 receives the source output enable signal SOE in response to the chip identification code CID1 / 2 of 'HL'. Outputs through the second output terminal OUT2. As a result, the source output enable signal SOE for controlling the output timing of the fifth and sixth source drive ICs SDIC # 5 and SDIC # 6 is delayed by ΔD2 + ΔD3.

The multiplexer 261 embedded in the seventh and eighth source drive ICs SDIC # 7 and SDIC # 8 receives the source output enable signal SOE in response to the chip identification code CID1 / 2 of 'HH'. Output through the first output terminal (OUT1). As a result, the source output enable signal SOE for controlling the output timing of the seventh and eighth source drive ICs SDIC # 7 and SDIC # 8 is delayed by ΔD1 + ΔD2 + ΔD3.

In recent years, as the liquid crystal display device becomes larger, the gate line delay length increases as the gate line becomes longer. In order to solve this problem, gate drive ICs GDIC # 1 to GDIC # 4 may be disposed on both sides of the liquid crystal display panel 10 as shown in FIG. 27. The gate drive ICs GDIC # 1 to GDIC # 4 simultaneously apply gate pulses on both sides of the same gate line under the control of the timing controller TCON.

Referring to FIG. 27, when the gate drive ICs GDIC # 1 to GDIC # 4 are disposed at both sides of the liquid crystal display panel 10, the delay time of the gate pulse toward the center of the liquid crystal display panel 10 is increased. Will grow. In consideration of the delay time of the gate pulse, the delay time of the source output enable signal SOE for controlling the output of the first and eighth source drive ICs SDIC # 1 and SDIC # 8 is controlled to a minimum. The delay time of the source output enable signal SOE for controlling the output of the fourth and fifth source drive ICs SDIC # 4 and SDIC # 5 is relatively large.

When the chip identification code CID1 / 2 is generated as in the example of FIG. 28, the operation of the delay circuit built in the source drive ICs SDIC # 1 to SDIC # 8 of the liquid crystal display shown in FIG. Will be described in conjunction with.

Referring to FIG. 29, the multiplexer 291 embedded in the first and eighth source drive ICs SDIC # 1 and SDIC # 8 may output a source output in response to a chip identification code CID1 / 2 of 'LL'. The enable signal SOE is output through the fourth output terminal OUT4. As a result, the source output enable signal SOE for controlling the output timing of the first and eighth source drive ICs SDIC # 1 and SDIC # 8 is hardly delayed.

The multiplexer 291 included in the second and seventh source drive ICs SDIC # 2 and SDIC # 7 generates a source output enable signal SOE in response to the chip identification code CID1 / 2 of 'LH'. Output through the third output terminal (OUT3). As a result, the source output enable signal SOE for controlling the output timing of the second and seventh source drive ICs SDIC # 2 and SDIC # 7 is delayed by ΔD3.

The multiplexer 291 included in the third and sixth source drive ICs SDIC # 3 and SDIC # 6 receives the source output enable signal SOE in response to the chip identification code CID1 / 2 of 'HL'. Outputs through the second output terminal OUT2. As a result, the source output enable signal SOE for controlling the output timing of the third and sixth source drive ICs SDIC # 3 and SDIC # 6 is delayed by ΔD2 + ΔD3.

The multiplexer 291 included in the fourth and fifth source drive ICs SDIC # 4 and SDIC # 5 generates a source output enable signal SOE in response to the chip identification code CID1 / 2 of 'HH'. Output through the first output terminal (OUT1). As a result, the source output enable signal SOE for controlling the output timing of the fourth and fifth source drive ICs SDIC # 4 and SDIC # 5 is delayed by ΔD1 + ΔD2 + ΔD3.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating wirings between the timing controller and the source drive ICs shown in FIG. 1.

3 and 4 are block diagrams showing the internal configuration of the source drive IC shown in FIG.

FIG. 5 is a block diagram illustrating an internal configuration of the gate drive IC shown in FIG. 1.

6 is a flowchart illustrating a signal transmission process between the timing controller and the source drive ICs shown in FIG.

7 is a block diagram illustrating in detail the clock separation and data sampling unit illustrated in FIG. 3.

8 shows an example of a serial communication control path and chip identification code that enables debugging of source drive ICs.

9 is a block diagram showing in detail the PLL shown in FIG.

10 is a waveform diagram illustrating a first stage signal generated by a timing controller.

11 is a waveform diagram illustrating a second stage signal generated by a timing controller.

12 and 13 are waveform diagrams illustrating a third stage signal generated by a timing controller.

14 is a diagram illustrating an example of a data mapping table of a source control packet and an RGB data packet.

15 is a diagram illustrating an example of a mapping table of a dummy source control packet, a real source control packet, and a last dummy source control packet.

16 is a diagram illustrating an example of control data in a real source control packet.

17 is a waveform diagram illustrating a source output enable signal and a polarity control signal controlled by the source output related control data and the polarity control related control data.

18A to 18C illustrate pulse widths of a source output signal adjusted according to source output related control data of a real source control packet.

19 is a waveform diagram showing an output of a clock separation and a data sampling unit.

20A to 20D are cross-sectional views illustrating the length of a data packet when the number of bits of the RGB data packet is changed.

21 and 22 are waveform diagrams showing a first stage signal according to another embodiment of the present invention.

FIG. 23 is a view illustrating a configuration added for a test mode in a liquid crystal display according to embodiments of the present invention.

24 is a diagram illustrating a delay time of a source output enable signal when gate drive ICs are disposed on one side of a liquid crystal display panel according to an exemplary embodiment of the present invention.

25 is a diagram illustrating an example of a chip identification code for controlling the delay time of a source output enable signal as shown in FIG. 24.

FIG. 26 is a circuit diagram illustrating a delay circuit embedded in the source drive ICs shown in FIG. 24.

27 is a diagram illustrating a delay time of a source output enable signal when gate drive ICs are disposed on both sides of a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 28 is a diagram illustrating an example of a chip identification code for controlling a delay time of a source output enable signal as shown in FIG. 27.

FIG. 29 is a circuit diagram illustrating a delay circuit embedded in the source drive ICs shown in FIG. 27.

Description of the Related Art

TCON: Timing Controllers SDIC: Source Drive ICs

GDIC: Gate Drive IC

Claims (7)

A liquid crystal display panel including a plurality of data lines and gate lines crossing the data lines; A timing controller for generating a source output enable signal and a chip identification code; And A plurality of source drives having a delay circuit for delaying the source output enable signal according to the chip identification code and outputting data voltages to be supplied to the data lines in response to the source output enable signal delayed by the delay circuit; And a plurality of ICs. Under 1, The timing controller, A second phase signal including a first stage signal including a preamble signal, the plurality of low logic bits being contiguous after a plurality of high logic bits are contiguous, and at least one source control packet including information of the source output enable signal And sequentially transmitting a third step signal including an RGB data packet to the source drive ICs through a data wire pair, Transmit the chip identification code to the source drive ICs via a control line; And transmitting a lock signal to the source drive ICs through a lock check wiring. Under the second, The source drive ICs, Lock output clocks according to the preamble signal, and feedback the lock signal to the timing controller when the output clock is locked, Generating a polarity control signal and the source output enable signal from the source control packet according to the output clock, And recovering the RGB data from the RGB data packet according to the output clock and converting the restored RGB data into a positive / negative data voltage according to the polarity control signal. The method of claim 1, Each of the source drive ICs, A multiplexer outputting the source output enable signal through any one of first to fourth output terminals according to the chip identification code; A first delay circuit connected between a first output terminal of the multiplexer and a second output terminal of the multiplexer; A second delay circuit connected between an output terminal of the first delay circuit and a third output terminal of the multiplexer; A third delay circuit connected between an output terminal of the second delay circuit and a fourth output terminal of the multiplexer; And An output circuit for outputting the positive / negative data voltage in response to the source output enable signal input from the third delay circuit; The second output terminal of the multiplexer is connected to a first node between the output terminal of the first delay circuit and the input terminal of the second delay circuit, and the third output terminal of the multiplexer is connected to the output terminal of the second delay circuit. And a second node between the input terminals of the third delay circuit. The method of claim 1, The source drive ICs adjust the pulse width of the source output enable signal in units of length x i (i is a natural number) of one of the source control packet and the RGB data packet according to the control data of the source control packet. Liquid crystal display device characterized in that. The method of claim 2, The second step signal is, Further comprising a second source control packet, The second source control packet includes PWRC1 / 2 option information for determining an output buffer amplification ratio of the source drive ICs, MODE option information for determining a charge share voltage output of the source drive ICs, and a reception path of the source output enable signal. The SOE_EN option information for determining the information, the PACK_EN option information for determining the reception path of the polarity control signal, the CHMODE option information for determining the number of output channels of the source drive ICs, and a unique chip identification code for each source drive IC. CID1 / 2 option information for independently controlling source drive ICs, and H_2DOT option information for determining a horizontal polarity inversion period of the positive / negative data voltages output from the source drive ICs. Liquid crystal display comprising a. The method of claim 1, The source drive ICs, After the output clock is locked, the lock signal is sequentially transmitted to neighboring source drive ICs, and the last source drive IC inputs the lock signal to the timing controller. And the timing controller transmits the second step signal after at least one of the last source drive IC and a test mode enable signal is input.

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