JP7402007B2 - LCD driver IC - Google Patents

Description

The present invention relates to a liquid crystal driver IC (Integrated Circuit) that drives a liquid crystal element.

The display driver IC proposed in Patent Document 1 can be used as a liquid crystal driver IC that drives a liquid crystal element, and can detect whether a short circuit failure has occurred in a circuit or signal line related to the output of a drive control signal. Can be judged.

International Publication No. 2018/066292 (Paragraphs 0043 to 0047 and Paragraphs 0050 to 0053)

However, in the display driver IC disclosed in Patent Document 1, if a short-circuit failure occurs in a circuit or signal line related to the output of any drive control signal, it is impossible to determine that a short-circuit failure has occurred. Even if it could be determined, it was not possible to specify in which circuit or signal line related to the output of the drive control signal the short-circuit failure occurred.

In view of the above-mentioned situation, the present invention provides that when a short-circuit failure occurs in a circuit or signal line related to the output of any drive control signal, the circuit or signal line related to the output of any drive control signal is An object of the present invention is to provide a liquid crystal driver IC that can identify whether a short-circuit failure has occurred.

The liquid crystal driver IC disclosed in this specification includes a logic circuit, an output section that outputs a drive control signal at a level corresponding to the output of the logic circuit to a liquid crystal section, and a drive control signal whose level corresponds to the output of the logic circuit. k (k is a natural number of 2 or more) circuit blocks including an error determination section that outputs an error when the level does not correspond to the output of the circuit and an address determination section; The liquid crystal driver IC includes an error signal generation section that generates an error signal that is a logical sum of the error outputs of the section, and the address determination section is arranged inside the liquid crystal driver IC and outside the circuit block. The error determination section determines whether or not the supplied address supplied from the address generator matches the unique address unique to each of the k circuit blocks, and the error determination unit determines whether or not the supplied address supplied from the address generator in If it is determined by the unit that the supply address and the unique address do not match, the error output is masked (first configuration).

In the liquid crystal driver IC having the first configuration, there are three or more levels corresponding to the output of the logic circuit, and the level detectable by the level detection function in the error determination section is limited to two specific values. (Second configuration) may also be used.

In the liquid crystal driver IC having the first or second configuration, the error signal generation section includes (k-1) two-input OR gates, and the (k-1) OR gates are arranged in a predetermined linear direction. are arranged in line along the (k-1) OR gates, the first input terminal and the second input terminal of the OR gate are arranged on one side of the predetermined linear direction, and the output of the OR gate is The OR gate has a terminal arranged on the other side of the predetermined linear direction, k is 3 or more, and of the (k-1) OR gates, the OR gate is arranged on the other side of the predetermined linear direction. The output terminals of the (k-2) OR gates excluding the above are each connected to the first input terminal of the OR gate adjacent to the other side in the predetermined linear direction (third configuration). Good too.

In the liquid crystal driver IC having any of the first to third configurations, the supply address and the unique address match when the level of the drive control signal is not at a level corresponding to the output of the logic circuit. The output of the logic circuit of the circuit block is determined by the logic circuit of the circuit block where the supply address and the unique address do not match when the level of the drive control signal is not at a level corresponding to the output of the logic circuit. A configuration (fourth configuration) that is different from the output may be used.

A liquid crystal device disclosed herein includes a liquid crystal driver IC having any of the first to fourth configurations, the liquid crystal section, and a light source that irradiates the liquid crystal section with light, and This is a configuration (fifth configuration) in which the unit includes a plurality of liquid crystal elements, and the liquid crystal driver IC drives the liquid crystal elements .

The liquid crystal device with the fifth configuration includes the liquid crystal driver IC with the fourth configuration, and during a period when the light source is turned off, the error determination unit is configured to detect the error determination unit by the address determination unit in the same circuit block. If it is determined that the supply address and the unique address do not match, the error output may be masked (sixth configuration).

In the liquid crystal device having the sixth configuration, during the period when the light source is on, the error determination unit may detect whether the supply address and the unique address are determined by the address determination unit in the same circuit block. A configuration (seventh configuration) may be adopted in which the error output is not masked even if it is determined that they do not match.

The vehicle disclosed in this specification has a configuration (eighth configuration) including a liquid crystal device having any of the fifth to seventh configurations described above.

According to the liquid crystal driver IC disclosed in this specification, when a short-circuit failure occurs in a circuit or signal line related to the output of any drive control signal, the output of any drive control signal is It can be determined whether a short circuit has occurred in the circuit or signal line.

Schematic top view of a liquid crystal display device according to one embodiment Block diagram showing an example of a configuration of a liquid crystal driver IC Diagram showing an example of a COM line pattern Diagram showing an example of a COM line pattern when there is only one COM line Diagram showing an example of SEG line pattern Diagram showing an example of display pattern Diagram showing an example of arrangement of data flip-flops A diagram showing an example of the configuration of the second determination circuit A diagram showing another configuration example of the second determination circuit Diagram showing the address generator and logic circuit of each circuit block Diagram showing an example of a configuration of a logic circuit Diagram showing an example of an operation sequence A diagram showing an example of a scanning signal and a data signal in scan mode operation of the second determination circuit Diagram showing an example of the configuration of the overall error signal output circuit Schematic transparent top view of LCD driver IC External view of a vehicle equipped with a liquid crystal display device

<Overall configuration>
FIG. 1 is a schematic top view of a liquid crystal display device according to one embodiment. The liquid crystal display device shown in FIG. 1 includes an MPU (Micro Processing Unit) 100 that is a host device, a liquid crystal driver IC 200 that receives display data from the MPU 100, and drive control signals (scanning signals COM0 to COM3 and data to be described later) from the liquid crystal driver IC 200. It has a liquid crystal display panel 300 that receives signals (SEG0 to SEG9) and a backlight (not shown).

The liquid crystal display panel 300 has a liquid crystal section 400 formed on a glass substrate. Liquid crystal section 400 has a plurality of liquid crystal elements. A backlight (not shown) irradiates the liquid crystal section 400 with light. The liquid crystal driver IC 200 is COG-mounted on the glass substrate of the liquid crystal display panel 300 and outputs a drive control signal to the liquid crystal element of the liquid crystal section 400.

FIG. 2 is a block diagram showing an example of the configuration of the liquid crystal driver IC 200.

The liquid crystal driver IC 200 is driven by an internal power supply voltage that is the difference between the power supply voltage VDD applied to the power supply voltage terminal T1 and the ground voltage VSS applied to the ground potential terminal T2. The power-on reset circuit 1 resets the entire operation of the liquid crystal driver IC 200 when the power supply voltage VDD applied to the power supply voltage terminal T1 decreases.

The serial interface 2 performs serial bus communication, such as I2C, with the MPU 100. The serial interface 2 is a logic circuit, and outputs the data sent from the MPU 100 to the command data decoder 3 while holding the data in a register.

The command data decoder 3 refers to the register value written in the command register 4 and decodes the command included in the serial data output from the serial interface 2.

Display data included in the serial data output from the serial interface 2 is output from the command data decoder 3 to a display data RAM (Random Access Memory) 5.

The oscillator 6 outputs to the COMMON counter 7 an external oscillation signal OSC supplied from the outside or an internal oscillation signal generated by oscillation of the oscillator 6 itself.

The COMMON counter 7 controls the scanning period based on the external oscillation signal OSC or the internal oscillation signal output from the oscillator 6.

The liquid crystal voltage generation section 8 divides a constant voltage VLCD for driving the liquid crystal supplied from the outside to generate four-value voltages V1 to V4. Voltage V1>voltage V2>voltage V3>voltage V4, where voltage V1 has the same value as constant voltage VLCD, and voltage V4 has the same value as ground voltage VSS.

The liquid crystal bias selection section group 9G has 14 liquid crystal bias selection sections. Each liquid crystal bias selection section supplies a voltage selected from voltages V1 to V4 to a COMMON driver or a SEGMENT driver.

The COMMON driver group 10G includes four COMMON drivers. The m-th (m is a natural number of 4 or less) COMMON driver generates a scanning signal COM (m-1) using the output of the m-th liquid crystal bias selection section and outputs it to the liquid crystal section 400. The SEGMENT driver group 11G has 10 SEGMENT drivers. The n-th (n is a natural number of 10 or less) COMMON driver uses the output of the (n+4)-th liquid crystal bias selection section to generate a data signal SEG (n-1) based on the display data output from the display data RAM 5. ) is generated and output to the liquid crystal section 400. Note that the number of scanning signals in this embodiment (=4) and the number of data signals in this embodiment (=10) are just examples, and the number of scanning signals and the number of data signals in this embodiment are different from each other. It is not limited.

Details of the first to fourth determination circuits 21 to 24 and the overall error signal output circuit 25 will be described later.

FIG. 3A is a diagram showing an example of a COM line pattern. Four COM lines to which scanning signals COM0 to COM3 are respectively supplied are arranged in the liquid crystal section 400 as shown in FIG. 3A. Unlike this embodiment, when using one COM line, the COM line may be arranged in the liquid crystal section 400, for example, as shown in FIG. 3B.

FIG. 4 is a diagram showing an example of a pattern of SEG lines. Ten SEG lines to which data signals SEG0 to SEG9 are respectively supplied are arranged in the liquid crystal section 400 as shown in FIG.

The example of the COM line pattern shown in FIG. 3 and the example of the SEG line pattern shown in FIG. 4 make it possible to display segments, such as the one shown in FIG. 5, for example.

<First judgment circuit>
The first determination circuit 21 has a configuration including a plurality of data flip-flops, and determines whether or not an abnormality has occurred in the register value of a register in a digital circuit. In the configuration example shown in FIG. 2, the serial interface 2, command data decoder 3, command register 4, display data RAM 5, and COMMON counter 7 constitute a digital circuit. Abnormalities occur in the register values of registers in digital circuits due to external electrical noise. Therefore, the data flip-flop is placed at a position where it is susceptible to external electrical noise. Then, the first determination circuit 21 determines that an abnormality has occurred in the register value of the register in the digital circuit when the value written to the data flip-flop (expected value) and the value read from the data flip-flop do not match. Since there is a high probability that this occurs, it is determined that an abnormality has occurred in the register value of the register in the digital circuit.

The first determination circuit 21 generates data to be written to the data flip-flop, and compares the value written to the data flip-flop (expected value) with the value read from the data flip-flop.

Here, it is desirable that the value written to the data flip-flop be an inverted value of the value written to the data flip-flop before writing. For example, when the first judgment circuit 21 sequentially generates data to be written to each of five data flip-flops, if the first data generated by the first judgment circuit 21 is "10101", then the data for the subsequent comparison will be The data generated later by the first determination circuit 21 may be set to "01010". This is because if the value written to the data flip-flop is fixed, problems may occur, such as the output of a damaged data flip-flop continuing to coincide with the value written to the data flip-flop.

FIG. 6 is a diagram showing an example of the arrangement of data flip-flops. The liquid crystal driver IC 200 has a rectangular shape in plan view, and the data flip-flops FF1 to FF4 are arranged at the four corners of the liquid crystal driver IC 200. This is because the four corners of the liquid crystal driver IC 200 are considered to be the positions most susceptible to the influence of external electrical noise.

Furthermore, fluctuations in the power supply voltage VDD can also result in external electrical noise. The power supply voltage wiring pattern P1 to which the power supply voltage terminal T1 is connected includes a guard ring part along the outer edge of the liquid crystal driver IC 200, a first linear part with a thick line width extending in the vertical direction in FIG. and a second linear portion extending in the left-right direction and having a narrower line width than the first linear portion. The data flip-flop FF5 is arranged in the vicinity of a point PT1 in the power supply voltage wiring pattern P1 where the impedance is the largest with respect to the power supply voltage terminal T1. This is because the location PT1 where the impedance is the largest is considered to be the location where the variation in the power supply voltage VDD is greatest and the variation in the power supply voltage VDD is most likely to cause external electrical noise.

Further, fluctuations in the ground voltage VSS can also become external electrical noise, similar to fluctuations in the power supply voltage VDD. Therefore, the data flip-flop may be arranged near the location where the impedance with respect to the ground potential terminal T2 is largest among the ground potential wiring patterns connected to the ground potential terminal T2.

Note that, unlike this embodiment, there may be a single data flip-flop.

<Second judgment circuit>
FIG. 7 is a diagram showing an example of the configuration of the second determination circuit 22. As shown in FIG. The liquid crystal driver IC 200 includes circuit blocks CB_COM3 to CB_COM0 that generate scanning signals COM3 to COM0, respectively, and circuit blocks CB_SEG0 to CB_SEG9 that generate data signals SEG0 to SEG9, respectively. Note that in FIG. 7, circuit blocks CB_COM0 and CB_SEG0 to CB_SEG8 are not shown.

Each circuit block has basically the same configuration. However, while the circuit blocks CB_COM3 to CB_COM0 are equipped with a COMMON driver 10 that outputs a scanning signal of a level corresponding to the output of the logic circuit 33, the circuit blocks CB_SEG0 to CB_SEG9 are equipped with a data signal of a level corresponding to the output of the logic circuit 33. It is equipped with a SEGMENT driver that outputs. The SEGMENT driver has the same configuration as the COMMON driver 10. Each circuit block includes a liquid crystal bias selection section 9, a COMMON driver 10 or a SEGMENT driver, a level shifter 32, and a logic circuit 33.

The second determination circuit 22 in the configuration example shown in FIG. 7 receives determination results from the TTL (Transistor Transistor Logic) buffer 31, level shifter 32, logic circuit 33, and level shifter 34 of each circuit block, and the logic circuit 33 of each circuit block. It is constituted by an OR gate 35 for receiving. Note that in the configuration example shown in FIG. 7, the level shifters 32 and 34 are provided on the premise that the power supply voltage VDD and constant voltage VLCD are voltages of different values, but if the power supply voltage VDD and constant voltage VLCD are the same, In the case of a voltage of a certain value, a configuration may be adopted in which the level shifters 32 and 34 are not provided.

The logic circuit 33 outputs an enable signal that enables the TTL buffer 31 only when the scanning signal or data signal is controlled to a specific binary value (for example, voltage V1 or voltage V4). The enable signal output from the logic circuit 33 is level-shifted by the level shifter 34 and then supplied to the TTL buffer 31. The input end of the TTL buffer 31 is connected to a signal line through which a scanning signal or a data signal is output. The signal output from the TTL buffer 31 is level-shifted by the level shifter 32 and then supplied to the logic circuit 33.

When the level shifter 32 returns a voltage corresponding to the voltage V1 while controlling the scan signal or data signal to the voltage V1, the logic circuit 33 outputs a circuit related to the output of the scan signal or data signal (COMMON driver 10 or SEGMENT). It is determined that no short-circuit failure has occurred in the driver) or the signal line, and that the level of the scanning signal or data signal is at a level corresponding to the output of the logic circuit 33. Similarly, when the level shifter 32 returns a voltage corresponding to the voltage V4 while controlling the scanning signal or the data signal to the voltage V4, the logic circuit 33 controls the circuit (COMMON driver) related to the output of the scanning signal or the data signal. 10 or SEGMENT driver) or the signal line, and the level of the scanning signal or data signal is determined to be at a level corresponding to the output of the logic circuit 33. As a result of the above determination, the logic circuit 33 outputs a high level signal (outputs an error) when it is determined that an abnormality has occurred, and outputs a low level signal when it is determined that no abnormality has occurred. Output a signal.

The OR gate 35 outputs the logical sum of the determination results output from the logic circuit 33 of each circuit block to the overall error signal output circuit 25 (see FIG. 2) as an output signal S2.

The second determination circuit 22 in the configuration example shown in FIG. 7 makes a determination using only specific two values (for example, voltage V1 or voltage V4) among the four-value voltages V1 to V4. This configuration eliminates the need to provide A/D converters corresponding to each of the voltages V1 to V4, making it possible to achieve downsizing and cost reduction. Note that the voltage generated by the liquid crystal voltage generation section 8 (see FIG. 2) is not limited to the four-value voltages V1 to V4, and may be any voltage of two or more values.

From the viewpoint of shortening the total length of the wiring within the second determination circuit 22, the configuration example shown in FIG. 8 is more preferable than the configuration example shown in FIG. 7. The second determination circuit 22 of the configuration example shown in FIG. 8 differs from the second determination circuit 22 of the configuration example shown in FIG. 7 in that it includes 13 OR gates 35_1 to 35_13 instead of the OR gate 35. Note that, compared to the second determination circuit 22 in the configuration example shown in FIG. 7, the second determination circuit 22 in the configuration example shown in FIG. . Furthermore, in the second determination circuit 22 of the configuration example shown in FIG. Since it can be used for each layout of CB_SEGa and OR gate 35_(a+4) (where a is an integer from 0 to 9), layout design becomes easy.

The OR gate 35_1 outputs the logical sum of the determination result output from the logic circuit 33 of the circuit block CB_COM3 and the determination result output from the logic circuit 33 of the circuit block CB_COM2. The OR gate 35_2 outputs the logical sum of the determination result output from the logic circuit 33 of the circuit block CB_COM1 and the output of the OR gate 35_1. Similar to the OR gate 35_2, the OR gates 35_3 to 35_12 output the logical sum of the determination result output from the logic circuit 33 of the corresponding circuit block and the output of the adjacent OR gate. The OR gate 35_13 outputs the logical sum of the determination result output from the logic circuit 33 of the circuit block CB_SEG9 and the output of the OR gate 35_12 to the overall error signal output circuit 25 (see FIG. 2) as an output signal S2.

Here, for example, if the configuration is such that each of the determination results output from the logic circuit 33 of each circuit block is sent to the serial interface 2, the serial interface 2 can be connected to the output of which drive control signal (scanning signal or data signal) It can be ascertained whether a short-circuit failure has occurred in the circuit or signal line. However, such a configuration requires extra wiring. In particular, when adopting the configuration example shown in FIG. 8, the wiring that connects the logic circuit 33 of each circuit block and the serial interface 2 becomes more complicated than the advantage of shortening the total length of the wiring in the second determination circuit 22. The disadvantages are greater.

Therefore, in this embodiment, by providing an address determination circuit in the logic circuit 33 of each circuit block, a short circuit failure occurs in a circuit or signal line related to the output of any drive control signal (scanning signal or data signal). If a short-circuit failure has occurred, it can be specified in which circuit or signal line related to the output of a drive control signal (scanning signal or data signal) a short-circuit failure has occurred. Note that although the address determination circuit is provided within the logic circuit 33 in this embodiment, the address determination circuit may be provided outside the logic circuit 33.

As shown in FIG. 9, the address generator 2A in the serial interface 2 supplies addresses to the logic circuits 33 of each circuit block. For example, the address generator 2A sequentially switches the value of the address (hereinafter also referred to as "supply address") supplied to the logic circuit 33 of each circuit block based on the internal oscillation signal generated by the oscillator 6.

FIG. 10 is a diagram showing an example of the configuration of the logic circuit 33. The logic circuit 33 includes an XOR gate 33A, an address determination section 33B, and an AND gate 33C.

When the logic circuit 33 is controlling the scan signal or data signal to the voltage VA, the XOR gate 33A generates an exclusive OR of the voltage VA and the voltage VB returned from the level shifter 32, and outputs the exclusive OR of the AND gate 33C. Output to the first input terminal. In other words, the XOR gate 33A outputs a high-level signal (outputs an error) when it determines that voltage VA and voltage VB do not match and an abnormality has occurred, and when voltage VA and voltage VB match, If it is determined that no abnormality has occurred, a low level signal is output.

The address determination unit 33B determines whether or not the supplied address A1 matches the unique address A2 unique to each circuit block, and if they match, outputs a high-level signal to the second input terminal of the AND gate 33C. However, if they do not match, a low level signal is output to the second input terminal of the AND gate 33C. The unique address A2 is stored in a storage section (not shown) within the logic circuit 33, for example. A storage section (not shown) within the logic circuit 33 may be volatile or nonvolatile. If the storage section (not shown) in the logic circuit 33 is volatile, the serial interface 2 may, for example, give the unique address A2 to the logic circuit 33 every time the power is turned on.

AND gate 33C outputs the logical product of the output of XOR gate 33A and the output of address determination section 33B. For example, the output of the AND gate 33C is supplied to the OR gate 35 if the second determination section has the configuration example shown in FIG. supplied to either. As a result, if the supply address A1 and the unique address A2 do not match, the error output is masked.

As a result, the determination results of only the circuit blocks in which the supply address A1 and the unique address A2 match are reflected in the output signal S2. Therefore, by simply checking the output signal S2 while sequentially switching the value of the supply address A1, it is possible to detect that a short-circuit failure has occurred in the circuit or signal line related to the output of one of the drive control signals (scanning signal or data signal). In this case, it can be determined in which circuit or signal line related to the output of the drive control signal (scanning signal or data signal) a short-circuit failure has occurred. The level of the output signal S2 for each value of the supply address A1, that is, the determination result of each circuit block, may be stored, for example, in a register (not shown) within the serial interface 2; (shown in the figure) may be directly sent to the MPU 100.

Note that if error output masking is not required, the address determination unit 33B sends a high-level signal to the second input terminal of the AND gate 33C, regardless of whether the supply address A1 and the unique address A2 match or not. All you have to do is supply it to

Next, the operation timing of the second determination circuit 22 will be explained with reference to FIGS. 11 and 12. FIG. 11 is a diagram showing an example of an operation sequence. FIG. 12 is a diagram showing an example of a scan signal and a data signal in the scan mode operation of the second determination circuit 22.

In an example of the operation sequence shown in FIG. 11, when the liquid crystal display device shown in FIG. 1 is powered on, the power supply voltage VDD first rises at timing t1. Thereafter, at timing t2, information regarding the scan mode setting is sent from the MPU 100 to the serial interface 2. At timing t3 when the transmission of information regarding the scan mode setting is completed, the constant voltage VLCD rises, and the COMMON driver group 10G and the SEGMENT driver group 11G start the scan mode operation based on the scan mode setting.

In the scan mode operation, as shown in FIG. 12, only one of the scan signals COM3 to COM0 and data signals SEG0 to SEG9 is sequentially controlled to a high level voltage (for example, voltage V1), and the rest are controlled to a low level voltage (for example, voltage V4). ) is performed in the first period P1, and then the scan signals COM3 to COM0 and the data signals SEG0 to SEG9 are sequentially controlled to a low level voltage (for example, voltage V4), and the remaining ones are controlled to a low level voltage (for example, voltage V4). A low-level voltage scan operation in which the voltage is controlled to a high-level voltage (for example, voltage V1) is performed in the second period P2.

The above-described scan mode operation allows the second determination circuit 22 to perform abnormality determination in each circuit block without being influenced by other circuit blocks. Note that in the scan mode operation described above, the content is not displayed on the liquid crystal unit 400, so during the period when the scan mode operation described above is executed (the period from timing t3 to timing t4), the liquid crystal display device It is desirable to turn off the backlight.

After timing t4 when the scan mode operation ends, the MPU 100 reads the determination result of the second determination circuit 22 stored in the register of the serial interface 2.

After reading out the determination results, the MPU 100 sends information regarding the normal mode setting to the serial interface 2, and the COMMON driver group 10G and the SEGMENT driver group 11G start normal mode operation (content display operation) based on the normal mode setting. .

<Third judgment circuit>
The MPU 100 includes a checksum in data transmitted to the serial interface 2 through serial bus communication. The third determination circuit 23 uses the checksum to determine whether an abnormality has occurred in the data transmitted from the MPU 100 to the serial interface 2 via serial bus communication.

<Fourth judgment circuit>
The fourth determination circuit 24 outputs a pulse signal CHKO. The pulse signal CHKO may be, for example, a pulse signal whose high level matches the value of the power supply voltage VDD and whose low level matches the value of the ground voltage VSS, or for example, whose high level matches the value of the constant voltage VLCD and whose low level matches the value of the constant voltage VLCD. It may also be a pulse signal that matches the value of the ground voltage VSS. A terminal to which the pulse signal CHKO is output is connected to one end of a transparent electrode line formed on the glass substrate of the liquid crystal display panel 300. The fourth determination circuit 24 determines whether or not the glass substrate of the liquid crystal display panel 300 is damaged, using the pulse signal CHKI input to the terminal connected to the other end of the transparent electrode line. If a pulse omission occurs in the pulse signal CHKI, the fourth determination circuit 24 determines that the glass substrate of the liquid crystal display panel 300 is damaged.

<Overall error signal output circuit>
FIG. 13 is a diagram showing an example of the configuration of the overall error signal output circuit 25. As shown in FIG. The overall error signal output circuit 25 has an OR circuit 36. Note that in the configuration example shown in FIG. 13, a part of the serial interface 2 also functions as a part of the overall error signal output circuit 25.

The first determination circuit 21 sets the output signal S1 to a high level when it is determined that an abnormality has occurred, and sets the output signal S1 to a low level when it is determined that no abnormality has occurred. The second determination circuit 22 sets the output signal S2 to a high level when determining that an abnormality has occurred, and sets the output signal S2 to a low level when determining that no abnormality has occurred. The third determination circuit 23 sets the output signal S3 to a high level when it is determined that an abnormality has occurred, and sets the output signal S3 to a low level when it is determined that no abnormality has occurred. The fourth determination circuit 24 sets the output signal S4 to a high level when it is determined that an abnormality has occurred, and sets the output signal S4 to a low level when it is determined that no abnormality has occurred.

The OR circuit 36 inputs the output signals S1 to S4 of the first to fourth determination circuits 21 to 24, and outputs the overall error signal ERROUT which is the logical sum of these signals to the MPU 100. The overall error signal ERROUT is a signal that informs whether or not a factor that causes a screen display abnormality on the liquid crystal display panel 300 has occurred, and it is determined that a factor that causes a screen display abnormality on the liquid crystal display panel 300 has occurred. It becomes a high level when the liquid crystal display panel 300 has a screen display abnormality, and becomes a low level when it is determined that no factor causing screen display abnormality of the liquid crystal display panel 300 has occurred. Therefore, the MPU 100 can recognize that an abnormality has occurred when the overall error signal ERROUT is at a high level. Thereby, the MPU 100 can take measures such as stopping the output of display data or reporting an abnormality when an abnormality occurs. As described above, when it is determined that an abnormality has occurred in at least one of the first to fourth determination circuits 21 to 24, the OR circuit 36 detects the occurrence of a factor that causes an abnormality in the screen display of the liquid crystal display panel 300. This is provided to notify the MPU 100 of what is being done. Therefore, a circuit having a circuit configuration different from that of the OR circuit 36 and playing the same role as the OR circuit 36 may be provided in place of the OR circuit 36. Further, it is desirable that the determination functions of the first to fourth determination circuits 21 to 24 can be switched ON/OFF by register settings. When the determination function is OFF, for example, the determination circuit may output an output signal indicating that it has determined that no abnormality has occurred, without performing determination.

The overall error signal output circuit 25 stores the states of the output signals S1 to S4 of the first to fourth determination circuits 21 to 24. Then, when the serial interface 2 receives a read command regarding the states of the output signals S1 to S4 of the first to fourth determination circuits 21 to 24 from the MPU 100, the serial interface 2 reads the output signals of the first to fourth determination circuits 21 to 24. The states of S1 to S4 are sent to the MPU 100.

<COG implementation status determination>
FIG. 14 is a schematic transparent top view of the liquid crystal driver IC 200. Dummy terminals T3 and T4 are provided at the corners of the lower surface of the liquid crystal driver IC 200. The dummy terminal T3 and the dummy terminal T4 are electrically connected inside the liquid crystal driver IC 200. Pads PD1 and PD2 are formed on the glass substrate of display panel 300. A wiring whose one end is connected to the pad PD1 is formed on the glass substrate of the display panel 300, and when COG mounting is performed, the other end of the wiring is electrically connected to the dummy terminal T3. A wiring whose one end is connected to the pad PD2 is formed on the glass substrate of the display panel 300, and when COG mounting is performed, the other end of the wiring is electrically connected to the dummy terminal T4. The quality of COG mounting can be determined by measuring the resistance value between pad PD1 and pad PD2. It is desirable that the dummy terminals T3 and T4 be provided at each of the four corners of the lower surface of the liquid crystal driver IC 200, as shown in FIG.

<Application>
The above-described liquid crystal display device can be suitably used, for example, as a part of an instrument panel disposed at a position visible to the driver of the vehicle X10 shown in FIG. 15.

<Points to note>
The various technical features disclosed in this specification can be modified in addition to the embodiments described above without departing from the gist of the technical creation. For example, in the above embodiments, the liquid crystal display device performs segment display, but the liquid crystal display device may perform matrix display. Further, in the above embodiments, a liquid crystal display device is used as an example of a liquid crystal device including a liquid crystal section including a plurality of liquid crystal elements, a light source that irradiates the liquid crystal section with light, and a liquid crystal driver IC that drives the liquid crystal element. Although described above, the liquid crystal device does not have to be a display device. That is, the above embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is defined by the claims rather than the description of the above embodiments. It should be understood that all changes that come within the meaning and range of equivalency of the claims are included.

1 Power-on reset circuit 2 Serial interface 3 Command data decoder 4 Command register 5 Display data RAM
6 Oscillator 7 COMMON counter 8 Liquid crystal voltage generation section 9, 9G Liquid crystal bias selection section, liquid crystal bias selection section group 10G COMMON driver group 11, 11G SEGMENT driver, SEGMENT driver group 21 to 24 1st to 4th judgment circuit 25 Overall error signal Output circuit 31 TTL buffer 32, 34 Level shifter 33 Logic circuit 33A XOR gate 33B Address judgment section 33C AND gate 35, 36 OR circuit 100 MPU
200 LCD driver IC
300 Liquid crystal display panel 400 Liquid crystal section FF1 to FF5 Data flip-flop PD1, PD2 Pad T1 Power supply voltage terminal T2 Ground potential terminal T3, T4 Dummy terminal X10 Vehicle

Claims (8)

logic circuit and
an output section that outputs a drive control signal at a level corresponding to the output of the logic circuit to the liquid crystal section ;
k (k is a natural number of 2 or more) circuit blocks including an error determination section that outputs an error when the level of the drive control signal is not at a level corresponding to the output of the logic circuit, and an address determination section. Individually prepared,
A liquid crystal driver IC comprising an error signal generation section that generates an error signal that is a logical sum of the error outputs of the k error determination sections,
The address determination unit determines whether a supplied address supplied from an address generator disposed inside the liquid crystal driver IC and outside the circuit block matches a unique address unique to each of the k circuit blocks. determine whether
The error determining unit is configured to mask the error output if the address determining unit in the same circuit block determines that the supplied address and the unique address do not match. There are three or more levels depending on the output of the logic circuit,
2. The liquid crystal driver IC according to claim 1 , wherein the level detectable by the level detection function in the error determination section is limited to specific binary values . The error signal generation section includes (k-1) two-input OR gates,
(k-1) of the OR gates are arranged in line along a predetermined linear direction,
In each of the (k-1) OR gates, a first input terminal and a second input terminal of the OR gate are arranged on one side of the predetermined linear direction, and an output terminal of the OR gate is arranged on one side of the predetermined linear direction. placed on the other side,
k is 3 or more, and outputs of (k-2) OR gates excluding the OR gate located closest to the other side of the predetermined linear direction among the (k- 1) OR gates; 3. The liquid crystal driver IC according to claim 1, wherein each terminal is connected to a first input terminal of the OR gate adjacent to the other side in the predetermined linear direction . When the level of the drive control signal is not at a level corresponding to the output of the logic circuit, the output of the logic circuit of the circuit block in which the supply address and the unique address match is the level of the drive control signal. 4. The supply address and the unique address are different from the output of the logic circuit of the circuit block with which the supply address and the unique address do not match when the address is not at a level corresponding to the output of the logic circuit. The liquid crystal driver IC described. A liquid crystal driver IC according to any one of claims 1 to 4,
the liquid crystal section;
a light source that irradiates the liquid crystal section with light;
Equipped with
The liquid crystal section includes a plurality of liquid crystal elements,
A liquid crystal device , wherein the liquid crystal driver IC drives the liquid crystal element . Comprising the liquid crystal driver IC according to claim 4,
During the period when the light source is off, the error determining unit masks the error output if the address determining unit in the same circuit block determines that the supply address and the unique address do not match. The liquid crystal device according to claim 5. During the period when the light source is on, the error determining unit detects the error even if the address determining unit in the same circuit block determines that the supplied address and the unique address do not match. 7. The liquid crystal device according to claim 6, wherein the output is not masked. A vehicle comprising the liquid crystal device according to any one of claims 5 to 7.

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