TWI416503B - And a semiconductor integrated circuit for display control - Google Patents

Abstract

The present invention provides a display control semiconductor integrated circuit having therein a RAM, capable of repairing a defective bit included in the RAM and improving the yield without significantly increasing the occupation area. A liquid crystal controller/driver in which a RAM for storing display data is provided in a chip and the storage capacity of the built-in RAM is determined according to the size of a display screen of a liquid crystal panel to be driven, includes a fuse circuit for setting a defect address, and a comparing circuit for comparing the defect address set in the fuse circuit with an input address. The liquid crystal controller/driver also has a redundant circuit, when the addresses match each other, for replacing the input address with an address that instructs the spare memory area and supplying the address to an address decoder.

Description

Display control semiconductor integrated circuit

The present invention relates to a technique which is effectively applicable to a RAM (random access memory) in which memory display data is incorporated, a display drive control device that drives a display device, and even a display drive control device that is circuitized by a semiconductor integrated circuit. For example, regarding a technique, it is effectively applied to a semiconductor integrated circuit for liquid crystal display control for driving a liquid crystal panel.

In recent years, as a portable electronic device such as a mobile phone or a PDA (personal digital assistant), a dot matrix type liquid crystal panel in which a plurality of display pixels are arranged in a matrix in two dimensions is generally used. Inside the machine, a liquid crystal display control device (liquid crystal controller) in which a semiconductor integrated circuit is controlled to perform display control of the liquid crystal panel, or a liquid crystal driver that drives the liquid crystal panel under the control of the control device, or a built-in A liquid crystal display drive control device (liquid crystal control driver) with a liquid crystal driver.

Previously, the liquid crystal control driver (including the liquid crystal controller) is a RAM with memory display data inside the chip, and the memory capacity of the built-in RAM is generally set according to the display screen size of the driven liquid crystal panel, which is more general. A so-called Redundant Circuit with small memory and no rescue defect bits.

The reason why the memory capacity of the built-in RAM is specified by the screen size of the liquid crystal panel is because the liquid crystal control driver sets the capacity of the built-in RAM to the size of the display material of one screen of the memory liquid crystal panel, and the RAM occupies the wafer. The proportion of the area will also increase, so increasing the memory capacity will directly involve the increase in wafer cost. Moreover, if it is a built-in RAM having a capacity to memorize the display material of one screen, the defect caused by the RAM has a problem that the productivity is lowered, and the necessity of setting a redundant circuit is also lowered. Avoid increasing the size of the wafer due to the lengthy circuitry.

Further, in the liquid crystal control driver, the memory capacity of the built-in RAM is set to the size of the display material for storing one screen portion, which is described, for example, in Patent Document 1.

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2000-347646

The inventors of the present invention have reduced the wafer cost by reducing the wafer size of the liquid crystal control driver, and have adopted a miniaturization process to increase the density of the built-in RAM. However, if the built-in RAM is densified, defects are likely to occur, and it is known that a decrease in productivity due to a RAM defect causes a problem.

Therefore, the memory defect rescue technique formed by the redundant circuit used in the general-purpose RAM is reviewed to improve the productivity. However, the versatile circuit used in the general-purpose RAM is as shown in FIG. 10, respectively, which is provided with a control circuit for selecting a regular memory row or column, and for selecting a memory bank or column for replacement with a defective bit (long memory) Control circuit. Therefore, when accessing a normal memory row or column and accessing a spare memory row or column, the operational characteristics such as the read speed are different, and thus the timing design of the memory peripheral circuit is difficult.

In addition, in the memory defect rescue technique used in the general-purpose RAM, in addition to a circuit having a programmable component such as a fuse and memorizing the address of the row or column of the rescue memory (hereinafter referred to as a fuse circuit), there must be a memory. Do you want to rescue, that is, whether to use the fuse circuit of the reserve memory row or column. Then, according to the state of the fuse circuit, a control signal for enabling or disabling the memory line or column is generated and supplied (the signal of the EN symbol is added in FIG. 10).

Further, in the redundant circuit of the general-purpose RAM, when a plurality of spare memory lines or columns are provided, it is necessary to supply a selection signal (a signal to which an SS symbol is attached in FIG. 10) to which any one of the memory lines or columns is to be used. Therefore, if the memory defect rescue technology of the general-purpose RAM is applied to the liquid crystal control driver as it is, the area occupied by the redundant circuit and the wiring becomes large, which is a main cause of hindering the reduction of the wafer area.

The purpose of the invention is to provide a semiconductor integrated circuit for liquid crystal display control, such as a liquid crystal control driver for a RAM having a memory display data, which does not excessively occupy an occupied area to rescue a defective bit included in the RAM. Improve productivity.

Another object of the present invention is to provide a semiconductor integrated circuit for liquid crystal display control such as a liquid crystal control driver for a RAM having a memory display material, such as when accessing a normal memory row or column, and accessing a preliminary memory row or In the case of columns, the operational characteristics such as the readout speed are not different, and the timing design of the peripheral circuits of the memory is easy.

The above and other objects and novel features of the invention will be apparent from the description and appended claims.

In the invention disclosed in the present invention, the outline of the representative will be described below.

That is, a semiconductor integrated circuit for display control, in which a RAM for storing display data is stored in the inside of the chip, and the memory capacity of the RAM is determined according to the display screen size of the driven liquid crystal panel; wherein the set defect address is set. A fuse circuit, and a comparison circuit that compares the defect address set to the fuse circuit with the input address. Then, when the address is the same, the input address is replaced with an address indicating the address of the preliminary memory area, and is supplied to the redundant circuit of the address decoder.

In general, the RAM capacity of the semiconductor integrated circuit for display control, such as a liquid crystal control driver, is set to the size of the display data of one of the screens of the liquid crystal panel; the screen size of the liquid crystal panel is based on the specifications. The address of the memory size or the number of bits of the data is determined differently, and does not become the nth power of 2 (n is an integer). That is, in the liquid crystal control driver, the address area of the built-in RAM is smaller than the effective address space specified by the number of address bits of the built-in RAM.

In view of this, the present invention allocates a spare memory area for rescue in an unused address area in the effective address space defined by the number of address bits of the built-in RAM. Accordingly, as a preset value of the fuse circuit, an address indicating that there is no area allocated to the rescue memory area in the unused address area in the effective address space is allocated.

Here, when the address setting register for the area for displaying the window is displayed on the display screen, the address of the preliminary memory area is set outside the address range that can be set by the temporary register. The window display area, generally the maximum can be set to the display screen, so the outside of the address range that can be set by the above-mentioned scratchpad is equivalent to the unused address area in the effective address space. Assuming that the liquid crystal control driver has a register capable of setting an effective memory area of the built-in RAM, it is of course possible to use the outside of the address range that can be set by the register as an unused address area.

According to the above method, it is not necessary to constitute a control circuit for selecting a normal memory row or column, and a different control circuit such as a control circuit for selecting a memory bank or a column for replacement of a defective bit, and thus the timing of the peripheral circuit of the memory. The design is simpler.

Moreover, the preset value of the fuse circuit indicates that there is no unused address area allocated to the rescue memory area in the effective address space, so there is no need to generate valid or invalidated spare memory lines or columns. Control signal.

Moreover, the spare memory area is allocated to the inactive address area in the effective address space, and when the comparison defect address is identical to the input address, the input address is replaced with the bit indicating the preliminary memory address. Address, to supply to the address decoder. Therefore, when a plurality of spare memory rows or columns are set, it is not necessary to additionally generate a selection signal specifying the use of any one of the spare memory rows or columns.

The effect that can be obtained by the representative of the invention disclosed in the present invention will be briefly described below.

In other words, according to the present invention, the liquid crystal display control semiconductor integrated circuit such as the liquid crystal control driver including the RAM for storing the display data does not excessively occupy the occupied area to rescue the defective bit included in the RAM. It can increase productivity.

Further, the liquid crystal display control semiconductor integrated circuit such as a liquid crystal control driver including a RAM for storing display data is read when accessing a normal memory row or column and when accessing a preliminary memory row or column The operating characteristics such as speed are not different, and the timing design of the peripheral circuits of the memory is easy.

Hereinafter, a preferred embodiment of the present invention will be described based on the drawings.

Fig. 1 is a block diagram showing an embodiment of a liquid crystal control driver 200 incorporating a RAM and a rescue circuit. The liquid crystal control driver 200 of this embodiment is provided with a RAM (hereinafter referred to as a display memory) as a memory for storing data of a display pattern of a dot matrix type liquid crystal display panel, and a write circuit and a readout circuit thereof. And a driver for outputting a driving signal of the liquid crystal display panel, together with a semiconductor integrated circuit on a semiconductor substrate.

The liquid crystal control driver 200 of this embodiment is provided with a control unit 201 that controls the entire inside of the wafer in accordance with an instruction from an external microprocessor or microcomputer (hereinafter referred to as a microcomputer). And a pulse generator 202 for generating a reference clock pulse inside the wafer according to an excitation signal from an external excitation signal or a vibrator connected from an external terminal; and generating a pulse internal to each other according to the pulse The timing control circuit 203 of the timing signal of the operation timing of the circuit.

Further, a system interface 204 for transmitting and receiving data such as a command or a still display data between a microcomputer and the like via a system bus (not shown) is provided, and a main data reception is performed via a display data bus (not shown). Animation data from an application processor, etc., or level. The external display interface 205 of the vertical sync signals HSYNC, VSYNC.

Further, the liquid crystal control driver 200 includes a display memory 206 for storing display data in a dot matrix format, and a bit conversion circuit 207 for performing bit processing such as bit arrangement of RGB write data from the microcomputer. Further, the write data latch circuit 208 that holds the display data converted by the bit conversion circuit 207 or the display data input via the external display interface 205, and the display read from the display memory 206 The read data latch circuit 209 holds the data; and the address generating circuit 210 corresponding to the selected address of the display memory 206 is generated.

The display memory 206 is composed of a memory array including complex digital lines and bit lines (data lines); and having the address supplied from the address generating circuit 210 decoded to generate a selected memory. Read/write RAM of the address decoder of the word line or bit line signal within the array. Further, the display memory 206 is a sense amplifier that amplifies a signal read from a memory cell, or a write driver that applies a specific voltage to a bit line in a memory array in accordance with a write data. Although not particularly limited, in this embodiment, the memory array is configured to have a memory capacity of 172,800 bytes, and the 17-bit signal can be used to read and write data in a column unit (18 bits).

Further, the first and second latch circuits 211 and 212 which latch the display data read from the display memory 206 in sequence, and the display data converted from the latch are required to be driven by the AC drive for preventing liquid crystal deterioration. The data exchange circuit 213; and a latch circuit 214 that holds the data converted by the circuit. Further, a liquid crystal driving level generating circuit 216 having a voltage for generating a plurality of levels required for liquid crystal driving; and a voltage suitable for color display or gray scale display according to a voltage generated by the liquid crystal driving level generating circuit 216 A gray scale voltage generating circuit 217 for gray scale voltage required for the signal; and a gamma adjusting circuit 218 for setting a gray scale voltage for correcting the gamma characteristic of the liquid crystal panel.

In the subsequent stage of the latch circuit 214, a source line driving circuit 215 is provided, and the voltage of the display data latched by the latch circuit 214 is selected from the gray scale voltage supplied from the gray scale voltage generating circuit 217. The voltage (source line driving signal) S1 to S720 applied to the source line as the signal line of the liquid crystal panel is output. On the other hand, a gate line driving circuit 219 that outputs a voltage (gate line driving signal) G1 to G320 applied as a gate line (also referred to as a common line) of a liquid crystal panel signal line is provided; and a liquid crystal panel is generated. The gate lines are sequentially driven to scan data required for selecting the level, and the scan data generating circuit 220 composed of the shift register.

Further, an internal reference voltage generating circuit 221 that generates an internal reference voltage, and a voltage regulator 222 that steps down a voltage Vcc such as 3.3V or 2.5V supplied from the outside to generate a power supply Vdd of an internal logic circuit such as 1.5V is provided. . In addition, in the first figure, SEL1 and SEL2 are data selectors which are respectively controlled by the switching signals outputted by the timing control circuit 203, and selectively pass any one of the plurality of input signals.

The control unit 201 is provided with a control register CTR for controlling the overall operation state of the wafer such as the operation mode of the liquid crystal control driver 200, and an index data required for storing the reference of the control register CTR or the display memory 206. Index IXR and other registers. When an external microcomputer or the like writes an instruction to be executed by writing to the index register IXR, a control signal corresponding to the instruction designated by the control unit 201 is generated and output.

By the control of the control unit 201 configured as described above, the liquid crystal control driver 200 performs the drawing processing for writing the display material to the display memory 206 when the liquid crystal panel display is performed in accordance with an instruction or data from a microcomputer or the like. . Further, reading processing for periodically reading the display material from the display memory 206 is performed, and a signal applied to the source line of the liquid crystal panel is generated and outputted, and a signal sequentially applied to the gate line is generated and output.

The system interface 204 is configured to send and receive signals to the temporary storage device, such as setting data or display data, which are required for the display of the memory 206, and a system control device such as a microcomputer. In this embodiment, it is configured to match the state of the IM3-1 and IM0/ID terminals, and as the 80-series interface, parallel input/output or serial input/output such as 18-bit, 16-bit, 9-bit, and 8-bit can be selected. Any one.

The liquid crystal control driver 200 of this embodiment is provided with a rescue circuit 230 corresponding to the display memory 206 for rescuing the internal defect bit; and the address of the rescued memory bank including the defective bit as the rescue information. And the rescue information setting circuit 240 is held. Further, the display memory 206 is provided with a rescue memory area 206a provided separately from the normal memory area of the memory display material.

Here, the relationship between the memory area of the memory 206 and the address space in the liquid crystal control driver 200 of the present embodiment will be described using FIG. As described above, in the present embodiment, the display memory 206 can read and write data of a column (18-bit) unit by using a 17-bit address signal. On the other hand, the liquid crystal control driver 200 of the present embodiment is a color QVGA liquid crystal panel having a horizontal direction of 240 × 320 pixels in the vertical direction, and one pixel is composed of three dots of red, green, and basket.

If each point is represented by 6-bit data, each pixel needs to have 18-bit data; and the display data of one screen of the QVGA LCD panel is 240×320×18=3110400 bits=172800 bits. group. If the 18-bit data is used as a column, as shown in Fig. 2, the size of the memory area MAR of the display material of one screen of the QVGA liquid crystal panel is 320 characters x 240 columns. In addition, in the present embodiment, one character is not a 16-bit element, but a memory cell group (in the embodiment, 540 bits) connected to one word line of the memory array.

Therefore, the character address required to select 320 characters respectively is 9 bits, and the column address required for selecting 240 columns is 8 bits. On the other hand, the address space ADS which can be represented by the 9-bit character address and the 8-bit column address is 512 characters x 256 columns. Therefore, when the memory capacity of the display memory 206 is set to the size of the display material of one screen of the QVGA liquid crystal panel, as shown in FIG. 2, there is an unused address space.

In the liquid crystal control driver 200 of the present embodiment, the area of the character direction in the address space is used, and the memory area 206a having the spare memory line is used to constitute the display memory 206 and the rescue circuit 230. . Furthermore, in the present embodiment, the preset value of the rescue information setting circuit (fuse circuit) is allocated in the unused address area in the address space, indicating the bit not allocated to the area of the spare memory area. site.

Thereby, it is not necessary to control the control circuit for selecting the normal memory line and the control circuit for selecting the reserve memory line (hereinafter referred to as a redundant character) of the rescue memory area 206a to be replaced with the defective bit, respectively. The circuit also does not need to generate control signals to enable or disable redundant characters. The reason is explained using the fourth and fifth figures.

In the following description, the rescue memory area 206a is provided with a redundant character of 4 characters, and can be replaced with a regular memory line by a unit of 2 characters. The replacement in units of 2 characters is because when a defect occurs in the memory array due to foreign matter adhering, it usually spans 2 characters, and the rescue can be effectively performed by the small-scale rescue circuit.

In Fig. 4, like the general-purpose RAM, the data memory area is used as the entire address space, so that there is no unused address space, and the relationship between the character selection address and the rescue information in the memory is indicated. Further, Fig. 5 is a view showing the relationship between the character selection address and the rescue information in the display memory of the liquid crystal drive controller of the embodiment.

In addition, in FIGS. 4 and 5, AD8~AD0 of the character selection address field indicates the elements of the character selection address. Further, "9'h" of the character selection address field is a hexadecimal representation of the ninth carry code of the octet, and "8'h" is a binary code representation of the octet. The rescue address is one bit less because it is replaced by a 2-character unit as described above, and as a 9-bit when it is replaced by a 1-character unit. In the fourth figure, "8'bXXXXXXXX" of the second field from the right side indicates that it can be any binary code.

According to FIG. 4, when the data memory area fills the entire address space, the rescue address corresponding to any one of the characters must be set to the fuse circuit, so that the rescue address has no space at all. Therefore, in addition to the fuse circuit for setting the rescue address, it is necessary to have a fuse circuit in which the rescue address is set to be valid or invalid.

On the other hand, if there is an unused address space in the memory, as shown in Fig. 5, a redundant character is allocated to the unused address space, whereby the normal character can be selected in the same operation. At the same time, when the rescue is not performed, there is no area allocated to the spare memory area in the unused address area in the address space, so the address indicated here is set to the fuse circuit.

This address does not have a corresponding memory in the address space, so even if this address is input into the memory, the memory will not operate. Therefore, it is known that it is not necessary to set the redundant character to a valid or invalid fuse circuit or control (actuation signal) signal. Further, if the address set when the rescue is not performed is taken as the preset value of the fuse circuit, and the preset value is, for example, "8'b11111111" in the initial state, the fuse is not required when the rescue is not performed. The advantages of the setting of the wire circuit.

Fig. 6 shows a configuration example of the rescue circuit 230, and Fig. 7 shows the operation timing thereof.

Although not shown in FIG. 1, the address generation circuit 210 is provided with an address counter 210a that generates the address when the display memory 206 is read or written by a microcomputer or the like; and for display of the liquid crystal panel, An address counter 210b that generates an address when the display material is read from the memory 206 is generated. In the rescue circuit 230, two comparison circuits 231a and 231b are provided corresponding to the two address counters 210a and 210b, and the addresses AC[16~8]P and CGAD[16~8 generated by the respective counters are input. ]P.

Further, the rescue circuit 230 is provided with a latch circuit 232 that takes in and receives the defective addresses FRADA[16-8]N and FRADB[16-8]N set in the rescue information setting circuit 240. The rescue information setting circuit 240 is configured by a fuse, a non-volatile memory, or the like, which is a programmable person after manufacture, and can maintain a set state even if the voltage is turned off once set; in this embodiment, it can be set. Two 9-bit characters select the upper octet of the address. By setting the upper 8 bits, it is easy to replace them in 2 character units.

The inverted defect addresses FRADA[16~8]P and FRADB[16~8]P taken in by the latch circuit 232 are supplied to the comparison circuits 231a and 231b to be compared with the address counter 210a. The upper address 8-bit AC[16~9]P and CGAD[16~9]P in the addresses AC[16~8]P and CGAD[16~8]P generated by 210b are compared.

Subsequent to the comparison circuits 231a, 231b, a replacement circuit 233 is provided. When the comparison results are inconsistent, AC[16~9]P, CGAD[16~9]P are passed as they are; when the comparison result is the same, the AC is replaced. [16~9]P, CGAD[16~9]P, the output selects the redundant address of the long character Y320, Y321 or Y322, Y386 upper 8 bits.

In place of the 8-bit address outputted by the circuit 233, the 1-bit AC[8] or CGAD[8] input to the comparison circuit is added, and the address of the 9-bit element is latched in the latch circuit. 234a or 234b. Then, by the selector 235 of the subsequent stage, the address latched to any one of the latch circuits 234a or 234b is selected, latched to the latch circuit 236, and supplied to the decoding driver DEC of the display memory 206. decoding. As a result, among the word lines Y0 to Y323 in the display memory 206, one word line corresponding to the decoded address is selected.

In the liquid crystal control driver 200 of this embodiment, if a defect bit in the display memory 206 is found by a probe inspection or the like performed at the last process of the process, the address of the memory row including the defective bit is The defect information setting circuit 240 is set as the defect address. Then, after being installed in the system, once the power is turned on, the defective address is read from the rescue information setting circuit 240, and the person is taken into the latch circuit 232 in the rescue circuit 230 and held until the power is turned off. If the rescue information setting circuit 240 is a circuit that continues to output during power-on, the latch circuit 232 can be omitted.

In the rescue information setting circuit 240, the state in which the defective address is not set is "00000000", so the preset value outputted by the latch circuit 232 is inverted and is "8'b11111111". When the initial state of the rescue information setting circuit 240 in which the defective address is not set is "11111111", it is supplied to the comparison circuit as the preset value "8'b11111111" without being inverted by the latch circuit 232. The rescue information setting circuit 240 of this embodiment does not set information indicating whether or not rescue is to be performed. Thus, there is no need for a control signal that validates or invalidates a regular character or a preliminary character (long character) based on such information.

Comparing Fig. 6 with Fig. 10 showing the previous redundant circuit, it can be seen that in Fig. 10, the control circuit and decoder of the normal memory row or column are selected, and the spare memory row or column for selecting the defective bit replacement is selected ( The control circuit and decoder of the lengthy memory are separate. Therefore, when accessing a normal memory row or column, and accessing a spare memory row or column, the readout speed and the like have different operational characteristics, and the timing design of the memory peripheral circuit is difficult. On the other hand, the redundant circuit of FIG. 6 commonizes the decoding driver for selecting a normal character and the decoding driver for selecting a redundant character, so that the readout speed and the like are the same when selecting one character, and the memory is the same. The timing design of the peripheral circuit is also relatively simple.

Fig. 7 shows the operation timing of the rescue circuit 230. The address from the address counter 210a that generates the write address causes the action of the rescue circuit 230, and the address from the address counter 210b that generated the read address causes the action of the rescue circuit 230 to be the same, so only The address from the address counter 210a is shown to cause the action of the rescue circuit 230.

As shown in FIG. 7, when the address AC[16~8]P from the address counter 210a coincides with A of the two defective addresses A, B set in the rescue information setting circuit 240, the comparison circuit 231a The output changes to a high level (timing t1). Thereby, the address output from the replacement circuit 233 is selected as the redundant character A (timing t2).

Therefore, the address of the redundant character A is latched to the latch circuit 234 of the subsequent stage as in the rise of the latch timing signal ACLATP (timing t3). According to FIG. 7, it is understood that in this embodiment, the circuit t is designed to have a certain margin between the timing t2 of switching the redundant character A and the rising timing t3 of the latch timing signal ALATP. It can prevent erroneous actions, so the timing design is simpler.

Further, in the sixth diagram, in relation to the operation of the rescue circuit 230, a circuit 250 for controlling the write prevention is collectively shown. The circuit for controlling the write prevention is originally provided when the window display shown in FIG. 3 is partially displayed on the display screen of the liquid crystal panel, in order to prohibit data writing to the area other than the window. Further, the write prevention control circuit 250 shown in Fig. 6 is conceptually represented, and is not limited to such a configuration.

261 is a register for setting the start address of the window (VSA, HSA), and 262 is a register for setting the end address of the window (VEA, HEA); these registers are configured to be the maximum displayable display screen. That is, the entire memory area of the memory 206 is displayed. The window setting registers 261 and 262 are provided as part of the control register CTR of FIG. 1 or as a separate register in the control unit 201.

The write prevention control circuit 250 is provided with a comparison circuit 251a which sets the addresses VSA, VEA set in the window setting registers 261, 262, and the address AC [16~8] P from the address counter 210a. Compare it. The comparison circuit 251a determines whether the write address is in or outside the area displayed by the window, and outputs a high level when the write address is in the window display area, and outputs when the write address is outside the window display area. Low level.

Further, the write prevention control circuit 250 is provided with a comparison circuit 251b that detects the highest upper bit AC16 of the address AC[16~8]P and whether the 3-bit AC14 becomes "1,1" from the upper level. ". The comparison circuit 251b determines whether the write address is inside or outside the address space. Referring to Fig. 5, it is known that in the display memory of this embodiment, AC16 and AC14 become address areas of "1, 1", which means that the address space is not used. The comparison circuit 251b outputs a high level when the write address is outside the unused address space, and outputs a low level when the write address is in the unused address space.

Although not particularly limited, the outputs of the comparison circuit 251a and the comparison circuit 251b are input to the OR gate 252, and the output signal VAE_Pt of the OR gate 252 is supplied to the display memory 206 via the AND gate 253 and the latch circuit 254. The driver (not shown); when VAE_Pt changes to the low level, the write operation is not performed. Further, the signal HAE_P input to the other terminal of the AND gate 253 is a signal of a write prevention control circuit (not shown) having the same structure and provided from the corresponding column side.

Fig. 8 shows an example of the structure of the replacement circuit 233. Further, the replacement circuit 233 has a circuit corresponding to the address counter 210a and the comparison circuit 231a, and a circuit corresponding to the address counter 210b and the comparison circuit 231b. However, these are the same structure, so only one side is shown, and the other side is omitted. .

The replacement circuit 233 of Fig. 8 is constituted by selectors SEL1 to SEL8. Each of the selectors is input with a bit from the address address AC[16~9]P of the address counter 210a, and each of the two redundant addresses RA_A[16~9] and RA_B[16~9]. Then, in these inputs, the address matching signals ACRWAE_P and ACRWBE_P from the comparison circuit 231a are matched, and any one of the selectors SEL1 to SEL8 is selected as ACCP [16~9].

Specifically, if the address matching signal ACRWAE_P becomes a high level indicating consistency, the redundant address RA_A[16~9] is selected and output. Further, if the address matching signal ACRWBE_P becomes a high level indicating consistency, the redundant address RA_B [16 to 9] is selected and output. When ACRWAE_P and ACRWBE_P are simultaneously low level indicating inconsistency, the address AC[16~9]P from the address counter 210a is selected for output.

The bits of the redundant address RA_A[16~9] and RA_B[16~9] can be inverted by, for example, the input being pulled up to the power supply voltage Vcc, or the input being pushed down to the ground point GND. To generate. Or directly connect the input terminal to Vcc or GND by the circuit form of the selectors SEL1~SEL8. The redundant address is fixed from the beginning, so it is not necessary to have a programmable circuit such as the rescue information setting circuit 240.

Moreover, in the rescue circuit using the replacement circuit of this embodiment, when the rescue information setting circuit 240 does not set the defect address, the address matching signals ACRWAE_P and ACRWBE_P do not become high level, so the address is not performed. Replace.

Fig. 9 shows another configuration example of the replacement circuit 233. Further, the replacement circuit 233 has a circuit corresponding to the address counter 210a and the comparison circuit 231a, and a circuit corresponding to the address counter 210b and the comparison circuit 231b. However, these are the same structure, so only one side is shown, and the other side is omitted. .

The replacement circuit 233 of Fig. 9 is composed of a combinational logic circuit composed of a plurality of logic gates. In the rescue circuit shown in FIG. 6, the case where the address compared with the comparison circuit 231a is micro-bits is 8-bit, and the replacement circuit 233 formed by the combinational logic circuit corresponding thereto is complicated to be illustrated. Therefore, for the sake of easy understanding, FIG. 9 illustrates a replacement circuit 233 when the address is micro 4-bit. In addition, the following description of FIG. 9 is used as the defect addresses FADA3 to FADA0 and FADB3 to FBDA0 set in the rescue information setting circuit 240 as "0001" and "1010", and the redundant addresses are "1100" and "1101". .

If the address ADIN3~ADIN0 input to the comparison circuit 231a by the address counter 210a coincides with the defect addresses FADA3~FADA0, the defect address A coincidence signal ACRWAE_P will be "1"; if it is consistent with FADB3~FBDA0, the defect bit The address B coincidence signal ACRWBE_P will be "1". When these signals ADIN3~ADIN0, ACRWAE_P, and ACRWBE_P are input to the replacement circuit 233 formed by the combinational logic circuit, as shown in the first table below, when ACRWAE_P and ACRWBE_P are simultaneously "0", ADIN3~ADIN0 will Output AD3~AD0 as they are.

Also, when ACRWAE_P is "1", the redundant address "1100" is output as AD3~AD0, and when ACRWBE_P is "1", the redundant address "1101" is output as AD3~AD0. That is, the truth table of the first table is satisfied, and the logic of the logic gate circuits LG1 to LG4 of the circuit 233 is formed. Further, the logic gate circuits LG1 to LG4 shown in Fig. 9 are an example, as long as the same logic is available.

In the first table, when any one of the defective address matching signals ACRWAE_P or ACRWBE_P is "1", the bit to be output "1" is the logic gate circuit LG3 (LG4); the defect address matching signal ACRWAE_P or ACRWBE_P is used. When one is "1", the bit to output "0" uses the logic gate circuit LG2. Further, when the defect address coincidence signal ACRWAE_P is "1" and ACRWBE_P is "0", "0" is output, and when the defective address coincidence signal ACRWAE_P is "0" and ACRWBE_P is "1", a bit of "1" is output. Yuan, use the logic gate circuit LG1.

On the contrary, when the defect address coincidence signal ACRWAE_P is "0" and ACRWBE_P is "1", "0" is output, and the defective address coincidence signal ACRWAE_P is "1" and when the ACRWBE_P is "0", "1" is output. The bit can be used as long as the inverter input in the logic gate circuit LG1 of FIG. 9 is not ACRWBE_P but ACRWAE_P. By using the replacement circuit 233 constituted by the combinational logic circuit of Fig. 9, it is not necessary to provide a circuit for generating the redundant address RA_A [16-9], RA_B [16-9].

The invention made by the inventors of the present invention has been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the invention.

For example, in the above embodiment, the provision of the memory area is set as a redundant character to perform character rescue; however, the spare memory area may be set as a redundant column to perform column rescue. Further, in the embodiment, although the rescue is performed by replacing the two-character unit, the rescue may be performed by replacing the unit of one character or three or more.

Furthermore, the present invention is applicable to a liquid crystal control driver capable of outputting a driving signal for a liquid crystal panel, and can be applied to a display memory in which two screens of memory are stored in a display memory, or for a superimposed display, and has a ratio of one screen. The display memory of the memory area in which the data storage area is larger.

Industrial availability

The above description mainly explains the invention completed by the inventors, and is applicable to the field of use of the background, that is, the case where the liquid crystal control driver that outputs the drive signal for the QVGA liquid crystal panel is output. The present invention is not limited thereto, and a liquid crystal control driver that outputs a drive signal for a liquid crystal panel other than the QVGA may be used for a display control semiconductor integrated circuit of a display device other than a liquid crystal such as an organic electroluminescence display panel. .

200. . . Display control semiconductor integrated circuit (liquid crystal control driver)

201. . . Control department

202. . . Clock signal generation circuit (pulse generator)

203. . . Timing control circuit

206. . . Display memory (with RAM)

207. . . Bit processing circuit

210. . . Address generation circuit

230. . . Rescue circuit

231. . . Comparison circuit

232. . . Latch circuit

233. . . Replace the circuit

234. . . Latch circuit

235. . . Selector

240. . . Rescue information setting circuit (fuse circuit)

250. . . Write blocking control circuit

251. . . Comparison circuit

261, 262. . . Window display area setting register

[Fig. 1] is a block diagram showing an embodiment of a liquid crystal control driver incorporating a RAM and a rescue circuit.

[Fig. 2] is an explanatory view showing a relationship between a memory area of a memory and an address space in the liquid crystal drive controller of the embodiment.

[Fig. 3] is an explanatory diagram showing the relationship between the display screen and the window area when the window display is performed.

[Fig. 4] As with the general-purpose RAM, the data memory area is used as the entire address space, so that there is no unused address space, and an explanatory diagram showing the relationship between the character selection address and the rescue information in the memory.

[Fig. 5] is an explanatory diagram showing the relationship between the character selection address and the rescue information in the display memory of the liquid crystal drive controller of the embodiment.

[Fig. 6] A block diagram showing a configuration example of a rescue circuit in the liquid crystal drive controller of the embodiment.

[Fig. 7] A timing chart showing the operation timing of the rescue circuit in the liquid crystal drive controller of the embodiment.

[Fig. 8] A block diagram showing a configuration example of a replacement circuit in the rescue circuit of the embodiment.

[Fig. 9] A block diagram showing another configuration example of a circuit in place in the rescue circuit of the embodiment.

[Fig. 10] A block diagram showing a redundant circuit configuration used in a general-purpose RAM.

200. . . Display control semiconductor integrated circuit (liquid crystal control driver)

201. . . Control department

202. . . Clock signal generation circuit (pulse generator)

203. . . Timing control circuit

204. . . System interface

205. . . External display interface

206. . . Display memory (with RAM)

206a. . . Rescue area

207. . . Bit processing circuit

208. . . Write data latch

209. . . Read data latch

210. . . Address generation circuit

211. . . Latch circuit

212. . . Latch circuit

213. . . AC circuit

214. . . Latch circuit

215. . . Source line driver circuit

216. . . Liquid crystal drive level generating circuit

217. . . Gray scale voltage generating circuit

218. . . Gamma adjustment circuit

219. . . Gate line driver circuit

220. . . Scan data generation circuit

221. . . Internal reference voltage generating circuit

222. . . Internal logic power regulator

230. . . Rescue circuit

231. . . Comparison circuit

232. . . Latch circuit

233. . . Replace the circuit

234. . . Latch circuit

235. . . Selector

240. . . Rescue information setting circuit (fuse circuit)

Claims (6)

A display integrated semiconductor integrated circuit having a memory area which is smaller than an n-th orientation address space represented by an address formed by a binary code of n (n is an integer) bit, and is internally mounted a display memory having a readable and writable memory for displaying data in the memory area; wherein the display memory is configured to have a preliminary memory area in addition to a normal memory area of the memory display data, and include the display memory The range of the defect is replaced with the pre-memory area, and the rescue circuit for performing the defect rescue is provided, and the rescue information setting means for setting the address information including the range of the defect in the display memory is supplied to the display memory. a first address counter of an input address for writing data to the display memory, and an input address supplied to the display memory for reading from the display memory The second address counter of the address for reading the data; the rescue circuit includes the address generated by the first address counter and the save address a first address comparison circuit for comparing the addresses of the information setting means, the second address comparison circuit for comparing the address generated by the second address counter with the address set in the rescue information setting means, and When the address is matched by the first or second address comparison circuit, the input address supplied to the display memory is replaced with an address replacement circuit for designating the address of the preliminary memory area; The address of the preliminary memory area is set in the address space outside the address range of the normal memory area; and the rescue information setting means, when the display memory includes address information of a range of defects When it is not set, in the address space, it is a state indicating an address other than the address range of the normal memory area and the preliminary memory area. The display integrated semiconductor integrated circuit according to the first aspect of the invention, wherein the address generated by the first address counter is detected, and whether the third bit is within the address range of the normal memory area And an address comparison circuit; and when the third address comparison circuit determines that the address generated by the first address counter is not within the address range of the normal memory area, generating display prohibition on the display memory The data is written to the signal and the output is written to the blocking control circuit. The semiconductor integrated circuit for display control according to the first or second aspect of the invention, further comprising: an address setting register for setting a region for displaying a window on a display screen; and an address of the preliminary memory region , is set outside the address range that can be set by the above-mentioned scratchpad. The display integrated semiconductor integrated circuit according to claim 1 or 2, wherein the display memory system includes an address decoder, and the address decoder is configured to perform the normal according to a common input address. The selection of the memory area and the selection of the above-mentioned preliminary memory area. The display integrated semiconductor integrated circuit according to claim 1 or 2, wherein the address substitution circuit is constituted by a complex logic gate circuit, and is configured by a combination logic circuit. The circuits are respectively input to the addresses of the first address comparison circuit and the second address comparison circuit, and the respective output signals of the first address comparison circuit and the second address comparison circuit are used as inputs, and are available. The logical action output specifies the address of the above-mentioned preliminary memory area. The semiconductor integrated circuit for display control according to the first or second aspect of the invention, wherein the rescue circuit causes the range of defects included in the display memory to be replaced by the read-memory area. The memory area of the display memory of the display line of the device is also performed in units of characters.