JP2005077527A - Drive circuit for image display element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit for an image display element in which the freedom of wiring in a wiring region is enhanced and the freedom of routing of the wiring in the wiring region is facilitated as a result. <P>SOLUTION: A signal line control circuit 5 in a driver IC 10 includes registers 51 to 58 corresponding to c pieces of output terminals 51a to 58a respectively. The registers 51 to 58 correspond one to one to [m/c] pieces of blocks in a memory 45 (m: the number of the output terminals). Each of the registers 51 to 58 includes mask bits and the data indicating whether the respective output terminals in an output terminal group are to be connected to column electrodes in a liquid crystal panel 1 or not is set. When the mask bit is set at "1", a prescribed voltage is output to c pieces of the output terminals regardless of the display data. When the mask bit is set at "0", a column voltage corresponding to the display data is output to the output terminals. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a drive circuit for driving a matrix type image display element in which scanning electrodes and data electrodes are orthogonally arranged.

  A plurality of scanning electrodes (hereinafter referred to as row electrodes) and a plurality of data electrodes (hereinafter referred to as column electrodes) are arranged in a matrix, and a liquid crystal layer as an electro-optical layer is disposed between the row electrodes and the column electrodes. In general, a driving IC (driver IC) is used to drive the arranged matrix type liquid crystal display element (hereinafter referred to as a liquid crystal panel). The output of the driver IC for driving the row electrode is connected to the row electrode of the liquid crystal panel, and the output of the driver IC for driving the column electrode is connected to the column electrode of the liquid crystal panel. A driver IC for driving the row electrodes and a driver IC for driving the column electrodes may be formed as one single-chip IC.

  A selection voltage or a non-selection voltage is applied to the row electrode from the driver IC. When a selection voltage is applied to a certain row electrode, that is, when a certain row is selected, a column voltage corresponding to display data of the selected row is applied to each column electrode from the driver IC. . A difference voltage between the row voltage and the column voltage becomes a driving voltage applied to the liquid crystal layer.

  As a method for mounting the driver IC, there is COG (Chip On Glass) mounting in which the driver IC is mounted on a glass substrate (hereinafter referred to as a substrate) on which a liquid crystal panel is formed. When COG is used, the ITO that forms each column electrode is pulled out so as to be connected to the output terminal of the driver IC on a one-to-one basis on the substrate. For example, as shown in FIG. 7A, a wiring (signal line) made of ITO is formed between the driver IC 11 and the liquid crystal panel 1 in a line-symmetrical manner with a chain line as an axis of symmetry. When the number of column electrodes a in the liquid crystal panel 1 is smaller than the number m of output terminals of the driver IC 11, as shown in FIG. 7B, a outputs at the center of the m output terminals. A signal line is formed between the terminal and each column electrode in the liquid crystal panel 1.

  When the signal line is formed as shown in FIG. 7B, the liquid crystal panel 1 is connected to the liquid crystal panel 1 from the left and right ends of the driver IC 11 as compared with the case where the signal line is formed as shown in FIG. The length of the reaching signal line is longer than the length of the signal line extending from the central portion of the driver IC 11 to the liquid crystal panel 1. As a result, the resistance value of the signal line extending from the left and right ends of the driver IC 11 to the liquid crystal panel 1 is higher than the resistance value of the signal line extending from the center portion of the driver IC 11 to the liquid crystal panel 1. As a result, the voltage applied to the left and right column electrodes in the liquid crystal panel 1 is lowered, and the display quality is deteriorated.

  In order to prevent deterioration of display quality, the width of the signal line from the central part of the driver IC 11 to the liquid crystal panel 1 is increased, or the length of the signal line from the central part of the driver IC 11 to the liquid crystal panel 1 is bothered. Measures such as making it longer are necessary. As a result, in the substrate, a wiring region, which is a region where signal lines are installed, becomes large, and the substrate size becomes large.

  For the purpose of reducing the degree of variation of the resistance value of the signal line, as shown in FIG. 8, when m> a, the output terminal at the center of the driver IC 11 is selected as an unconnected terminal. (For example, refer to Patent Document 1).

JP 2003-186416 A (paragraphs 0038 to 0040, FIG. 1)

  However, in the drive circuit described in Patent Document 1, the variation in the length of the signal line is smaller than in the case shown in FIG. 7B, but two (a / 2) signal lines are provided. In each of the groups, the length of the signal line located at the center of the signal line group is still longer than the length of the signal line located at the left and right ends. Therefore, when the signal line is formed, a measure for reducing variation in the resistance value of the signal line is not completely eliminated.

  In the driver IC, [m−a] output terminals are unconnected terminals to which no signal line is arranged. However, when a general commercially available driver IC is used, [m−a] a] The unconnected terminals of the book are also driven. Therefore, power is unnecessarily consumed in the driver IC.

  Therefore, the present invention further increases the degree of freedom of wiring in the wiring region, facilitates the routing of the wiring in the wiring region, and can further reduce the variation in the length of the signal line between the column electrodes. It is an object to provide a driving circuit for an element.

  The drive circuit of the image display element according to the present invention is selected so as not to overlap with the output terminals in the other output terminal groups, and is c (natural number of 1 ≦ c <m) output terminals arranged in a spatially continuous manner. Connection state indicating means for setting data indicating whether to connect each output terminal in the output terminal group to a column electrode in the image display element, corresponding to each of the output terminal group consisting of Display data storage control means for storing display data in an area in the storage means corresponding to the output terminal connected to the column electrode according to the data set in the instruction means.

  The display data storage control means, for example, when display data is input, an address indicating an area in the storage means corresponding to the output terminal in the output terminal group set in the connection state instruction means to be connected to the column electrode Among them, the address next to the address where the display data was written immediately before is generated as the write address.

  It is preferable to include switching prevention means for stopping switching of the circuit elements between the output terminals in the output terminal group set in the connection state instruction means as not being connected to the column electrodes and the storage means.

  The switching prevention means fixes the output of the drive element to the output terminal in the output terminal group that is set to the connection state instruction means not connected to the column electrode, and performs display data output from the storage means and AC drive It is preferable that one or more of the output inversion signal instructing the AC switching and the clock signal for latching the signal based on the display data be blocked.

  The present invention is particularly effective when the drive circuit is composed of a one-chip IC and is mounted by COG.

  According to the present invention, the degree of freedom of wiring in the wiring region can be further increased, and wiring in the wiring region is facilitated. In particular, there is an effect that the variation in the length of the signal line between the column electrodes can be further reduced.

  In addition, when the switching prevention means for stopping the switching of the circuit element between the storage means and the output terminal not connected to the column electrode is provided, the power consumption in the drive circuit can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a conceptual diagram for explaining the gist of the present invention. As shown in FIG. 1, a simple matrix type liquid crystal panel 1 in which an STN liquid crystal layer as an electro-optic layer (not shown) is arranged between a row electrode (not shown) and a column electrode (not shown). Are formed on the substrate 100, and the drive circuit 10 is mounted on the substrate 100. Since the drive circuit 10 can be realized by a one-chip driver IC, the drive circuit 10 is hereinafter expressed as a driver IC 10. The combination of the liquid crystal panel 1 and the driver IC 10 may be hereinafter referred to as a liquid crystal display device.

  The driver IC 10 includes a memory 45 as a storage unit. Display data is written in the memory 45 from an MPU outside the liquid crystal display device. The driver IC 10 includes a signal line control circuit 5. In this example, the number of output terminals m of the driver IC 10 is 64, and the memory 45 can store display data of 64 words. Each address in the memory 45 has a one-to-one correspondence with one of the output terminals.

  Here, an example is given in which the signal line control circuit 5 collectively controls eight output terminals arranged in succession. Note that the signal line control circuit 5 collectively controls c (c ≧ 1) output terminals when a column voltage corresponding to display data is output to the output terminal or a predetermined voltage is applied regardless of the display data. Whether to output to the output terminal is determined collectively in units of c.

  The signal line control circuit 5 includes registers 51 to 58 corresponding to c (here, c = 8) output terminals 51a to 58a. Each of the output terminals 51a to 58a corresponds to an output terminal group composed of c output terminals that are arranged spatially (positionally) continuously and do not overlap with output terminals in other output terminal groups. The registers 51 to 58 correspond to [m / c] blocks in the memory 45 on a one-to-one basis. Therefore, in the present embodiment, the memory 45 is divided into # 1 block to # 8 block having consecutive addresses. Each block has an area for storing eight display data.

  Each of the registers 51 to 58 includes a mask bit, and realizes a connection state instructing unit in which data indicating whether to connect each output terminal in the output terminal group to the column electrode in the liquid crystal panel 1 is set. For example, when the mask bit is set to “1” in a register, a predetermined voltage is output to c output terminals in the output terminal group corresponding to the register regardless of display data. When the mask bit is set to “0” in the register, the column voltage corresponding to the display data is output to the c output terminals in the output terminal group corresponding to the register.

  FIG. 1 illustrates a case where m = 64 and the number of column electrodes a in the liquid crystal panel 1 is 32. Then, 32 output terminals from the driver IC 10 are connected to the liquid crystal panel 1 by a signal line made of ITO every 8 lines. In this case, display data is stored in blocks # 1, # 3, # 6, and # 8 in the memory 45 so that signal lines are formed in line symmetry, and mask bits of the registers 51, 53, 56, and 58 are stored. Is set to “0”, and the mask bits of the registers 52, 54, 55, and 57 are set to “1”.

  Next, a specific circuit example of the drive circuit of the present invention will be described. FIG. 2 is a block diagram showing the drive circuit (driver IC 10) together with the liquid crystal panel 1. As shown in FIG. In the configuration shown in FIG. 2, the MPU interface unit 41 is a circuit that distributes commands and data from MPUs outside the driver IC 10. The command decoder 42 is a circuit that decodes a command received from the MPU via the MPU interface unit 41 and outputs a decoding result to the controller (control circuit) 43. The controller 43 is a circuit that generates a signal indicating drive timing and a setting signal such as a drive voltage ratio and a contrast voltage value. In addition, the controller 43 includes registers 51 to 58. The oscillation circuit 44 is a circuit that generates a clock signal that defines driving timing and supplies the clock signal to the controller 43 and other circuits. The memory 45 is a RAM for temporarily storing display data received from the MPU via the MPU interface unit 41. The controller 43 also manages the write address and read address of the memory 45. The power supply circuit 8 is a circuit that generates liquid crystal driving voltages (drive voltages) at a plurality of voltage levels and supplies them to the row driver 2 and the column driver 3.

  The row electrodes are driven line-sequentially by the row driver 2. A voltage corresponding to display data is applied to the column electrode by the column driver 3.

  The controller 43 performs at least FLM (first line marker) indicating the start of one frame, LP (latch pulse) indicating switching of a driving row (selected row), and AC driving for the row driver 2 and the column driver 3. M (output inversion signal) for instructing alternating current and / DOFF (display off signal) which is a non-display instruction signal are output. When the FLM is input, the row driver 2 switches the driving row according to the LP input subsequently. When LP is input, the column driver 3 captures display data from the memory 45 and applies a voltage corresponding to the captured display data to the column electrodes. Note that “/” indicates low active.

  Further, the controller 43 outputs the mask bits (MB) stored in the registers 51 to 58 to the column driver 3. It is not necessary to supply MB to the row driver 2.

As shown in the explanatory diagram for explaining an example of the drive voltage in FIG. 3, V ₄ is used as a selection voltage (drive voltage output when the row driver 2 is selected) at the time of AC drive positive polarity drive. V ₃ is used as and positive drive during the OFF drive voltage of negative polarity at the time of driving on the drive voltage (drive voltage column driver 3 outputs when on display) (drive voltage column driver 3 outputs to the OFF state display) . V ₂ is used as a non-selection voltage (driving voltage line driver 2 is output when non-selected). V ₁ was used as an on drive voltage and off the drive voltage of the negative polarity driving during positive drive. V ₀ is used as a selection voltage during negative polarity driving. In the present embodiment, when M is at a low level, it is during positive polarity driving. Note _that it is _{V 4> V 3> V 2} > V 1> V 0.

  Next, a method of storing display data input from the MPU in the memory 45 will be described with reference to the flowchart of FIG. FIG. 4 shows a process of writing display data for one line into the memory 45. The MPU outputs a command for setting (setting “1”) or resetting (setting “0”) the mask bit (MB) of the register 5 of the controller 43 to the driver IC 10 in advance. The controller 43 knows that the command has been input from the decoding result of the command decoder 42, and sets or resets the MB in the registers 51 to 58 according to the command. In the example shown in FIG. 1, the mask bits of the registers 51, 53, 56, and 58 are set to “0”, and the mask bits of the registers 52, 54, 55, and 57 are set to “1”.

  Further, the controller 43 has an address pointer, for example, and sets the contents of the address pointer to the head address of the first block among the blocks of the memory 45 corresponding to the register whose MB is “0” (step S1). In the example shown in FIG. 1, the head address of the # 1 block is set as the address pointer.

  Each time display data is input from the MPU, the controller 43 outputs the contents of the address pointer as a write address to the memory 45 and increases the contents of the address pointer by one address (steps S2 and S3). When the contents of the address pointer are updated c times (eight times in this embodiment), that is, when the process of step S3 is executed C times (step S4), the contents of the address pointer are stored in the register whose MB is “0”. The start address of the next block among the corresponding blocks of the memory 45 is set (step S5). In the example shown in FIG. 1, the head address of block # 3 is set as the address pointer.

  Until the writing of the display data for one line is completed (step S6), the processes of steps S2 to S5 are repeatedly executed. And the process of step S1-S6 is performed again about the display data of the next line.

  Through the processing in steps S1 to S6, the display data input from the MPU is sequentially written in the block of the memory 45 corresponding to the register whose MB is “0”. In the example shown in FIG. 1, display data is written in blocks # 1, # 3, # 6, and # 8. When the display data is input from the MPU in the above processing, the controller 43 operating as the display data storage control means connects the output terminals in the output terminal group set in the register to be connected to the column electrodes. Of the addresses indicating the area in each block in the corresponding memory 45, the address next to the address where the display data was written immediately before is generated as the write address.

  The control (see FIG. 4) for writing the display data to the skipped block of the memory 45 corresponding to the register whose MB is “0” is executed by the controller 43 in the driver IC 10. Therefore, the MPU does not need to execute address control for writing display data to a skipped block. That is, the MPU can output the display data to the driver IC 10 as writing the display data to consecutive addresses without being conscious of writing the display data to the skipped blocks. In other words, each block corresponding to the register whose MB is “0” can be shown to the MPU as a continuous area. Therefore, it is not necessary to change the display data output control of the MPU from the conventional control that does not introduce MB.

  FIG. 5 is a block diagram showing a configuration example of the column driver 2 together with the memory 45. FIG. 5 shows only a portion corresponding to one output terminal in the column driver 2, but the circuits (excluding the memory 45) shown in FIG. 5 correspond to all output terminals. Is provided.

  In the column driver 2, the OR circuit (OR circuit) 31 passes the display data read from the memory as it is when the MB is “0”. When MB is “1”, the value of the display data output from the OR circuit 31 is fixed. The display data output from the OR circuit 31 is converted into data corresponding to the gradation by the gradation control circuit 32.

  The inverting OR circuit (NOR circuit) 33 allows M (output inversion signal) to pass when MB is “0”, but fixes the output when MB is “1”. The data output from the gradation control circuit 32 is subjected to an exclusive OR operation with M output from the inverting OR circuit 33 by an exclusive OR circuit (EXOR circuit) 34 and output.

  A signal obtained by logically inverting MB by the inverting circuit 36 is input to one input of the logical product circuit (AND circuit) 35. The clock signal (CLK) from the oscillation circuit 44 is input to the other input of the AND circuit 35. The AND circuit 35 passes CLK only when MB is “0”. The latch circuit 37 latches the output of the exclusive OR circuit 34, that is, the data affected by M (output inversion signal) at the rising edge of the output of the AND circuit 35 and outputs the latched data to the OR circuit 38.

MB is input to the other input of the OR circuit 38. The output of the OR circuit 38 is connected to an analog switch 39 as a drive element that applies a drive voltage of either V ₃ or V ₁ to the output terminal. Analog switch 39 has an input and outputs a low voltages V ₁ when a high level, outputs the high voltage V ₃ when the input is at a low level. Therefore, when the MB is "0", although the analog switch 39 outputs a voltage corresponding to the output of the latch circuit 37, when the MB is "1", always outputs the low voltage V _1.

Incidentally, when using the V _{SS (ground)} as voltage applied to the column electrodes is preferably MB fixes the output level is always V _SS when it is "1". In FIG. 5, the circuit portion 51 surrounded by a broken line, that is, the OR circuit 31, the inverting OR circuit 33, the AND circuit 35, the inverting circuit 36, and the OR circuit 38 may not be connected to the column electrode. This corresponds to switching prevention means for stopping switching of circuit elements between the output terminals in the output terminal group set in the register and the memory 45. Further, a combination of the circuit portion 51 and the registers 51 to 58 provided in the controller 43 corresponds to the signal line control circuit 5 shown in FIG.

  As shown in FIG. 1, MB is set to “1” in the register corresponding to the output terminal group whose output terminal is not connected to the column electrode of the liquid crystal panel 1. Therefore, it is not necessary to drive the output terminals in the output terminal group corresponding to the register whose MB is set to “1” and the circuit elements reaching those output terminals. Therefore, as described above, the OR circuit 31 fixes the output to “1” regardless of the content of the display data output from the memory 45 when the MB is “1”. Therefore, when MB = 1, logic changes (change from high level to low level and change from low level to high level) do not occur in the subsequent circuit elements, so that power consumption is reduced. Further, the inverting OR circuit 33 fixes the output to “0” when MB is “1”. Therefore, the passage of M (inverted output signal) is blocked, and in subsequent circuit elements, switching for alternating current does not occur, and power consumption is reduced.

  Further, the AND circuit 35 fixes the output to “0” when the MB is “1”. Therefore, the passage of CLK is prevented, and switching based on the clock signal does not occur in the subsequent circuit elements, so that power consumption is reduced. Further, when the MB is “1”, the OR circuit 38 fixes the output voltage of the output terminal to a low value and reduces the power consumption in the analog switch 39.

  As described above, the driver IC 10 of the present embodiment fixes the output voltage to a low value when the MB is “1”, that is, when the output terminal does not drive any column electrode, and the memory The power consumption in the data path from 45 to the analog switch 39 can be reduced. When all of the OR circuit 31, the inverting OR circuit 33, the AND circuit 35, and the inverting circuit 36 are provided, the effect of reducing the power consumption in the data path from the memory 45 to the analog switch 39 is great. However, if one or more of these circuit elements are provided, power consumption in the data path from the memory 45 to the analog switch 39 can be reduced.

  FIG. 6 is an explanatory diagram illustrating an example of a method of forming signal lines between the liquid crystal panel 1 and the driver IC 10 mounted on the substrate in the COG according to the present embodiment. As shown in FIG. 6, c signal line groups can be connected to the output terminal of the driver IC 10 in a jumping manner. That is, the output terminal of the driver IC 10 can be connected / unconnected to the liquid crystal panel 1 in units of c. Therefore, the degree of freedom of wiring in the wiring area is increased, and wiring in the wiring area is facilitated. In addition, since variations in the length of each signal line can be reduced, the wiring area can be reduced and the substrate size can be reduced.

  In the above embodiment, the case where the driver IC 10 having the configuration illustrated in FIGS. 2 and 5 is used as an example. However, such a configuration is an example, and output terminals in other output terminal groups. Data corresponding to each of the output terminal groups composed of c (c ≧ 1) output terminals selected so as not to overlap with each other and spatially continuous, and each output terminal in the output terminal group is A register in which data indicating whether or not to connect to the column electrode in the liquid crystal panel 1 is set, and display in an area in the storage means corresponding to the output terminal connected to the column electrode according to the data set in the register If a circuit corresponding to a control circuit for storing data is provided, a driver IC having a configuration different from the configuration illustrated in FIGS. 2 and 5 or a configuration partially different from the configuration illustrated in FIGS. The present invention can be applied with.

  In the above embodiment, the driving circuit for driving the simple matrix type liquid crystal panel 1 having the STN liquid crystal layer as the image display element is taken as an example. However, the active matrix type liquid crystal panel and the organic EL panel are driven. The present invention can also be applied to a driver circuit.

  When an image display element such as a liquid crystal panel and a drive circuit are mounted on a substrate, the present invention improves the connection flexibility of wiring between the drive circuit and the image display element in the substrate, and Stops driving empty output terminals at, contributing to lower power consumption.

The conceptual diagram for demonstrating the summary of this invention. The block diagram which shows a drive circuit with a liquid crystal panel. Explanatory drawing for demonstrating an example of a drive voltage. The flowchart which shows the method of storing display data in memory. The block diagram which shows the structural example of a column driver with memory. Explanatory drawing which shows an example of the method of forming the signal line between a liquid crystal panel and driver IC. Explanatory drawing which shows how to form the signal line between the conventional liquid crystal panel and driver IC. Explanatory drawing which shows how to form the signal line between the conventional liquid crystal panel and driver IC.

Explanation of symbols

1 liquid crystal panel 2 row driver 3 column driver 5 signal line control circuit 10 driver IC (drive circuit)
39 Analog switch (drive element)
43 Controller (control circuit)
45 Memory 51-58 Register 100 Substrate (glass substrate)

Claims (5)

It has m (m: natural number) output terminals, and has storage means for storing display data in a region corresponding to each output terminal, and a plurality of scan electrodes to which a selection voltage or a non-selection voltage is applied and display data In a drive circuit for applying a drive voltage based on display data stored in the storage unit to a column electrode in an image display element in which a plurality of column electrodes to which a corresponding voltage is applied are arranged orthogonally,
Data corresponding to each output terminal group consisting of c (natural number of 1 ≦ c <m) output terminals selected so as not to overlap with output terminals in other output terminal groups and arranged spatially continuously. A connection state indicating means for setting data indicating whether or not each output terminal in the output terminal group is connected to a column electrode in the image display element;
Display data storage control means for storing display data in an area of the storage means corresponding to an output terminal connected to a column electrode in accordance with data set in the connection state instruction means. A driving circuit for the image display element. When the display data is input, the display data storage control means is an address indicating an area in the storage means corresponding to the output terminal in the output terminal group set in the connection state instruction means to be connected to the column electrode. 2. The drive circuit for an image display element according to claim 1, wherein an address next to an address at which display data is written immediately before is generated as a write address. The switching prevention means which stops switching of the circuit element between the output terminal in the output terminal group set to the connection state instruction | indication means that it is not connected to a column electrode, and a memory | storage means is provided. Drive circuit for the image display element. A driving element for supplying a driving voltage to the output terminal;
The switching prevention means fixes the output of the drive element with respect to the output terminal in the output terminal group set in the connection state instruction means as not being connected to the column electrode,
Blocking passage of any one or more of display data output from the storage means, an output inversion signal instructing AC conversion when performing AC driving, and a clock signal for latching a signal based on the display data The drive circuit of the image display element of Claim 3. The drive circuit of the image display element according to any one of claims 1 to 4, wherein the drive circuit is configured by a one-chip IC and is COG-mounted.

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