JP5141097B2 - Integrated circuit device, display device, and electronic device - Google Patents

Description

  The present invention relates to an integrated circuit device, a display device, and an electronic apparatus.

  Each pixel of the liquid crystal panel is AC driven to prevent liquid crystal burn-in. The drive voltage of each pixel is given a γ (gamma) characteristic for correcting the display characteristic of the liquid crystal panel.

  Since the γ characteristic of the positive pixel driving voltage (hereinafter referred to as positive γ characteristic) and the γ characteristic of the negative pixel driving voltage (hereinafter referred to as negative gradation voltage) are different, in the liquid crystal driver IC, It is necessary to generate both a gradation voltage having a positive γ characteristic and a gradation voltage having a negative γ characteristic.

  It is possible to generate both positive / negative gradation voltages in a time division manner using a single gradation voltage generation circuit. However, when dot inversion driving is used to invert the polarity of the pixel driving voltage for each dot in order to improve display quality, the inversion period is short. It may not be possible.

  In this case, the liquid crystal driver IC includes a first gradation voltage generation circuit that generates a gradation voltage having a positive γ characteristic and a second gradation voltage that generates a gradation voltage having a negative γ characteristic. It is necessary to provide a gradation voltage generation circuit in parallel to simultaneously generate gradation voltages of each polarity.

  Further, one pixel of the liquid crystal panel is composed of, for example, R (red), G (green), and B (blue) subpixels, and each subpixel is arranged in the row direction (scanning line direction) in this order. When it is repeatedly arranged (that is, when one row is composed of RGBRGB... Sub-pixels), each of the output terminals of the liquid crystal driver IC is 1: 1 to the sub-pixel RGBRGB. Correspondingly arranged.

  That is, each of the output terminals for driving each subpixel is arranged along the long side of the liquid crystal driver IC that faces the liquid crystal panel.

  Corresponding to each output terminal, D / A converters that generate pixel drive voltages (which are also voltages for driving data lines and may be referred to as data line drive voltages in the following description) are arranged in a line. The

  A column of D / A converters that generate a data line driving voltage having a negative γ characteristic and a column of D / A converters that generate a data line driving voltage having a positive γ characteristic are arranged in the same column. As a result, each D / A changer row is arranged in two stages.

A driver IC for a liquid crystal panel for dot inversion driving having such a configuration is described in Patent Document 1 and Patent Document 2, for example.
Japanese Patent Laying-Open No. 2006-106657 (for example, FIG. 8) Japanese Patent Laid-Open No. 11-153981 (for example, FIG. 5)

  In the liquid crystal driver IC, when simultaneously generating gradation voltages having positive / negative γ characteristics, each D / A conversion that generates a data line driving voltage having positive / negative γ characteristics as described above. The column of containers is arranged in two stages.

  That is, driver circuits having the same type of configuration are arranged in parallel, and the area occupied by the circuit increases. Further, since these circuits operate simultaneously, the power consumption of the circuit also increases. Hereinafter, this point will be specifically described.

  FIGS. 16A to 16C are diagrams for explaining dot inversion driving of a dot matrix liquid crystal display device in which one pixel (one pixel) is composed of sub-pixels of three colors.

  In the liquid crystal display device of FIG. 16A, one pixel (one pixel) is composed of subpixels of three colors of R (red), G (green), and B (blue).

  In the liquid crystal display device of FIG. 16A, in the nth frame, as shown in FIG. 16B, the polarity is inverted for every adjacent dot vertically and horizontally. “Polarity” is the positive / negative of the pixel drive voltage with reference to the voltage (VCOM) of the common electrode of the liquid crystal.

  In the (n + 1) th frame, since the polarity is inverted, the drive pattern shown in FIG.

  FIG. 17 is a diagram showing a main configuration of a liquid crystal driver IC having a layout configuration in which each D / A converter for generating a data line driving voltage having positive / negative γ characteristics is arranged in two stages.

  Here, it is assumed that the liquid crystal driver IC 11 of FIG. 17 performs dot inversion driving of one row of subpixel columns (RGBRGBRGBRGB) provided in the TFT array unit (liquid crystal display unit) 13. Each subpixel has an active matrix type structure including a TFT (thin film transistor) as a switching element. Each subpixel is selected by a scan line and a data line (not shown).

  The gradation voltage generation circuit 17 provided in the liquid crystal driver IC 11 includes a γ (positive) circuit 15a that generates 256-bit gradation voltages (VS0 to VS255) having a positive γ characteristic, and a 256 having a negative γ characteristic. And a γ (negative) circuit 15b for generating bit gradation voltages (VS0 to VS255).

  In addition, the liquid crystal driver IC 11 uses a gradation voltage (VS0 to VS255) having a positive γ characteristic from the γ (positive) circuit 15a to generate a plurality of D / Ds that generate a data line driving voltage (pixel driving voltage). A plurality of D / A's for creating a data line driving voltage (pixel driving voltage) using gradation voltages (VS0 to VS255) having negative γ characteristics from the A converter 19a and the γ (negative) circuit 15b. And a converter 19b.

  As shown in the drawing, 256 gray scale voltages (VS0 to VS255) are supplied to a plurality of D / V via dedicated wirings for positive polarity / negative polarity (each of 256 γ gradation wirings). A is supplied to each of the A converters 19a and 19b.

  FIGS. 18A and 18B are diagrams illustrating examples of positive and negative γ characteristics. The positive γ characteristic has, for example, an input gradation value-gradation voltage characteristic as indicated by a characteristic line PQ1 in FIG. The negative γ characteristic has, for example, an input gradation value-gradation voltage characteristic as indicated by a characteristic line PQ2 in FIG.

  Each of the plurality of D / A converters 19a and 19b in FIG. 17 corresponds to the subpixel column (RGBRGBRGBRGB) in the TFT array unit (liquid crystal display unit) 13 in a 1: 1 ratio. Similarly, the output terminals (TA1 to TA12) of the liquid crystal driver IC 11 respectively correspond to the subpixel columns (RGBRGBRGBRGB) in the TFT array unit (liquid crystal display unit) 13 at 1: 1.

  Each of the plurality of D / A converters 19a and 19b selects a gradation voltage corresponding to the gradation value of the input image signal to generate a data line driving voltage.

  A data line driving voltage having a positive γ characteristic is supplied to the positive sub-pixels via output terminals (TA1 to TA12) and a data line (not shown). Similarly, a data line driving voltage having negative γ characteristics is supplied to the negative sub-pixels via output terminals (TA1 to TA12) and a data line (not shown).

  As described above, in the liquid crystal driver IC 11 of FIG. 17, it is necessary to arrange the D / A converters 19a and 19b that generate data line driving voltages having positive / negative γ characteristics in two stages and arranged in parallel. . The dedicated wiring (γ gradation wiring) for supplying the gradation voltage to the D / A converter also requires 512 lines (256 lines × 2).

  Accordingly, the width of the laying region of the dedicated wiring (γ gradation wiring) is increased, which hinders the reduction of the size in the short side direction of the liquid crystal driver IC (bare chip having a horizontally long shape).

  In addition, since two stages of the same type of circuit operate simultaneously, the power consumption of the circuit increases.

  Further, since the wiring length of the γ gradation wiring from the γ (positive) circuit 15a and the γ (negative) circuit 15b to the D / A converter located at the farthest position is increased, the time constant of the wiring is increased. The discharge time becomes longer. This hinders high-speed generation of the data line driving voltage.

  The present invention has been made based on such consideration. According to some aspects of the present invention, it is possible to effectively reduce the chip size by reducing the circuit layout of the driver IC for the display device, and to reduce the power consumption of the circuit. Therefore, it is possible to generate a high-speed data line driving voltage.

  (1) In one aspect of the integrated circuit device of the present invention, one pixel is configured by subpixels corresponding to a plurality of different colors, the pixels are arranged in a matrix, and each of the subpixels is a scanning line and a data line. A first γ circuit for generating a first gradation voltage to which a γ characteristic having a first polarity is provided, and an integrated circuit device for performing dot inversion driving on a display unit selected by And a second polarity circuit for generating a second gradation voltage to which a second γ characteristic having a polarity γ characteristic is applied, and a first polarity in one subpixel column of the display unit A plurality of D / A converters corresponding to the sub-pixels driven by the first γ circuit, and a first γ-th floor that supplies the first gradation voltage from the first γ circuit to the plurality of D / A converters. A first data line driver including a control wiring and one row of the display unit A plurality of D / A converters corresponding to each of the sub-pixels driven with the second polarity in the sub-pixel column, and the second gradation voltage from the second γ circuit are converted into the plurality of D / A converters. Each of the data line drive voltages output from each of the plurality of D / A converters, and a second data line driver including a second γ gradation wiring to be supplied to the A converter. Is supplied to each of the corresponding data lines in the display section via a data line driving voltage supply path of a multilayer wiring structure.

  In the dot inversion driving, in general, the driving polarity is inverted for each adjacent subpixel (= 1 dot). Therefore, when one row includes n subpixels (n dots), positive polarity (for example, the first polarity) The number of subpixels (dots) driven with the polarity of (n) is (n / 2), and similarly, the number of subpixels (dots) driven with the negative polarity (for example, the second polarity) is (n / 2). It is. That is, it is only necessary to have (n / 2) D / A converters for generating data line drive voltages of positive / negative polarities. Focusing on this point, it is possible to reduce (halve) the number of D / A converters by arranging the necessary number of D / A converters and deleting unnecessary D / A converters. . As a result, the layout area can be reduced and the power consumption of the circuit can be reduced. In addition, since the number of positive / negative D / A converters is halved, each D / A converter is arranged in a single stage (that is, the D / A converters are arranged in a horizontal row). Possible). Therefore, it is possible to arrange the positive / negative data line drivers conventionally required to be arranged in two stages in one stage (horizontal one row). In addition, if the D / A converters with positive / negative polarities are arranged in a horizontal line, the length of the γ gradation wiring for supplying the gradation voltage is also halved. Is shortened, and high-speed data line driving is realized. However, when such a data line driver layout is adopted, the arrangement order of the D / A converters does not correspond to the arrangement order of the sub-pixels in the display unit, and therefore is output from the driver IC (integrated circuit device). Therefore, a data line driving voltage supply path (dedicated wiring for supplying data line driving voltage) for accurately supplying each data line driving voltage to each corresponding data line in the display unit is required. Therefore, in the present invention, the data line driving voltage supply wiring is constructed using a multilayer wiring structure capable of three-dimensional intersection. Thus, each data line driving voltage output from the IC can be supplied to each corresponding data line. The data line driving voltage supply path (multilayer wiring region for supplying data line driving voltage) having this multilayer wiring structure may be provided on the display device substrate or in the IC.

  (2) In another aspect of the integrated circuit device of the present invention, the data line driving voltage supply path of the multilayer wiring structure is formed on a display device substrate on which the display section is formed.

  It is clear that a data line driving voltage supply path (multilayer wiring region for supplying data line driving voltage) having a multilayer wiring structure is provided on a substrate for a display device. A data line driving voltage supply path (multilayer wiring region for supplying data line driving voltage) of this multilayer wiring structure is formed on a display device substrate (active matrix substrate) using, for example, a TFT (thin film transistor) using a low-temperature polysilicon process. Can be formed at the same time. In this case, since it is not necessary to provide a multilayer wiring structure in the IC, the size of the IC does not increase, which is advantageous in terms of occupied area or cost.

  (3) In another aspect of the integrated circuit device of the present invention, the first data line driver and the second data line driver, the first γ circuit, and the second γ circuit are In the integrated circuit device, they are arranged in a line along the arrangement direction of the one row of sub-pixel columns of the display unit.

  Conventionally, the positive / negative data line drivers (including the D / A converter and the γ gradation wiring) that had to be arranged in two stages are arranged in one stage (one horizontal row: that is, one row of sub-pixel arrangements). The points are arranged in a horizontal direction along the direction of the scanning line or the arrangement direction of the scanning lines. If the D / A converters with positive / negative polarities are arranged in a horizontal row, the length of the γ gradation wiring for supplying the gradation voltage is also halved, so the time required for wiring charging / discharging is shortened. Thus, high-speed data line driving is realized.

  (4) In another aspect of the integrated circuit device of the present invention, the integrated circuit device includes a first short side, a second short side opposite to the first short side, and the first short side. And a third long side perpendicular to the second short side and a fourth long side opposite to the third short side, from the first short side toward the second short side A direction is a first direction, a direction opposite to the first direction is a second direction, a direction from the third long side toward the fourth long side is a third direction, and the first direction is When the direction opposite to the direction 3 is the fourth direction, the first voltage side of the grayscale voltage generation circuit is arranged on either the first direction side or the second direction side. A data line driver is arranged, and the second data line driver is arranged on the other side.

  It is clear that the first and second data line drivers are arranged on both sides of the grayscale voltage generation circuit including the first and second γ circuits. Since the first and second γ circuits can be centrally arranged in the center of the IC, variations in the resistance value of the ladder resistor that generates the gradation voltage can be suppressed, and a compact layout can be realized. .

  (5) In another aspect of the integrated circuit device of the present invention, when the first direction is the right direction and the second direction is the left direction, the first data line driver and the second direction The data line driver is arranged symmetrically with respect to the gradation voltage generation circuit.

  It is clarified that the first and second data line drivers are arranged symmetrically on both sides of the gradation voltage generating circuit including the first and second γ circuits. By adopting a symmetrical layout, a compact layout with no wasted space is realized. In addition, the length of the γ gradation wiring is the same on the left and right, so that the amount of voltage drop in each γ gradation wiring can be made comparable.

  (6) In another aspect of the integrated circuit device of the present invention, the polarity of the gradation voltage generated by the first γ circuit and the polarity of the gradation voltage generated by the second γ circuit are: The display unit is switched every scan of at least one line.

  In dot inversion driving, for example, the driving polarity is inverted for each line. In order to cope with the polarity inversion of this line unit, the polarity of the gradation voltage generated by the first γ circuit and the polarity of the gradation voltage generated by the second γ circuit in accordance with the polarity inversion of the line unit. Are switched (replaced). The polarity inversion of the γ circuit can be realized by, for example, inversion of the power supply voltage level or adjustment of the resistance value of the unit variable resistor in the ladder resistor circuit. Even in the case of dot inversion driving, an irregular driving method in which the polarity is inverted every two lines or every three lines may be employed. In such a case, the polarity of the γ circuit may be switched every two-line scan (or three-line scan). Therefore, the switching of the polarity of the γ circuit is performed at least every scanning of one line (not limited to one line, but may be two lines or three lines).

  (7) In another aspect of the integrated circuit device of the present invention, data serving as a supply destination of the data line drive voltage output from each of two adjacent output ends of the data line drive voltage supply path of the multilayer wiring structure The data line drive voltage is supplied to the corresponding data line via a data supply destination switching switch that switches the line at least every one line scan in the display unit.

  Instead of switching the polarity of the first γ circuit and the polarity of the second γ circuit, the data line to which the data line drive voltage is supplied is switched at least for each line scan using a switch. This makes it possible to cope with polarity inversion in line units without switching the polarity of the γ circuit. The switch may be provided on the display device substrate or in the IC. Since the polarity switching between the γ circuits is not performed, the charging / discharging current does not flow through the ladder resistor due to the polarity switching, which is advantageous in terms of generating a high-speed gradation voltage.

  (8) In another aspect of the integrated circuit device of the present invention, input image data for a sub-pixel driven with the first polarity is supplied to the first data line driver, and driven with the second polarity. An input image data order conversion circuit for supplying input image data for the sub-pixels to the second data line driver.

  As the layouts of the first and second data line drivers are changed, the order of input image signals (input image data) is changed (order conversion) so as to correspond to this, and then each image data is changed to each data. It is supplied to the line driver.

  (9) One aspect of the display device of the present invention includes the integrated circuit device of the present invention and a display device substrate on which the integrated circuit device is mounted.

  As a result, a display device (for example, a high-definition display device for a portable terminal that displays an image of one-segment broadcasting) that is excellent in small size, low power consumption, and capable of high-speed and high-definition display is realized.

  (10) The electronic device of the present invention is equipped with the display device of the present invention.

  Accordingly, electronic devices that are small, have low power consumption, and are capable of high-speed and high-definition display (for example, mobile terminals that display one-seg broadcast images: mobile phone terminals, PDA terminals, and portable computer terminals are included. ) Is realized.

  As described above, according to some embodiments of the present invention, the chip size can be effectively reduced by devising the circuit layout of the display driver IC. In addition, the power consumption of the circuit of the driver IC for display device can be reduced. In addition, it is possible to shorten the wiring length of the γ gradation wiring and to generate a high-speed data line driving voltage.

  Next, embodiments of the present invention will be described with reference to the drawings. Note that the present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are as means for solving the present invention. It is not always essential.

(First embodiment)
(Internal configuration example of liquid crystal display and liquid crystal driving IC)
Hereinafter, an example of the internal configuration of the liquid crystal display unit and the liquid crystal driving IC (an example of the driver IC for the display device of the present invention) will be specifically described.

  FIG. 1 is a block diagram showing a main configuration of a liquid crystal display unit and a liquid crystal driving IC. As illustrated, the liquid crystal display unit (TFT array unit) 312 includes a plurality of data lines (DL1, DL2...), A plurality of scanning lines (W1, W2...), A data line and a scanning line. A plurality of dots (subpixels) specified by

  In the liquid crystal display unit (hereinafter, sometimes referred to as a display unit at the end) 312 in FIG. 1, one pixel includes a plurality of subpixels (one dot).

  One subpixel (one dot) includes a TFT (thin film transistor) as a switching element, a liquid crystal element LC, and a storage capacitor C1. An MIM or the like can be used instead of the TFT. Note that the display unit 312 may be a panel other than the active matrix system, or may be a display unit (such as an organic EL display unit) other than the liquid crystal display unit.

  The liquid crystal driving IC 10 has the following circuit configuration.

  That is, the high-speed I / F circuit 200 realizes high-speed serial transfer via the serial bus. The host I / F (interface) circuit 46 realizes a host interface that accesses the memory 20 by generating an internal pulse for each access from the host (MPU) 330 (see FIG. 1). The RGB interface circuit 48 implements an RGB interface that writes moving image RGB data to the memory 20 using a dot clock.

  The memory 20 (RAM) stores image data. The memory cell array 22 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). The memory 20 includes a row address decoder 24 (MPU / LCD row address decoder), a column address decoder 26 (MPU column address decoder), and a write / read circuit 28 (MPU write / read circuit). Note that the memory 20 may be omitted depending on circumstances.

  The logic circuit 40 (driver logic circuit: a region surrounded by a dotted line in FIG. 5) is a circuit block that generates a display control signal for controlling display timing and data processing timing. The logic circuit 40 is a circuit designed by a semi-custom IC method such as a gate array (G / A).

  The control circuit 42 generates various control signals and controls the entire apparatus. The display timing control circuit 44 generates a display timing control signal, and controls reading of image data from the memory 20 and supply timing of the read image data to the liquid crystal display unit 312.

  The power supply circuit 110 generates various power supply voltages and supplies them to the data line driver 50, the scan driver 70, the gradation voltage generation circuit 110, and the like. The gradation voltage generation circuit 110 (which also functions as a γ correction circuit) generates, for example, a gradation voltage of 256 gradations, and outputs the generated gradation voltage to the data line driver 50.

  The data driver 50 generates a data line driving signal (data line driving voltage) for driving the data lines (D1, D2,...) Of the liquid crystal display unit 312. Specifically, the data driver 50 receives gradation data as image data from the memory 20 and receives a plurality (for example, 256 levels) of gradation voltages (gradation reference voltages) from the gradation voltage generation circuit 110. . The data line driver 50 includes a D / A converter (not shown), and the D / A converter selects a voltage corresponding to the gradation data from the plurality of gradation voltages described above and selects the data line. A drive signal (data line drive voltage) is generated, and the data line drive signal (data line drive voltage) is output to each data line (DL1, DL2...) Of the liquid crystal display unit 312. Further, the scan driver 70 generates a scan signal for driving the scan lines (W1, W2,...) Of the liquid crystal display unit 312.

  In the present invention, it is assumed that the TFT array unit (liquid crystal display unit) 312 is driven by dot inversion (pixel inversion driving). In order to reduce the size of the IC 10 and improve the low power consumption, in particular, the gradation voltage generation The layout of the circuit (γ circuit) 110 and the data line driver 50 is optimized.

  In the present invention, a multilayer wiring is used as the wiring LD for supplying the data line driving voltage output from the data line driver 50 to the data lines DL1 and DL2.

(Overview of overall configuration of display device (display module))
An outline of the entire configuration of the display device (display module) will be described. FIG. 2 is a diagram showing an overall configuration and connection form of a display device (display module: here a liquid crystal display panel) of the present invention.

  A liquid crystal display panel (liquid crystal panel module) 300 includes a TFT array unit (liquid crystal display unit: hereinafter simply referred to as a display unit) provided on a glass substrate (liquid crystal display device substrate or active matrix substrate: hereinafter referred to as an array substrate) 310. 312) and a liquid crystal driving IC (hereinafter simply referred to as an IC) 10.

  In the TFT array portion (liquid crystal display portion) 312, a plurality of subpixels (in this case, RGB subpixels) selected by scanning lines and data lines are arranged in a matrix.

  The IC 10 drives the scanning lines of the TFT array unit (liquid crystal display unit) 312 via the wirings (LWa, LWb), and similarly the data of the TFT array unit (liquid crystal display unit) 312 via the wiring LD. Drive the line.

  The IC 10 and the host processor 330 are connected by, for example, an FPC board (flexible printed circuit board).

(Configuration of array substrate before IC is mounted)
FIG. 3 is a plan view showing the configuration of the array substrate (active matrix substrate) before the IC is mounted.

In FIG. 3, terminals TB <b> 1 to TBn represent the data line drive voltage output from the IC 10.
An input terminal for supplying to the TFT array unit (liquid crystal display unit) 312.

  The data line driving voltage is supplied to the TFT array unit (liquid crystal display unit) via a data line driving voltage supply path (hereinafter simply referred to as a multilayer wiring structure) 320 having a multilayer wiring structure provided on the substrate 310. ) 312 is provided to the data lines (DL1 to DLn). The multilayer wiring composition tail 320 can also be provided inside the IC 10.

(Cross sectional structure of the main part of the display panel)
4 is a cross-sectional view taken along the line AA in the display device of FIG. As shown in the drawing, conductive patterns 2, 3, 4 (4a, 4b) are arranged on the array substrate 310 (the wiring 3 is, for example, a VCOM wiring).

  Bump electrodes 8 and 9 are provided on the back surface of the IC 10. The IC 10 and the array substrate 310 are connected via the anisotropic conductive film 6. Further, a connection terminal 5 is provided on the back surface of the front end of the FPC board 314, and the connection terminal 5 is connected to the wiring pattern 2 on the array board 310 via a conductive adhesive or the like.

  In addition, the multilayer wiring structure 320 formed on the array substrate 310 includes a first layer wiring (4a, 4b), a second layer wiring 7, an interlayer insulating film 322a, and a passivation film 322b. The first layer wiring (4a, 4b) and the second layer wiring 7 are connected to each other through the through holes TH1, TH2.

(Example of arrangement of gradation voltage generation circuit and data line driver)
FIG. 5 is a diagram illustrating an arrangement example of the gradation voltage generation circuit and the data line driver. Here, for convenience of explanation, it is assumed that one row of subpixel columns (RGBRGBRGBRGB) is driven (this example is an extremely simplified example for convenience of explanation).

  In this subpixel column, for example, the drive polarity is inverted every line. In the following description, it is assumed that the polarity of each sub-pixel column is “+ − + − + − + − + − + −”.

  Although twelve subpixels are arranged, in the case of dot inversion driving, since the driving polarity is generally inverted for each adjacent subpixel (= 1 dot), positive polarity (for example, the first polarity) The number of subpixels (dots) driven by is 6 and, similarly, the number of subpixels (dots) driven by negative polarity (for example, the second polarity) is also six. That is, six D / A converters for generating positive / negative polarity data line drive voltages are sufficient.

  Focusing on this point, in the IC 10 of FIG. 5, the number of D / A converters (601 to 606) actually required (= 6) are disposed as positive γ D / A converters, By deleting unnecessary D / A converters, the number of D / A converters is reduced (halved).

  Similarly, the necessary number (= 6) of D / A converters (607 to 612) are arranged as negative γ D / A converters, and unnecessary D / A converters are deleted. By doing so, the number of D / A converters is reduced (halved).

  As a result, the layout area can be reduced and the power consumption of the circuit can be reduced. Since the number of positive / negative D / A converters (601 to 606, 607 to 612) is halved, the data line driver (50a) that has been configured in two stages in the conventional example (see FIG. 17) , 50b) are arranged in a horizontal row to form a one-stage configuration. That is, in FIG. 6, it is possible to arrange each D / A converter (601-612) in a horizontal line.

  The first data line driving circuit 50 a is arranged on the left side of the gradation voltage generating circuit 110, and the second data line driving circuit 50 b is arranged on the right side of the gradation voltage generating circuit 110. That is, a symmetrical layout is adopted. Thereby, a compact arrangement is realized.

  The gradation voltage generation circuit 110 includes a first γ circuit 110a that generates 256 gradation gradation voltages (see FIG. 18A) to which a positive γ characteristic is added, and a negative γ characteristic. The second γ circuit 110b that generates the 256 gradation voltages (see FIG. 18B), and the first γ circuit 110a and the second γ circuit 110b are Adjacent to each other. However, the present invention is not limited to this, and it is also possible to separate the first γ circuit 110a and the second γ circuit 110b and to arrange them on the left and right short sides of the IC 10, respectively.

  The gradation voltage having the positive γ characteristic generated by the first γ circuit 110a is supplied to the positive γ D / A converters 601 to 606 via the γ gradation wiring (LK1). Is done. Similarly, the gradation voltage having negative γ characteristics generated by the second γ circuit 110b passes through the γ gradation wiring (LK2), and the negative γ D / A converter (607). To 612).

  The D / A converters (601 to 606, 607 to 612) select a gradation voltage at a level corresponding to the gradation value of the input image data from the gradation voltages given via the γ gradation wiring. Then, the selected gradation voltage is output as the data line drive voltage.

  By arranging the D / A converters of positive / negative polarities in a horizontal row, the length of the γ gradation wirings (LK1, LK2) for supplying gradation voltages is also half that of the conventional one (FIG. 17). In the conventional example, the total length of the γ gradation wiring is LA, but in FIG. 5, it is (LA / 2)). Therefore, the time required for wiring charging / discharging is shortened, and high-speed data line driving is realized.

  However, when such a layout of the data line drivers 50a and 50b is adopted, the arrangement order (RBGRBG / GRBGGRB) of each D / A converter (601 to 606, 607 to 612) is the arrangement of subpixels in the display unit 312. The order (RGBRGBRGBRGB) does not correspond.

  Therefore, a data line driving voltage supply path (data line driving voltage) for accurately supplying each data line driving voltage output from the IC (integrated circuit device) 10 to each corresponding data line in the display unit 312. A dedicated wiring for supply) LD is required. As is clear from FIG. 5, these wirings LD cross each other, and cannot be configured with a single-layer wiring.

  Therefore, the wiring LD for supplying the data line driving voltage is constructed using the multilayer wiring structure 320 capable of three-dimensional intersection. Thereby, each data line drive voltage output from the IC 10 can be appropriately supplied to each corresponding data line.

  The data line driving voltage supply path (multilayer wiring region for supplying data line driving voltage) 320 having this multilayer wiring structure may be provided on the display device substrate (array substrate 310) or in the IC 10. In FIG. 5, the multilayer wiring structure 320 is provided on a display device substrate (array substrate 310).

  A data line driving voltage supply path (multilayer wiring region for supplying data line driving voltage) 320 having a multilayer wiring structure is formed on a display device substrate (active matrix substrate) 310 by using, for example, a TFT (thin film transistor) using a low-temperature polysilicon process. ) And the like can be formed at the same time. In this case, since it is not necessary to provide the multilayer wiring structure 320 in the IC 10, the size of the IC 10 does not increase, which is advantageous in terms of occupied area or cost.

  In the dot inversion driving, for example, the driving polarity is inverted for each line (see FIGS. 16B and 16C). In order to cope with the polarity reversal of this line unit, in the IC 10 of FIG. 5, the polarity of the gradation voltage generated by the first γ circuit (110a) in accordance with the polarity reversal of the line unit and the second γ The polarity of the gradation voltage generated by the circuit (110b) is appropriately switched (replaced).

  That is, the first γ circuit (110a) is switched from positive polarity to negative polarity, and the second γ circuit (110b) is switched from negative polarity to positive polarity.

  When the input image data is appropriately distributed in accordance with the polarity switching of each γ circuit (110a, 110b) (that is, the image data of the pixel to be driven with the negative polarity is supplied to the first γ circuit 110a this time. However, if pixel image data to be driven with a positive polarity is supplied to the second γ circuit 110b), it is possible to cope with polarity inversion driving in units of lines.

  The polarity inversion of the γ circuit can be realized, for example, by inverting the power supply voltage level or adjusting the resistance value of the unit variable resistor in a ladder resistor circuit (described later with reference to FIGS. 6 and 7). Even in the case of dot inversion driving, an irregular driving method in which the polarity is inverted every two lines or every three lines may be employed. In such a case, the polarity of the γ circuit may be switched every two-line scan (or three-line scan). Therefore, the switching of the polarity of the γ circuit is performed at least every scanning of one line (not limited to one line, but may be two lines or three lines).

  Even when the polarity of the first and second γ circuits (110a, 110b) is not switched, the method of switching the output destination of the data line driving voltage with a switch can be used to reverse the polarity in units of lines. (This point will be described later with reference to FIGS. 11 to 14).

(Specific configuration example of gradation voltage generation circuit (γ circuit)).
FIG. 6 is a diagram illustrating a specific configuration example of the gradation voltage generation circuit (γ circuit). As shown in the figure, the grayscale voltage generation circuit (γ) circuit has a ladder resistor circuit (QRC) including a ladder resistor (RD) in which a plurality of unit variable resistors (R) are connected in series. The resistance value of the resistor (R) can be finely adjusted by adjustment data input to the adjustment register 116.

  The level of the voltage applied to both ends of the ladder resistor circuit (QRC) can be switched by the power supply voltage level switching switches (SK1, SK2). This makes it possible to reverse the polarity of the γ characteristic. The switches (SK1, SK2) are switched based on the γ polarity control data input to the adjustment register 116.

  FIG. 7 is a diagram illustrating a specific configuration example of the unit variable resistor (R). As shown in the figure, a switch circuit K (having a plurality of changeover switches K1 to K4) is provided, and the switch K is appropriately switched by a control signal from the adjustment register 116. As a result, the voltage level of the gradation voltages (VS (i) to VS (i + 3)) can be finely adjusted.

(Specific configuration example of internal circuit of IC)
FIG. 8 is a diagram showing a specific configuration example of the internal circuit of the IC (the state in which the first row line is driven). The basic configuration and operation are the same as in FIG.

  In FIG. 8, for convenience of explanation, it is assumed that six sub-pixel columns “R1, G1, B1, R2, G2, B2” are driven. The subpixels R1, B1, and G2 are driven with a positive polarity, and the subpixels G1, R2, and B2 are driven with a negative polarity.

  The IC 10 includes a first short side (S1), a second short side (S2) opposite to the first short side (S1), a first perpendicular to the first short side and the second short side. 3 long sides (S3) and a fourth long side (S4) opposite to the third short side.

  The direction from the first short side (S1) to the second short side (S2) is the first direction (D1), and the direction opposite to the first direction (D1) is the second direction (D2). The direction from the third long side (S3) to the fourth long side (S4) is the third direction (D3), and the direction opposite to the third direction (D3) is the fourth direction ( D4), either one of the first direction (D1) side and the second direction (D2) side of the gradation voltage generation circuit (110) (the second direction D2 side in FIG. 8) ), The first data line driver (50a) is arranged, and the second data line driver (50b) is arranged on the other side (first direction D1 side).

  In FIG. 8, the first data line driver (50a) generates a data line driving voltage having a positive γ characteristic, and the second data line driver (50b) is a data line driving voltage having a negative γ characteristic. Is generated.

  A latch circuit 500 latches input image data. The order conversion circuit 502 rearranges the latched image data and supplies image data for each of the subpixels “R1, B1, G2” driven with positive polarity to the first data line driver 50a. Similarly, the image data for each sub-pixel of “G1, R2, B2” driven with negative polarity is supplied to the second data line driver 50b.

  The multilayer wiring structure 320 has six lateral directions extending in the first direction D1 or the second direction D2 (this direction coincides with the arrangement direction of one subpixel column or the direction of the scanning line). It has wiring (Q1-Q6). Each sub-pixel of “R1, B1, G2” is connected to Q1, Q3, Q5. Each sub-pixel of “G1, R1, B2” is connected to Q2, Q4, Q6. Of the output terminals of the IC, each of TA1 to TA3 is connected to Q1, Q3, and Q5. Each of TA4 to TA6 is connected to Q2, Q4 and Q6.

  FIG. 9 is a diagram showing an internal configuration when the second line in the IC of FIG. 8 is driven. In FIG. 9, the sub-pixels “R3, B3, G4” are driven with negative polarity, and the sub-pixels “G3, R4, B4” are driven with positive polarity.

  In FIG. 9, the polarity of the ladder resistor circuit QRC (γ (positive) and γ (negative)) is switched to the reverse of FIG. 8.

  In accordance with this, the order conversion circuit 502 rearranges the latched image data, and converts the image data for each of the sub-pixels “G3, R4, B4” driven with the positive polarity into the second data line driver. 50b. Similarly, image data for each of the sub-pixels “R3, B3, G4” driven with negative polarity is supplied to the first data line driver 50a.

(Mode in which the data path is switched by a switch without inverting the polarity of the γ circuit)
In the above example, the polarity of the γ circuit is switched at least for each line. However, even if the polarity of the γ circuit is not switched, if the path switching switch as shown in FIG. It can correspond to inversion.

  FIG. 10 is a diagram illustrating the function of the path switching switch. This switch (SW) is a switch with two inputs and two outputs. By changing the route of the internal routes RT1 and RT2, the through output as shown in FIG. 10 (A) and the crossing as shown in FIG. 10 (B) ( Cross) output can be selected.

  FIG. 11 is a diagram illustrating a configuration in the driving state of the n-th row of another example of the internal configuration of the IC (an example in which the data path is switched by the switch of FIG. 10 without performing the polarity inversion of the γ circuit). .

  The configuration of the IC of FIG. 11 is almost the same as the configuration of FIG. 5, but the polarity of the first and second γ circuits (110a, 110b) is not switched, and the switch having the function of FIG. The difference is that SW1 to SW6 are provided. The switches SW1 to SW6 are in a through state as shown in FIG.

  12 is a diagram showing a configuration in the driving state of the (n + 1) th row of another example of the internal configuration of the IC (example in which the data path is switched by the switch of FIG. 10 without performing the polarity inversion of the γ circuit). It is.

  In FIG. 12, the drive polarity of each pixel is inverted along with the line inversion. In order to cope with this, the switches SW1 to SW6 are switched to a cross state as shown in FIG. Further, the image data of the sub-pixel driven with positive polarity is supplied to the first data line driving circuit 50a, and the image data of the sub-pixel driven with negative polarity is supplied to the second data line driving circuit 50b. To do.

  In this way, by switching the data line (that is, the subpixel) to which the data line driving voltage output from the D / A converter is supplied at least for each line scan, using the switches (SW1 to SW6), Without switching the polarity of the γ circuit (110a, 110b), it is possible to cope with polarity inversion in line units. The switches (SW1 to SW6) may be provided on the display device substrate (array substrate) 310 or may be provided in the IC 10. In this aspect, since the polarity is not switched between the γ circuits (110a, 110b), the charging / discharging current does not flow through the ladder resistor (RD) in accordance with the polarity switching, which is advantageous in terms of generating a high-speed gradation voltage. It becomes.

  FIG. 13 is a diagram showing a specific internal configuration example of the IC in which the data path is switched by a switch without performing the polarity reversal of the γ circuit (the state in which the subpixel column in the first row is driven). is there.

  FIG. 13 corresponds to FIG. The basic configuration of the IC in FIG. 13 is the same as the IC in FIG.

  FIG. 14 is a diagram illustrating a specific internal configuration example of the IC in which the data path is switched by the switch without performing the polarity inversion of the γ circuit (the state in which the subpixel column in the second row is driven). is there.

  FIG. 14 corresponds to FIG. The basic configuration of the IC in FIG. 14 is the same as the IC in FIG.

(Second Embodiment)
In this embodiment, a display device and an electronic apparatus equipped with the display device will be described.

  The display device (liquid crystal display device) of the present invention shown in FIG. 2 includes the IC 10 of the present invention and a display device substrate (array substrate) 310 on which the IC is mounted.

  For example, when the display device substrate (array substrate) 310 is an active matrix substrate using low-temperature polysilicon, a multilayer wiring structure as shown in FIG. 3 is formed on the display device substrate (array substrate) 310, for example. 320 can be formed, and the switches (SW1 to SW6) shown in FIGS. 10 to 14 can be formed. The switches SW1 to SW6 can be configured by combining a plurality of transfer gates using TFTs formed by, for example, a low-temperature polysilicon process.

  As a result, a display device (for example, a high-definition display device for a portable terminal that displays an image of one-segment broadcasting) that is excellent in small size, low power consumption, and capable of high-speed and high-definition display is realized.

  15A to 15B are diagrams illustrating an example of the electronic device of the present invention on which the display device of the present invention is mounted.

  FIG. 15A shows a mobile phone terminal 950. The cellular phone terminal 950 includes a speaker 956, a display panel 954 of the present invention, and operation keys 952.

  FIG. 15B shows a portable game machine terminal 960. The portable game machine terminal 960 includes a speaker 968, a display panel 966 of the present invention, operation keys 962, and function keys 964.

  FIG. 15C illustrates the mobile phone terminal 970. The cellular phone terminal 970 includes a speaker 976, a display panel 974 of the present invention, and operation keys 972.

  Since the display device of the present invention is small and excellent in low power consumption, the above-described electronic device that is required to be small, high-speed, and high-definition display (a mobile terminal that displays an image of one-segment broadcasting: a mobile phone terminal, (Including PDA terminals, game machine terminals, and portable computer terminals), thereby improving the display performance of the electronic device.

As described above, according to the embodiment of the present invention, the following effects can be obtained. However, the following effects are not always obtained at the same time, and the enumeration of the following effects should not be used as a basis for unduly limiting the technical idea of the present invention.
(1) The chip size can be effectively reduced by devising the circuit layout of the display driver IC.
(2) The power consumption of the display driver IC can be reduced.
(3) It is possible to shorten the wiring length of the γ gradation wiring and to generate a high-speed data line driving voltage.
(4) A display device (for example, a high-definition display device for a portable terminal that displays an image of one-segment broadcasting) that is compact and has low power consumption and capable of high-speed and high-definition display is realized.
(5) Electronic devices that are small and have low power consumption and capable of high-speed and high-definition display (for example, mobile terminals that display one-segment broadcast images: mobile phone terminals, PDA terminals, and portable computer terminals) ) Is realized.

  In addition, although this embodiment was explained in full detail, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Therefore, all such modifications are included in the present invention.

  For example, the first γ circuit and the second circuit may be arranged centrally in the IC, or may be separated from each other and arranged at the left and right ends of the IC. Also, as an aspect of dot inversion driving, when an irregular driving method in which the driving polarity is inverted every plural dots is adopted, or when an irregular driving method in which the driving polarity is inverted every plural line scanning is adopted However, the present invention is applicable, and such examples are also included in the present invention. In other words, an actual necessary number of D / A converters are prepared, a multilayer wiring structure capable of correctly supplying the necessary data line driving voltage to the corresponding data line is prepared, and, for example, in accordance with an actual line scan By switching the polarity between the γ circuits, it is possible to flexibly cope with the above irregular driving system. In the description of the embodiments, driving of three color (RGB) subpixels has been described as an example. However, the present invention is not limited to this, and the present invention is also applied to driving of subpixels of more colors. Is possible.

  The present invention relates to an integrated circuit device for a driver of a display unit (liquid crystal driver IC, organic EL driver IC, etc.), a substrate for a display device (for example, an active matrix type liquid crystal substrate using TFT: array substrate), a display device (display) It is suitable as an electronic device (such as a high-definition liquid crystal display for a portable terminal) in which a driver IC is mounted on a device substrate).

The block diagram which shows the principal part structure of liquid crystal display part and liquid crystal drive IC The figure which shows the whole structure and connection form of the display apparatus (display module: Here, it is set as a liquid crystal display panel) of this invention. Plan view showing the configuration of the array substrate (active matrix substrate) before the IC is mounted Sectional view along the AA line in the display device of FIG. The figure which shows the example of arrangement | positioning of a gradation voltage generation circuit and a data line driver The figure which shows the specific structural example of a gradation voltage generation circuit (gamma circuit). The figure which shows the specific structural example of a unit variable resistance (R). The figure which shows the specific structural example (The state which is driving the line of the 1st row) of the internal circuit of IC. The figure which shows an internal structure when driving the line of the 2nd row in IC of FIG. FIGS. 10A and 10B are diagrams each showing a function of a path switching switch. The figure which shows the drive state of the nth row of the other example of the internal configuration of the IC (example in which the data path is switched by the switch of FIG. 10 without inverting the polarity of the γ circuit) The figure which shows the drive state of the (n + 1) th line of the other example (example which switches a data path by the switch of FIG. 10 without performing polarity inversion of (gamma) circuit) of internal structure of IC. The figure which shows the specific internal structural example (the drive state of the sub pixel column of the 1st row) of IC of the aspect which switches a data path by a switch, without performing polarity inversion of (gamma) circuit The figure which shows the specific internal structural example (The drive state of the sub pixel column of the 2nd row) of IC of the aspect which switches a data path by a switch, without performing polarity inversion of (gamma) circuit Each of FIGS. 15A to 15C is a diagram illustrating an example of the electronic apparatus of the invention in which the display device of the invention is mounted. FIGS. 16A to 16C are diagrams for explaining dot inversion driving of a dot matrix liquid crystal display device in which one pixel (one pixel) is composed of three subpixels. The figure which shows the principal part structure of the liquid crystal driver IC of the layout structure which has arrange | positioned each D / A converter which generate | occur | produces the data line drive voltage which has each positive / negative (gamma) characteristic in 2 steps | paragraphs. 18A and 18B are diagrams showing examples of positive and negative γ characteristics.

Explanation of symbols

10 liquid crystal driving IC (display device driver IC), 110 gradation voltage generating circuit,
110a, 110b first and second γ circuits, 300 display panel,
310 glass substrate (array substrate), 312 TFT array (liquid crystal display),
314 FPC board, 320 multilayer wiring structure (data line voltage supply path of multilayer wiring structure),
330 host processor, 601-606 D / A converter,
LK1, LK2 γ gradation wiring

Claims (9)

An integrated circuit that performs dot inversion driving on a display unit in which one pixel is composed of subpixels corresponding to a plurality of different colors, the pixels are arranged in a matrix, and each of the subpixels is selected by a scanning line and a data line A device,
A first γ circuit for generating a first gradation voltage to which a γ characteristic of the first polarity is given;
A gradation voltage generation circuit including a second γ circuit that generates a second gradation voltage to which a γ characteristic of the second polarity is provided;
A plurality of D / A converters corresponding to sub-pixels driven with a first polarity in one row of sub-pixel columns of the display unit, and the first gradation voltage from the first γ circuit. A first data line driver including a first γ gradation wiring to be supplied to the plurality of D / A converters;
A plurality of D / A converters corresponding to each of the sub-pixels driven with the second polarity in the sub-pixel column of one row of the display unit, and the second gradation from the second γ circuit A second data line driver including a second γ gradation wiring for supplying a voltage to the plurality of D / A converters,
Each of the data line drive voltage outputted from each of said plurality of D / A converter via the data line drive voltage supply path of the multi-layer wiring structure, each of said data lines corresponding to the said display unit Supplied to
The integrated circuit device includes a first short side, a second short side facing the first short side, and a third long side perpendicular to the first short side and the second short side. And a fourth long side opposite to the third short side,
When the direction from the first short side to the second short side is the first direction and the direction opposite to the first direction is the second direction,
The first data line driver is disposed on one of the first direction side and the second direction side of the grayscale voltage generation circuit, and the second data is provided on the other side. An integrated circuit device comprising a line driver. An integrated circuit device according to claim 1, wherein
The integrated circuit device, wherein the data line driving voltage supply path of the multilayer wiring structure is formed on a display device substrate on which the display unit is formed. An integrated circuit device according to claim 1 or 2,
The first data line driver and the second data line driver, the first γ circuit, and the second γ circuit are sub-rows of the one row of the display unit in the integrated circuit device. An integrated circuit device, wherein the integrated circuit devices are arranged in a line along a pixel column arrangement direction. An integrated circuit device according to any one of claims 1 to 3,
When the first direction is the right direction and the second direction is the left direction, the first data line driver and the second data line driver are based on the gradation voltage generation circuit. An integrated circuit device characterized by being arranged symmetrically. An integrated circuit device according to any one of claims 1 to 4,
The polarity of the gradation voltage generated by the first γ circuit and the polarity of the gradation voltage generated by the second γ circuit are switched every scan of at least one line in the display unit. An integrated circuit device. An integrated circuit device according to any one of claims 1 to 4,
Switching the data line to which the data line driving voltage is output from each of the two adjacent output terminals of the data line driving voltage supply path of the multilayer wiring structure at least every one line scan in the display unit; An integrated circuit device, wherein the data line driving voltage is supplied to the corresponding data line via a data supply destination switching switch. An integrated circuit device according to any one of claims 1 to 6,
Input image data for sub-pixels driven with the first polarity is supplied to the first data line driver, and input image data for sub-pixels driven with the second polarity is supplied to the second data. An integrated circuit device comprising a sequence conversion circuit for input image data supplied to a line driver. An integrated circuit device according to any one of claims 1 to 7,
A display device substrate on which the integrated circuit device is mounted;
A display device comprising:   An electronic device equipped with the display device according to claim 8.

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