KR102383826B1 - Source driver ic and display device - Google Patents

Abstract

The present embodiments relate to a source driver integrated circuit and a display device having a structure capable of improving image quality by preventing a block dim phenomenon.

Description

SOURCE DRIVER IC AND DISPLAY DEVICE

The present embodiments relate to a source driver integrated circuit and a display device.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display device, a plasma display device, and an organic light emitting display device ( Various display devices such as Organic Light Emitting Display Device) are being used.

The display device includes a display panel in which data lines and gate lines are disposed and subpixels are disposed, a data driver to drive the data lines, a gate driver to sequentially drive the gate lines, a data driver and a gate driver and a timing controller for controlling the

The above-described data driver includes one or more source driver integrated circuits, each source driver integrated circuit converting data corresponding to a digital image signal received from the timing controller into a data voltage corresponding to an analog image signal to be transmitted to a plurality of channels. Outputs to a plurality of corresponding data lines.

There has been a problem in that a block dim phenomenon occurs in the screen area corresponding to the channels in charge of the source driver integrated circuit, and thus the picture quality deteriorates.

It is an object of the present embodiments to provide a source driver integrated circuit and a display device capable of improving image quality by preventing a block dim phenomenon.

Another object of the present embodiments is to provide a source driver integrated circuit having a structure capable of preventing a block dim phenomenon and a display device including the same.

Another object of the present embodiments is to provide a source driver integrated circuit having a structure capable of preventing a block dim phenomenon in the left and right screen areas even when a process deviation of a resistor string or a channel digital analog converter (DAC) occurs. and a display device including the same.

An embodiment includes a core unit including a first color left resistance string disposed on the left side and a first color right resistance string disposed on the right side, a plurality of first color left channel DACs disposed on the left side of the core unit; a left channel output unit including a plurality of second color left channel DACs and a plurality of third color left channel DACs, disposed on the right side of the core unit, the plurality of first color right channel DACs, and the plurality of second color right channels A source driver integrated circuit including a DAC and a right channel output including a plurality of third color right channel DACs may be provided.

Another embodiment is a source driver including a core unit including a plurality of resistor strings and a data receiver, a plurality of left channel DACs disposed on the left side of the core unit, and a plurality of right channel DACs disposed on the right side of the core unit An integrated circuit may be provided.

In such a source driver integrated circuit, the number of resistor strings positioned on both sides of the data receiver may be the same.

According to another exemplary embodiment, a display panel having a plurality of data lines and a plurality of gate lines and a plurality of sub-pixels disposed therein, and one or more source drivers receiving data and outputting analog voltages to the plurality of data lines are integrated A display device including a circuit and a timing controller for transmitting data to one or more source driver integrated circuits may be provided.

In such a display device, each source driver integrated circuit includes a core unit including a first color left resistor string disposed on the left side and a first color right resistance string disposed on the right side, and disposed on the left side of the core unit, a plurality of a left channel output unit including a first color left channel DAC, a plurality of second color left channel DACs, and a plurality of third color left channel DACs, disposed on the right side of the core unit, the plurality of first color right channel DACs; and a right channel output unit including a plurality of second color right channel DACs and a plurality of third color right channel DACs.

According to the present exemplary embodiments as described above, it is possible to provide a source driver integrated circuit and a display device capable of improving image quality by preventing a block dim phenomenon.

In addition, according to the present embodiments, it is revealed that the block dim phenomenon is due to the arrangement structure of the resistor string in the source driver integrated circuit, and the source driver integrated circuit having a structure capable of preventing the block dim phenomenon and the display including the same device can be provided.

In addition, according to the present embodiments, even if a process deviation of a resistor string or a channel digital analog converter (DAC) occurs, the source driver integrated circuit has a structure that can prevent a block dim phenomenon in the left and right screen areas. and a display device including the same.

1 is a system configuration diagram of a display device according to the present exemplary embodiment.
2 is an exemplary diagram of a pixel structure of a display device according to the present exemplary embodiment.
3 is a schematic block diagram of a source driver integrated circuit according to the present embodiments.
4 is a diagram illustrating a source driver integrated circuit having a first core structure according to the present embodiments.
5 is a diagram illustrating an output voltage waveform of a source driver integrated circuit having a first core structure according to the present embodiments.
6 is a diagram illustrating a block dim phenomenon occurring in a screen according to the source driver integrated circuit having the first core structure according to the present embodiments.
7 is a diagram illustrating a source driver integrated circuit having a second core structure according to the present embodiments.
8 to 10 are diagrams illustrating a source driver integrated circuit having a first RS connection structure under a second core structure according to the present embodiments.
11 to 13 are diagrams illustrating a source driver integrated circuit having a second RS connection structure under a second core structure according to the present embodiments.
14 is a graph illustrating a waveform of an output voltage of a source driver integrated circuit having a second core structure according to the present exemplary embodiment.
15 is a diagram illustrating that a block dim phenomenon occurring on a screen is prevented according to the source driver integrated circuit having the second core structure according to the present embodiments.
16 is a diagram illustrating a first RS connection structure of a source driver integrated circuit having a third core structure according to the present embodiments.
17 is a diagram illustrating a second RS connection structure of a source driver integrated circuit having a third core structure according to the present embodiments.
18 is an exemplary diagram of each channel DAC included in the source driver integrated circuit having the first, second, and third core structures according to the present embodiments.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It should be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

1 is a system configuration diagram of a display device 100 according to the present exemplary embodiment. 2 is an exemplary diagram of a pixel structure of the display device 100 according to the present exemplary embodiments.

Referring to FIG. 1 , in the display device 100 according to the present exemplary embodiments, a plurality of data lines DL and a plurality of gate lines GL are disposed, and a plurality of subpixels SP are disposed on a display panel. 110 , the data driver 120 driving the plurality of data lines DL, the gate driver 130 driving the plurality of gate lines GL, the data driver 120 , and the gate driver 130 . may include a timing controller 140 for controlling the .

The data driver 120 receives data DATA corresponding to the digital image signal transmitted to the timing controller 140 , converts it into an analog image signal, that is, a data voltage Vdata corresponding to an analog voltage, and converts it into a plurality of data lines By outputting , multiple data lines are driven.

The gate driver 130 sequentially drives the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines.

The timing controller 140 supplies various control signals DCS and GCS to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130 .

The timing controller 140 starts scanning according to the timing implemented in each frame, and converts the image data input from the outside to match the data signal format used by the data driver 120 to convert the converted data DATA. It outputs and controls the data operation at an appropriate time according to the scan.

The gate driver 130 sequentially drives the plurality of gate lines by sequentially supplying a scan signal of an on voltage or an off voltage to the plurality of gate lines under the control of the timing controller 140 . .

The gate driver 130 may be positioned on only one side of the display panel 110 as shown in FIG. 1 or, in some cases, on both sides, according to a driving method.

The gate driver 130 may include one or more gate driver integrated circuits (GD-ICs).

When a specific gate line is opened, the data driver 120 converts the image data received from the timing controller 140 into analog data voltage and supplies it to the data lines, thereby driving a plurality of data lines.

The data driver 120 may include at least one source driver integrated circuit (SD-IC).

Each source driver integrated circuit (SD-IC) includes a shift register, a latch circuit, a digital-to-analog converter (DAC) and an output buffer. can do.

All or some of the internal components of each source driver integrated circuit SD-IC may exist for each channel CH corresponding to each data line.

In addition, each source driver integrated circuit SD-IC shifts the voltage level of the data DATA corresponding to the digital image signal corresponding to the logic signal input from the timing controller 140 to a desired voltage level (high voltage level). It may further include a level shifter (Level Shifter).

Meanwhile, the timing controller 140 includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE: Data Enable) signal, a clock signal (CLK), etc. together with the input image data. It receives various timing signals from the outside (eg, host system).

The timing controller 140 converts the input image data input from the outside according to the data signal format used by the data driver 120 to output data DATA corresponding to the converted digital image signal, as well as the data driver In order to control the 120 and the gate driver 130 , timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable signal DE, and a clock signal are received, and various control signals are received. are generated and output to the data driver 120 and the gate driver 130 .

For example, the timing controller 140 controls the gate driver 130 , a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). : Outputs various gate control signals (GCS: Gate Control Signal) including Gate Output Enable).

Here, the gate start pulse GSP controls the operation start timing of the gate driver integrated circuit GD-IC. The gate shift clock GSC is a clock signal commonly input to the gate driver integrated circuit GD-IC, and controls the shift timing of the scan signal (gate pulse). The gate output enable signal GOE designates timing information of the gate driver integrated circuit GD-IC.

In addition, the timing controller 140 controls the data driver 120 , a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE: Source). Output Enable) and output various data control signals (DCS: Data Control Signal).

Here, the source start pulse SSP controls the data sampling start timing of the source driver integrated circuit SD-IC constituting the data driver 120 . The source sampling clock SSC is a clock signal that controls sampling timing of data in each of the source driver integrated circuits SD-IC. The source output enable signal SOE controls the data output timing of the source driver integrated circuit SD-IC.

Each sub-pixel may include circuit elements such as a transistor and a capacitor.

Two or more of these sub-pixels may be combined to constitute one pixel.

Referring to FIG. 2 , each pixel may have, for example, a structure such as an RGB pixel structure, a pentile pixel structure, and a RWGB pixel structure.

Referring to FIG. 2 , in the case of the RGB pixel structure, each pixel may include a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B).

In this case, the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B are repeatedly disposed on the display panel 110 .

Referring to FIG. 2 , in the case of the RWGB pixel structure, each pixel may include a red sub-pixel (R), a white sub-pixel (W), a green sub-pixel (G), and a blue sub-pixel (B).

In this case, the red sub-pixel R, the white sub-pixel W, the green sub-pixel G, and the blue sub-pixel B are repeatedly disposed on the display panel 110 .

Referring to FIG. 2 , in the case of the pentile pixel structure, each pixel may be composed of two sub-pixels.

In the case of such a pentile pixel structure, the sub-pixels may be arranged in various shapes. As in the example of FIG. 2 , a red sub-pixel R and a green sub-pixel G constitute one pixel, and the adjacent pixel is composed of a blue sub-pixel B and a green sub-pixel G. can That is, the two pixels may include a red sub-pixel (R), a green sub-pixel (G), a blue sub-pixel (B), and a green sub-pixel (G). Here, the green subpixel G may have a smaller size than the red subpixel R and the blue subpixel B.

The pentile pixel structure utilizes the fact that the human eye cannot distinguish each sub-pixel and that green is best identified with the naked eye.

Meanwhile, the display device 100 according to the present exemplary embodiments may prevent abnormal phenomena such as block dims occurring on the screen.

To this end, the source driver integrated circuit (SD-IC) included in the display device 100 according to the present exemplary embodiment has a unique internal structure.

Here, the unique internal structure of the source driver integrated circuit (SD-IC) includes the "core structure" of the core unit included in the source driver integrated circuit (SD-IC) and the source driver integrated circuit (SD). -IC) includes an "RS connection structure" between a plurality of channel DACs (CH DACs) and a resistor string (RS) included in the IC).

Hereinafter, the source driver integrated circuit (SD-IC) according to the present embodiments will be described in more detail.

3 is a schematic block diagram of a source driver integrated circuit (SD-IC) according to the present embodiments.

Referring to FIG. 3 , the source driver integrated circuit (SD-IC) according to the present exemplary embodiments includes a core unit 300 , a left channel output unit 310 , a right channel output unit 320 , and the like.

The core unit 300 receives data DATA corresponding to the digital image signal transmitted from the timing controller 140 , and transmits the received data DATA to the left channel output unit 310 and the right channel output unit 320 . ) is passed to

The timing controller 140 provides data DATA to the source driver integrated circuit SD-IC through an interface such as an EPI interface. In this case, the timing controller 140 provides a signal including the data DATA and a clock signal. can be sent to

Accordingly, the core unit 300 of the source driver integrated circuit SD-IC separates the data DATA and the clock signal from the signal received from the timing controller 140 , and outputs the data DATA from which the clock signal is separated. It may be transmitted to the left channel output unit 310 and the right channel output unit 320 .

When the source driver integrated circuit (SD-IC) outputs the data voltage Vdata to 2n (n is a natural number greater than or equal to 1) data lines, that is, 2n channels (CH 1, CH 2, ... , CH 2n). ), the left channel output unit 310 uses the data DATA transmitted from the core unit 300 to output 2n channels CH 1 , CH 2 , ... , CH 2n) outputs the data voltage Vdata to each of the n left channels (CH 1 , CH 2 , ... CH n), and the right channel output unit 320 is transmitted from the core unit 300 . Data voltage is applied to each of n right channels (CH n+1, CH n+2, ... CH 2n) among 2n channels (CH , CH 2, ... , CH 2n) using the data DATA. (Vdata) can be output.

Meanwhile, the left channel output unit 310 receives data DATA corresponding to a digital image signal and outputs a data voltage Vdata corresponding to an analog image signal (analog voltage) to n left channels CH 1 and CH 2 . , ... CH n), it may include n left channel DACs, n left channel output buffers, etc., as well as n or less shift registers, n first latches, n A second latch may be further included.

Each of the n left channel DACs converts a digital image signal DATA corresponding to a corresponding left channel among the n left channels CH 1 , CH 2 , ... CH n into an analog image signal.

Each of the n left channel output buffers amplifies the analog video signal converted in the left channel DAC and amplified so that the analog video signal converted in the left channel DAC has sufficient current driving capability to drive the data line. The data voltage Vdata, which is a signal, is output to a data line corresponding to the corresponding left channel.

Similarly, the right channel output unit 320 receives the data DATA corresponding to the digital image signal and transmits the data voltage Vdata corresponding to the analog image signal (analog voltage) to the n right channels (CH n+1). , CH n+2, ... CH 2n), may include n right channel DACs, n right channel output buffers, etc. It may further include one latch, n second latches, and the like.

Each of the n right channel DACs converts a digital video signal DATA corresponding to a corresponding right channel among the n right channels CH n+1, CH n+2, ... CH 2n into an analog video signal.

Each of the n right channel output buffers amplifies the analog video signal converted in the right channel DAC and amplified so that the analog video signal converted in the right channel DAC has sufficient current driving capability to drive the data line. The data voltage Vdata, which is a signal, is output to a data line corresponding to the corresponding right channel.

Meanwhile, the core unit 300 includes a data receiving unit for receiving data DATA, which is a digital image signal, from the timing controller 140 and transmitting the data to the left channel output unit 310 and the right channel output unit 320 , and the left Each of the channel output unit 310 and the right channel output unit 320 may include a resistance string RS for each color used to perform digital-to-analog conversion.

Meanwhile, in the source driver integrated circuit (SD-IC) according to the present embodiments, the core unit 300 has a core structure in which the data receiving unit 400 receiving data is disposed in the center.

And, according to the number and position of the resistance strings (R-RS, G-RS, B-RS) for each color included in the core unit 300 , the core structure is the first core structure, the second core structure, and the third core. structure can be divided into

In the first core structure, one resistor string (G-RS) corresponding to the first color, one resistor string (R-RS) corresponding to the second color, and one resistor string (B-RS) corresponding to the third color. It is a core structure that only exists.

The second core structure includes two resistance strings (G-RS) corresponding to the first color, a resistance string (R-RS) corresponding to the second color, and two resistance strings (B-RS) corresponding to the third color. It is a core structure that only exists.

The third core structure may include one of a resistance string (G-RS) corresponding to the first color, a resistance string (R-RS) corresponding to the second color, and a resistance string (B-RS) corresponding to the third color, or There are two of them, and the other is a core structure in which only one exists.

The "first color", "second color" and "third color" described herein may be red, green, and blue. For example, the first color may be red, the second color may be green, and the third color may be blue, the first color may be green, the second color may be red (or blue), and the third color may be blue. (or red).

The first color described herein may be a color with the highest visibility (eg, green).

In addition, "left" and "right" described in this specification are because the source driver integrated circuit (SD-IC) has a structure in which the channel output units 310 and 320 are on both sides with respect to the central core unit 300 . , is only used to distinguish the channel compression units 310 and 320 on both sides with respect to the core unit 300 from each other, and does not necessarily mean Left and Right.

Hereinafter, for each core structure, the source driver integrated circuit (SD-IC) will be described in more detail.

4 is a diagram illustrating a source driver integrated circuit (SD-IC) having a first core structure according to the present embodiments. 5 is a graph illustrating a waveform of an output voltage of a source driver integrated circuit (SD-IC) having a first core structure according to the present exemplary embodiment. 6 is a diagram illustrating a block dim phenomenon occurring in a screen according to the source driver integrated circuit having the first core structure according to the present embodiments.

Referring to FIG. 4 , in the core unit 300 in the source driver integrated circuit (SD-IC) having the first core structure according to the present embodiments, the resistor string G-RS corresponding to the first color, the second There is only one resistor string R-RS corresponding to the two colors and one resistor string B-RS corresponding to the third color.

For example, as shown in FIG. 4 , in the core unit 300 , with respect to the data receiving unit 400 disposed in the center, one color resistance string R-RS is disposed on the left side, and two The colored resistor strings G-RS and B-RS may be disposed on the right side.

Hereinafter, a resistor string disposed on the left side with respect to the data receiver 400 is referred to as a “left resistor string” and a resistor string disposed on the right side is called a “right resistor string”.

In addition, the left resistance string and the right resistance string associated with the first color are referred to as the first color left resistance string and the first color right resistance string. The left resistance string and the right resistance string associated with the second color are referred to as the second color left resistance string and the second color right resistance string. The left resistance string and the right resistance string associated with the third color are referred to as the third color left resistance string and the third color right resistance string.

n left channel DACs included in the left channel output unit 310 (CH DAC #1, CH DAC #2, CH DAC #3, CH DAC #4, ... , CH DAC #n-3, CH DAC # Each of n-2, CH DAC #n-1, and CH DAC #n) is connected to a resistor string matching its own color.

In addition, n right channel DACs included in the right channel output unit 320 (CH DAC #n+1, CH DAC #n+2, CH DAC #n+3, CH DAC #n+4, ... , Each of CH DAC #2n-3, CH DAC #2n-2, CH DAC #2n-1, CH DAC #2n) is connected to a resistor string matching its color.

As shown in FIG. 4 , the first color right resistance string G-RS included in the core unit 300 includes n left channel DACs (CH DAC #1, CH DAC #2, CH DAC #3, A plurality of left channel DACs of the first color corresponding to the first color among CH DAC #4, ... , CH DAC #n-3, CH DAC #n-2, CH DAC #n-1, CH DAC #n) and n right channel DACs (CH DAC #n+1, CH DAC #n+2, CH DAC #n+3, CH DAC #n+4, ... , CH DAC #2n-3, CH It is also connected to a plurality of right channel DACs of the first color corresponding to the first color among DAC #2n-2, CH DAC #2n-1, and CH DAC #2n).

Similarly, as shown in FIG. 4 , the second color right resistance string R-RS included in the core unit 300 includes n left channel DACs (CH DAC #1, CH DAC #2, CH DAC #). 3, CH DAC #4, ... , CH DAC #n-3, CH DAC #n-2, CH DAC #n-1, CH DAC #n) of a plurality of second colors corresponding to the second color left Connected to channel DAC, n right channel DACs (CH DAC #n+1, CH DAC #n+2, CH DAC #n+3, CH DAC #n+4, ... , CH DAC #2n-3 , CH DAC #2n-2, CH DAC #2n-1, CH DAC #2n) is also connected to a plurality of right channel DACs of the second color corresponding to the second color.

Also, similarly, as shown in FIG. 4 , the third color right resistance string B-RS included in the core unit 300 includes n left channel DACs (CH DAC #1, CH DAC #2, CH A plurality of thirds corresponding to the third color among DAC #3, CH DAC #4, ... , CH DAC #n-3, CH DAC #n-2, CH DAC #n-1, CH DAC #n) Color Connected to left channel DAC, n right channel DACs (CH DAC #n+1, CH DAC #n+2, CH DAC #n+3, CH DAC #n+4, ... , CH DAC #2n -3, CH DAC #2n-2, CH DAC #2n-1, CH DAC #2n) is also connected to a plurality of right channel DACs of the third color corresponding to the third color.

As described above, in the first core structure, there is only one resistance string (G-RS, R-RS, B-RS) for each color, but the resistance string (G-RS, R-RS, B-RS) exists only on one side (left or right) with respect to the central data receiving unit 400 .

In the case of the first core structure, since the distances from the resistor strings of one color to the channel DACs simultaneously connected are different from each other, the resistance from the left channel DAC to the corresponding resistor string and the resistance from the right channel DAC to the corresponding resistor string are different. A resistance deviation occurs between them, and due to this, waveforms of output voltages (ie, data voltages) output from the left channel and the right channel may be different as shown in FIG. 5 .

For example, assuming that the left channel CH 1 and the right channel CH 2n are the second color (eg, red), the left channel DAC (CH DAC #1) outputting a data voltage to the left channel CH 1 and the right channel CH When the right channel DAC (CH DAC #2n) outputting the data voltage in 2n is simultaneously connected to the second color left resistor string R-RS, the second color left left resistor string R-RS is connected to the core unit 300 ), the distance A2 from the corresponding right channel DAC (CH DAC #2n) to the second color left resistance string (R-RS) is the left channel DAC (CH DAC #1). to the second color left resistance string (R-RS) is longer than the distance A1.

Accordingly, the resistance in the connection line from the right channel DAC (CH DAC #n+1) corresponding to the right channel CH 2n to the second color left resistance string R-RS is the left channel corresponding to the left channel CH 1 It is greater than the resistance in the connecting line from the DAC (CH DAC #1) to the second color left resistance string (R-RS).

Due to this resistance difference, the output voltage (Right Red CH OUT) output through the right channel DAC (CH DAC #n+1) corresponding to the right channel CH 2n is the left channel DAC (CH Compared to the output voltage (Left Red CH OUT) output through DAC #1), it rises more slowly to the corresponding voltage value. For this reason, the digital-to-analog conversion delay of the right channel DAC (CH DAC #n+1) may be larger than that of the left channel DAC (CH DAC #1). This phenomenon can be confirmed through the red channel output voltage waveform Red CH OUT of FIG. 5 .

Accordingly, as shown in FIG. 6 , in the entire area 600 supplied with the data voltage by one source driver integrated circuit (SD-IC), the screen area 610 corresponding to the right channel CH 2n is the left channel. A luminance deviation that appears darker than the screen area 620 corresponding to CH 1 may occur. Due to the luminance deviation, a vertical block dim phenomenon occurs.

As another example, assuming that the left channel CH 2 and the right channel CH 2n-1 are the first color (eg, green), the left channel DAC (CH DAC #2) that outputs the data voltage to the left channel CH 2, When the right channel DAC (CH DAC #2n-1) that outputs the data voltage to the right channel CH 2n-1 is simultaneously connected to the first color left resistor string (G-RS), the first color left resistor string (G- RS) is located biased to the "right" in the core unit 300, the distance B1 from the left channel DAC (CH DAC #2) to the first color left resistance string (G-RS) is the right channel The distance B2 from the DAC (CH DAC #2n-1) to the first color left resistance string (G-RS) is longer than B2.

Accordingly, the resistance in the connection line from the left channel DAC (CH DAC #2) corresponding to the left channel CH 2 to the first color left resistance string (G-RS) is the right channel corresponding to the right channel CH 2n-1 It is greater than the resistance in the connecting line from the DAC (CH DAC #2n-1) to the first color left resistance string (G-RS).

Due to this resistance difference, the output voltage (Left Green CH OUT) output through the left channel DAC (CH DAC #2) corresponding to the left channel CH 2 is the right channel DAC (CH OUT) corresponding to the right channel CH 2n-1 Compared to the output voltage (Right Green CH OUT) output through DAC #2n-1), it rises more slowly to the corresponding voltage value. For this reason, the digital-to-analog conversion delay of the left channel DAC (CH DAC #2) may be larger than that of the right channel DAC (CH DAC #2n-1). This phenomenon can be confirmed through the green channel output voltage waveform (Green CH OUT) of FIG. 5 .

Accordingly, as shown in FIG. 6 , in the entire area 600 supplied with the data voltage by one source driver integrated circuit (SD-IC), the screen area 630 corresponding to the left channel CH 2 is the right channel. A luminance deviation that appears darker than the screen area 640 corresponding to CH 2n-1 may occur. Due to the luminance deviation, a vertical block dim phenomenon occurs.

In the case of not only the first color (eg, green) but also the second color (eg, blue), since the left resistance string (B-RS) of the second color is located biased toward the “right” in the core unit 300 , The same block dim phenomenon as in the first color may occur.

Below, a source driver having a second core structure according to the present embodiments capable of preventing a block dim phenomenon that may occur in a source driver integrated circuit (SD-IC) having a first core structure according to the present embodiments. An integrated circuit (SD-IC) will be described.

In the drawings related to the second core structure, the resistor string is denoted as "(color index)-RS-# (position index)".

Here, the color index indicates which color of the channel DAC the corresponding resistor string is connected to. When the corresponding resistor string is connected to the channel DAC of the first color, the color index is denoted as G, and the corresponding resistor string is the second color. When connected to the color channel DAC, the color index is indicated by R, and when the corresponding resistor string is connected to the second color channel DAC, the color index is indicated by B.

And, the position index indicates whether the corresponding resistance string is located on the left side or the right side of the data receiving unit 400, and when the corresponding resistance string is located on the left side of the data receiving unit 400, the position index is expressed as 1, and the corresponding When the resistance string is located on the right side of the data receiving unit 400 , the position index is indicated by 2.

In addition, the channel DAC (left channel DAC, right channel DAC) related to the second core structure is expressed as "(color index) (RS identification index)-CH DAC # (channel identification index)".

Here, the color index indicates a color of a sub-pixel to which a data voltage is output through the corresponding channel DAC, and is expressed as one of R, G, and B.

And, the RS identification index identifies the position of the resistance string connected to the corresponding channel DAC. When the resistance string connected to the corresponding channel DAC is located on the left side of the data receiving unit 400, the RS identification index is expressed as 1 and , when the resistance string connected to the corresponding channel DAC is located on the right side of the data receiving unit 400 , the RS identification index is indicated by 2.

And, the channel identification index identifies the channel (left channel, right channel) corresponding to the corresponding channel DAC, and in the case of the left channel, the channel identification index is one of 1, 2, 3, ..., n, and , in the case of the right channel, the channel identification index is one of n+1, n+2, n+3, ..., 2n.

7 is a diagram illustrating a source driver integrated circuit (SD-IC) having a second core structure according to the present embodiments.

Referring to FIG. 7 , a source driver integrated circuit (SD-IC) having a second core structure according to the present embodiments includes a core unit 300 and a left channel output unit ( 310 , and a right channel output unit 320 on the right side of the core unit 300 , and the like.

Referring to FIG. 7 , in the core unit 300 , the data receiving unit 400 is disposed at the center.

Referring to FIG. 7 , in the core unit 300 , on the “left” side of the data receiving unit 400 , a left resistance string of a first color (G-RS #1) and a left resistance string of a second color (R-RS #1) are ) and the third color left resistor string (B-RS #1) are disposed.

Referring to FIG. 7 , in the core unit 300 , on the “right side” of the data receiving unit 400 , a first color right resistance string (G-RS #2) and a second color right resistance string (R-RS #2) are ) and a third color right resistance string (B-RS #2) are disposed.

As described above, in the case of the second core structure, there are two resistance strings for each color in the core unit 300 , and the two resistance strings for each color are located on the left and right sides with respect to the data receiving unit 400 . placed one by one.

That is, three resistor strings (R-RS #1, G-RS #1, B-RS #1) are disposed on the left side of the data receiver 400 , and three resistor strings (R-RS #1, G-RS #1, B-RS #1) are also disposed on the right side of the data receiver 400 R-RS #2, G-RS #2, B-RS #2) are deployed.

Referring to FIG. 7 , the left channel output unit 310 is disposed on the left side of the core unit 300 , and n left channels corresponding to n left channels CH 1 , CH 2 , ... CH n . Includes DACs (CH DAC #1, CH DAC #2, …, CH DAC #n).

These n left channel DACs (CH DAC #1, CH DAC #2, ..., CH DAC #n) are a plurality of first color left channel DACs, a plurality of second color left channel DACs, and a plurality of third color left channels. It consists of a channel DAC.

In addition, referring to FIG. 7 , the right channel output unit 320 is disposed on the right side of the core unit 300 , and is provided to n right channels (CH n+1, CH n+2, ... CH 2n). Includes n corresponding right channel DACs (CH DAC #n+1, CH DAC #n+2, ..., CH DAC #2n).

The n right channel DACs (CH DAC #n+1, CH DAC # n+2, …, CH DAC #2n) include a plurality of first color right channel DACs, a plurality of second color right channel DACs, and a plurality of second color right channel DACs. It consists of a three-color right-channel DAC.

The source driver integrated circuit (SD-IC) having the second core structure according to the above-described embodiments may be applied to all pixel structures.

However, a plurality of first color left channel DACs, a plurality of second color left channel DACs, and a plurality of third colors constituting n left channel DACs (CH DAC #1, CH DAC #2, ..., CH DAC #n) The arrangement order of the left channel DAC may vary depending on the pixel structure.

For example, when the pixel structure is the RGB pixel structure of FIG. 2 , n left channel DACs (CH DAC #1, CH DAC #2, ..., CH DAC #n) are the red left channel DACs (second color left Channel DAC), green left channel DAC (first color left channel DAC), and blue channel DAC (third color left channel DAC) may be repeatedly arranged in the order.

For another example, when the pixel structure is the pentile pixel structure of FIG. 2 , n left channel DACs (CH DAC #1, CH DAC #2, ..., CH DAC #n) are the red left channel DACs (second color left channel DAC), green left channel DAC (first color left channel DAC), blue channel DAC (third color left channel DAC), and green left channel DAC (first color left channel DAC) are to be placed repeatedly in the order can

In the core unit 300 of the source driver integrated circuit (SD-IC) having the second core structure according to the above-described embodiments, the first, second, and third color left resistor strings R-RS #1, G-RS #1, B-RS #1) and the first, second, and third right resistance strings (R-RS #2, G-RS #2, B-RS #2) are connected to n left channel DACs ( (CH DAC #1, ..., CH DAC #n) and the n right channel DACs (CH DAC #n+1, ..., CH DAC #2n) are connected to the structure (RS connection structure), It may be a 1 RS connection structure or a second RS connection structure.

In the first RS connection structure, first, second, and third color left resistance strings (R-RS #1, G-RS #1, B-RS #1) have n left channel DACs ((CH DAC #1) , ... , CH DAC #n) and the first, second, and third right resistance strings (R-RS #2, G-RS #2, B-RS #2) are n right channel DACs (CH DAC #n+1, ... , CH DAC #2n) is the only structure connected.

In the second RS connection structure, the first, second, and third color left resistance strings (R-RS #1, G-RS #1, B-RS #1) have n left channel DACs ((CH DAC #1) , ... , CH DAC #n) and n right channel DACs (CH DAC #n+1, ... , CH DAC #2n) are all connected, R-RS #2, G-RS #2, B-RS #2) also n left channel DACs ((CH DAC #1, ... , CH DAC #n) and n right channel DACs (CH DAC # It is a structure connected to all n+1, ... , CH DAC #2n).

Hereinafter, the first RS connection structure in the source driver integrated circuit (SD-IC) having the second core structure according to the present embodiments will be described. However, it is assumed that the pixel structure is an RGB structure.

8 to 10 are diagrams illustrating a source driver integrated circuit (SD-IC) having a first RS connection structure under a second core structure according to the present embodiments.

Referring to FIG. 8 , the plurality of second color left channel DACs (R1-CH DAC #1, R1-CH DAC #4, ..., R1-CH DAC #n-2) includes a second color left resistance string R -RS #1) is all connected.

In addition, the plurality of first color left channel DACs (G1-CH DAC #2, G1-CH DAC #5, ..., G1-CH DAC #n-1) includes the first color left channel DAC (G-RS #1). ) are all connected with

In addition, the plurality of third color left channel DACs (B1-CH DAC #3, B1-CH DAC #6, …, B1-CH DAC #n) includes a third color left resistance string (B-RS #1) and all connected

Referring to FIG. 8 , the plurality of second color right channel DACs (R2-CH DAC #n+1, …, R2-CH DAC #2n-5, R2-CH DAC #2n-2) is a second color right Both are connected to the resistor string (R-RS #2).

In addition, the plurality of first color right channel DACs (G2-CH DAC #n+2, …, G2-CH DAC #2n-4, G2-CH DAC #2n-1) is a first color right channel DAC (G- RS #2) is all connected.

In addition, the plurality of third color right channel DACs (B2-CH DAC #n+3, …, B2-CH DAC #2n-3, B2-CH DAC #2n) is a third color right channel DAC (B-RS # 2) is all connected.

The second connection structure as above will be described from the standpoint of the resistor string as follows.

The second color left resistance string (R-RS #1) is, as shown in FIG. 9, assuming a 10-bit channel DAC, all second color left channel DACs (R1-CH DAC #1, R1-CH DAC #4) , R1-CH DAC #7, …, R1-CH DAC #n-2).

In addition, the second color right resistance string (R-RS #2) is all the second color right channel DACs (R2-CH DAC #n+1, R2- It is connected to CH DAC #n+4, R2-CH DAC #n+7, …, R2-CH DAC #2n-2).

And, the first color left resistance string (G-RS #1) is, all first color left channel DACs (G1-CH DAC #2, G1-CH DAC #5, G1-CH DAC #8, …, G1- CH DAC #n-1) is connected.

And, the first color right resistance string (G-RS #2) is all the first color right channel DACs (G2-CH DAC #n+2, G2-CH DAC #n+5, G2-CH DAC #n+) 8, …, G2-CH DAC #2n-1) is connected.

And, the third color left resistance string (B-RS #1) is, all the third color left channel DACs (B1-CH DAC #3, B1-CH DAC #6, B1-CH DAC #9, …, B1- CH DAC #n) is connected.

And, the third color right resistance string (B-RS #2), all the third color right channel DACs (B2-CH DAC #n+3, B2-CH DAC #n+6, B2-CH DAC #n+) 9, …, B2-CH DAC #2n) is connected.

The above-described first RS connection structure may be organized as shown in Table 1 below.

Meanwhile, with respect to the source driver integrated circuit (SD-IC) having the first RS connection structure under the second core structure according to the present embodiments described above, the effect of reducing the deviation between the RS connection distances will be examined. However, the first color will be considered representatively.

Referring to FIG. 8 , an odd number of the plurality of first color left channel DACs (G1-CH DAC #2, G1-CH DAC #5, G1-CH DAC #8, …, G1-CH DAC #n-1) As a representative of the first color left channel DAC, G1-CH DAC #2 is spaced apart from the first color left resistance string (G-RS #1) by L (G1-CH DAC #2).

Even-numbered first color left channel DAC among the plurality of first color left channel DACs (G1-CH DAC #2, G1-CH DAC #5, G1-CH DAC #8, …, G1-CH DAC #n-1) As a representative of , G1-CH DAC #5 is spaced apart from the left resistance string (G-RS #1) of the first color by L (G1-CH DAC #5).

Referring to FIG. 8 , a plurality of first color right channel DACs (G2-CH DAC #n+2, G2-CH DAC #n+5, G2-CH DAC #n+8, …, G2-CH DAC #2n) As a representative of the odd-numbered first color right channel DAC among -1), G2-CH DAC #2n-4 is equal to the first color right resistance string (G-RS #2) and L(G2-CH DAC #2n-4). away

Even number of first color right channel DACs (G2-CH DAC #n+2, G2-CH DAC #n+5, G2-CH DAC #n+8, …, G2-CH DAC #2n-1) As a representative of the first color right channel DAC, G2-CH DAC #2n-1 is spaced apart from the first color right resistance string (G-RS #2) by L(G2-CH DAC #2n-1).

Referring to FIG. 8 , the distance value obtained by adding L(G1-CH DAC #2) and L(G1-CH DAC #5) is L(G2-CH DAC #2n-4) and L(G2-CH DAC # It is almost equal to the distance value plus 2n-1).

If this relational characteristic is generalized to all colors, it can be expressed as Equation (1).

Referring to the first expression of Equation 1, all second color left channel DACs (R1-CH DAC #1, R1-CH DAC #4, R1-CH DAC #7, …, R1-CH DAC #n- 2), the sum of the distances to the left resistance string of the second color (R-RS #1), and all the right channel DACs of the second color (R2-CH DAC #n+1, R2-CH DAC #n) +4, R2-CH DAC #n+7, … , R2-CH DAC #2n-2) with respect to the sum of the distances with the second color right resistance string (R-RS #2) will be approximately the same. (∑L(R1-CH DAC #a) ≒ ∑L(R2-CH DAC #n+a), a=1, 4, 7, …, n-2).

Referring to the second expression of Equation 1, all first color left channel DACs (G1-CH DAC #2, G1-CH DAC #5, G1-CH DAC #8, …, G1-CH DAC #n- For 1), the sum of the distances from the first phase left resistance string (G-RS #1) and all first color right channel DACs (G2-CH DAC #n+2, G2-CH DAC #n) For +5, G2-CH DAC #n+8, …, G2-CH DAC #2n-1), the sum of the distances with the first color right resistance string (G-RS #2) will be approximately the same. (∑L(G1-CH DAC #b) ≒ ∑L(G2-CH DAC #n+b, b=2, 5, 8, …, n-1).

Referring to the third expression of Equation 1, all third color left channel DACs (B1-CH DAC #3, B1-CH DAC #6, B1-CH DAC #9, …, B1-CH DAC #n) is the sum of the distance to the third color left resistor string (B-RS #1) and all third color right channel DACs (B2-CH DAC #n+3, B2-CH DAC #n+6) , B2-CH DAC #n+9, …, B2-CH DAC #2n) may have approximately the same distance value as the sum of the distances from the third color right resistor string (B-RS #2) (∑). L(B1-CH DAC #c) ≒ ∑ L(B2-CH DAC #n+c), c=3, 6, 9, …, n).

Hereinafter, the second RS connection structure in the source driver integrated circuit (SD-IC) having the second core structure according to the present embodiments will be described. However, it is assumed that the pixel structure is an RGB structure.

11 to 13 are diagrams illustrating a source driver integrated circuit (SD-IC) having a second RS connection structure under a second core structure according to the present embodiments.

11 , a plurality of second color left channel DACs (R1-CH DAC #1, R2-CH DAC #4, R1-CH DAC #7, R2-CH DAC #10, …, R1-CH DAC # n-5, R2-CH DAC #n-2) are alternately connected to the second color left resistance string R-RS #1 and the first color right resistance string G-RS #2.

And, a plurality of first color left channel DACs (G1-CH DAC #2, G2-CH DAC #5, G1-CH DAC #8, G2-CH DAC #11, …, G1-CH DAC #n-4, G2-CH DAC #n-1) is alternately connected to the first color left resistance string (G-RS #1) and the first color right resistance string (G-RS #2).

And, a plurality of third color left channel DACs (B1-CH DAC #3, B2-CH DAC #6, B1-CH DAC #9, B2-CH DAC #12, …, B1-CH DAC #n-3, B2-CH DAC #n) is alternately connected to the third color left resistance string (B-RS #1) and the first color right resistance string (G-RS #2).

11 , a plurality of second color right channel DACs (R1-CH DAC #n+1, R2-CH DAC #n+4, R1-CH DAC #n+7, R2-CH DAC #n+10) , …, R1-CH DAC #2n-5, R2-CH DAC #2n-2), the second color left resistance string (R-RS #1) and the second color right resistance string (R-RS #2) is alternately connected with

And, a plurality of first color right channel DACs (G1-CH DAC #n+2, G2-CH DAC #n+5, G1-CH DAC #n+8, G2-CH DAC #n+11, …, G1 -CH DAC #2n-4, G2-CH DAC #2n-1) are alternately connected to the first color left resistance string (G-RS #1) and the first color right resistance string (G-RS #2) do.

And, a plurality of third color right channel DACs (B1-CH DAC #n+3, B2-CH DAC #n+6, B1-CH DAC #n+9, B2-CH DAC #n+12, …, B1) -CH DAC #2n-3, B2-CH DAC #2n) are alternately connected to the third color left resistance string (B-RS #1) and the third color right resistance string (B-RS #2).

Table 2 below summarizes the second RS connection structure from the viewpoint of the aforementioned channel DAC.

Hereinafter, the second RS connection structure will be described again from the standpoint of the resistor string.

The second color left resistance string (R-RS #1) is a plurality of second color left channel DACs (R1-CH DAC #1, R2- Among the CH DAC #4, R1-CH DAC #7, R2-CH DAC #10, …, R1-CH DAC #n-5, R2-CH DAC #n-2), the odd-numbered left channel DAC (R1-CH Connected to DAC #1, R1-CH DAC #7, …, R1-CH DAC #n-5), and a plurality of second color right channel DACs (R1-CH DAC #n+1, R2-CH DAC #n) +4, R1-CH DAC #n+7, R2-CH DAC #n+10, …, R1-CH DAC #2n-5, R2-CH DAC #2n-2), the odd-numbered right channel DAC (R1) -CH DAC #n+1, R1-CH DAC #n+7, ..., R1-CH DAC #2n-5) may be connected.

The second color right resistance string (R-RS #2) is a 10-bit channel DAC, as shown in FIG. 13 , a plurality of second color left channel DACs (R1-CH DAC #1, R2-) Among the CH DAC #4, R1-CH DAC #7, R2-CH DAC #10, …, R1-CH DAC #n-5, R2-CH DAC #n-2), the even-numbered left channel DAC (R2-CH Connected to DAC #4, R2-CH DAC #10,…, R2-CH DAC #n-2), and a plurality of second color right channel DACs (R1-CH DAC #n+1, R2-CH DAC #n) +4, R1-CH DAC #n+7, R2-CH DAC #n+10, …, R1-CH DAC #2n-5, R2-CH DAC #2n-2), even-numbered right channel DAC (R2) -CH DAC #n+4, R2-CH DAC #n+10, ..., R2-CH DAC #2n-2) may be connected.

The first color left resistance string (G-RS #1) includes a plurality of first color left channel DACs (G1-CH DAC #2, G2-CH DAC #5, G1-CH DAC #8, G2-CH DAC # 11, …, G1-CH DAC #n-4, G2-CH DAC #n-1) of the odd-numbered first color left channel DAC (G1-CH DAC #2, G1-CH DAC #8, …, G1-) CH DAC #n-4) and a plurality of first color right channel DACs (G1-CH DAC #n+2, G2-CH DAC #n+5, G1-CH DAC #n+8, G2-CH DAC #n+11, …, G1-CH DAC #2n-4, G2-CH DAC #2n-1) of the odd-numbered first color right channel DAC (G1-CH DAC #n+2, G1-CH DAC # n+8, …, G1-CH DAC #2n-4).

The first color right resistance string (G-RS #2) includes a plurality of first color left channel DACs (G1-CH DAC #2, G2-CH DAC #5, G1-CH DAC #8, G2-CH DAC # 11, …, G1-CH DAC #n-4, G2-CH DAC #n-1) of the even-numbered first color left channel DAC (G2-CH DAC #5, G2-CH DAC #11, …, G2- CH DAC #n-1) and a plurality of first color right channel DACs (G1-CH DAC #n+2, G2-CH DAC #n+5, G1-CH DAC #n+8, G2-CH Among DAC #n+11, …, G1-CH DAC #2n-4, G2-CH DAC #2n-1), even-numbered first color right channel DAC (G2-CH DAC #n+5, G2-CH DAC # n+11, …, G2-CH DAC #2n-1).

The third color left resistor string (B-RS #1) includes a plurality of third color left channel DACs (B1-CH DAC #3, B2-CH DAC #6, B1-CH DAC #9, B2-CH DAC # 12, …, B1-CH DAC #n-3, B2-CH DAC #n) of the third odd color left channel DAC (B1-CH DAC #3, B1-CH DAC #9, …, B1-CH DAC) #n-3) and a plurality of third color right channel DACs (B1-CH DAC #n+3, B2-CH DAC #n+6, B1-CH DAC #n+9, B2-CH DAC # Among n+12, …, B1-CH DAC #2n-3, B2-CH DAC #2n), the odd third color right channel DAC (B1-CH DAC #n+3, B1-CH DAC #n+9, …, B1-CH DAC #2n-3) can be connected.

The third color right resistor string (B-RS #2) is composed of a plurality of third color left channel DACs (B1-CH DAC #3, B2-CH DAC #6, B1-CH DAC #9, B2-CH DAC # 12, …, B1-CH DAC #n-3, B2-CH DAC #n) of even-numbered third color left channel DAC (B2-CH DAC #6, B2-CH DAC #12, …, B2-CH DAC) #n) and a plurality of third color right channel DACs (B1-CH DAC #n+3, B2-CH DAC #n+6, B1-CH DAC #n+9, B2-CH DAC #n+ 12, …, B1-CH DAC #2n-3, B2-CH DAC #2n) of even-numbered third color right channel DAC (B2-CH DAC #n+6, B2-CH DAC #n+12, … , B2-CH DAC #2n) can be connected.

Table 3 below summarizes the second RS connection structure in terms of the above-described resistance string.

Hereinafter, the effect of reducing the deviation between the RS connection distances of the source driver integrated circuit (SD-IC) having the second RS connection structure under the second core structure according to the above-described embodiments will be described. However, the first color will be considered representatively.

Referring to FIG. 11 , G1-CH DAC #2 as a representative among the odd-numbered first color left channel DACs (G1-CH DAC #2, G1-CH DAC #8, …, G1-CH DAC #n-4) Wow, the left resistor string (G-RS #1) of the first color is spaced apart by L (G1-CH DAC #2). G2-CH DAC #5 as a representative among the even-numbered left channel DACs of the first color (G2-CH DAC #5, G2-CH DAC #11, ..., G2-CH DAC #n-1) and the right of the first color The resistor strings (G-RS #2) are spaced apart by L(G2-CH DAC #5).

And, G1-CH DAC #2n as a representative among odd-numbered first color right channel DACs (G1-CH DAC #n+2, G1-CH DAC #n+8, …, G1-CH DAC #2n-4) -4 and the first color left resistor string (G-RS #1) are spaced apart by L(G1-CH DAC #2n-4). G2-CH DAC #2n-1 as a representative among even-numbered first color right channel DACs (G2-CH DAC #n+5, G2-CH DAC #n+11, …, G2-CH DAC #2n-1) And, the first color right resistance string (G-RS #2) is spaced apart by L(G2-CH DAC #2n-1).

At this time, the distance value obtained by adding L(G1-CH DAC #2) and L(G2-CH DAC #5) is L(G1-CH DAC #2n-4) and L(G2-CH DAC #2n-1) It is almost equal to the distance value plus

If this relational characteristic is generalized to all colors, it can be expressed as Equation (2).

Referring to the first equation in Equation 2, all odd-numbered second color left channel DACs (R1-CH DAC #d, d=1, 7, 13, …, n-5) and the second color left resistance string The sum of the distances of (R-RS #1) (∑ L(R1-CH DAC #d)) and all even-numbered second color left channel DACs (R2-CH DAC #e, e=4, 10, 16) , …, n-2) and the sum of the distances (∑ L(R2-CH DAC #e)) of the second color right resistor string (R-RS #2) The sum of the distances between the channel DACs (R1-CH DAC #n+d, d=1, 7, 13, …, n-5) and the second color left resistance string (R-RS #1) (∑ L(R1) -CH DAC #n+d)) and all even-numbered second color left channel DACs (R2-CH DAC #n+e, e=4, 10, 16, …, n-2) and second color right The sum of the distances of the resistor strings R-RS #2 (∑ L(R2-CH DAC #n+e)) is approximately equal to a distance value.

Referring to the second equation in Equation 2, all odd-numbered first color left channel DACs (G1-CH DAC #f, f=2, 8, 14, ..., n-4) and the first color left resistance string The sum of the distances of (G-RS #1) (∑ L(G1-CH DAC #f)) and all even-numbered first color left channel DACs (G2-CH DAC #g, g=5, 11, 17) , …, n-1) and the sum of the distances (∑ L(G2-CH DAC #g)) of the first color right resistor string (G-RS #2) The sum of the distances between the channel DACs (G1-CH DAC #n+f, f=2, 8, 14, …, n-4) and the first color left resistance string (G-RS #1) (∑ L(G1) -CH DAC #n+f)) and all even-numbered first color right channel DACs (G2-CH DAC #n+g, g=5, 11, 17, …, n-1) and first color right The sum of the distances (∑ L(G2-CH DAC #n+g)) of the resistor strings G-RS #2 is approximately the same.

Referring to the third equation in Equation 2, all odd-numbered third color left channel DACs (B1-CH DAC #h, h=3, 9, 15, …, n-3) and the third color left resistor string The sum of the distances of (B-RS #1) (∑ L(B1-CH DAC #h)) and all even-numbered third color left channel DACs (B2-CH DAC #i, i=6, 12, 18) , …, n) and the sum of the distances of the third color right resistance string (B-RS #2) (∑ L(B2-CH DAC #i)), the distance value is,

Distance between all odd-numbered third color right channel DACs (B1-CH DAC #n+h, h=3, 9, 15, …, n-3) and third color left resistance string (B-RS #1) sum (∑ L(B1-CH DAC #n+h)) and all even-numbered third color right channel DACs (B2-CH DAC #n+i, i=6, 12, 18, …, n) The sum of the distances (∑ L(B2-CH DAC #n+i)) of the third color right resistor string (B-RS #2) is almost the same.

14 is a graph illustrating a waveform of an output voltage of a source driver integrated circuit (SD-IC) having a second core structure according to the present exemplary embodiment. 15 is a diagram illustrating that a block dim phenomenon occurring in a screen is prevented according to the source driver integrated circuit having the second core structure according to the present embodiments.

Referring to FIG. 14 , as described above, for each of the first color, the second color, and the third color, the distance between the left channel DACs and the left and right resistance strings of the corresponding color, and the right channel DACs and the corresponding color Since the distances of the left and right resistance strings of is almost the same, the output voltage waveform output from the left channel and the output voltage waveform output from the right channel are almost the same.

That is, in the first core structure, the resistor string is biased to the left or right, so that the output voltage waveform output from the left channel and the output voltage waveform output from the right channel are different, and the delay of the digital-to-analog conversion process occurs significantly, In the second core structure, since there is one resistor string on the left and one on the right side of the same color, the output voltage waveform output from the left channel is almost the same as the output voltage waveform output from the right channel, and the delay of the digital-to-analog conversion process is almost also doesn't happen

Accordingly, as shown in FIG. 15 , in the entire region 1500 supplied with the data voltage by one source driver integrated circuit (SD-IC), for example, the second color corresponds to the right channel CH 2n. There is no luminance deviation between the screen area 1510 corresponding to the left channel CH 1 and the screen area 1520 corresponding to the left channel CH 1 . Accordingly, a vertical block dim phenomenon occurring in the first core structure does not occur.

In addition, as shown in FIG. 15 , in the entire region 1500 supplied with the data voltage by one source driver integrated circuit (SD-IC), for example, the first color corresponds to the left channel CH 2 There is no luminance deviation between the screen area 1530 corresponding to the screen area 1530 and the screen area 1540 corresponding to the right channel CH 2n-1. Accordingly, a vertical block dim phenomenon occurring in the first core structure does not occur.

However, in the source driver integrated circuit (SD-IC) having the second core structure according to the present exemplary embodiments, resistors corresponding to all colors (first, second, and third colors) on the left side of the data receiver 400 . Since the string and resistor strings corresponding to all colors (first, second, and third colors) must also be disposed on the right side of the data receiving unit 400 , the size of the core unit 300 is turned on to the source driver integrated circuit There may be a disadvantage in that the size of the (SD-IC) increases.

Therefore, it is advantageous to design the second core structure in terms of line resistance deviation, DAC delay and block dim prevention, but for size reduction, one color or two colors sensitive to line resistance deviation, DAC delay and block dim phenomenon are used. For color only, the resistor string is placed on both the left and right sides of the data receiver 400, and for two colors or one color that is less sensitive to line resistance deviation, DAC delay and block dim, the resistor string is used in the data receiver ( 400), it can also be considered to design with a third core structure arranged only on the left or right side.

As an example of the third structure, resistor strings G-RS #1 and G-RS #2 corresponding to the first color are disposed on both the left and right sides of the data receiver 400 , and the resistor strings G-RS #1 and G-RS #2 corresponding to the second color The source driver integrated circuit has a structure in which the resistor string R-RS is disposed only on the left side of the data receiver 400 , and the resistor string B-RS corresponding to the third color is disposed only on the right side of the data receiver 400 . (SD-IC) will be described with reference to FIGS. 16 to 17 .

16 and 17 , the core unit 300 includes a data receiver 400 , a first color left resistance string (G-RS #1), a first color right resistance string (G-RS #2), a second color left resistance string R-RS and a third color right resistance string B-RS.

In the core unit 300 , the data receiving unit 400 for receiving data is disposed at the center, and the first color left resistance string (G-RS #1) is disposed on the left side of the data receiving unit 400 , and the first color The right resistance string G-RS #2 is disposed on the right side of the data receiver 400 .

Also, in the core unit 300 , the second color left resistance string R-RS is disposed on the left side of the data receiving unit 400 , and the third color right resistance string B-RS is the data receiving unit 400 . placed on the right

16 and 17 , the left channel output unit 310 is disposed on the left side of the core unit 300, and includes a plurality of first color left channel DACs, a plurality of second color left channel DACs, and a plurality of second color left channel DACs. It includes n left channel DACs (CH DAC #1, CH DAC #2, …, CH DAC #n) consisting of three color left channel DACs.

In addition, the right channel output unit 320 is disposed on the right side of the core unit 300 and includes a plurality of first color right channel DACs, a plurality of second color right channel DACs, and a plurality of third color right channel DACs. It includes n right channel DACs (CH DAC #n+1, CH DAC #n+2, ..., CH DAC #2n).

16 is a diagram illustrating a first RS connection structure of a source driver integrated circuit (SD-IC) having a third core structure according to the present embodiments. However, it is assumed that the pixel structure is an RGBG pen tile structure.

Referring to FIG. 16 , the plurality of left channel DACs of the first color (G1-CH DAC #2, G1-CH DAC #4, ...) are all connected to the left resistance string of the first color (G-RS #1). In addition, the plurality of first color right channel DACs (..., G2-CH DAC #2n-2, G2-CH DAC #2n) are all connected to the first color right channel DAC (G-RS #2).

That is, the first color left resistance string (G-RS #1) is selected from among n left channel DACs (CH DAC #1, CH DAC #2, ..., CH DAC #n) included in the left channel output unit 310 . All first color left channel DACs (G1-CH DAC #2, G1-CH DAC #4, ...) are connected. The first color right resistance string (G-RS #2) includes n right channel DACs (CH DAC #n+1, CH DAC # n+2, …, CH DAC #2n) included in the right channel output unit 320 . ) among all first color right channel DACs (…, G2-CH DAC #2n-2, G2-CH DAC #2n).

Meanwhile, a plurality of second color left channel DACs (R-CH DAC #1, R-CH DAC #5, …) and a plurality of second color right channel DACs (…, R-CH DAC #2n-7, R- CH DAC #2n-3) are all connected to the second color left resistor string R-RS.

That is, the second color left resistance string R-RS is a plurality of n left channel DACs (CH DAC #1, CH DAC #2, ..., CH DAC #n) included in the left channel output unit 310 . 2nd color left channel DAC of (R-CH DAC #1, R-CH DAC #5, …) and n right channel DACs (CH DAC #n+1, CH DAC # n+2, …, CH DAC # 2n), all of the plurality of second color right channel DACs (..., R-CH DAC #2n-7, R-CH DAC #2n-3) are connected.

In addition, a plurality of third color left channel DACs (B-CH DAC #3, B-CH DAC #7, …) and a plurality of third color right channel DACs (…, B-CH DAC #2n-5, B- CH DAC #2n-1) is connected to the third color right resistor string (B-RS).

That is, the third color right resistance string B-RS includes a plurality of n left channel DACs (CH DAC #1, CH DAC #2, ..., CH DAC #n) included in the left channel output unit 310 . 3rd color left channel DAC of (B-CH DAC #3, B-CH DAC #7, …) and n right channel DACs (CH DAC #n+1, CH DAC # n+2, …, CH DAC # 2n), all of the third color right channel DACs (..., B-CH DAC #2n-5, B-CH DAC #2n-1) are connected.

The source driver integrated circuit (SD-IC) having a first RS connection structure under the third core structure shown in FIG. 16 has a first RS connection structure under the second core structure shown in FIG. 8 for a first color. Although it has the advantages of the source driver integrated circuit (SD-IC) (prevention of line resistance deviation, DAC delay and block dim phenomenon, etc.), it does not have these advantages for the second color and the third color.

However, since the second color and the third color are colors with low visibility, in order to reduce the size, the resistor string R-RS corresponding to the second color is placed only on the left side of the data receiving unit 400 , Even if the resistor strings B-RS corresponding to the three colors are disposed only on the right side of the data receiving unit 400 , the block dim phenomenon caused by the line resistance deviation and the DAC delay may not be severe enough to be negligible.

Unlike the second color and the third color, in the case of the first color, the resistance corresponding to the first color is a color with high visibility that can seriously cause block dim even by a slight line resistance deviation and DAC delay. The strings G-RS #1 and G-RS #2 are designed to have a redundant structure disposed on both the left and right sides of the data receiver 400 .

17 is a diagram illustrating a second RS connection structure of a source driver integrated circuit (SD-IC) having a third core structure according to the present embodiments.

Referring to FIG. 17 , a plurality of left channel DACs of a first color (G1-CH DAC #2, G2-CH DAC #4, ...) include a left resistance string of a first color (G-RS #1) and a first color It is connected alternately with the right resistance string (G-RS #2).

That is, among the plurality of first color left channel DACs (G1-CH DAC #2, G2-CH DAC #4, …), G1-CH DAC #2, G1-CH DAC #6, …, G1-CH DAC #n-2 is connected to the first color left resistor string (G-RS #1). G2-CH DAC #4, G2-CH DAC# 8, ... , G2-CH DAC #n are connected to the first color right resistance string (G-RS #2).

Referring to FIG. 17 , the plurality of first color right channel DACs (..., G2-CH DAC #2n-2, G2-CH DAC #2n) includes a first color left resistance string (G-RS #1) and a first It is connected alternately with the color right resistor string (G-RS #2).

That is, among the plurality of first color right channel DACs (..., G2-CH DAC #2n-2, G2-CH DAC #2n), G1-CH DAC #n+2, G1-CH DAC #n+6, . .. , G1-CH DAC #2n-2 is connected to the first color left resistor string (G-RS #1). G2-CH DAC #n+4, G2-CH DAC #n+8, ..., G2-CH DAC #2n are connected to the first color right resistance string (G-RS #2).

Meanwhile, a plurality of second color left channel DACs (R-CH DAC #1, R-CH DAC #5, …) and a plurality of second color right channel DACs (…, R-CH DAC #2n-7, R- CH DAC #2n-3) are all connected to the second color left resistor string R-RS.

That is, the second color left resistance string R-RS is a plurality of n left channel DACs (CH DAC #1, CH DAC #2, ..., CH DAC #n) included in the left channel output unit 310 . 2nd color left channel DAC of (R-CH DAC #1, R-CH DAC #5, …) and n right channel DACs (CH DAC #n+1, CH DAC # n+2, …, CH DAC # 2n), all of the plurality of second color right channel DACs (..., R-CH DAC #2n-7, R-CH DAC #2n-3) are connected.

In addition, a plurality of third color left channel DACs (B-CH DAC #3, B-CH DAC #7, …) and a plurality of third color right channel DACs (…, B-CH DAC #2n-5, B- CH DAC #2n-1) is connected to the third color right resistor string (B-RS).

That is, the third color right resistance string B-RS includes a plurality of n left channel DACs (CH DAC #1, CH DAC #2, ..., CH DAC #n) included in the left channel output unit 310 . 3rd color left channel DAC of (B-CH DAC #3, B-CH DAC #7, …) and n right channel DACs (CH DAC #n+1, CH DAC # n+2, …, CH DAC # 2n), all of the third color right channel DACs (..., B-CH DAC #2n-5, B-CH DAC #2n-1) are connected.

In the case of the second RS connection structure shown in FIG. 17 , similarly to the first RS connection structure, the resistance strings G-RS #1 and G-RS #2 corresponding to the first color with high visibility are transferred to the data receiving unit 400 . ), the line resistance deviation and DAC delay can be reduced by designing to have a redundant structure disposed on both the left and right sides, and thus the block dim phenomenon can be prevented.

Meanwhile, a process deviation between the left channel DACs and the right channel DACs, or the left resistance strings (R-RS #1, G-RS #1, B-RS #1) and the right resistance strings (R-RS #2) , G-RS #2, B-RS #2) When a process deviation occurs between the first RS-connected structure and the left-right block dim phenomenon according to the process deviation, the second RS-connected structure may It can greatly reduce or prevent the left and right block dims that can occur due to deviation.

18 is a diagram illustrating each channel DAC included in the source driver integrated circuit (SD-IC) having the first, second, and third core structures according to the present embodiments in the form of a 3-bit DAC.

According to the present exemplary embodiments as described above, it is possible to provide a source driver integrated circuit (SD-IC) and a display device 100 capable of improving image quality by preventing a block dim phenomenon.

In addition, according to the present embodiments, it is revealed that the block dim phenomenon is due to the arrangement structure of the resistor string in the source driver integrated circuit, and the structure (second, third core structure, first structure) capable of preventing the block dim phenomenon , a source driver integrated circuit (SD-IC) having a second RS connection structure) and a display device 100 including the same can be provided.

In addition, according to the present embodiments, even if a process deviation of a resistor string or a channel digital analog converter (DAC) occurs, a structure (second and third) capable of preventing a block dim phenomenon in the left and right screen areas It is possible to provide a source driver integrated circuit (SD-IC) having a core structure and a second RS connection structure) and a display device 100 including the same.

The above description and the accompanying drawings are merely illustrative of the technical spirit of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine configurations within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: data driving unit
130: gate driver
140: timing controller
300: core unit
310: left channel output unit
320: right channel output unit
400: data receiving unit

Claims (13)

A source driver integrated circuit comprising:
a core unit including a left resistance string of a first color disposed on a left side and a right resistance string of a first color disposed on a right side;
a left channel output unit disposed on the left side of the core unit and including a plurality of first color left channel DACs, a plurality of second color left channel DACs, and a plurality of third color left channel DACs; and
a right channel output unit disposed on the right side of the core unit and including a plurality of first color right channel DACs, a plurality of second color right channel DACs, and a plurality of third color right channel DACs;
The core unit is
Further comprising a second color left resistor string and a third color left resistor string disposed on the left side,
A source driver integrated circuit further comprising a second color right resistor string and a third color right resistor string disposed on the right side. According to claim 1,
The core unit, the data receiving unit for receiving data is disposed in the center,
the first color left resistor string is disposed on the left side of the data receiving unit;
The first color right resistor string is a source driver integrated circuit disposed on a right side of the data receiving unit. delete According to claim 1,
The plurality of first color left channel DACs are all connected to the first color left resistance string, and the plurality of first color right channel DACs are all connected to the first color right resistance string,
the plurality of second color left channel DACs are all connected to the second color left resistance string, and the plurality of second color right channel DACs are all connected to the second color right resistance string,
The plurality of third color left channel DACs are all connected to the third color left resistance string, and the plurality of third color right channel DACs are all connected to the third color right resistance string. According to claim 1,
the plurality of first color left channel DACs are alternately connected to the first color left resistance string and the first color right resistance string;
the plurality of first color right channel DACs are alternately connected to the first color left resistance string and the first color right resistance string;
the plurality of second color left channel DACs are alternately connected to the second color left resistance string and the second color right resistance string;
the plurality of second color right channel DACs are alternately connected to the second color left resistance string and the second color right resistance string;
the plurality of third color left channel DACs are alternately connected to the third color left resistance string and the third color right resistance string;
The plurality of third color right channel DACs are alternately connected to the third color left resistance string and the third color right resistance string. A source driver integrated circuit comprising:
a core unit including a left resistance string of a first color disposed on a left side and a right resistance string of a first color disposed on a right side;
a left channel output unit disposed on the left side of the core unit and including a plurality of first color left channel DACs, a plurality of second color left channel DACs, and a plurality of third color left channel DACs; and
a right channel output unit disposed on the right side of the core unit and including a plurality of first color right channel DACs, a plurality of second color right channel DACs, and a plurality of third color right channel DACs;
The core unit is
Further comprising a second color left resistance string disposed on the left side,
The source driver integrated circuit further comprising a third color right resistor string disposed on the right side. 7. The method of claim 6,
The plurality of first color left channel DACs are all connected to the first color left resistance string, and the plurality of first color right channel DACs are all connected to the first color right resistance string,
all of the plurality of second color left channel DACs and the plurality of second color right channel DACs are connected to the second color left resistance string;
The plurality of third color left channel DACs and the plurality of third color right channel DACs are both connected to the third color right resistance string. 7. The method of claim 6,
The plurality of first color left channel DACs are alternately connected to the first color left resistance string and the first color right resistance string, and the plurality of first color right channel DACs include the first color left resistance string and the first color right channel DAC. It is alternately connected to the first color right resistance string,
all of the plurality of second color left channel DACs and the plurality of second color right channel DACs are connected to the second color left resistance string;
The plurality of third color left channel DACs and the plurality of third color right channel DACs are both connected to the third color right resistance string. delete a display panel in which a plurality of data lines and a plurality of gate lines are disposed, and a plurality of subpixels are disposed;
one or more source driver integrated circuits for receiving data and outputting analog voltages to the plurality of data lines; and
a timing controller to transmit the data to the one or more source driver integrated circuits;
Each of the source driver integrated circuits,
a core unit including a left resistance string of a first color disposed on a left side and a right resistance string of a first color disposed on a right side;
a left channel output unit disposed on the left side of the core unit and including a plurality of first color left channel DACs, a plurality of second color left channel DACs, and a plurality of third color left channel DACs; and
a right channel output unit disposed on the right side of the core unit and including a plurality of first color right channel DACs, a plurality of second color right channel DACs, and a plurality of third color right channel DACs;
The core unit is
Further comprising a second color left resistance string disposed on the left side,
The display device further comprising a third color right resistance string disposed on the right side. 11. The method of claim 10,
The core unit, the data receiving unit for receiving the data is disposed in the center,
the first color left resistor string is disposed on the left side of the data receiving unit;
The first color right resistance string is disposed on a right side of the data receiving unit. a display panel in which a plurality of data lines and a plurality of gate lines are disposed, and a plurality of subpixels are disposed;
one or more source driver integrated circuits for receiving data and outputting analog voltages to the plurality of data lines; and
a timing controller to transmit the data to the one or more source driver integrated circuits;
Each of the source driver integrated circuits,
a core unit including a left resistance string of a first color disposed on a left side and a right resistance string of a first color disposed on a right side;
a left channel output unit disposed on the left side of the core unit and including a plurality of first color left channel DACs, a plurality of second color left channel DACs, and a plurality of third color left channel DACs; and
a right channel output unit disposed on the right side of the core unit and including a plurality of first color right channel DACs, a plurality of second color right channel DACs, and a plurality of third color right channel DACs;
The core unit is
Further comprising a second color left resistor string and a third color left resistor string disposed on the left side,
The display device further comprising a second color right resistance string and a third color right resistance string disposed on the right side. delete

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