KR102215935B1 - Organic light emitting display device and method for driving the same - Google Patents

Abstract

The present embodiments relate to an organic light emitting display device capable of shortening a sensing and compensation time for a characteristic value deviation of driving transistors through a sensing block-based sensing method and a driving method thereof.

Description

Organic light emitting display device and its driving method {ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

The present embodiments relate to an organic light emitting display device and a driving method thereof.

Recently, organic light emitting display devices that are in the spotlight as display devices use organic light emitting diodes (OLEDs) that emit light by themselves, so that the response speed is fast, and the contrast ratio, luminous efficiency, luminance and viewing angle are large. There is an advantage.

Each sub-pixel disposed on the organic light-emitting display panel of the organic light-emitting display device basically includes an organic light-emitting diode and a driving transistor that drives the organic light-emitting diode.

Such an organic light emitting display device displays an image by adjusting the brightness of the organic light emitting diode using a driving current of a driving transistor determined based on a data voltage output from a data driver.

Meanwhile, the driving transistors in each subpixel on the organic light emitting display panel have unique characteristic values such as a threshold voltage and mobility. As the driving time increases, the driving transistor undergoes degradation, so that the intrinsic characteristic values change.

Such deterioration of the driving transistor may cause a variation in characteristic values between the driving transistors in each subpixel, resulting in a variation in luminance between the subpixels, thereby degrading image quality.

Accordingly, a technique for compensating for luminance deviation between subpixels, that is, a technique for sensing and compensating for characteristic value deviations between driving transistors, has been proposed.

However, there is a problem in that it takes a considerable amount of time to sense a variation in characteristic values of the driving transistors of the subpixels arranged on the organic light emitting display panel. In particular, as the resolution increases, the sensing time becomes longer as the number of subpixels increases.

In addition, since it takes a considerable amount of time to sense the characteristic value deviation, the timing of performing the compensation process (e.g., data compensation amount calculation, data change, etc.) to compensate for the characteristic value deviation is delayed that much, and only after a long time has passed. , The final characteristic value deviation compensation procedure (luminance deviation compensation procedure) can be completed.

This delay in sensing and compensation may cause considerable inconvenience to customers.

In addition, since sensing and compensation are not performed when the characteristic value deviation actually occurs, sensing and compensation may be unnecessary.

In addition, when sensing and compensation are performed when a power-off signal of the organic light emitting display device is generated, power may actually be turned off while sensing and compensation are in progress. In this case, some sensing and compensation procedures performed before the power is actually turned off becomes meaningless, and there is a disadvantage that the sensing and compensation procedure is performed again from the beginning next time.

In addition, if the degree of deviation of the characteristic value is not very large, sensing and compensation that is performed frequently involves excessive accumulation and storage of related information (e.g. sensing data, threshold voltage deviation, data compensation amount, etc.). , There is also a disadvantage that can lower the image quality.

An object of the present embodiments is to provide an organic light emitting display device capable of shortening sensing and compensation time and a driving method thereof.

Another object of the present embodiments is to provide an organic light-emitting display device and a driving method thereof that prevents unnecessary and unnecessary sensing and compensation procedures from proceeding.

In an exemplary embodiment, a plurality of data lines and a plurality of gate lines are disposed, and a plurality of subpixels are disposed in a matrix type, a data driver driving a plurality of data lines, and a plurality of gate lines are provided. A gate driver to drive, and a timing controller for controlling the data driver and the gate driver, wherein the timing controller outputs a first gate driving control signal having N signal sections corresponding to N subpixel rows to the gate driver. An organic light-emitting display device can be provided.

In the first gate driving control signal output from the timing controller of such an organic light emitting display device, the selected B (2≤B<N) representative subpixel rows from among N signal sections corresponding to N subpixel rows. The length of the signal section may be longer than the length of the section corresponding to each of the remaining subpixel rows.

Another embodiment may provide a method of driving an organic light emitting display device in which a plurality of data lines and a plurality of gate lines are disposed, and a plurality of subpixels are disposed in a matrix type.

The driving method of the organic light emitting display device includes the steps of setting two or more representative subpixel rows in a plurality of subpixel rows, sensing a threshold voltage deviation for driving transistors in the two or more representative subpixel rows, and If the sensed threshold voltage deviation is less than the threshold value, sensing is terminated, and if the sensed threshold voltage deviation is greater than or equal to the threshold value, driving transistors in the remaining subpixel rows excluding at least two representative subpixel rows from a plurality of subpixel rows It may include the step of sensing a threshold voltage deviation.

According to the exemplary embodiments described above, it is possible to provide an organic light emitting display device capable of shortening sensing and compensation time and a driving method thereof.

In addition, according to the present exemplary embodiments, it is possible to provide an organic light-emitting display device and a driving method thereof that prevents unnecessary and unnecessary sensing and compensation procedures from proceeding.

1 is a schematic system configuration diagram of an organic light emitting display device according to example embodiments.
2 is an exemplary diagram of a subpixel structure of an organic light emitting display device according to the present embodiments.
3 and 4 are exemplary diagrams of a pixel structure of an organic light emitting display device according to the present embodiments.
5 and 6 are diagrams illustrating a sensing structure and a sensing method of the organic light emitting display device according to the present embodiments.
7 is a diagram illustrating a sensing block for compensating a threshold voltage according to the present embodiments.
8 and 9 are diagrams for describing a sensing operation based on a sensing block according to the present embodiments.
10 is a flowchart of a sensing method based on a sensing block according to the present embodiments.
11 is a diagram illustrating a sensing block information table for a sensing block-based sensing operation according to the present embodiments.
12 is an exemplary diagram of a sensing operation based on a sensing block according to the present embodiments.
13 is a diagram illustrating a first gate driving control signal VSC and a second gate driving control signal VOE required for gate driving for a sensing operation based on a sensing block according to the present embodiments.
14 is a diagram illustrating a first gate driving control signal VSC and a second gate driving control signal VOE before sensing block information is updated in an example of a sensing operation based on a sensing block according to the present embodiments. .
15 is a diagram illustrating a first gate driving control signal VSC and a second gate driving control signal VOE after sensing block information is updated in an example of a sensing operation based on a sensing block according to the present embodiments. .

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to elements of each drawing, the same elements may have the same numerals as possible even if they are indicated on different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known configuration or function may obscure the subject matter of the present invention, a detailed description thereof may be omitted.

In addition, in describing the constituent elements of the present invention, terms such as first, second, A, B, (a), (b) may be used. These terms are only for distinguishing the component from other components, and the nature, order, order, or number of the component is not limited by the term. When a component is described as being "connected", "coupled" or "connected" to another component, the component may be directly connected or connected to that other component, but other components between each component It is to be understood that is "interposed", or that each component may be "connected", "coupled" or "connected" through other components.

1 is a schematic system configuration diagram of an organic light emitting display device 100 according to the present embodiments.

Referring to FIG. 1, an organic light emitting display device 100 according to the present embodiments includes an organic light emitting display panel 110, a data driver 120, a gate driver 130, a timing controller 140, and the like. .

On the organic light-emitting display panel 110, C (C is the number of colors, 3 or 4) * M (M is a natural number of 1 or more) data lines (DL 1, DL 2, ..., DL C*M) are arranged When N (N is a natural number of 1 or more) gate lines GL 1, ..., GL N are disposed, (C*M)*N sub-pixels (SP: Sub-Pixels) may be disposed. .

Meanwhile, N (N is a natural number of 1 or more) gate lines GL 1 ′, ..., GL N ′ may be further disposed on the OLED display panel 110 according to the subpixel structure.

In this way, even when N gate lines (GL 1', ..., GL N') are further arranged, the number of subpixels may be the same as (C*M)*N. In this case, one Two gate lines are connected to the subpixel.

The data driver 120 drives C*M data lines DL 1, DL 2, ..., DL C*M.

The gate driver 130 sequentially sequentially performs N or 2N gate lines (GL 1, ..., GL N, or GL 1, ..., GL N, GL 1', ..., GL N') Drive.

The timing controller 140 controls the data driver 120 and the gate driver 130.

The timing controller 140 starts scanning according to the timing implemented in each frame, converts the image data input from the host system (not shown) according to the data signal format used by the data driver 120 to convert the converted data. (Data) is output, and data drive is controlled at an appropriate time according to the scan.

The gate driver 130 sequentially drives the gate lines by sequentially supplying scan signals of an on voltage or an off voltage to the gate lines under the control of the timing controller 140.

The gate driver 130 may be positioned on only one side of the display panel 110 as shown in FIG. 1, or may be positioned on both sides in some cases, depending on the driving method.

In addition, the gate driver 130 may include a plurality of gate driver integrated circuits (Gate Driver ICs), such a plurality of gate driver integrated circuits, tape automated bonding (TAB: Tape Automated mated bonding) method or chip It may be connected to the bonding pad of the display panel 110 in an on-glass (COG) method, or implemented in a GIP (Gate In Panel) type and directly disposed on the display panel 110, and in some cases, display It may be integrated and disposed on the panel 110.

Each of the plurality of gate driver integrated circuits mentioned above may include a shift register, a level shifter, and the like.

When a specific gate line is opened, the data driver 120 converts the data received from the timing controller 140 into an analog data voltage Vdata and supplies the data to the data lines, thereby driving the data lines.

The data driver 120 may include a plurality of source driver integrated circuits (also referred to as source driver ICs, data driver ICs), and the plurality of source driver integrated circuits include tape-automated bonding ( TAB: Tape Automated Bonding) or chip-on-glass (COG) is connected to the bonding pad of the display panel 110, or may be directly disposed on the display panel 110. In some cases, the display panel It may be integrated and disposed at (110).

Each of the plurality of source driver integrated circuits mentioned above includes a shift register, a latch, a digital analog converter (DAC), an output butter, etc., and in some cases, sensing an analog voltage value for subpixel compensation It may further include an analog digital converter (ADC) for converting into digital values and generating and outputting sensing data.

A plurality of source driver integrated circuits may be implemented in a Chip On Film (COF) method. In each of the plurality of source driver integrated circuits, one end is bonded to at least one source printed circuit board, and the other end is bonded to the display panel 110.

Meanwhile, the host system mentioned above includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE) signal, and a clock signal (CLK), along with the image data of the input image. Various timing signals are transmitted to the timing controller 140.

In addition to converting the image data Data input from the host system according to the data signal format used by the data driving unit 120 to output the converted image data Data, the data driving unit 120 ) And the gate driver 130, a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, and a timing signal such as a clock signal are received, and various control signals are generated to control the data driver 120 ) And the gate driver 130.

For example, in order to control the gate driver 130, the timing controller 140 includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). : Outputs a gate control signal (GCS) including Gate Output Enable). The gate start pulse GSP controls operation start timings of the gate driver integrated circuits constituting the gate driver 130. The gate shift clock GSC is a clock signal commonly input to gate driver integrated circuits and controls shift timing of a scan signal (gate pulse). The gate output enable signal GOE designates timing information of gate driver integrated circuits.

In order to control the data driver 120, the timing controller 140 includes a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE: Souce Output Enable). ) Outputs a data control signal (DCS) including. The source start pulse SSP controls the data sampling start timing of the source driver integrated circuits constituting the data driver 120. The source sampling clock SSC is a clock signal that controls the sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the data driver 120. In some cases, if image data (Data) input to the data driver 120 is transmitted according to the mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse (SSP) and the source sampling clock (SSC) may be omitted. have.

Referring to FIG. 1, the display device 100 is a power controller that supplies various voltages or currents to the display panel 110, the data driver 120, the gate driver 130, or controls various voltages or currents to be supplied. (Not shown) may further be included. Such a power controller is also referred to as a power management integrated circuit (PMIC).

In each of the C*M*N subpixels SP arranged on the organic light emitting display panel 110 of the organic light emitting display device 100 according to the above-described embodiments, one organic light emitting diode (OLED) As a driving circuit for driving an Emitting Diode), a driving transistor (DRT), a switching transistor for applying a data voltage to a gate node of the driving transistor when a corresponding row is selected by a scan signal. ), and a storage capacitor (Cstg: Storage Capacitor) that maintains the data voltage for one frame time.

That is, each subpixel of the organic light emitting display device 100 according to the present embodiments includes two or more transistors and one or more capacitors.

Meanwhile, the driving transistor DRT in each subpixel has intrinsic characteristic values such as a threshold voltage (Vth) and mobility.

As the driving time of the driving transistor DRT increases, degradation proceeds, and the inherent characteristic value also changes.

Accordingly, a variation in characteristic values between the driving transistors DRT in each subpixel may occur, and thus, a variation in luminance between each subpixel may occur.

The luminance deviation between each sub-pixel may cause a luminance non-uniformity phenomenon in the organic light emitting display panel 110, and thus image quality may be greatly degraded.

Accordingly, the organic light emitting display device 100 according to the present exemplary embodiments provides a technology for sensing the unique characteristic value between the driving transistors (DRT) in each subpixel, identifying the characteristic characteristic value deviation, and compensating for the characteristic characteristic value deviation. do.

Hereinafter, a technique for compensating for such an intrinsic characteristic value will be described in more detail.

However, below, for convenience of explanation, a threshold voltage deviation compensation technology is described as a unique characteristic value deviation compensation technology, and each subpixel includes one organic light emitting diode (OLED), three transistors, and one capacitor. An example of a 3T (Transistor) 1C (Capacitor) structure will be described.

First, a subpixel having a 3T1C structure will be described with reference to FIG. 2.

2 is an exemplary diagram of a subpixel structure of the organic light emitting display device 100 according to the present embodiments.

Referring to FIG. 2, each subpixel includes, in addition to one organic light emitting diode (OLED), three transistors including a driving transistor (DRT), a switching transistor (T1), and a sensing transistor (T2), and one storage. It has a 3T1C structure including a capacitor (Cstg).

The sub-pixel structure illustrated in FIG. 2 is an exemplary diagram of a structure to which a sensing and compensation function is applied to compensate for a deviation in characteristic values (eg, threshold voltage and mobility) of the driving transistor DRT.

Intrinsic characteristic value deviation compensation of the driving transistor (DRT) is used in the same meaning as the luminance deviation compensation of the sub-pixel, and since the data to be supplied to the sub-pixel must be changed to compensate for the luminance deviation, it is also used in the same meaning as "data compensation" do. That is, transistor characteristic value deviation compensation, luminance deviation compensation, data compensation, and pixel compensation are all used interchangeably.

A driving transistor (DRT) is a transistor that drives an organic light-emitting diode (OLED), a first node (N1 node) corresponding to a gate node, and a first electrode of the organic light-emitting diode (OLED) (for example, an anode electrode or A third node electrically connected to a second node (N2 node, for example, a source node or drain node) electrically connected to a drain electrode) and a driving voltage line (DVL) for supplying a driving voltage (EVDD). It has a node (N3 node, eg drain node or source node).

The switching transistor T1 is a transistor for applying a data voltage Vdata to a node N1 corresponding to a gate node of the driving transistor DRT, and the scan signal SCAN applied to the gate node through the corresponding gate line GL ), and is electrically connected between the N1 node corresponding to the gate node of the driving transistor DRT and the data line DL.

A storage capacitor (Cstg) is electrically connected between nodes N1 and N2 of the driving transistor DRT, and serves to maintain a constant voltage for one frame time.

The sensing transistor T2 is controlled by a sense signal SENSE, which is a type of scan signal applied to the gate node from the corresponding gate line GL', and a reference voltage line that supplies a reference voltage (Vref) ( It is electrically connected between the RVL: Reference Voltage Line) and the N2 node of the driving transistor (DRT).

Meanwhile, the organic light emitting display device 100 may be electrically connected to the reference voltage line RVL by a switch SW connected to one side of the reference voltage line RVL and a switching operation of the switch SW. It may further include an analog to digital converter (ADC).

The analog-to-digital converter (ADC) senses a voltage of a sensing node in each of a plurality of subpixels, generates sensing data based on the sensed voltage, and transmits the sensing data to the timing controller 140. Here, the sensing node is a node capable of sensing the threshold voltage of the driving transistor DRT, and may be an N2 node of the driving transistor DRT.

The switch SW may connect the reference voltage supply node 210 or the node 220 connected to the analog-to-digital converter (ADC) to the node 230 connected to the reference voltage line RVL according to the switching timing control signal. have.

When the switch SW connects the reference voltage supply node 210 to the node 230 connected to the reference voltage line RVL according to the switching timing control signal, the reference voltage Vref is applied to the reference voltage line RVL. By being supplied, the reference voltage Vref may be applied to the node N2 of the driving transistor DRT through the turned-on sensing transistor T2.

When the switch SW connects the node 220 connected to the analog-to-digital converter ADC to the node 230 connected to the reference voltage line RVL according to the switching timing control signal, the analog digital corresponding to the sensing unit The converter ADC may sense the voltage of the reference voltage line RVL.

In this case, when the sensing transistor T2 is turned on, the analog-to-digital converter ADC may sense the voltage of the node N2 of the driving transistor DRT.

In this way, the sensing node through which the analog-to-digital converter (ADC) senses a voltage may be an N2 node corresponding to a source node or a drain node of the driving transistor DRT.

Here, the voltage sensed by the analog-to-digital converter ADC is output to the drain node or the source node of the switching transistor T1 through the data line DL and applied to the N1 node of the driving transistor DRT. ) And the threshold voltage Vth of the driving transistor DRT (sensed voltage = Vdata-Vth).

Accordingly, the threshold voltage Vth of the driving transistor DRT can be determined using the voltage Vdata-Vth sensed by the analog-to-digital converter ADC and the known data voltage Vdata.

The analog-to-digital converter (ADC) senses the voltage of a sensing node in each of a plurality of subpixels, converts the sensed voltage to a digital value, and generates sensing data including the converted digital value to the timing controller 140. Perform the sensing process to transmit.

When such an analog-to-digital converter (ADC) is used, the voltage (analog value) of the sensing node in each subpixel is sensed, converted into a digital value, and provided to the timing controller 140, so that the timing controller 140 is based on the digital value. The threshold voltage of the driving transistor DRT can be accurately sensed.

Here, the voltage sensed by the analog-to-digital converter ADC may be expressed as a data voltage Vdata and a threshold voltage Vth of the driving transistor DRT (sense voltage = Vdata-Vth).

The timing controller 140 may receive the sensing data and, based on the received sensing data, find out the threshold voltage Vth of the driving transistor DRT in each subpixel, and determine the threshold voltage deviation ΔVth. .

Here, the timing controller 140 may store the received sensing data, the found threshold voltage, or the determined threshold voltage deviation data in the memory 200.

The timing controller 140 calculates a data compensation amount (ΔData) for each subpixel, and transfers the calculated data compensation amount (ΔData) to the memory 200 to compensate for the threshold voltage deviation (ΔVth). You can save it.

In this way, after the data compensation amount for each subpixel is calculated, the timing controller 140 changes the data to be supplied to each subpixel based on the data compensation amount for each subpixel and supplies it to the data driver 120. , The data driver 120 converts the supplied data into a data voltage and applies it to the subpixels, so that compensation is actually performed.

Meanwhile, the switching timing control signal mentioned above is a switching operation in order to set the voltage of the second node N2 of the driving transistor DRT according to the driving operation of the display mode or the sensing mode. As a signal for controlling (On/Off), it may be output from the timing controller 140.

Meanwhile, the analog-to-digital converter (ADC) described above may be included in each of a plurality of source driver integrated circuits included in the data driver 120.

In this way, by including the analog-to-digital converter (ADC) corresponding to the sensing configuration for compensation in each source driver integrated circuit, the number of parts can be reduced, and the sensing operation can be performed in connection with data driving. have.

Meanwhile, one reference voltage line RVL may exist for each subpixel column or one for each of two or more subpixel columns.

Meanwhile, referring to FIG. 2, two gate lines GL and GL' for applying two scan signals SCAN and SENSE to the gate nodes of two transistors T1 and T2 in each subpixel are different gates. It may be a line or the same single gate line.

If the two gate lines GL and GL' that apply two scan signals SCAN and SENSE to the gate nodes of the two transistors T1 and T2 in each subpixel are different gate lines, FIG. 1 Each of the N gate lines GL 1, GS 2, ..., GL N shown in FIG. 1 is considered to include two gate lines.

For example, in FIG. 1, GL 1 is a gate line GL 1 that applies a scan signal SCAN to a gate node of a switching transistor T1 in a corresponding subpixel, and a gate node of a sensing transistor T2 in a corresponding subpixel. It includes a gate line GL 1'that applies a low sense signal SENSE.

3 and 4 are exemplary diagrams of a pixel structure of an organic light emitting display device according to the present embodiments.

3 and 4, C*M*N subpixels SP are disposed on the organic light emitting display panel 110, and M*N number of subpixels SP are arranged. Pixel (P: Pixel) is defined.

Here, "C" is the number of colors of subpixels, which is 3 or 4.

Referring to FIG. 3, when C=3, one pixel P may be composed of a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B.

In this case, 3*M*N subpixels SP are disposed on the organic light emitting display panel 110 to define M*N pixels P having an RGB subpixel structure.

Referring to FIG. 4, when C=4, one pixel (P) is composed of a red subpixel (R), a white subpixel (W), a green subpixel (G), and a blue subpixel (B). I can.

In this case, 4*M*N subpixels SP are disposed on the organic light-emitting display panel 110 to define M*N pixels P having an RWGB subpixel structure.

If, in the organic light-emitting display panel 110, 4*M*N subpixels SP are arranged in an RWGB subpixel structure, and one reference voltage line RVL is arranged for every four subpixel columns. In this case, as shown in FIG. 6, the organic light emitting display panel 110 and the sensing structure may be shown.

5 and 6 are diagrams for describing a sensing structure and a sensing method of the organic light emitting display device 100 according to the present embodiments.

5 is a plan view of the display device 100 according to the exemplary embodiments. However, FIG. 5 shows a case of C=4, in which 4*M*N subpixels are arranged on the organic light emitting display panel 110 in an RWGB subpixel structure.

Referring to FIG. 5, the organic light emitting display panel 110 includes 4M data lines DL 1, DL 2, ..., DL 4M, and N gate lines GL 1, ..., GL N. And 4*M*N subpixels are arranged, so that M*N pixels each including four subpixels R, W, G, and B are defined.

Referring to FIG. 5, two driving voltage lines for supplying the driving voltage EVDD may be disposed for each pixel column. One reference voltage line RVL supplying the reference voltage Vref may be disposed for each pixel column (four subpixel columns).

Referring to FIG. 5, two driving voltage lines arranged in correspondence with each pixel column are on both sides of each pixel column, that is, the left side of the red subpixel R and the right side of the blue subpixel B. May be formed parallel to the direction in which the data line is formed.

For example, two driving voltage lines arranged to correspond to the first pixel column including P(1,1), ..., P(1,N) are DVL 1 and DVL 1'. Two driving voltage lines arranged corresponding to the m-th pixel column including P(m,1), ..., P(m,N) are DVL m and DVL m'. The two driving voltage lines arranged in correspondence with the M-th pixel column including P(M,1), ..., P(M,N) are DVL M and DVL M'. Here, the number attached to the DVL is a number that identifies the pixel row.

Referring to FIG. 5, among two driving voltage lines formed corresponding to each pixel column, one driving voltage line applies a driving voltage EVDD to a red subpixel R and a white subpixel W. The remaining driving voltage lines may supply the driving voltage EVDD to the green subpixel G and the blue subpixel B.

Referring to FIG. 5, in the organic light emitting display panel 110, reference voltage lines RVL 1, ..., RVL m, .. corresponding to four sub-pixel columns (ie, one pixel column) exist one by one in the organic light emitting display panel 110. ., RVL M) is placed. That is, in the organic light emitting display panel 110, there are M reference voltage lines RVL 1, ..., RVL m, ..., RVL M.

For example, one reference voltage line RVL formed corresponding to each pixel column is formed in the middle of each pixel column, that is, parallel to the data line formation direction between the white subpixel W and the green subpixel G Can be. However, in FIG. 5, in order to distinguish the pixel column, the reference voltage line is displayed by attaching numbers (1, ..., m, ..., M) identifying the pixel column to the RVL.

Referring to FIG. 5, reference voltage lines RVL 1, ..., RVL m, ..., RVL M arranged one for each pixel column are red sub-pixels (R) and white sub-pixels. The reference voltage Vref may be supplied to all of the (W), green subpixels G, and blue subpixels B.

Meanwhile, referring to FIG. 5, a plurality of analog-to-digital converters (ADCs) are electrically connected to M reference voltage lines (RVL 1, ..., RVL m, ..., RVL M).

Referring to FIG. 6, a plurality of analog-to-digital converters (ADCs) simultaneously sense red sub-pixels in a first sub-pixel row (sub-pixels receiving a scan signal SCAN from GL 1), and then, white The subpixels are simultaneously sensed, then the green subpixels are sensed at the same time, and the blue subpixels are sensed at the same time. As such, when the sensing operation for the first subpixel row is all completed, the second subpixel row ( The same sensing operation is also performed for subpixels receiving the scan signal SCAN from GL 2 ).

Referring to FIG. 6, a plurality of analog-to-digital converters (ADCs) perform a sensing operation for an N-1th subpixel row (subpixels receiving a scan signal SCAN from GL N-1) in the same manner. After all of the sensing operations are performed on the N-th subpixel row (subpixels receiving the scan signal SCAN from GL N), all sensing operations on the organic light emitting display panel 110 are performed. To complete.

Accordingly, the time Tpanel for sensing all 4*M*N subpixels arranged on the organic light emitting display panel 110 is "(4*Tsp)*N". Here, Tsp is the time taken to sense one subpixel, and since subpixels of the same color are sensed together in one subpixel row, Tsp is used to sense all subpixels of the same color in one subpixel row. It can also be called the time it takes. N is the number of subpixel rows and is the number of gate lines that supply the scan signal SCAN to the gate node of the switching transistor T1.

According to the above-described sensing operation, in order to detect the threshold voltage deviation by sensing the threshold voltages for the driving transistors DRT in all subpixels disposed on the organic light emitting display panel 110, it is possible to detect the threshold voltage deviation for a considerable long time (approximately a few minutes to Tens of minutes) may be required.

In addition, since it takes a considerable time to find out the threshold voltage deviation, the timing of performing the compensation process (e.g., data compensation amount calculation, data change, etc.) to compensate for the threshold voltage deviation is delayed that much, and only after a long period of time has passed. The final compensation process can be concluded.

This delay in sensing and compensation may cause considerable inconvenience to customers.

In addition, since sensing and compensation are not performed when the threshold voltage deviation actually occurs, sensing and compensation may be unnecessary.

In addition, when sensing and compensation are performed when a power-off signal of the organic light-emitting display device 100 is generated, power may actually be turned off during sensing and compensation. In this case, some sensing and compensation procedures performed before the power is actually turned off becomes meaningless, and there is a disadvantage that the sensing and compensation procedure is performed again from the beginning next time.

In addition, when the degree of the threshold voltage deviation is not very large, the frequent sensing and compensation is a disadvantage of excessively accumulating and storing related information (e.g., sensing data, threshold voltage deviation, data compensation amount, etc.). For this reason, there is also a disadvantage in that the image quality may be rather deteriorated.

Accordingly, the present embodiments provide a sensing block-based sensing method capable of greatly reducing sensing and compensation time and minimizing meaningless sensing and compensation procedures by overcoming the disadvantages of the above-described sensing and compensation method.

According to the sensing block-based sensing method according to the present embodiments, the driving transistors in two or more representative subpixel rows selected from among a plurality of subpixel rows are not sensed, rather than sensing characteristic values of the driving transistors in the entire plurality of subpixel rows Sensing the characteristic value deviation (e.g., threshold voltage deviation) for each field, and if the sensed threshold voltage deviation is less than the threshold value, the sensing is terminated, and only when the sensed threshold voltage deviation is greater than the threshold value, two subpixel rows are Threshold voltage deviation of the driving transistors in the remaining subpixel rows except for the representative subpixel row above is sensed.

Hereinafter, a sensing method based on a sensing block according to the present embodiments will be described with reference to FIGS. 7 to 15.

7 is a diagram illustrating a sensing block for compensating a threshold voltage according to the present embodiments. 8 and 9 are diagrams for describing a sensing operation based on a sensing block according to the present embodiments.

Referring to FIG. 7, the organic light emitting display device 100 according to the present embodiments provides a sensing method based on a sensing block to compensate for a threshold voltage.

To this end, as shown in FIG. 7, N subpixel rows arranged on the organic light emitting display panel 110 are grouped by L (2≤L<N) and B (B: a natural number of 2≤B<N, N : The number of subpixel rows or gate lines) is grouped into sensing blocks (SB #0, SB #1, ..., SB #(B-1)).

Here, B is the number of sensing blocks, and L is the number of subpixel rows in one sensing block.

Referring to FIG. 7, each of B sensing blocks (SB #0, SB #1, ..., SB #(B-1)) includes L subpixel rows.

Here, the L subpixel rows correspond to the L gate lines GL.

That is, each of the L subpixel rows is a set of subpixels arranged in the same row receiving the scan signal SCAN from one gate line GL, and includes a plurality of red subpixels R and a plurality of white subpixels. A pixel W, a plurality of green subpixels G, and a plurality of blue subpixels B are included.

Referring to FIG. 7, SB #0 includes L subpixel rows.

The L subpixel rows may be identified as L*0+1, L*0+2, ..., L*0+L.

Also, the L subpixel rows may correspond to the L gate lines GL.

Therefore, L gate lines (GL) corresponding to L subpixel rows are also identified by L*0+1, L*0+2, ..., L*0+L identification information (ID: Identifier). Can be.

Here, the L gate lines GL have the subpixel structure of FIG. 2, and L*0+1 th subpixel row, L*0+2 th subpixel row, ..., L*0+L sub This is a gate line that supplies the scan signal SCAN to the gate node of the switching transistor T1 disposed in the subpixels in the pixel row.

Referring to FIG. 7, SB #1 also includes L subpixel rows.

The L subpixel rows may be identified as L*1+1, L*1+2, ..., L*1+L.

Also, the L subpixel rows may correspond to the L gate lines GL.

Accordingly, the L gate lines GL corresponding to the L subpixel rows can also be identified with the identification information (ID) of L*1+1, L*1+2, ..., L*1+L. have.

Here, the L gate lines GL have the subpixel structure of FIG. 2, and the L*1+1th subpixel row, L*1+2th subpixel row, ..., L*1+L subpixels This is a gate line that supplies the scan signal SCAN to the gate node of the switching transistor T1 disposed in the subpixels in the pixel row.

Referring to FIG. 7, SB #(B-1) also includes L subpixel rows.

L subpixel rows can be identified by ID: L*(B-1)+1, L*(B-1)+2, ..., L*(B-1)+L. I can.

Also, the L subpixel rows correspond to the L gate lines GL.

Therefore, L gate lines GL corresponding to L subpixel rows are also L*(B-1)+1, L*(B-1)+2, ..., L*(B-1) It can be identified with the identification information (ID) of +L.

Here, the L gate lines GL have the subpixel structure of FIG. 2, and L*(B-1)+1 th subpixel row, L*(B-1)+2 th subpixel row, .. ., L*(B-1)+L This is a gate line that supplies the scan signal SCAN to the gate node of the switching transistor T1 disposed in the subpixels in the subpixel row.

Hereinafter, a sensing method based on a sensing block as illustrated in FIG. 7 will be described as an example. For illustrative purposes, taking UDD resolution as an example, assume that the number of subpixel rows (= number of gate lines) N is 2160, the number of sensing blocks B is 135, and the number of subpixel rows in one sensing block (i.e., one For example, the number of gate lines in the sensing block) L is 16.

Referring to FIG. 8, the organic light emitting display device 100 according to the present exemplary embodiments performs a sensing operation on all subpixels disposed on the organic light emitting display panel 110, that is, mode subpixel rows. Rather, by performing a sensing operation on only one representative subpixel row among 16 subpixel rows included in each of 135 sensing blocks (SB #0, SB #1, ..., SB #134), sensing block-based The sensing operation is performed.

Referring to FIG. 8, in SB #0, a threshold voltage deviation of driving transistors in subpixels belonging to a representative subpixel row having an identification information (ID) of 16*0+1 is sensed. In SB #1, a threshold voltage deviation of the driving transistors in subpixels belonging to a representative subpixel row having an identification information (ID) of 16*1+2 is sensed. In SB #134, threshold voltage deviations for driving transistors in subpixels belonging to a representative subpixel row having an identification information (ID) of 16*134+16 are sensed.

As described above, the organic light emitting display device 100 according to the present embodiments is one of 16 subpixel rows included in each of 135 sensing blocks (SB #0, SB #1, ..., SB #134). After sensing is performed on only the representative subpixel rows of, subpixels belonging to each of 135 representative subpixel rows (ID: 16*0+1, 16*1+2, ..., 16*134+16) When the threshold voltage deviation ΔVth of the driving transistors at is smaller than a preset threshold, the sensing and compensation process for the organic light emitting display panel 110 is completed. In this case, a data compensation amount for compensating the threshold voltage deviation (△Vth) for the driving transistors in the subpixels belonging to each representative subpixel row may be calculated, and if the threshold voltage deviation (△Vth) is very small , Data compensation amount may not be calculated.

If, in the subpixels belonging to 135 representative subpixel rows (ID: 16*0+1, 16*1+2, ..., 16*134+16), the threshold voltage deviation ( When ΔVth) is equal to or greater than a preset threshold, as shown in FIG. 9, 135 representative subpixel rows (IDs: 16*0+1, 16*1+2, ..., 16*134+16) In addition, sensing is performed for all the remaining subpixel rows to determine the threshold voltage deviation (ΔVth) for all driving transistors of the organic light emitting display panel 110, and based on this, data compensation for all subpixels Calculate the quantity.

The above-described sensing block-based sensing method will be described in more detail with reference to the flowchart of FIG. 10, sensing block information 1100 stored in the memory 200 of FIG. 11 and the exemplary diagram of FIG. 12.

10 is a flowchart of a sensing method based on a sensing block according to the present embodiments. 11 is a diagram illustrating sensing block information 1100 for a sensing block-based sensing operation according to the present embodiments. 12 is an exemplary diagram of a sensing operation based on a sensing block according to the present embodiments.

Referring to FIGS. 10 to 12, first, sensing block information 1100 is initialized and stored in the memory 200 (S1010).

10 and 11, the sensing block information 1100 includes identification information (SB_ID) for 135 sensing blocks (SB #0, SB #1, ..., SB #134) and 135 sensing blocks. It includes identification information (REP_LINE_ID) for 135 representative subpixel rows or 135 representative gate lines corresponding to blocks SB #0, SB #1, ..., SB #134.

Initialization of the sensing block information 1100 includes identification information (SB_ID) for 135 sensing blocks (SB #0, SB #1, ..., SB #134) and 135 sensing blocks (SB #0, It means initially setting identification information (REP_LINE_ID) for 135 representative subpixel rows or 135 representative gate lines corresponding to SB #1, ..., SB #134).

10 and 11, when the sensing block information 1100 is initialized, as an example, 16 subs included in each of 135 sensing blocks (SB #0, SB #1, ..., SB #134) The first subpixel row among the pixel rows may be initialized as a representative subpixel row.

Accordingly, in the initialized sensing block information 1100, the identification information (REP_LINE_ID) of the representative subpixel row (representative gate line) corresponding to SB #0 is 16*0+1, and the representative sub-pixel corresponding to SB #1 The identification information (REP_LINE_ID) of the pixel row (representative gate line) is 16*1+1, and the identification information (REP_LINE_ID) of the representative subpixel row (representative gate line) corresponding to SB #2 is 16*2+1. And identification information (REP_LINE_ID) of the representative subpixel row (representative gate line) corresponding to SB #134 is 16*134+1.

In this way, by checking the sensing block information 1100 stored in the memory 200, a sensing block-based sensing operation can be quickly performed.

10 and 12, after the above-described sensing block information initialization (S1010), the timing controller 140, for each of 135 sensing blocks (SB #0, SB #1, ..., SB #134), A threshold voltage deviation (ΔVth) in the representative subpixel row is obtained (S1020).

More specifically, referring to FIGS. 10 and 12, a plurality of analog-to-digital converters (ADCs) are 135 sensing blocks (SB #0, SB #1, ..., SB #134). Voltage sensed by sensing the voltage to the sensing node in the subpixels included in each of the four representative subpixel rows (REP_LINE_ID: 16*0+1, 16*1+1, ..., 16*134+1) The sensing data generated based on is transmitted to the timing controller 140.

Accordingly, referring to FIGS. 10 and 12, the timing controller 140 includes 135 representative subpixel rows (REP_LINE_ID: 16*0+1), based on sensing data received from a plurality of analog-to-digital converters (ADCs). For each of 16*1+1, ..., 16*134+1), the threshold voltage deviation (ΔVth) of the driving transistors in the subpixels included in the corresponding representative subpixel row can be identified and obtained. .

Thereafter, referring to FIGS. 10 and 12, the timing controller 140 includes 135 representative subpixel rows (REP_LINE_ID: 16*0+1, 16*1+1, ..., 16*) based on the sensing data. 134+1) A threshold voltage deviation (ΔVth) determined for the driving transistors in the subpixels included in each of the subpixels is compared with a preset threshold (S1030).

That is, the timing controller 140, based on the sensing data, for each of 135 representative subpixel rows (REP_LINE_ID: 16*0+1, 16*1+1, ..., 16*134+1) Compare the voltage deviation (ΔVth) with the threshold.

Referring to FIGS. 10 and 12, the timing controller 140 includes 16 subpixels included in each of 135 sensing blocks (SB #0, SB #1, ..., SB #134) according to a comparison result. It is possible to determine whether to perform the sensing process for the remaining L-1 subpixel rows excluding the representative subpixel row among the rows.

In this way, all 16 subpixel rows included in each of 135 sensing blocks (SB #0, SB #1, ..., SB #134) are not sensed, but only one representative subpixel row is sensed and sensed. The resultant threshold voltage deviation is compared with a threshold value (which is the minimum threshold voltage deviation that requires meaningful threshold voltage deviation compensation to improve image quality), and according to the comparison result, the remaining subpixel rows are sensed in addition to the representative subpixel row. Therefore, it is possible to reduce unnecessary sensing procedures and unnecessary sensing time accordingly.

Referring to FIG. 10, the timing controller 140 compares the threshold voltage deviation (ΔVth) with the threshold value, and when the threshold voltage deviation (ΔVth) is less than the threshold value, 135 representative subpixel rows (REP_LINE_ID: 16*0) +1, 16*1+1, ..., 16*134+1) Calculate and store data compensation values to compensate for the identified threshold voltage deviation (△Vth) or the identified threshold voltage deviation (△Vth) Alternatively, it can be terminated immediately without calculating the data compensation value.

On the other hand, referring to FIGS. 10 and 12, the timing controller 140, when the determined threshold voltage deviation (ΔVth) is greater than or equal to the threshold, 135 sensing blocks (SB #0, SB #1, ..., SB) #134) Of the 16 subpixel rows included in each, the remaining L-1 subpixels excluding the representative subpixel rows (REP_LINE_ID: 16*0+1, 16*1+1, ..., 16*134+1) The remaining subpixels excluding the representative subpixel row among the 16 subpixel rows included in each of 135 sensing blocks (SB #0, SB #1, ..., SB #134) by performing a sensing process on the pixel row The threshold voltage deviation may also be determined for each row (S1040).

Accordingly, all deviations in threshold voltages of the driving transistors in all subpixels on the organic light emitting display panel 110 are recognized.

In this way, the representative subpixel row (REP_LINE_ID: 16*0+1, 16*1+1, ..., 16*) for each of 135 sensing blocks (SB #0, SB #1, ..., SB #134) 135 sensing blocks (SB #0, 134+1) when the detected threshold voltage deviation (△Vth) exceeds the threshold value, that is, a meaningful threshold voltage deviation that needs to compensate for the threshold voltage deviation occurs. Since the sensing process is performed on the remaining subpixel rows included in SB #1, ..., SB #134), unnecessary sensing and compensation time can be reduced.

Thereafter, referring to FIGS. 10 and 12, the timing controller 140, for each of 135 sensing blocks (SB #0, SB #1, ..., SB #134), for 16 subpixel rows. A new representative subpixel row is selected by selecting the maximum value among the identified 16 threshold voltage deviations.

Thereafter, referring to FIGS. 10 and 12, the timing controller 140 identifies 134 representative subpixel rows or 134 representative gate lines on the sensing block information 1100 stored in the memory 200 (REP_LINE_ID). Is updated (S1050).

In this way, since the identification information (REP_LINE_ID) for the representative subpixel row or representative gate line for each sensing block in the sensing block information 1100 is updated, sensing and compensation operations are performed based on the latest threshold voltage deviation occurrence state. And, while effectively reducing the sensing and compensation time, it is possible to accurately identify situations in which overall sensing is required.

At this time, referring to FIGS. 11 and 12, the identification information (REP_LINE_ID) of 16 new representative subpixel rows is, for example, 16*0+P, 16*1+Q, ..., 16*134+R. to be.

That is, in SB #0, the 16*0+P-th sub-pixel row (or gate line) changes the representative sub-pixel row (or the representative gate line), and in SB #1, the 16*1+Q-th sub-pixel row (Or gate line) changes the representative subpixel row (or representative gate line), and in SB #134, the 16*134+Rth subpixel row (or gate line) is the representative subpixel row (or representative gate line) Is changed.

Thereafter, the timing controller 140, the threshold voltage deviation (ΔVth) identified for each of the 16 subpixel rows included in each of the 135 sensing blocks (SB #0, SB #1, ..., SB #134) or A data compensation value for compensating for the identified threshold voltage deviation ΔVth may be calculated and stored in the memory 200.

In this case, the stored threshold voltage deviation (ΔVth) may be used as a threshold value in the next sensing block-based sensing operation.

13 is a diagram illustrating a first gate driving control signal VSC and a second gate driving control signal VOE required for gate driving for a sensing operation based on a sensing block according to the present embodiments.

Referring to FIG. 13, the timing controller 140 receives a first gate driving control signal VSC and a second gate driving control signal VOE required for gate driving for a sensing block-based sensing operation. Output as

The first gate drive control signal VSC and the second gate drive control signal VOE are a kind of gate control signal GCS, and the first gate drive control signal VSC has 135 sensing blocks (SB #0, SB #1, ..., SB #134) may be a signal for controlling gate driving timing for each of the 16 subpixel rows included in each. The second gate driving control signal VOE is used to indicate whether to sense each of the 16 subpixel rows included in each of 135 sensing blocks (SB #0, SB #1, ..., SB #134). It may be a control signal or a control signal indicating a representative subpixel row.

As the above-described first gate drive control signal VSC, one of the existing gate control signals, GSC, may be used. As the second gate drive control signal VOE, one of the existing gate control signals, GOE, may be used.

14 is a diagram illustrating a first gate driving control signal VSC and a second gate driving control signal VOE before the sensing block information 1100 is updated in an example of a sensing operation based on a sensing block according to the present embodiments. It is a figure shown. 15 is an example of a sensing operation based on a sensing block according to the present embodiments, a first gate driving control signal VSC and a second gate driving control signal VOE after the sensing block information 1100 is updated. It is a figure shown.

As mentioned in the previous example, in the sensing block information 1100 before the update, 135 representative subpixel rows corresponding to 135 sensing blocks (SB #0, SB #1, ..., SB #134) The identification information (ID) of is 16*0+1, 16*1+1, ..., 16*134+1.

And, in the sensing block information 1100 after the update, the identification information (ID) of 135 representative subpixel rows corresponding to 135 sensing blocks (SB #0, SB #1, ..., SB #134) is , 16*0+P, 16*1+Q, ..., 16*134+R.

Referring to FIGS. 14 and 15, the timing controller 140 transmits a first gate driving control signal VSC having N signal sections corresponding to N (eg, 2160) subpixel rows to the gate driver 130. Output as

14 and 15, in the first gate driving control signal VSC, corresponding to each of B (eg, B=135) representative subpixel rows selected from among signal sections corresponding to each of 2160 subpixel rows. The length of the signal section is longer than the length of the section corresponding to each of the remaining subpixel rows.

In other words, referring to FIGS. 14 and 15, the first gate drive control signal VSC includes sections corresponding to 135 sensing blocks (SB #0, SB #1, ..., SB #134). Thus, in a section corresponding to one sensing block, sections corresponding to 16 subpixel rows exist again.

14 and 15, in the first gate driving control signal VSC, looking at the lengths of sections corresponding to 16 subpixel rows, the length of the section corresponding to the representative subpixel row is the representative subpixel row. It is longer than the length of the section corresponding to the remaining subpixel rows.

14 and 15, the first gate driving control signal VSC is output in a slow clock mode in a section corresponding to a representative subpixel row, and the remaining subpixels other than the representative subpixel row In the section corresponding to the row, it is output in fast clock mode.

Using the first gate drive control signal (VSC) having such a signal waveform, each of the 16 subpixel rows included in each of 135 sensing blocks (SB #0, SB #1, ..., SB #134) By accurately controlling the driving timing of the gate, it is possible to enable the sensing operation based on the sensing block as described above.

Referring to FIGS. 14 and 15, when a deviation of a threshold voltage identified as a result of sensing a representative subpixel row for each sensing block is greater than or equal to a threshold value, and sensing the remaining subpixel rows is required, a first gate driving control signal In (VSC), the section corresponding to the representative subpixel row is shorter than the section corresponding to the remaining subpixel rows other than the representative subpixel row. That is, a section corresponding to a subpixel row in which sensing is actually performed is longer than a section corresponding to a subpixel row in which sensing is not performed.

Meanwhile, referring to FIGS. 14 and 15, the timing controller 140 transmits a second gate driving control signal VOE having B (eg, B=135) high level sections and B low level sections You can print it as (130).

14 and 15, in the second gate driving control signal VOE, 135 high-level sections (or low-level sections) correspond to 135 representative subpixel rows, and 135 low-level sections (or high-level sections). The level interval) may correspond to the remaining subpixel rows other than the representative subpixel row.

Referring to FIGS. 14 and 15, when a deviation of a threshold voltage identified as a result of sensing a representative subpixel row for each sensing block is greater than or equal to a threshold value, and thus sensing of the remaining subpixel rows is required, a second gate driving control signal In (VOE), a section corresponding to 135 representative subpixel rows is a low level section (or high level section), and a section corresponding to the remaining subpixel rows other than the representative subpixel rows is a high level section (or low level section). )to be. That is, a section corresponding to a subpixel row in which sensing is actually performed is a high level section (or a low level section), and a section corresponding to a subpixel row in which sensing is not performed is a low level section (or a high level section).

If the second gate drive control signal (VOE) having the signal waveform as described above is used, 16 subpixels included in each of 135 sensing blocks (SB #0, SB #1, ..., SB #134) It is possible to accurately indicate whether each row is sensed, and to accurately indicate 135 representative subpixel rows, thereby enabling gate driving that enables the sensing operation based on the sensing block as described above.

According to the exemplary embodiments described above, it is possible to provide the organic light emitting display device 100 and a driving method thereof capable of shortening the sensing and compensation time.

In addition, according to the present embodiments, it is possible to provide an organic light emitting display device 100 and a driving method thereof that prevents the progress of a senseless and unnecessary sensing and compensation procedure.

The description above and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the technical field to which the present invention pertains, combinations of configurations without departing from the essential characteristics of the present invention Various modifications and variations, such as separation, substitution and alteration, will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

100: display device
110: display panel
120: data driver
130: gate driver
140: timing controller

Claims (10)

An organic light-emitting display panel in which a plurality of data lines and a plurality of gate lines are disposed, and a plurality of subpixels are disposed in a matrix type;
A data driver driving the plurality of data lines;
A gate driver driving the plurality of gate lines; And
A timing controller that controls the data driver and the gate driver,
The timing controller,
Outputting a first gate driving control signal having N signal sections corresponding to N subpixel rows to the gate driver,
In the first gate driving control signal, the length of the signal section corresponding to each of the B (2≤B<N) representative subpixel rows selected from among N signal sections corresponding to the N subpixel rows is the remaining subpixel An organic light emitting display device, characterized in that it is longer than a length of a section corresponding to each of the rows. The method of claim 1,
The timing controller,
Outputting a second gate driving control signal having B high level sections and B low level sections to the gate driver,
In the second gate driving control signal, the B high-level sections correspond to the B representative subpixel rows, and the B low-level sections correspond to the remaining subpixel rows. The method of claim 1,
Identification information for B sensing blocks each including L (L=N/B) subpixel rows, and identification information for B representative subpixel rows or B representative gate lines corresponding to the B sensing blocks The organic light-emitting display device further comprises a memory for storing the. The method of claim 3,
Each of the plurality of subpixels,
An organic light-emitting diode, a driving transistor for driving the organic light-emitting diode, and a switching transistor controlled by a scan signal applied to a gate node through a gate line, and electrically connected between a gate node and a data line of the driving transistor. Is composed of
The organic light emitting display device further comprises an analog-to-digital converter for sensing a voltage of a sensing node in each of the plurality of subpixels, generating sensing data based on the sensed voltage, and transmitting the sensing data to the timing controller. The method of claim 4,
Wherein the analog-to-digital converter is included in the data driver. The method of claim 4,
The sensing node,
A source node or a drain node of the driving transistor,
The sensed voltage is,
And a data voltage output to a drain node or a source node of the switching transistor through the data line and a threshold voltage of the driving transistor. The method of claim 4,
The timing controller,
Based on the sensing data, a threshold voltage deviation for the driving transistor in subpixels included in each of the B representative subpixel rows is determined, and the determined threshold voltage deviation is compared with a threshold value,
According to the comparison result, it is determined whether to perform the sensing process for the remaining L-1 subpixel rows excluding the representative subpixel row among L subpixel rows included in each of the B sensing blocks. Luminous display device. The method of claim 7,
The timing controller,
When the identified threshold voltage deviation is more than the threshold value,
And determining to perform the sensing process on the remaining L-1 subpixel rows excluding the representative subpixel row among L subpixel rows included in each of the B sensing blocks. The method of claim 8,
The timing controller,
After performing the sensing process for the remaining L-1 subpixel rows,
A new representative subpixel row is selected by selecting a maximum value among threshold voltage deviations for L subpixel rows included in each of the B sensing blocks,
And updating identification information for the B representative subpixel rows or the B representative gate lines stored in the memory. A method of driving an organic light emitting display device in which a plurality of data lines and a plurality of gate lines are arranged, and a plurality of subpixels are arranged in a matrix type,
Setting two or more representative subpixel rows from the plurality of subpixel rows; And
Sensing a threshold voltage deviation for driving transistors in the at least two representative subpixel rows; And
When the sensed threshold voltage deviation is less than a threshold, sensing is terminated, and if the sensed threshold voltage deviation is greater than or equal to the threshold, the plurality of subpixel rows except for the two or more representative subpixel rows A method of driving an organic light emitting display device comprising sensing a threshold voltage deviation for driving transistors.

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