KR20160142015A - Source driver ic and display device - Google Patents

Abstract

According to embodiments of the present invention, disclosed are a source driver integrated circuit and a display device thereof which has a structure capable of preventing block dim phenomena to improve image quality. The source driver integrated circuit comprises: a core unit including a left resistance spring and a right resistance spring; a left channel output unit arranged in a left side of the core unit; and a right channel output unit arranged in a right side of the core unit.

Description

≪ Desc / Clms Page number 1 > SOURCE DRIVER IC AND DISPLAY DEVICE [

The embodiments relate to a source driver integrated circuit and a display device.

BACKGROUND ART Demands for a display device for displaying an image have been increasing in various forms as an information society has developed. Recently, a liquid crystal display device, a plasma display device, an organic light emitting display device Organic Light Emitting Display Device) are being utilized.

Such a display device includes a display panel in which data lines and gate lines are arranged and in which subpixels are arranged, a data driver for driving the data lines, a gate driver for sequentially driving the gate lines, a data driver, And the like.

The data driver may include at least one source driver integrated circuit. Each source driver integrated circuit converts data corresponding to the digital video signal received from the timing controller into a data voltage corresponding to the analog video signal, And outputs it to a corresponding plurality of data lines.

There has been a problem that the picture quality is deteriorated due to a block dim phenomenon occurring in a screen area corresponding to the channels of the source driver integrated circuit.

It is an object of the present embodiments to provide a source driver integrated circuit and a display device capable of preventing a block dim phenomenon and improving image quality.

It is another object of the present embodiments to provide a source driver integrated circuit having a structure capable of preventing a block dim phenomenon and a display device including the same.

It is still another object of the present embodiments to provide a source driver IC having a structure capable of preventing a block dim phenomenon in a left and right screen region even when a process deviation of a resistor string or a digital analog converter (DAC) And a display device including the same.

One embodiment includes a core unit comprising a first color left resistance string disposed on the left and a first color right resistance string disposed on the right and a plurality of second color left channel DACs disposed on the left side of the core unit, A left channel output unit including a plurality of second color left channel DACs and a plurality of third color left channel DACs, and a plurality of first color right channel DACs, a plurality of second color right channel A DAC and a right channel output portion including a plurality of third color right channel DACs.

Another embodiment includes a core unit including a plurality of resistor strings and a data receiving unit, a plurality of left channel DACs disposed on the left side of the core unit, and a plurality of right channel DACs disposed on the right side of the core unit. An integrated circuit can be provided.

In such a source driver integrated circuit, the number of resistor strings located on both sides of the data receiving unit may be the same.

Another embodiment provides a display device including a display panel in which a plurality of data lines and a plurality of gate lines are arranged and in which a plurality of subpixels are arranged and at least one source driver integrated circuit for receiving data and outputting an analog voltage to the plurality of data lines Circuit and a timing controller for transmitting data to one or more source driver integrated circuits.

In such a display device, each source driver integrated circuit includes: a core unit including a first color left resistance string disposed on the left side and a first color right side resistance string disposed on the right side; A left channel output unit including a first color left channel DAC, a plurality of second color left channel DACs and a plurality of third color left channel DACs, and a plurality of first color right channel DACs, A right channel output including a plurality of second color right channel DACs and a plurality of third color right channel DACs.

According to the embodiments described above, it is possible to provide a source driver integrated circuit and a display device capable of preventing block-dim phenomenon and improving image quality.

Further, according to the embodiments, it is revealed that the block dim phenomenon is caused by the arrangement structure of the resistance string in the source driver integrated circuit, and the source driver integrated circuit having the structure capable of preventing the block dim phenomenon and the display Device can be provided.

In addition, according to the present embodiments, even if a process deviation of a resistor string or a channel digital-to-analog converter (DAC) occurs, a source driver IC having a structure capable of preventing block- And a display device including the same.

1 is a system configuration diagram of a display apparatus according to the present embodiments.
2 is an exemplary view of a pixel structure of a display device according to the present embodiments.
3 is a schematic block diagram of a source driver integrated circuit according to the present embodiments.
4 is a diagram showing a source driver integrated circuit having a first core structure according to the present embodiments.
5 is a diagram showing an output voltage waveform of a source driver integrated circuit having a first core structure according to the present embodiments.
6 is a diagram illustrating a block dim phenomenon occurring in a screen according to a source driver integrated circuit having a first core structure according to the present embodiments.
7 is a diagram showing a source driver integrated circuit having a second core structure according to the present embodiments.
8 to 10 are diagrams showing a source driver integrated circuit having a first RS connection structure under a second core structure according to the present embodiments.
11 to 13 are diagrams showing a source driver integrated circuit having a second RS connection structure under a second core structure according to the present embodiments.
14 is a graph showing the waveform of the output voltage of the source driver integrated circuit having the second core structure according to the present embodiments.
FIG. 15 is a diagram illustrating a block dim phenomenon occurring in a screen according to a source driver integrated circuit having a second core structure according to the present embodiments.
16 is a diagram showing a first RS connection structure of a source driver integrated circuit having a third core structure according to the present embodiments.
17 is a diagram showing a second RS connection structure of a source driver integrated circuit having a third core structure according to the present embodiments.
18 is an exemplary diagram of each channel DAC included in the source driver integrated circuit having the first, second, and third core structures according to the present embodiments.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a system configuration diagram of a display apparatus 100 according to the present embodiments. 2 is an exemplary view of the pixel structure of the display device 100 according to the present embodiments.

Referring to FIG. 1, a display device 100 according to the present embodiment includes a plurality of data lines DL and a plurality of gate lines GL, A data driver 120 driving a plurality of data lines DL; a gate driver 130 driving a plurality of gate lines GL; a data driver 120 and a gate driver 130; And a timing controller 140 for controlling the timing controller 140 and the like.

The data driver 120 receives the data DATA corresponding to the digital video signal transmitted to the timing controller 140 and converts the data into a data voltage Vdata corresponding to an analog video signal, Thereby driving a plurality of data lines.

The gate driver 130 sequentially supplies the scan signals to the plurality of gate lines to sequentially drive the plurality of gate lines GL.

The timing controller 140 supplies various control signals DCS and GCS to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130. [

The timing controller 140 starts scanning in accordance with the timing implemented in each frame, switches the image data input from the outside according to the data signal format used by the data driver 120, and outputs the converted data (DATA) And controls the data driving at a suitable time according to the scan.

Under the control of the timing controller 140, the gate driver 130 sequentially supplies the scan signals of the On voltage or the Off voltage to the plurality of gate lines to sequentially drive the plurality of gate lines .

1, the gate driver 130 may be located only on one side of the display panel 110, or may be located on both sides, depending on the case.

The gate driver 130 may include at least one gate driver IC (GD-IC).

When the specific gate line is opened, the data driver 120 converts the image data received from the timing controller 140 into analog data voltages and supplies the data voltages to the data lines to drive the plurality of data lines.

The data driver 120 may include at least one source driver integrated circuit (SD-IC).

Each source driver integrated circuit (SD-IC) includes a shift register, a latch circuit, a digital analog converter (DAC), an output buffer, and the like can do.

All or a part of the internal configurations of each of the source driver integrated circuits (SD-ICs) may exist for each channel (CH) corresponding to each data line.

In addition, each source driver IC (SD-IC) shifts the voltage level of the data (DATA) corresponding to the digital video signal corresponding to the logic signal input from the timing controller 140 to a desired voltage level (high voltage level) (Level Shifter) for level shifting.

On the other hand, the timing controller 140 includes a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, an input data enable (DE) signal, a clock signal CLK, and the like And receives various timing signals from the outside (e.g., the host system).

In addition to outputting data (DATA) corresponding to the converted digital video signal by switching the input video data inputted from the outside according to the data signal format used by the data driver 120, A timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable signal DE and a clock signal to control the gate driver 120 and the gate driver 130, And outputs the generated data to the data driver 120 and the gate driver 130.

For example, in order to control the gate driver 130, the timing controller 140 generates a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal GOE : Gate Output Enable), and the like.

Here, the gate start pulse GSP controls the operation start timing of the gate driver IC (GD-IC). The gate shift clock GSC is a clock signal commonly input to the gate driver IC (GD-IC), and controls the shift timing of the scan signal (gate pulse). The gate output enable signal GOE designates the timing information of the gate driver IC (GD-IC).

The timing controller 140 includes a source start pulse SSP, a source sampling clock SSC and a source output enable signal SOE to control the data driver 120. [ Output enable (DCS) data control signals.

Here, the source start pulse SSP controls the data sampling start timing of the source driver IC (SD-IC) constituting the data driver 120. The source sampling clock SSC is a clock signal for controlling the sampling timing of data in each of the source driver integrated circuits (SD-IC). The source output enable signal SOE controls the data output timing of the source driver integrated circuit (SD-IC).

Each sub-pixel may be composed of a circuit element such as a transistor, a capacitor, or the like.

Two or more such subpixels may form one pixel.

Referring to FIG. 2, each pixel may have a structure such as an RGB pixel structure, a Pentile pixel structure, and an RWGB pixel structure, for example.

Referring to FIG. 2, in the case of the RGB pixel structure, each pixel may be composed of a red subpixel R, a green subpixel G, and a blue subpixel B.

In this case, the red subpixel R, the green subpixel G, and the blue subpixel B are repeatedly arranged on the display panel 110.

Referring to FIG. 2, in the case of the RWGB pixel structure, each pixel may be composed of a red subpixel R, a white subpixel W, a green subpixel G and a blue subpixel B.

In this case, the red subpixel R, the white subpixel W, the green subpixel G and the blue subpixel B are repeatedly arranged on the display panel 110.

Referring to FIG. 2, in the case of a penta-pixel structure, each pixel may be composed of two sub-pixels.

In the case of this penta-pixel structure, the subpixels can be arranged in various forms. As shown in the example of Fig. 2, the red subpixel R and the green subpixel G constitute one pixel, and the adjacent pixel is composed of the blue subpixel B and the green subpixel G . That is, two pixels may be composed of a red subpixel R, a green subpixel G, a blue subpixel B, and a green subpixel G. [ Here, the green subpixel G may be smaller in size than the red subpixel R and the blue subpixel B.

This penta-pixel structure is based on the fact that human eyes can not distinguish sub pixels one by one, and that green is best recognized by human eyes.

On the other hand, the display device 100 according to the present embodiments can prevent an abnormal phenomenon such as a block dim in the screen.

To this end, the source driver integrated circuit (SD-IC) included in the display device 100 according to the present embodiments has a unique internal structure.

Here, the unique internal structure of the source driver integrated circuit (SD-IC) includes a "core structure" of the core unit included in the source driver integrated circuit (SD-IC) RS connection structure "between a plurality of channel DACs (CH DACs) and resistor strings (RSs) included in the I /

Hereinafter, the source driver integrated circuit (SD-IC) according to the present embodiments will be described in more detail.

3 is a schematic block diagram of a source driver integrated circuit (SD-IC) according to the present embodiments.

3, the source driver integrated circuit (SD-IC) according to the present embodiment includes a core unit 300, a left channel output unit 310, a right channel output unit 320, and the like.

The core unit 300 receives the data DATA corresponding to the digital video signal transmitted from the timing controller 140 and outputs the received data DATA to the left channel output unit 310 and the right channel output unit 320 ).

The timing controller 140 provides data (DATA) to a source driver IC (SD-IC) through an interface such as an EPI interface. At this time, the timing controller 140 generates a signal Lt; / RTI >

Accordingly, the core unit 300 of the source driver integrated circuit (SD-IC) separates the data (DATA) and the clock signal from the signal received from the timing controller 140, and outputs the separated data (DATA) To the left channel output unit 310 and the right channel output unit 320, respectively.

When the source driver IC (SD-IC) outputs the data voltage (Vdata) with 2n (n is a natural number of 1 or more) data lines, that is, 2n channels (CH 1, CH 2, The left channel output unit 310 outputs 2n channels (CH 1, CH 2, ...) by using the data (DATA) transmitted from the core unit 300. The right channel output unit 320 outputs the data voltage Vdata to each of the n left channels CH 1, CH 2, ..., CH n of the core units 300, The data voltage is applied to n right channels (CH n + 1, CH n + 2, ... CH 2n) of 2n channels (CH, CH 2, ..., CH 2n) (Vdata) can be output.

The left channel output unit 310 receives the data DATA corresponding to the digital video signal and supplies the data voltage Vdata corresponding to the analog video signal to the n left channels CH 1 and CH 2 ,..., CH n), n left channel DACs, n left channel output buffers, and the like, as well as n or less shift registers, n first latches, n A second latch, and the like.

Each of the n left channel DACs converts a digital video signal DATA corresponding to the left channel of the n left channels (CH 1, CH 2, ... CH n) into an analog video signal.

Each of the n left channel output buffers amplifies the analog video signal converted in the left channel DAC so that the analog video signal converted in the left channel DAC has sufficient current driving capability to drive the data line, And outputs the data voltage Vdata, which is a signal, to the data line corresponding to the left channel.

Similarly, the right channel output unit 320 receives the data (DATA) corresponding to the digital video signal and outputs the data voltage Vdata corresponding to the analog video signal (analog voltage) to the n right channel (CH n + 1) , N right channel DACs, n right channel output buffers, and the like, as well as n shift registers, n shift registers, One latch, n second latches, and the like.

Each of the n right channel DACs converts the digital video signal DATA corresponding to the right channel among the n right channels (CH n + 1, CH n + 2, ... CH 2n) into an analog video signal.

Each of the n right channel output buffers amplifies the analog video signal converted in the corresponding right channel DAC so that the analog video signal converted in the right channel DAC has sufficient current driving capability to drive the data line, And outputs the data voltage Vdata, which is a signal, to the data line corresponding to the right channel.

The core unit 300 includes a data receiving unit for receiving data DATA as a digital video signal from the timing controller 140 and transmitting the data to the left channel output unit 310 and the right channel output unit 320, (RS) for each color used to perform the digital-analog conversion in the channel output unit 310 and the right channel output unit 320, respectively.

On the other hand, in the source driver integrated circuit (SD-IC) according to the present embodiments, the core unit 300 has a core structure in which a data receiving unit 400 for receiving data is arranged at the center.

Depending on the number and location of the resistor strings R-RS, G-RS and B-RS for each color included in the core unit 300, the core structure may be divided into a first core structure, Structure.

The first core structure includes a resistance string (G-RS) corresponding to the first color, a resistance string (R-RS) corresponding to the second color, and a resistance string (B-RS) corresponding to the third color Is a core structure that exists only in the core.

The second core structure includes two resistive strings (G-RS) corresponding to a first color, a resistance string (R-RS) corresponding to a second color, and a resistance string (B-RS) Is a core structure that exists only in the core.

The third core structure may be one of a resistance string (G-RS) corresponding to the first color, a resistance string (R-RS) corresponding to the second color and a resistance string (B-RS) There are two of them and there is only one core structure remaining.

The "first color", "second color", and "third color" described herein may be red, green, and blue. For example, the first color may be red, the second color may be green, the third color may be blue, the first color may be green, the second color may be red (or blue), the third color may be blue (Or red).

The first color described herein may be the color with the highest visibility (e.g. green).

It should also be noted that the "left" and "right" aspects described herein are based on the structure in which the channel output portions 310, 320 are on both sides of the core unit 300 in the middle of the source driver integrated circuit (SD- And the channel power units 310 and 320 on both sides of the core unit 300 are not necessarily referred to as left and right.

Hereinafter, the source driver integrated circuit (SD-IC) will be described in more detail for each core structure.

4 is a diagram showing a source driver integrated circuit (SD-IC) having a first core structure according to the present embodiments. 5 is a graph showing waveforms of output voltages of a source driver integrated circuit (SD-IC) having a first core structure according to the present embodiments. 6 is a diagram illustrating a block dim phenomenon occurring in a screen according to a source driver integrated circuit having a first core structure according to the present embodiments.

Referring to FIG. 4, in the source driver IC (SD-IC) having the first core structure according to the present embodiment, a resistor string (G-RS) corresponding to the first color, There is only one resistor string (R-RS) corresponding to two colors and one resistor string (B-RS) corresponding to the third color.

For example, as shown in FIG. 4, a resistor string (R-RS) of one color is arranged on the left side of the core unit 300, and two resistor strings The color resistance strings (G-RS, B-RS) can be placed on the right side.

In the following, the resistance string disposed on the left side with respect to the data receiving unit 400 is referred to as a "left resistance string", and the resistance string disposed on the right side is referred to as a "right resistance string".

Also, the left resistance string and the right resistance string associated with the first color are referred to as a first color left resistance string and a first color right resistance string. The left resistance string and the right resistance string associated with the second color are referred to as a second color left resistance string and a second color right resistance string. The left resistance string and the right resistance string associated with the third color are referred to as a third color left resistance string and a third color right resistance string.

..., CH DAC # n-3, CH DAC # 2, CH DAC # 3, CH DAC # 4, ... included in the left channel output unit 310, n-2, CH DAC # n-1, and CH DAC #n, respectively, are connected to a resistor string that matches their color.

In addition, the n right channel DACs (CH DAC # n + 1, CH DAC # n + 2, CH DAC # n + 3, CH DAC # n + Each of the CH DAC # 2n-3, CH DAC # 2n-2, CH DAC # 2n-1, and CH DAC # 2n is connected to a resistor string matching its own color.

4, the first color right resistor string (G-RS) included in the core unit 300 includes n left channel DACs (CH DAC # 1, CH DAC # 2, CH DAC # 3, Corresponding to the first color among the first color left channel DACs (CH DAC # 4, CH DAC # n-3, CH DAC # n-2, CH DAC # n- , CH DAC # 2n-3, CH DAC # 2n-3, CH DAC # n + 1, CH DAC # DAC # 2n-2, CH DAC # 2n-1, and CH DAC # 2n) corresponding to the first color.

4, the second color right side resistor string R-RS included in the core unit 300 includes n left channel DACs (CH DAC # 1, CH DAC # 2, CH DAC # Corresponding to the second color among the first color left side (CH DAC # 3, CH DAC # 4, ..., CH DAC # n-3, CH DAC # n-2, CH DAC # n- N DAC # n + 1, CH DAC # n + 2, CH DAC # n + 3, CH DAC # n + , CH DAC # 2n-2, CH DAC # 2n-1, CH DAC # 2n) corresponding to the second color.

4, the third color right side resistor string (B-RS) included in the core unit 300 includes n left channel DACs (CH DAC # 1, CH DAC # 2, CH 3 corresponding to the third color among the DAC # 3, CH DAC # 4, ..., CH DAC # n-3, CH DAC # n-2, CH DAC # n- N DAC # n + 1, CH DAC # n + 2, CH DAC # n + 3, CH DAC # n + 4, ..., CH DAC # 2n 3, CH DAC # 2n-2, CH DAC # 2n-1, CH DAC # 2n).

As described above, in the first core structure, only one resistance string (G-RS, R-RS, B-RS) B-RS exist only on one side (left side or right side) with respect to the central data receiving unit 400 as a reference.

In this first core structure, since the distances from the resistance string of one color to the channel DAC connected at the same time are different from each other, the resistance from the left channel DAC to the corresponding resistance string and the resistance from the right channel DAC to the corresponding resistance string The waveform of the output voltage (i.e., the data voltage) output from the left channel and the right channel may be different as shown in FIG.

For example, it is assumed that the left channel CH 1 and the right channel CH 2n are the second color (for example, red), the left channel DAC (CH DAC # 1) outputting the data voltage to the left channel CH 1, RS is connected to the core unit 300 (R-RS) when the right channel DAC (CH DAC # 2n) outputting the data voltage at 2n is simultaneously connected to the second color left resistance string The distance A2 from the right channel DAC (CH DAC # 2n) to the second color left resistance string (R-RS) is set to the left channel DAC (CH DAC # 1) To the second color left resistance string (R-RS).

Therefore, the resistance in the connection line from the right channel DAC (CH DAC # n + 1) to the second color left resistance string (R-RS) corresponding to the right channel CH 2n is the left channel Is greater than the resistance in the connection line from the DAC (CH DAC # 1) to the second color left resistance string (R-RS).

Due to such a resistance difference, the output voltage (Right Red CH OUT) output through the right channel DAC (CH DAC # n + 1) corresponding to the right channel CH 2n is the left channel DAC (Left Red CH OUT) output through the DAC # 1. As a result, the digital-to-analog conversion delay of the right channel DAC (CH DAC # n + 1) may be larger than that of the left channel DAC (CH DAC # 1). This phenomenon can be confirmed by the red channel output voltage waveform (Red CH OUT) of FIG.

6, in the entire area 600 supplied with the data voltage by one source driver IC (SD-IC), the screen area 610 corresponding to the right channel CH 2n is connected to the left channel A luminance deviation that appears darker than the screen area 620 corresponding to CH1 may occur. Such a luminance deviation causes a block dim phenomenon in the vertical direction.

For another example, assume that the left channel CH 2 and the right channel CH 2n-1 are a first color (for example, green), a left channel DAC (CH DAC # 2) for outputting a data voltage to the left channel CH 2, When the right channel DAC (CH DAC # 2n-1) outputting the data voltage to the right channel CH 2n-1 is simultaneously connected to the first color left resistance string (G-RS), the first color left resistance string G- The distance B1 from the left channel DAC (CH DAC # 2) to the first color left resistance string (G-RS) is set to the right channel Is longer than the distance B2 from the DAC (CH DAC # 2n-1) to the first color left resistance string (G-RS).

Therefore, the resistance in the connection line from the left channel DAC (CH DAC # 2) to the first color left resistance string (G-RS) corresponding to the left channel CH 2 is the right channel corresponding to the right channel CH 2n- Is greater than the resistance at the connection line from the DAC (CH DAC # 2n-1) to the first color left resistance string (G-RS).

Due to such a resistance difference, the output voltage (Left Green CH OUT) output through the left channel DAC (CH DAC # 2) corresponding to the left channel CH 2 becomes the right channel DAC (CH (Right Green CH OUT) output through the DAC # 2n-1 to the corresponding voltage value. As a result, the digital-to-analog conversion delay of the left channel DAC (CH DAC # 2) can be larger than that of the right channel DAC (CH DAC # 2n-1). This phenomenon can be confirmed by the green channel output voltage waveform (Green CH OUT) of FIG.

6, in the entire area 600 supplied with the data voltage by one source driver IC (SD-IC), the screen area 630 corresponding to the left channel CH 2 is connected to the right channel A luminance deviation that appears darker than the screen area 640 corresponding to CH 2n-1 may occur. Such a luminance deviation causes a block dim phenomenon in the vertical direction.

Since the second color left resistance string (B-RS) is biased to the " right "side in the core unit 300, even in the case of the first color (e.g. green) as well as the second color The same block dim phenomenon as in the first color may occur.

Hereinafter, a source driver IC having a second core structure according to the present embodiments, which can prevent a block dim phenomenon that may occur in a source driver integrated circuit (SD-IC) having a first core structure according to the present embodiments, An integrated circuit (SD-IC) will be described.

In the drawings related to the second core structure, the resistance string is denoted as "(color index) -RS - # (position index) ".

Here, the color index indicates how the corresponding resistor string is connected to the channel DAC of a certain color. When the corresponding resistor string is connected to the channel DAC of the first color, the color index is denoted by G, When connected to a color channel DAC, the color index is denoted by R, and if the corresponding resistor string is connected to the channel DAC of the second color, the color index is denoted by B.

The position index indicates whether the corresponding resistance string is located on the left side or the right side of the data receiving unit 400. If the corresponding resistance string is located on the left side of the data receiving unit 400, When the resistor string is located on the right side of the data receiving unit 400, the position index is denoted by 2.

Also, the channel DAC (left channel DAC, right channel DAC) associated with the second core structure is denoted by "(color index) (RS identification index) -CH DAC # (channel identification index)".

Here, the color index indicates the color of the subpixel to which the data voltage is output through the corresponding channel DAC, and is represented by one of R, G, and B.

The RS identification index identifies the position of the resistance string connected to the corresponding channel DAC. When the resistance string connected to the channel DAC is located on the left side of the data receiving unit 400, the RS identification index is marked as 1 , And if the resistance string connected to the channel DAC is located on the right side of the data receiving unit 400, the RS identification index is indicated as 2. [

The channel identification index identifies a channel (left channel, right channel) corresponding to the channel DAC. In the case of the left channel, the channel identification index is one of 1, 2, 3, ..., n , And in the case of the right channel, the channel identification index is one of n + 1, n + 2, n + 3, ..., 2n.

7 is a diagram showing a source driver integrated circuit (SD-IC) having a second core structure according to the present embodiments.

7, a source driver integrated circuit (SD-IC) having a second core structure according to the present embodiment includes a core unit 300 and a left channel output unit 310, a right channel output unit 320 on the right side of the core unit 300, and the like.

Referring to FIG. 7, in the core unit 300, a data receiving unit 400 is disposed at the center.

Referring to FIG. 7, in the core unit 300, a first color left resistance string G-RS # 1, a second color left resistance string R-RS # 1 And a third color left resistance string (B-RS # 1).

Referring to FIG. 7, in the core unit 300, a first color right resistor string G-RS # 2, a second color right resistor string R-RS # 2 And a third color right side resistor string (B-RS # 2).

As described above, in the case of the second core structure, in the core unit 300, there are two resistor strings for each color, and two resistor strings for each color are arranged on the left and right sides of the data receiving unit 400 Respectively.

That is, three resistor strings R-RS # 1, G-RS # 1 and B-RS # 1 are arranged on the left side of the data receiving unit 400, R-RS # 2, G-RS # 2, and B-RS # 2.

7, the left channel output unit 310 is disposed on the left side of the core unit 300 and includes n left channels (CH1, CH2, ..., CHn) corresponding to n left channels DACs (CH DAC # 1, CH DAC # 2, ..., CH DAC #n).

These n left channel DACs (CH DAC # 1, CH DAC # 2, ..., CH DAC #n) are connected to a plurality of first color left channel DACs, a plurality of second color left channel DACs, Channel DAC.

7, the right channel output unit 320 is disposed on the right side of the core unit 300 and is connected to n right channels CH n + 1, CH n + 2, ... CH 2n And the corresponding n right channel DACs (CH DAC # n + 1, CH DAC # n + 2, ..., CH DAC # 2n).

The n number of right channel DACs (CH DAC # n + 1, CH DAC # n + 2, ..., CH DAC # 2n) 3 color right channel DAC.

A source driver integrated circuit (SD-IC) having a second core structure according to the above-described embodiments can be applied to all pixel structures.

It should be noted that a plurality of first color left channel DAC, a plurality of second color left channel DAC, and a plurality of third colors DAC, which constitute n left channel DACs (CH DAC # 1, CH DAC # 2, ..., CH DAC # The arrangement order of the left channel DACs may vary depending on the pixel structure.

For example, when the pixel structure is the RGB pixel structure of FIG. 2, n left channel DACs (CH DAC # 1, CH DAC # 2, ..., CH DAC # Channel DAC), a green left channel DAC (first color left channel DAC), and a blue channel DAC (third color left channel DAC).

2, the n left channel DACs (CH DAC # 1, CH DAC # 2, ..., CH DAC #n) are connected to the red left channel DAC (First color left channel DAC), green left channel DAC (first color left channel DAC), blue channel DAC (third color left channel DAC), and green left channel DAC .

In the core unit 300 of the source driver IC (SD-IC) having the second core structure according to the above-described embodiments, the first, second and third color left resistance strings R-RS # 1, RS # 1 and B-RS # 1) and the first, second and third right resistance strings R-RS # 2, G-RS # 2 and B- (RS connection structure) for connecting to the right channel DACs (CH DAC # 1, ..., CH DAC #n) and n right channel DACs (CH DAC # n + 1, ..., CH DAC # 2n) 1 RS connection structure, or may be a second RS connection structure.

The first RS connection structure is such that the first, second and third left color left resistance strings R-RS # 1, G-RS # 1 and B- Second, and third right resistance strings R-RS # 2, G-RS # 2 and B-RS # 2 are connected only to n right channel DACs # (CH DAC # n + 1, ..., CH DAC # 2n).

The second RS connection structure is configured such that the first, second and third left color left resistance strings R-RS # 1, G-RS # 1 and B- ..., CH DAC #n) and n right channel DACs (CH DAC # n + 1, ..., CH DAC # 2n), and the first, second, (CH DAC # 1, ..., CH DAC # n) and n right channel DACs (CH DAC # 2, n + 1, ..., CH DAC # 2n).

Hereinafter, a first RS connection structure in a source driver integrated circuit (SD-IC) having a second core structure according to the present embodiments will be described. However, it is assumed that the pixel structure is an RGB structure.

8 to 10 are diagrams showing a source driver IC (SD-IC) having a first RS connection structure under a second core structure according to the present embodiments.

Referring to FIG. 8, a plurality of second color left channel DACs (R1-CH DAC # 1, R1-CH DAC # -RS # 1).

The first color left channel DAC (G1-CH DAC # 2, G1-CH DAC # 5, ..., G1-CH DAC # n- ).

A plurality of third color left channel DACs B1-CH DAC # 3, B1-CH DAC # 6, ..., B1-CH DAC #n are connected to the third color left resistance string B- All connected.

Referring to FIG. 8, a plurality of second color right channel DACs (R2-CH DAC # n + 1, ..., R2-CH DAC # 2n- And the resistor string (R-RS # 2).

The first color right side channel DAC (G2-CH DAC # n + 2, ..., G2-CH DAC # 2n-4, G2- RS # 2).

The third color right-side channel DAC (B2-CH DAC # n + 3, ..., B2-CH DAC # 2n-3, B2-CH DAC # 2n) 2).

The second connection structure as described above will be described in terms of a resistor string as follows.

The second color left resistance string R-RS # 1 includes all the second color left channel DACs R1-CH DAC # 1 and R1-CH DAC # 4, as shown in FIG. 9, , R1-CH DAC # 7, ..., R1-CH DAC # n-2).

The second color right-side resistor string R-RS # 2 includes all the second color right channel DACs (R2-CH DAC # n + 1, R2- R DAC # n + 4, R 2 -CH DAC # n + 7, ..., R 2 -CH DAC # 2n-2.

The first color left resistance string G-RS # 1 includes all the first color left channel DACs G1-CH DAC # 2, G1-CH DAC # 5, G1-CH DAC # CH DAC # n-1).

The first color right-side resistor string G-RS # 2 includes all the first color right channel DACs G2-CH DAC # n + 2, G2-CH DAC # n + 8, ..., G2-CH DAC # 2n-1).

..., B1-CH DAC # 3, B1-CH DAC # 6, B1-CH DAC # 9, ..., CH DAC #n).

The third color right side resistor string B-RS # 2 includes all the third color right side channel DACs (B2-CH DAC # n + 3, B2-CH DAC # n + 9, ..., B2-CH DAC # 2n).

The first RS connection structure described above can be summarized as shown in Table 1 below.

On the other hand, the effect of reducing the deviation between the RS connection distances will be described with respect to the source driver integrated circuit (SD-IC) having the first RS connection structure in the second core structure according to the above-described embodiments. However, the first color will be exemplified.

8, among the plurality of first color left channel DACs (G1-CH DAC # 2, G1-CH DAC # 5, G1-CH DAC # As a representative of the first color left channel DAC, G1-CH DAC # 2 is separated by the first color left resistance string (G-RS # 1) and L (G1-CH DAC # 2).

Numbered first color left channel DACs among the plurality of first color left channel DACs (G1-CH DAC # 2, G1-CH DAC # 5, G1-CH DAC # The G1-CH DAC # 5 is separated from the first color left resistance string (G-RS # 1) by L (G1-CH DAC # 5).

Referring to FIG. 8, a plurality of first color right channel DACs (G2-CH DAC # n + 2, G2-CH DAC # n + 5, G2- (G-RS # 2) and L (G2-CH DAC # 2n-4) as a representative of the odd-numbered first color right channel DAC among the first color right-side resistor string Away.

Of the plurality of first color right channel DACs (G2-CH DAC # n + 2, G2-CH DAC # n + 5, G2-CH DAC # n + 8, ..., G2-CH DAC # 2n- As a representative of the first color right channel DAC, G2-CH DAC # 2n-1 is separated from the first color right resistor string (G-RS # 2) by L (G2-CH DAC # 2n-1).

8, a distance value obtained by adding L (G1-CH DAC # 2) and L (G1-CH DAC # 5) 2n-1).

If such a relationship characteristic is generalized for all colors, it can be expressed as Equation (1).

Referring to the first equation of Equation 1, all the second color left channel DACs R1-CH DAC # 1, R1-CH DAC # 4, R1-CH DAC # 2) and the distance value obtained by adding the distance from the first color left-side resistor string (R-RS # 1) to the second color right side channel DAC (R2-CH DAC # The distance value obtained by adding the distance from the second color right side resistance string (R-RS # 2) to the second color right side resistance string (R-RS # 2) ..., (N-2)). In other words, the following equation is satisfied:? L (R1-CH DAC #

Referring to the second equation of Equation 1, all first color left channel DACs (G1-CH DAC # 2, G1-CH DAC # 5, G1-CH DAC # 1) and the distance value obtained by adding the distance from the first upper left resistance string (G-RS # 1) to all the first color right channel DACs (G2-CH DAC # n + 2, G2- The distance value obtained by adding the distance from the first color right side resistor string (G-RS # 2) to the first color right side resistor string (G-RS # 2) (G2-CH DAC # n + b, b = 2, 5, 8, ..., n-1).

., B1-CH DAC # n, B1-CH DAC # 3, B1-CH DAC # 6, (DAC # n + 3, B2-CH DAC # n + 6) and a distance value obtained by adding the distance from the first color left-side resistor string , The distance value obtained by adding the distance from the third color right-side resistance string (B-RS # 2) to the B2-CH DAC # n + 9, ..., B2-CH DAC # 2n may be substantially the same L (B1-CH DAC # c)?? L (B2-CH DAC # n + c), c = 3, 6, 9, ..., n.

Hereinafter, a second RS connection structure in a source driver integrated circuit (SD-IC) having a second core structure according to the present embodiments will be described. However, it is assumed that the pixel structure is an RGB structure.

11 to 13 are diagrams showing a source driver IC (SD-IC) having a second RS connection structure under a second core structure according to the present embodiments.

Referring to FIG. 11, a plurality of second color left channel DACs R1-CH DAC # 1, R2-CH DAC # 4, R1-CH DAC # n-5 and R2-CH DAC # n-2 are alternately connected to the second color left resistance string R-RS # 1 and the first color right resistance string G-RS # 2.

The first color left channel DACs G1-CH DAC # 2, G2-CH DAC # 5, G1-CH DAC # 8, G2- G2-CH DAC # n-1) is alternately connected to the first color left resistance string G-RS # 1 and the first color right resistance string G-RS # 2.

., B1-CH DAC # n-3, B2-CH DAC # 3, B2-CH DAC # B2-CH DAC #n) is alternately connected to the third color left resistance string (B-RS # 1) and the first color right resistance string (G-RS # 2).

Referring to FIG. 11, a plurality of second color right channel DACs (R1-CH DAC # n + 1, R2-CH DAC # n + 4, RS # 1 and R-RS # 2) of the first color left-side resistor string (R-RS # 1, ..., R1-CH DAC # 2n- Respectively.

The first color right channel DAC (G1-CH DAC # n + 2, G2-CH DAC # n + 5, G1-CH DAC # n + 8, G2- (G-RS # 1) and the first color right side resistor string (G-RS # 2) are alternately connected to the first color left side resistor string (G-RS # do.

In addition, a plurality of third color right channel DACs (B1-CH DAC # n + 3, B2-CH DAC # n + 6, B1-CH DAC # n + -CH DAC # 2n-3 and B2-CH DAC # 2n are alternately connected to the third color left resistance string B-RS # 1 and the third color right resistance string B-RS # 2.

The second RS connection structure from the above-mentioned channel DAC view is summarized in Table 2 below.

In the following, the second RS connection structure in the resistance string position will be described again.

The second color left resistance string (R-RS # 1) includes a plurality of second color left channel DACs (R1-CH DAC # 1, R2- Numbered left channel DAC (R1-CH (n-1)) out of the odd-numbered left channel DACs # 1, # 2, # 1, # 2, (DAC # 1, R1-CH DAC # 7, ..., R1-CH DAC # n-5), and a plurality of second color right channel DACs The odd-numbered right channel DAC (R1) is selected among the odd-numbered right channel DACs # 1, # 2, # 3, # 4, # 1, # 2, 1 -CH DAC # n + 1, R1-CH DAC # n + 7, ..., R1-CH DAC # 2n-5.

The second color right resistance string R-RS # 2 includes a plurality of second color left channel DACs (R1-CH DAC # 1, R2-R) as shown in FIG. 13, Numbered left channel DAC (R2-CH (n-1)) among the R-CH DAC # 4, R1-CH DAC # 7, R2-CH DAC # 10, ..., R1-CH DAC # (DAC # 4, R2-CH DAC # 10, ..., R2-CH DAC # n-2) and a plurality of second color right channel DACs The even-numbered right channel DAC (R2) is selected among the even-numbered right channel DACs (R2, +4, R1-CH DAC # n + 7, R2-CH DAC # n + 10, ..., R1- -CH DAC # n + 4, R2-CH DAC # n + 10, ..., R2-CH DAC # 2n-2.

The first color left resistance string G-RS # 1 includes a plurality of first color left channel DACs G1-CH DAC # 2, G2-CH DAC # 5, G1-CH DAC # ..., G1-CH DAC # 1, ..., G1-CH DAC # 2, ..., G1-CH DAC # CH DAC # n-4, and a plurality of first color right channel DACs G1-CH DAC # n + 2, G2-CH DAC # n + 5, G1- Numbered first color right channel DAC (G1-CH DAC # n + 2, G1-CH DAC # 2 + 1) among the odd-numbered first color right channel DACs (DAC # n + 11, ..., G1-CH DAC # 2n- n + 8, ..., G1-CH DAC # 2n-4).

The first color right resistor string G-RS # 2 includes a plurality of first color left channel DACs G1-CH DAC # 2, G2-CH DAC # 5, G1-CH DAC # G2-CH DAC # 5, G2-CH DAC # 11, ..., G2-CHD among the even-numbered first color left channel DAC (G2-CH DAC # CH DAC # n-1), and a plurality of first color right channel DACs (G1-CH DAC # n + 2, G2-CH DAC # n + 5, G1- G2-CH DAC # n + 5 and G2-CH DAC # n + 5 among the first-color right-channel DACs (DAC # n + 11, ..., G1-CH DAC # 2n- n + 11, ..., G2-CH DAC # 2n-1).

The third color left resistance string B-RS # 1 includes a plurality of third color left channel DACs B1-CH DAC # 3, B2-CH DAC # 6, B1-CH DAC # ..., B1-CH DAC (B1-CH DAC # 2, ..., B1-CH DAC # n-3, B2-CH DAC # n + 6, B1-CH DAC # n + 9 and B2-CH DAC # (DAC # n + 3, B1-CH DAC # n + 9, n-1) among the odd-numbered third right-channel DACs ..., B1-CH DAC # 2n-3).

The third color right resistance string B-RS # 2 includes a plurality of third color left channel DACs B1-CH DAC # 3, B2-CH DAC # 6, B1-CH DAC # B2-CH DAC # 6, B2-CH DAC # 12, ..., B2-CH DAC (n-1) among the even-numbered third color left channel DAC n + 3, B2-CH DAC # n + 6, B1-CH DAC # n + 9 and B2-CH DAC # n + ..., DAC (B2-CH DAC # n + 6, B2-CH DAC # n + 12, ..., B1-CH DAC # 2n- B2-CH DAC # 2n).

The second RS connection structure in terms of the above-described resistance string is summarized in Table 3 below.

Below, the effect of reducing the deviation between the RS connection distances of the source driver integrated circuit (SD-IC) having the second RS connection structure under the second core structure according to the above-described embodiments will be described. However, the first color will be exemplified.

11, G1-CH DAC # 2 as a representative of odd-numbered first color left channel DACs (G1-CH DAC # 2, G1-CH DAC # And the first color left resistance string (G-RS # 1) are separated by L (G1-CH DAC # 2). G2-CH DAC # 5 as a representative among the even-numbered first color left channel DACs (G2-CH DAC # 5, G2-CH DAC # The resistance string (G-RS # 2) is separated by L (G2-CH DAC # 5).

As a representative of the odd-numbered first color right channel DACs G1-CH DAC # n + 2, G1-CH DAC # n + 8, ..., G1-CH DAC # 2n- -4 and the first color left resistance string G-RS # 1 are separated by L (G1-CH DAC # 2n-4). 2-CH DAC # 2n-1 as a representative among the even-numbered first color right channel DACs (G2-CH DAC # n + 5, G2-CH DAC # n + 11, ..., G2- And the first color right resistance string (G-RS # 2) are separated by L (G2-CH DAC # 2n-1).

The distance values obtained by adding L (G1-CH DAC # 2) and L (G2-CH DAC # 5) are L (G1-CH DAC # 2n- Is almost the same as the distance value.

If such a relationship characteristic is generalized for all the colors, it can be expressed as the following equation (2).

Referring to the first equation in Equation 2, all odd-numbered second color left channel DACs (R1-CH DAC # d, d = 1, 7, 13, ..., n- (R2-CH DAC # e, e = 4, 10, 16) of all the even-numbered second color left channel DACs (R2-CH DAC # (R2-CH DAC # e) of the distances between the first color right side resistor string (R-RS # 2, ..., n-2) and the second color right side resistor string The sum of the distances between the channel DACs (R1-CH DAC # n + d, d = 1, 7, 13, ..., n-5) and the second color left resistance string (DAC # n + e, e = 4, 10, 16, ..., n-2) and the second color right side channel DACs The sum of the distances of the resistive strings R-RS # 2 (? L (R2-CH DAC # n + e)) is almost the same.

Referring to the second equation in Equation 2, all odd-numbered first color left channel DACs (G1-CH DAC # f, f = 2, 8, 14, ..., n- (G2-CH DAC # g, g = 5, 11, 17) of all the even-numbered first color left channel DACs (G2-CH DAC # (G2-CH DAC # g) of the distances between the first color right resistor string (G-RS # 2, ..., n-1) The sum of the distances between the channel DACs (G1-CH DAC # n + f, f = 2, 8, 14, ..., n-4) and the first color left resistance string (DAC # n + g, g = 5, 11, 17, ..., n-1) and the first color right side channel DAC (G2-CH DAC # n + g) of the resistance strings (G-RS # 2) are almost the same.

Referring to the third equation in Equation 2, all odd-numbered third color left channel DACs (B1-CH DAC #h, h = 3,9,15, ..., n- (B1-CH DAC #h) of all the even-numbered third color left channel DACs (B2-CH DAC #i, i = 6,12,18 (B2-CH DAC #i) of the distances of the third color right-side resistor strings (B-RS # 2, ..., n)

The distance between all odd-numbered third color right channel DACs (B1-CH DAC # n + h, h = 3,9,15, ..., n- (DAC # n + i, i = 6, 12, 18, ..., n) (B2-CH DAC # n + i) of the distances of the third color right-side resistor string (B-RS # 2)

14 is a graph showing the waveform of the output voltage of the source driver integrated circuit (SD-IC) having the second core structure according to the present embodiments. FIG. 15 is a diagram illustrating a block dim phenomenon occurring in a screen according to a source driver integrated circuit having a second core structure according to the present embodiments.

Referring to FIG. 14, for each of the first color, the second color, and the third color, the distance between the left channel DACs and the left and right resistance strings of the corresponding color, the distance between the right channel DACs and the corresponding color The output voltage waveform outputted from the left channel and the output voltage waveform outputted from the right channel are almost equal to each other.

In other words, in the first core structure, the resistance string is biased to the left or the right, and the output voltage waveform output from the left channel and the output voltage waveform output from the right channel are different, In the second core structure, since there is one resistor string of the same color on the left and one on the right, the output voltage waveform outputted from the left channel and the output voltage waveform outputted from the right channel are almost the same, Does not occur.

Therefore, as shown in Fig. 15, in the entire area 1500 to which the data voltage is supplied by one source driver IC (SD-IC), for example, for the second color, corresponding to the right channel CH 2n And the screen area 1520 corresponding to the left channel CH 1 does not occur. Therefore, a block dim phenomenon in the longitudinal direction that occurred in the first core structure does not occur.

As shown in Fig. 15, in the entire area 1500 where the data voltage is supplied by one source driver IC (SD-IC), for example, for the first color, corresponding to the left channel CH2 And the screen area 1540 corresponding to the right channel CH 2n-1 does not occur. Therefore, a block dim phenomenon in the longitudinal direction that occurred in the first core structure does not occur.

However, the source driver integrated circuit (SD-IC) having the second core structure according to the present embodiments has a resistance corresponding to all colors (first, second, and third colors) on the left side of the data receiving unit 400 The resistor string corresponding to all the colors (first, second, and third colors) must be disposed on the right side of the data receiving unit 400. Thus, the size of the core unit 300 is turned on, (SD-IC) may become large.

Therefore, it is advantageous to design with the second core structure in terms of line resistance variation, DAC delay, and blocking dimming. However, in order to reduce the size, one color or two colors that are sensitive to line resistance variation, DAC delay and block dim phenomenon For two colors or one color that is less sensitive to line resistance variation, DAC delay, and block dim phenomenon, the resistor string is placed in the data receiver (400) 400 may be designed to have a third core structure disposed only on the left side or the right side.

As an example of the third structure, the resistance strings (G-RS # 1 and G-RS # 2) corresponding to the first color are arranged on both the left and right sides of the data receiving unit 400, The resistor string (R-RS) corresponding to the third color is disposed only on the left side of the data receiving unit 400 and the resistor string (B-RS) corresponding to the third color is disposed on the right side of the data receiving unit 400. [ (SD-IC) will be described with reference to Figs. 16 to 17. Fig.

16 and 17, the core unit 300 includes a data receiving unit 400, a first color left resistance string G-RS # 1, a first color right resistance string G-RS # 2, A second color left resistance string (R-RS) and a third color right resistance string (B-RS).

The first color left resistance string G-RS # 1 is disposed on the left side of the data receiving unit 400 and the first color left side resistor string G-RS # 1 is disposed on the left side of the data receiving unit 400. In the core unit 300, The right resistance string (G-RS # 2) is disposed on the right side of the data receiving unit 400.

In the core unit 300, the second color left resistance string R-RS is disposed on the left side of the data receiving unit 400, and the third color right side resistor string B-RS is disposed on the left side of the data receiving unit 400. [ Respectively.

16 and 17, the left channel output unit 310 is disposed on the left side of the core unit 300 and includes a plurality of first color left channel DACs, a plurality of second color left channel DACs, And n left channel DACs (CH DAC # 1, CH DAC # 2, ..., CH DAC #n) of three color left channel DACs.

The right channel output unit 320 is disposed on the right side of the core unit 300 and includes a plurality of first color right channel DACs, a plurality of second color right channel DACs, and a plurality of third color right channel DACs n right channel DACs (CH DAC # n + 1, CH DAC # n + 2, ..., CH DAC # 2n).

16 is a diagram showing a first RS connection structure of a source driver integrated circuit (SD-IC) having a third core structure according to the present embodiments. However, it is assumed that the pixel structure is an RGBG pen tile structure.

Referring to FIG. 16, a plurality of first color left channel DACs (G1-CH DAC # 2, G1-CH DAC # 4, ...) are all connected to a first color left resistance string (G-RS # 1). The first color right channel DAC (..., G2-CH DAC # 2n-2, G2-CH DAC # 2n) is connected to the first color right resistor string (G-RS # 2).

That is, the first color left resistance string (G-RS # 1) is selected from the n left channel DACs (CH DAC # 1, CH DAC # 2, ..., CH DAC #n) included in the left channel output section 310 Are connected to all first color left channel DACs (G1-CH DAC # 2, G1-CH DAC # 4, ...). The first color right resistor string G-RS # 2 includes n right channel DACs (CH DAC # n + 1, CH DAC # n + 2, ..., CH DAC # 2n ..., G2-CH DAC # 2n-2, and G2-CH DAC # 2n).

(R-CH DAC # 1, R-CH DAC # 5, ...) and a plurality of second color right-side channels DAC CH DAC # 2n-3) are all connected to the second color left resistance string (R-RS).

That is, the second color left resistance string (R-RS) includes a plurality of n left channel DACs (CH DAC # 1, CH DAC # 2, ..., CH DAC #n) included in the left channel output section 310 ..., CH DAC # 1, R-CH DAC # 5, ...) and n right-channel DACs (CH DAC # n + 1, CH DAC # n + (R-CH DAC # 2n-7, R-CH DAC # 2n-3) among the plurality of second color right channel DACs

..., B-CH DAC # 2n-5, B-CH DAC # 7, ...) and a plurality of third color right channel DACs CH DAC # 2n-1) are all connected to the third color right resistance string (B-RS).

That is, the third color right-side resistor string B-RS is connected to one of the n left channel DACs (CH DAC # 1, CH DAC # 2, ..., CH DAC #n) included in the left channel output unit 310 ..., CH DAC # 7, ...) and n right channel DACs (CH DAC # n + 1, CH DAC # n + ..., B-CH DAC # 2n-5, and B-CH DAC # 2n-1 among the plurality of third color right channel DACs (2,

The source driver integrated circuit (SD-IC) having the first RS connection structure under the third core structure shown in FIG. 16 has the first RS connection structure under the second core structure shown in FIG. 8 for the first color (Prevention of line resistance variation, DAC delay and block dim phenomenon) of the source driver IC (SD-IC) having the first color and the third color.

However, since the second color and the third color are colors having insignificant visibility, in order to reduce the size, the resistance string (R-RS) corresponding to the second color is arranged only on the left side of the data receiving unit 400, Even if the resistor string (B-RS) corresponding to three colors is disposed on the right side of the data receiving unit 400, the block dim phenomenon caused by the line resistance variation and the DAC delay may not be negligibly large.

Unlike the second color and the third color, in the case of the first color, since the block dim phenomenon can be seriously caused even by a slight line resistance variation and a DAC delay, the color corresponding to the first color The strings (G-RS # 1, G-RS # 2) are designed to have a redundant structure to be disposed on both the left and right sides of the data receiving unit 400.

17 is a diagram showing a second RS connection structure of a source driver integrated circuit (SD-IC) having a third core structure according to the present embodiments.

Referring to FIG. 17, a plurality of first color left channel DACs G1-CH DAC # 2 and G2-CH DAC # 4 are connected to a first color left resistance string G- And the right resistance string (G-RS # 2).

.., G1-CH (DAC # 2, G1-CH DAC # 4, ...) among the plurality of first color left channel DACs DAC # n-2 is connected to the first color left resistance string (G-RS # 1). G2-CH DAC # 4, G2-CH DAC # 8, ..., G2-CH DAC #n are connected to the first color right resistance string (G-RS # 2).

17, a plurality of first color right channel DACs (..., G2-CH DAC # 2n-2 and G2-CH DAC # 2n) It is interchanged with the color right resistor string (G-RS # 2).

Namely, among the plurality of first color right channel DACs (..., G2-CH DAC # 2n-2, G2-CH DAC # 2n), G1-CH DAC # n + 2, G1-CH DAC # n + ..., G1-CH DAC # 2n-2 are connected to the first color left resistance string (G-RS # 1). G2-CH DAC # n + 4, G2-CH DAC # n + 8, ..., G2-CH DAC # 2n are connected to the first color right resistor string (G-RS # 2).

(R-CH DAC # 1, R-CH DAC # 5, ...) and a plurality of second color right-side channels DAC CH DAC # 2n-3) are all connected to the second color left resistance string (R-RS).

That is, the second color left resistance string (R-RS) includes a plurality of n left channel DACs (CH DAC # 1, CH DAC # 2, ..., CH DAC #n) included in the left channel output section 310 ..., CH DAC # 1, R-CH DAC # 5, ...) and n right-channel DACs (CH DAC # n + 1, CH DAC # n + (R-CH DAC # 2n-7, R-CH DAC # 2n-3) among the plurality of second color right channel DACs

..., B-CH DAC # 2n-5, B-CH DAC # 7, ...) and a plurality of third color right channel DACs CH DAC # 2n-1) are all connected to the third color right resistance string (B-RS).

That is, the third color right-side resistor string B-RS is connected to one of the n left channel DACs (CH DAC # 1, CH DAC # 2, ..., CH DAC #n) included in the left channel output unit 310 ..., CH DAC # 7, ...) and n right channel DACs (CH DAC # n + 1, CH DAC # n + ..., B-CH DAC # 2n-5, and B-CH DAC # 2n-1 among the plurality of third color right channel DACs (2,

In the case of the second RS connection structure shown in FIG. 17, a resistor string (G-RS # 1, G-RS # 2) corresponding to a first color having high visibility is connected to the data receiver 400 , The line resistance variation and the DAC delay can be reduced, thereby preventing a block dim phenomenon.

On the other hand, the process deviations between the left channel DACs and the right channel DACs, or the left resistance strings R-RS # 1, G-RS # 1, B- The first RS connection structure may cause a left / right block dim phenomenon according to the process variation, but the second RS connection structure may not perform the process It is possible to greatly reduce or prevent the left and right block dim phenomenon caused by the deviation.

18 is a diagram illustrating each channel DAC included in a source driver integrated circuit (SD-IC) having first, second, and third core structures according to the present embodiments in the form of a 3-bit DAC.

According to the embodiments as described above, it is possible to provide a source driver IC (SD-IC) and a display device 100 that can prevent block-dim phenomenon and improve image quality.

Further, according to the embodiments, it is revealed that the block dim phenomenon is caused by the arrangement structure of resistance strings in the source driver integrated circuit, and a structure capable of preventing the block dim phenomenon (second, third core structure, , A second RS connection structure), and a display device 100 including the source driver integrated circuit (SD-IC).

In addition, according to the embodiments, even if a process deviation of a resistor string or a channel digital-to-analog converter (DAC) occurs, a structure capable of preventing a block dim phenomenon in the right and left screen regions A core structure, and a second RS connection structure) and a display device 100 including the source driver integrated circuit (SD-IC).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display device
110: Display panel
120: Data driver
130: Gate driver
140: Timing controller
300: core unit
310: Left channel output section
320: Right channel output section
400: Data receiving unit

Claims (13)

In a source driver integrated circuit,
A core unit including a first color left resistance string arranged on the left side and a first color right side resistance string arranged on the right side;
A left channel output unit disposed on the left side of the core unit and including a plurality of first color left channel DACs, a plurality of second color left channel DACs and a plurality of third color left channel DACs; And
And a right channel output portion disposed on the right side of the core unit and including a plurality of first color right channel DACs, a plurality of second color right channel DACs, and a plurality of third color right channel DACs. The method according to claim 1,
The core unit includes a data receiving unit for receiving data,
The first color left resistance string is disposed on the left side of the data receiving unit,
And the first color right resistance string is disposed on the right side of the data receiving unit. 3. The method of claim 2,
Wherein the core unit comprises:
A second color left resistance string and a third color left resistance string disposed on the left side of the data receiving unit,
A second color right resistor string and a third color right resistor string disposed on the right side of the data receiving unit. The method of claim 3,
The plurality of first color left channel DACs are all connected to the first color left channel resistor string and the plurality of first color right channel DACs are all connected to the first color right channel resistor string,
Wherein the plurality of second color left channel DACs are all connected to the second color left channel resistor string and the plurality of second color right channel DACs are all connected to the second color right channel resistor string,
Wherein the plurality of third color left channel DACs are all connected to the third color left channel resistor string and the plurality of third color right channel DACs are all connected to the third color right channel resistor string. The method of claim 3,
The plurality of first color left channel DACs being alternately connected to the first color left resistor string and the first color right resistor string,
Wherein the plurality of first color right channel DACs are alternately connected to the first color left resistor string and the first color right resistor string,
The plurality of second color left channel DACs being alternately connected to the second color left resistor string and the second color right resistor string,
The plurality of second color right channel DACs being alternately connected to the second color left resistance string and the second color right resistance string,
Wherein the plurality of third color left channel DACs are alternately connected to the third color left resistance string and the third color right resistance string,
Wherein the plurality of third color right channel DACs are alternately connected to the third color left resistor string and the third color right resistor string. 3. The method of claim 2,
Wherein the core unit comprises:
And a second color left resistance string disposed on the left side of the data receiving unit,
And a third color right resistance string disposed on the right side of the data receiving section. The method according to claim 6,
The plurality of first color left channel DACs are all connected to the first color left channel resistor string and the plurality of first color right channel DACs are all connected to the first color right channel resistor string,
The plurality of second color left channel DAC and the plurality of second color right channel DAC are all connected to the second color left resistance string,
Wherein the plurality of third color left channel DACs and the plurality of third color right channel DACs are all coupled to the third color right side resistor string. The method according to claim 6,
Wherein the plurality of first color left channel DACs are interchanged with the first color left resistor string and the first color right resistor string and the plurality of first color right channel DACs are connected to the first color left resistor string and the first color right resistor string, The first color right resistor string is connected to the first color right resistor string,
The plurality of second color left channel DAC and the plurality of second color right channel DAC are all connected to the second color left resistance string,
Wherein the plurality of third color left channel DACs and the plurality of third color right channel DACs are all coupled to the third color right side resistor string. A core unit including a plurality of resistor strings and a data receiving unit;
A plurality of left channel DACs disposed on the left side of the core unit; And
And a plurality of right channel DACs disposed on the right side of the core unit,
Wherein the number of resistor strings located on both sides of the data receiving unit is the same. A display panel in which a plurality of data lines and a plurality of gate lines are arranged and in which a plurality of subpixels are arranged;
One or more source driver integrated circuits for receiving data and outputting an analog voltage to the plurality of data lines; And
And a timing controller for transmitting the data to the one or more source driver integrated circuits,
Each source driver integrated circuit comprising:
A core unit including a first color left resistance string arranged on the left side and a first color right side resistance string arranged on the right side;
A left channel output unit disposed on the left side of the core unit and including a plurality of first color left channel DACs, a plurality of second color left channel DACs and a plurality of third color left channel DACs; And
And a right channel output portion disposed on the right side of the core unit and including a plurality of first color right channel DACs, a plurality of second color right channel DACs, and a plurality of third color right channel DACs. 11. The method of claim 10,
Wherein the core unit includes a data receiving unit for receiving the data,
The first color left resistance string is disposed on the left side of the data receiving unit,
And the first color right resistance string is disposed on the right side of the data receiving unit. 11. The method of claim 10,
Wherein the core unit comprises:
A second color left resistance string and a third color left resistance string disposed on the left side of the data receiving unit,
And a second color right resistance string and a third color right resistance string disposed on the right side of the data receiving unit. 11. The method of claim 10,
Wherein the core unit comprises:
And a second color left resistance string disposed on the left side of the data receiving unit,
And a third color right resistance string disposed on the right side of the data receiving unit.

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