JP4807070B2 - Electro-optical device driving method, display driver, electro-optical device, and electronic apparatus - Google Patents

Description

  The present invention relates to a driving method of an electro-optical device, a display driver, an electro-optical device, and an electronic apparatus.

  Conventionally, there is a frame rate control (FRC) method in which the number of gradations is increased by changing the luminance of each color component dot corresponding to gradation data of a given number of bits with a time difference. The liquid crystal display (LCD) panel (electro-optical device in a broad sense) is used as a driving method.

  While the FRC method can increase the number of gradations at low cost, it appears as “flickering” when the brightness of dots is changed at a low rate. For this reason, the FRC method requires a high-speed and high-rate luminance change, which tends to increase power consumption. Also, depending on the type of FRC pattern that defines how to adjust the brightness of each dot, it may appear as a striped pattern even at a high rate.

Therefore, various techniques for realizing driving of the LCD panel by the FRC method with low power consumption while suppressing such image quality deterioration are disclosed. For example, Patent Document 1 uses a line memory that stores gradation data of one horizontal line before, and based on the distribution of halftone dots of gradation data of the current horizontal line and gradation data of the previous horizontal line. A technique is disclosed in which halftone data is generated and gradation expression is realized by on data, off data, and halftone data. Further, for example, Patent Document 2 is provided with a state table in which a state symbol for adjusting the luminance of each pixel is provided, and corresponds to lower bits of input data to be removed from output data and pixel positions of the input data in the state table. A technique for adjusting the luminance of a pixel of output data corresponding to input data based on a status symbol is disclosed. Furthermore, for example, Patent Document 3 discloses a technique for driving an LCD panel that performs gradation expression by pulse width modulation or pulse height modulation using the lower bits and performs gradation expression by FRC using the upper bits. Has been. For example, Patent Document 4 discloses a technique for preventing a fixed pattern from being generated when driven by the FRC method by optimizing a combination of a drive pattern that reverses the polarity of the applied voltage of the liquid crystal and the FRC pattern. It is disclosed.
JP-A-5-210356 JP 2000-231368 A JP 2003-84732 A JP 2005-157280 A

  However, in the technique disclosed in Patent Document 1, it is necessary to provide a line memory for storing gradation data of the previous horizontal line, which increases the circuit scale and the image quality depends on halftone data. There is a problem that the control becomes complicated in order to improve the efficiency.

  The technique disclosed in Patent Document 2 requires an FRC pattern other than a checkered pattern. Furthermore, in the technique disclosed in Patent Document 3, it is necessary to perform pulse width modulation or pulse height modulation, which complicates the driving method. Therefore, these techniques cause an increase in circuit scale and power consumption.

  Furthermore, in the technique disclosed in Patent Document 4, a combination of a drive pattern that reverses the polarity of the applied voltage of the liquid crystal and the FRC pattern is optimized, so that a specific pattern appears depending on the type of display pattern on the entire screen. There is a case.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide FRC (Frame Rate Control) by simple control with low power consumption without causing an increase in circuit scale. It is an object to provide a driving method of an electro-optical device, a display driver, an electro-optical device, and an electronic apparatus for performing gradation display by a method.

In order to solve the above problems, the present invention
For gradation display by FRC (Frame Rate Control) method using lower-order k (j>k> 0, k is an integer) bit data of j (j ≧ 2, j is an integer) bit gradation data A method for driving an electro-optical device, comprising:
An FRC pattern for designating whether or not to perform gradation data increment processing for adjusting the brightness of the dot position based on the lower-order k-bit data of the gradation data of each dot constituting the pixel, Differently when the lower (k + 1) bit data of the data is 0 and when the lower (k + 1) bit data of the gradation data is 1.
An electro-optical device that performs the increment processing according to different FRC patterns according to the lower (k + 1) -bit data and drives the electro-optical device based on the (j−k) -bit gradation data after the increment processing. Related to the driving method.

In the driving method of the electro-optical device according to the invention,
First to Pth FRC patterns (P ≧ 2 ^k , P is an integer) are prepared,
Different FRC patterns are selected when the lower (k + 1) bit data of the gradation data is 0 and when the lower (k + 1) bit data of the gradation data is 1.
The increment process is performed in accordance with the selected FRC pattern, and the electro-optical device can be driven based on the (j−k) -bit gradation data after the increment process.

  According to any one of the above-described inventions, for example, a so-called diagonal gradation image display pattern is used by using a checkered FRC pattern that performs an increment process dispersed in time and space to prevent deterioration in image quality. However, after the increment process, it is possible to avoid a situation in which the pixels for which the process for increasing the brightness is performed and the pixels for which the process for decreasing the brightness are performed are aligned on the entire screen. In addition, since it is only necessary to change the FRC pattern according to the lower (k + 1) -th bit data of the gradation data, it is possible to simplify the control.

In the driving method of the electro-optical device according to the invention,
Selected when the lower (k + 1) -bit data is 1 for the dot designated to perform the increment processing in the FRC pattern selected when the lower-order (k + 1) -bit data is 0 The FRC pattern is designated not to perform the increment process,
Select when the lower (k + 1) -bit data is 1 for the dot designated not to perform the increment processing in the FRC pattern selected when the lower (k + 1) -bit data is 0 The FRC pattern may be designated to perform the increment process.

  According to the present invention, it is only necessary to invert the element data of the FRC pattern without adding the FRC pattern, so that an increase in circuit scale can be prevented. Moreover, it is possible to avoid a situation in which the frame period for gradation display by FRC becomes long, and the image quality can be improved.

In the driving method of the electro-optical device according to the invention,
The FRC pattern is
Whether or not to perform the increment processing can be designated for each dot.

In the driving method of the electro-optical device according to the invention,
k is 1,
The FRC pattern may be a checkered pattern in which dots designated to perform increment processing and dots designated not to perform increment processing are adjacent.

In the driving method of the electro-optical device according to the invention,
The FRC pattern is
Whether or not to perform the increment processing can be designated for each pixel.

The present invention also provides
A display driver for driving at least the first to sixth data lines of the plurality of data lines of the electro-optical device,
First to sixth data line driving circuits for driving each data line of the first to sixth data lines based on gradation data,
An FRC control circuit that generates first and second FRC control signals that change based on the vertical synchronization signal and the horizontal synchronization signal and have opposite phases to each other;
When the i-th (1 ≦ i ≦ 5, i is an integer) data line is adjacent to the (i + 1) -th data line,
Each data line driving circuit of the first to sixth data line driving circuits includes:
An FRC processing circuit for performing gradation data increment processing based on the first or second FRC control signal and lower two bits of j (j ≧ 2, j is an integer) bit gradation data;
A voltage selection circuit that selects a reference voltage corresponding to (j−1) -bit gradation data among gradation data after the increment processing from a plurality of reference voltages;
An output circuit for driving a data line using a reference voltage selected by the voltage selection circuit,
An FRC processing circuit of each data line driving circuit of the adjacent first to third data line driving circuits is provided.
The gradation data is incremented based on the first FRC control signal and the lower 2 bits of the j-bit gradation data,
An FRC processing circuit of each data line driving circuit of the adjacent fourth to sixth data line driving circuits is provided.
The present invention relates to a display driver that performs gradation data increment processing based on the second FRC control signal and lower 2 bits of j-bit gradation data.

  According to the present invention, for example, even a display pattern of a so-called diagonal gradation image, a checkered FRC that prevents deterioration in image quality by performing an incremental process dispersed temporally and spatially after the FRC process is performed. By using a pattern, it is possible to avoid a situation in which pixels that have been processed to increase brightness and pixels that have been processed to decrease brightness are aligned on the entire screen. Since it is only necessary to change the FRC pattern according to the bit-th data, the control can be simplified. Further, since it is only necessary to invert the element data of the FRC pattern without adding the FRC pattern, an increase in circuit scale can be prevented. Moreover, it is possible to avoid a situation in which the frame period for gradation display by FRC becomes long, and the image quality can be improved.

In the display driver according to the present invention,
Each data line driving circuit of the first to sixth data line driving circuits includes:
A comparison circuit for comparing a gradation value corresponding to the input gradation data with a given maximum gradation value or minimum gradation value;
On the condition that the gradation value does not match the maximum gradation value or the minimum gradation value, the voltage selection circuit generates a reference voltage corresponding to the upper (j−1) bits of the input gradation data. You can choose.

  According to the present invention, the comparison circuit is provided, and so-called exceptional processing is performed in accordance with the gradation data, so that the electro-optic is based on an unnecessary processing result generated at the time of specific gradation data in the increment processing. The situation of driving the apparatus can be avoided and the deterioration of the image quality can be prevented.

The present invention also provides
A plurality of scan lines;
Multiple data lines,
A plurality of pixels specified by the scanning lines and the data lines;
A scan driver for scanning the scan line;
The present invention relates to an electro-optical device including the display driver described above that drives the data line based on the gradation data.

  According to the present invention, it is possible to provide an electro-optical device that performs gradation display by the FRC method with low power consumption and simple control without causing an increase in circuit scale.

The present invention also provides
The present invention relates to an electronic apparatus including the electro-optical device described above.

  According to the present invention, it is possible to provide an electronic apparatus including an electro-optical device that performs gradation display by the FRC method with low power consumption and simple control without causing an increase in circuit scale.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. FRC (Frame Rate Control)
FIG. 1 is a diagram for explaining the principle of FRC.

  FRC is a technique for expressing an image with a larger number of gradations using gradation data with a small number of bits by changing the luminance of pixels or dots constituting the pixels with a time difference. For example, when attention is paid to a certain dot, a dot with a high gradation GS2 is displayed after a dot with a low gradation GS1 is displayed. By doing so, it is possible to make a person who sees the dot appear to be displayed with the brightness of the gradation GS3 which is an intermediate gradation between the gradations GS1 and GS2.

  Thus, FRC can increase the number of gradations at low cost. On the other hand, when the gradations GS1 and GS2 are switched at a low speed, so-called “flickering” appears in the image, leading to degradation of image quality. Therefore, in order to improve the image quality, it is necessary to switch the gradations GS1 and GS2 at high speed, and there is a disadvantage that an increase in mounting area and power consumption due to an additional circuit for that purpose are caused.

  When realizing such FRC, an FRC pattern (pattern in a broad sense) that defines how to adjust the luminance of each pixel or each dot is used.

  FIG. 2 is an explanatory diagram of an example of the FRC pattern.

  Here, a processing example of so-called 1-bit FRC is shown. In order to eliminate so-called “flickering”, a so-called checkered FRC pattern in which dots (pixels) for increasing luminance and dots (pixels) for decreasing luminance are adjacent to each other is virtually arranged on the entire screen. . In the following, each element of the FRC pattern is represented by dots (pixels) that increase the luminance as squares that are not shaded, and dots (pixels) that decrease the luminance are represented by squares that are shaded. For convenience of explanation, FIG. 2 shows a 2 dot × 2 dot FRC pattern.

  Then, by changing the brightness of each dot with a time difference according to the FRC pattern, an intermediate gradation is expressed. For example, when attention is focused on the dot DP1, processing for increasing the luminance and processing for decreasing the luminance are alternately performed according to the gradation data. When attention is paid to the dot DP2, the process of decreasing the brightness and the process of increasing the brightness are alternately performed according to the gradation data. In this way, by changing the checkered FRC pattern with a time difference, the dots that are processed to increase the luminance and the dots that are processed to decrease the luminance are dispersed both temporally and spatially. Deterioration of image quality such as “flickering” and striped patterns can be prevented.

  The FRC may be processed for each dot constituting the pixel according to the FRC pattern designated by the dot unit constituting the pixel, or may be processed for each pixel according to the FRC pattern designated by the pixel unit. Good.

  FIG. 3 illustrates an example of processing using the FRC pattern.

First, it is assumed that gradation data is held in a frame memory (display memory) (not shown) in units of pixels for one screen (or dots constituting the pixels), for example. In FIG. 3, the gradation data of the pixels DP ₁₁ , DP ₁₂ , DP ₂₁ , DP ₂₂ constituting 2 pixels × 2 pixels arranged in the horizontal direction and the vertical direction are represented by P ₁₁ , P ₁₂ , P ₂₁ , P ₂₂ .

The FRC pattern includes element data PAT (P ₁₁ ), PAT (P ₁₂ ), PAT (P ₂₁ ), and PAT (P ₂₂ ) for each pixel of the pixels DP ₁₁ , DP ₁₂ , DP ₂₁ , and DP _22. Is assigned. That is, for example, the element data PAT (P ₁₁ ) of the FRC pattern is assigned to the pixel DP ₁₁ whose gradation data is P ₁₁ . Each element data is data for designating whether to perform a process for increasing the brightness or a process for decreasing the brightness. In the following, it is assumed that element data specifying a process for increasing luminance is “bright pattern” (= 1), and element data specifying a process for increasing luminance is “dark pattern” (= 0).

Here, the gradation data after processing using the FRC pattern (increment processing, FRC processing in a broad sense) for each pixel of the pixels DP ₁₁ , DP ₁₂ , DP ₂₁ , DP ₂₂ is GP ₁₁ , GP ₁₂ , GP _21. , GP ₂₂ .

  FIG. 4 shows an example of the FRC process including the increment process.

FIG. 4 shows a flowchart of an example of FRC processing performed for each pixel. First, element data PAT (P _i ) corresponding to a pixel that is gradation data P _i (where i is any one of 11, 12, 21, and 22) is read from the FRC pattern. Here, it is determined whether or not the element data PAT (P _i ) is a “bright pattern” (step S10).

In step S10, when the element data PAT (P _i ) is a “bright pattern” (step S10: Y), it is determined whether or not the gradation data P _i is even data (step S11).

In step S11, when the gradation data P _i is even data (step S11: Y), the data from which the least significant bit (LSB) of the gradation data P _i is deleted is used as the gradation data GP _i after the FRC process. It is generated (step S12). For example, when the least significant bit of the gradation data P _i is 0, it can be determined that the gradation data P _i is even data.

In step S10, when the element data PAT (P _i ) is a “dark pattern” (step S10: N), the data in which the least significant bit (LSB) of the gradation data P _i is deleted is the same after the FRC processing. It is generated as gradation data GP _i (step S12).

In step S12, assuming that the number of bits of the gradation data GP _i after the FRC process is J, the number of bits of the gradation data P _i is (J−1). Then, for example, while switching ^{two one} FRC pattern, gray scale display is performed.

On the other hand, in step S11, when the gradation data _Pi is odd data (step S11: N), an increment process is performed (step S13). For example, when the least significant bit of the gradation data P _i is 1, it can be determined that the gradation data P _i is odd data. Increment processing is a processing for adding 1 to the least significant bit of the grayscale data P _i. Then, after the increment process, the process proceeds to step S12.

  Next, a specific processing example of so-called 1-bit FRC will be described with reference to the diagrams shown in FIGS.

  FIG. 5 is an explanatory diagram of a specific processing example of the FRC of FIGS. 3 and 4.

In FIG. 5, the gradation data P ₁₁ , P ₁₂ , P ₂₁ , and P _{22 of} the pixels DP ₁₁ , DP ₁₂ , DP ₂₁ , and DP ₂₂ are ₁₁ , 3, 8, and 5, respectively. For the processing of 1-bit FRC, checkered FRC patterns X and Y are prepared in which the element data are mutually inverted. In the FRC pattern X, the element data PAT (P ₁₁ ) is 1 (“bright pattern”), the element data PAT (P ₁₂ ) is 0 (“dark pattern”), the element data PAT (P ₂₁ ) is 1, and the element data PAT (P ₂₂ ) is 0. In the FRC pattern Y, the element data PAT (P ₁₁ ) is 0, the element data PAT (P ₁₂ ) is 1, the element data PAT (P ₂₁ ) is 0, and the element data PAT (P ₂₂ ) is 1.

First, the case of the FRC pattern X is calculated as an example. For the pixel DP ₁₁ , the gradation data P ₁₁ is 11 (= 1011b, b is a binary number), and the element data PAT (P ₁₁ ) is 1, so that the gradation data P ₁₁ after the increment processing is 12 (= 1100b). Therefore, the gradation data _{GP 11} after FRC processing cutting LSB becomes 6 (= 110b).

The pixel _{DP 12,} grayscale data _{P 12} is 3 (= 0011b), because element data PAT _{(P 12)} is 0, the gradation data _{GP 12} after FRC processing cut LSB is 1 (= 001b) It becomes.

The pixel _{DP 21,} grayscale data _{P 21} is 8 (= 1000b), because element data PAT _{(P 21)} is 0, the gradation data _{GP 21} after FRC processing cut LSB is 4 (= 100b) It becomes.

The pixel _{DP 22,} grayscale data _{P 22} is 15 (= 1111b), because element data PAT _{(P 22)} is 1, the gradation data _{P 22} after the increment processing is 16 (= 10000b). Therefore, the gradation data GP ₂₂ after the FRC process with the LSB cut is 8 (= 1000b).

The same calculation can be performed for the FRC pattern Y. The pixel _{DP 11,} grayscale data _{P 11} is 11 (= 1011b), because element data PAT _{(P 11)} is 0, the gradation data _{GP 11} after FRC processing cut LSB is 5 (= 101b) It becomes.

The pixel _{DP 12,} grayscale data _{P 12} is 3 (= 0011b), because element data PAT _{(P 12)} is 1, the gradation data _{P 12} after the increment processing is 4 (= 0100b). Therefore, the grayscale data _{GP 12} after FRC processing cutting LSB becomes 2 (= 010b).

For the pixel DP ₂₁ , since the gradation data P ₂₁ is 8 (= 1000b) and the element data PAT (P ₂₁ ) is 1, the gradation data P ₂₁ after the increment processing is 9 (= 1001b). Therefore, the gradation data GP ₂₁ after the FRC process with the LSB cut is 4 (= 100b).

The pixel _{DP 22,} grayscale data _{P 22} is 15 (= 1111b), because element data PAT _{(P 22)} is 0, the gradation data _{GP 22} after FRC processing cutting LSB is 7 (= 111b) It becomes.

  In this way, after driving the LCD panel based on the gradation data of each pixel generated based on the FRC pattern X, a predetermined time difference is provided to the gradation data of each pixel generated based on the FRC pattern Y. Based on this, the LCD panel is driven. Thereafter, the LCD panel is driven based on the gradation data of each pixel generated based on the FRC pattern X again. As described above, by driving the LCD panel while alternately switching the gradation data of each pixel generated by the FRC patterns X and Y, intermediate gradations can be expressed, and gradation display with a larger number of gradations can be achieved. Will be able to do.

2. By the way, as described above, it is desirable that the pixels on which the FRC process for increasing the luminance is performed be dispersed both temporally and spatially. In addition, it is desirable that the pixels on which the FRC process for reducing the luminance is performed are dispersed both temporally and spatially.

  However, as described above, since the FRC processing is performed using the gradation data of the pixels, the pixels on which the same FRC processing is performed may be dispersed both temporally and spatially depending on the display pattern of the screen. It may be impossible. When the FRC process is performed on such a display pattern, the pixels that have been subjected to the process of increasing the brightness and the pixels that have been subjected to the process of decreasing the brightness are aligned and appear to blink on the entire screen. There is.

  For example, consider an image after FRC processing for a display pattern of a horizontal gradation image, a display pattern of a vertical gradation image, and a display pattern of an oblique gradation image. Here, the horizontal gradation image refers to an image that continuously changes in the direction in which the gradation value of each pixel increases (or decreases) in the horizontal direction. A vertical gradation image refers to an image that continuously changes in the vertical direction in which the gradation value of each pixel increases (or decreases). Furthermore, the diagonal gradation image refers to an image that continuously changes in the direction in which the gradation value of each pixel increases (or decreases) in the horizontal direction and the vertical direction.

  FIG. 6 is an explanatory diagram of the FRC process for the display pattern of the horizontal gradation image.

  In FIG. 6, an image of 10 pixels × 10 pixels arranged in the horizontal direction and the vertical direction is shown as the display pattern DISP1 of the horizontal gradation image (original image). That is, in FIG. 6, the gradation data of each pixel continuously changes in the horizontal direction in the order of 0, 1, 2,. Consider a case in which an FRC process is performed on such a display pattern DISP1 using checkered FRC patterns FP1 and FP2 in which element data is inverted. In the FRC patterns FP1 and FP2, data of elements not hatched indicates “bright patterns”, and data of elements hatched is “dark patterns”.

  In FIG. 6, the display pattern after the FRC process using the FRC pattern FP1 for the display pattern DISP1 is FDISP1, and the display pattern after the FRC process using the FRC pattern FP2 for the display pattern DISP1 is FDISP2. Also in the display patterns FDISP1 and FDISP2, the gradation data of each pixel is shown, the gradation data of the pixel that has been subjected to the process of decreasing the luminance is surrounded by a square, and the gradation data of the pixel that has been subjected to the process of increasing the luminance Is circled. Note that gradation data that is not surrounded by a square or a circle indicates that FRC processing is not performed.

  The LCD panel is driven alternately using the display patterns FDISP1 and FDISP2 after such FRC processing. At this time, in the entire screen, the pixels subjected to the process for increasing the brightness and the pixels subjected to the process for decreasing the brightness are dispersed both temporally and spatially, so that the image quality is not deteriorated. .

  FIG. 7 shows an explanatory diagram of the FRC process for the display pattern of the vertical gradation image.

  FIG. 7 shows a 10 × 10 pixel image arranged in the horizontal direction and the vertical direction as the display pattern DISP2 of the vertical gradation image (original image). That is, in FIG. 7, the gradation data of each pixel continuously changes in the vertical direction in the order of 0, 1, 2,... Consider a case in which an FRC process is performed on such a display pattern DISP2 using checkered FRC patterns FP1 and FP2 in which element data is inverted.

  In FIG. 7, the display pattern after FRC processing using the FRC pattern FP1 for the display pattern DISP2 is FDISP3, and the display pattern after FRC processing using the FRC pattern FP2 for the display pattern DISP2 is FDISP4. Also in the display patterns FDISP3 and FDISP4, the gradation data of each pixel is shown, the gradation data of the pixel that has been subjected to the process of decreasing the luminance is surrounded by a square, and the gradation data of the pixel that has been subjected to the process of increasing the luminance Is circled. Note that gradation data that is not surrounded by a square or a circle indicates that FRC processing is not performed.

  The LCD panel is driven alternately using the display patterns FDISP3 and FDISP4 after such FRC processing. At this time, in the entire screen, the pixels subjected to the process for increasing the brightness and the pixels subjected to the process for decreasing the brightness are dispersed both temporally and spatially, so that the image quality is not deteriorated. .

  As described above, the image quality of the display pattern of the horizontal gradation image and the vertical gradation image is not deteriorated. However, the display pattern of the diagonal gradation image has the following problems.

  FIG. 8 is an explanatory diagram of FRC processing for a display pattern of an oblique gradation image.

  FIG. 8 shows an image of 10 pixels × 10 pixels arranged in the horizontal direction and the vertical direction as the display pattern DISP3 of the oblique gradation image (original image). That is, in FIG. 8, the gradation data of each pixel continuously changes in the horizontal direction and the vertical direction in the order of 0, 1, 2,... Consider a case in which an FRC process is performed on such a display pattern DISP3 using checkered FRC patterns FP1 and FP2 in which element data is inverted.

  In FIG. 8, the display pattern after FRC processing using the FRC pattern FP1 for the display pattern DISP3 is FDISP5, and the display pattern after FRC processing using the FRC pattern FP2 for the display pattern DISP3 is FDISP6. Also in the display patterns FDISP5 and FDISP6, the gradation data of each pixel is shown, the gradation data of the pixel that has been subjected to the process of reducing the brightness is surrounded by a square, and the gradation data of the pixel that has been subjected to the process of increasing the brightness Is circled. Note that gradation data that is not surrounded by a square or a circle indicates that FRC processing is not performed.

  The LCD panel is driven alternately using the display patterns FDISP5 and FDISP6 after such FRC processing. At this time, in the display pattern FDISP5, there are only pixels that have been subjected to the process of increasing the brightness and pixels that are not subjected to the FRC process in the entire screen, and in the display pattern FDISP6, a process of decreasing the brightness of the entire screen is performed. There are only pixels that are displayed and pixels that are not subjected to FRC processing. Accordingly, the pixels on which the process for increasing the brightness is performed and the pixels on which the process for decreasing the brightness are performed are aligned on the entire screen and appear to blink, leading to deterioration in image quality.

  In order to avoid such a situation, it is conceivable to add an FRC pattern and perform processing using more types of FRC patterns. However, not only the frame period for gradation display by FRC becomes longer, but also the circuit scale increases and the control becomes complicated.

3. Description of the present embodiment In order to avoid the above situation, in this embodiment, the lower-order k (j>k> 0, k is an integer) bits of j (j ≧ 2, j is an integer) bits of gradation data When the electro-optical device is driven by the FRC (Frame Rate Control) method using the above-described data and gradation display is performed, the dot position is determined based on the lower k bits of the gradation data of each dot constituting the pixel. An FRC pattern for designating whether or not to perform gradation data increment processing for adjusting the luminance of each pixel or dot, and gradation data when the lower (k + 1) -th bit data of the gradation data is 0 Are different from those when the lower (k + 1) -th bit data is 1. Then, FRC processing is performed according to different FRC patterns according to lower (k + 1) -th bit data, and the electro-optical device is driven based on (j−k) -bit gradation data after the FRC processing.

Furthermore, in the present embodiment, first to Pth (P ≧ 2 ^k , P is an integer) FRC patterns are prepared, and when the lower (k + 1) -th bit data of the gradation data is 0 and the lower order of the gradation data A different FRC pattern is selected when the (k + 1) -th bit data is 1. Then, it is desirable to perform an increment process according to the selected FRC pattern and drive the electro-optical device based on the (j−k) -bit gradation data after the increment process.

  By doing this, even if the display pattern is an oblique gradation image, a checkered FRC pattern is used after the FRC process, in which an increment process dispersed in time and space is performed to prevent image quality degradation. Thus, it is possible to avoid a situation in which the pixels for which the process for increasing the brightness is performed and the pixels for which the process for decreasing the brightness are performed are aligned on the entire screen. In addition, since it is only necessary to change the FRC pattern according to the lower (k + 1) -th bit data of the gradation data, it is possible to simplify the control.

  The lower (k + 1) th bit of the gradation data is compared with the dot (pixel) designated to perform the increment process in the FRC pattern selected when the lower (k + 1) th bit data of the gradation data is 0. In the FRC pattern selected when the data is 1, it is desirable to specify that the increment process is not performed. When the lower (k + 1) -bit data is 1 with respect to a dot (pixel) designated not to be incremented in the FRC pattern selected when the lower (k + 1) -bit data is 0 It is desirable that the FRC pattern selected in the above is designated to perform the increment process. Thereby, it is only necessary to invert the element data of the FRC pattern without adding the FRC pattern, so that an increase in circuit scale can be prevented. Moreover, it is possible to avoid a situation in which the frame period for gradation display by FRC becomes long, and the image quality can be improved.

  By the way, when k is 1, it corresponds to a so-called 1-bit FRC. In this case, the FRC pattern is desirably a checkered pattern in which pixels designated to perform the increment process and dots (pixels) designated not to perform the increment process are adjacent to each other.

  FIG. 9 shows an example of the FRC process including the increment process of the present embodiment.

9, parts that are the same as those in FIG. 3 are given the same reference numerals, and descriptions thereof will be omitted as appropriate. First, it is determined whether or not the lower (k + 1) -th bit data of dot gradation data P _i for FRC processing (where i is any one of 11, 12, 21, and 22) is 1 ( Step S20).

In step S20, if the lower (k + 1) th bit of the data of the grayscale data _{P i} is 0 (step S20: N), the process proceeds to step S22 to prepare the original FRC pattern. On the other hand, in step S20, when the lower gray scale data _{P i} (k + 1) th bit of the data is 1 (step S20: Y), Collect all inverted FRC pattern element data of the original FRC pattern ( The process proceeds to step S21) and step S22.

  Here, taking the example of the 1-bit FRC scheme when k is 1, when the original FRC pattern is the FRC pattern FP1 of FIGS. 6 to 8, the FRC pattern to be prepared in step S21 is FIG. To FRC pattern FP2 in FIG. When the original FRC pattern is the FRC pattern FP2 of FIGS. 6 to 8, the FRC pattern to be prepared in step S21 is the FRC pattern FP1 of FIGS.

Subsequently, in step S22, it is determined whether or not the element data PAT (P _i ) is a “bright pattern” (step S22).

In step S22, when the element data PAT (P _i ) is a “bright pattern” (step S22: Y), it is determined whether or not the gradation data P _i is even data (step S23).

In step S23, when the gradation data P _i is even data (step S23: Y), the data from which the least significant bit (LSB) of the gradation data P _i is deleted is the gradation data GP _i after the FRC process. It is generated (step S24). For example, when the least significant bit of the gradation data P _i is 0, it can be determined that the gradation data P _i is even data.

In step S22, when the element data PAT (P _i ) is a “dark pattern” (step S22: N), the data in which the least significant bit (LSB) of the gradation data P _i is deleted is the same after the FRC processing. It is generated as gradation data GP _i (step S24).

In step S24, if the number of bits of the gradation data GP _i after the FRC processing is J, the number of bits of the gradation data P _i is (J−1). Then, for example, while switching ^{two one} FRC pattern, gray scale display is performed.

On the other hand, in step S23, when the gradation data _Pi is odd data (step S23: N), an increment process is performed (step S25). For example, when the least significant bit of the gradation data P _i is 1, it can be determined that the gradation data P _i is odd data. Increment processing is a processing for adding 1 to the least significant bit of the grayscale data P _i. Then, after the increment process, the process proceeds to step S24.

  Hereinafter, in the present embodiment, a description will be given of a processing example when the element data of the FRC pattern is inverted according to the lower-order second bit data of the gradation data when 1-bit FRC with k = 1 is performed. .

  First, the case where the FRC process including the increment process in this embodiment is performed on the display pattern of the horizontal gradation image, the display pattern of the vertical gradation image, and the display pattern of the oblique gradation image will be described.

  FIG. 10 is an explanatory diagram of the FRC process of the present embodiment for the display pattern of the horizontal gradation image. 10, the same parts as those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  FIG. 10 shows an image of 10 pixels × 10 pixels arranged in the horizontal direction and the vertical direction as the display pattern DISP1 of the horizontal gradation image (original image).

  In FIG. 10, the display pattern after the FRC process including the increment process using the FRC pattern FP1 for the display pattern DISP1 is displayed as FDISP10, and the display pattern after the FRC process including the increment process using the FRC pattern FP2 is performed for the display pattern DISP1. The pattern is FDISP20. Also in the display patterns FDISP10 and FDISP20, the gradation data of each pixel is shown, the gradation data of the pixel that has been subjected to the process of decreasing the luminance is surrounded by a square, and the gradation data of the pixel that has been subjected to the process of increasing the luminance Is circled. Note that gradation data that is not surrounded by squares or circles indicates that FRC processing including increment processing is not performed. In FIG. 10, display patterns FDISP1 and FDISP2 after the FRC process of FIG. 6 are shown as comparative examples.

  Also in this embodiment, the LCD panel is driven alternately using the display patterns FDISP10 and FDISP20 after such FRC processing. At this time, as in the comparative example using the display patterns FDISP1 and FDISP2, the pixels subjected to the processing for increasing the luminance and the pixels subjected to the processing for decreasing the luminance are both temporally and spatially in the entire screen. Since it is dispersed, the image quality is not deteriorated.

  FIG. 11 is an explanatory diagram of the FRC process of the present embodiment for the display pattern of the vertical gradation image. In FIG. 11, the same parts as those in FIG.

  In FIG. 11, as a display pattern DISP2 of the vertical gradation image (original image), an image of 10 pixels × 10 pixels arranged in the horizontal direction and the vertical direction is shown.

  In FIG. 11, the display pattern after the FRC process including the increment process using the FRC pattern FP1 for the display pattern DISP2 is displayed as FDISP11, and the display pattern after the FRC process including the increment process using the FRC pattern FP2 is performed for the display pattern DISP2. The pattern is FDISP21. Also in the display patterns FDISP11 and FDISP21, the gradation data of each pixel is shown, the gradation data of the pixel that has been subjected to the process of decreasing the luminance is surrounded by a square, and the gradation data of the pixel that has been subjected to the process of increasing the luminance Is circled. Note that gradation data that is not surrounded by squares or circles indicates that FRC processing including increment processing is not performed. In FIG. 11, the display patterns FDISP3 and FDISP4 after the FRC process of FIG. 7 are shown as comparative examples.

  Also in the present embodiment, the LCD panel is driven alternately using the display patterns FDISP11 and FDISP21 after such FRC processing. At this time, as in the comparative example using the display patterns FDISP3 and FDISP4, the pixels subjected to the processing for increasing the luminance and the pixels subjected to the processing for decreasing the luminance are both temporally and spatially in the entire screen. Since it is dispersed, the image quality is not deteriorated.

  FIG. 12 is an explanatory diagram of the FRC process of the present embodiment for the display pattern of the oblique gradation image. In FIG. 12, the same parts as those of FIG.

  In FIG. 12, as the display pattern DISP3 of the diagonal gradation image (original image), an image of 10 pixels × 10 pixels arranged in the horizontal direction and the vertical direction is shown.

  In FIG. 12, the display pattern after the FRC process including the increment process using the FRC pattern FP1 for the display pattern DISP3 is displayed as FDISP12, and the display pattern after the FRC process including the increment process using the FRC pattern FP2 is performed for the display pattern DISP3. The pattern is FDISP22. Also in the display patterns FDISP12 and FDISP22, the gradation data of each pixel is shown, the gradation data of the pixel that has been subjected to the process of reducing the brightness is surrounded by a square, and the gradation data of the pixel that has been subjected to the process of increasing the brightness Is circled. Note that gradation data that is not surrounded by a square or a circle indicates that FRC processing is not performed.

  The LCD panel is driven alternately using the display patterns FDISP12 and FDISP22 after the FRC process including the increment process. At this time, unlike the comparative example using the display patterns FDISP5 and FDISP6, the pixels subjected to the processing for increasing the luminance and the pixels subjected to the processing for decreasing the luminance are both temporally and spatially in the entire screen. Since it is dispersed, the image quality is not deteriorated.

  As described above, according to the present embodiment, it is possible to realize an FRC that does not deteriorate the image quality of a display pattern of an oblique gradation image with a simple configuration without adding an FRC pattern.

4). Next, an example in which the driving method using the FRC method according to the present embodiment is applied to an electro-optical device will be described.

4.1 Liquid Crystal Display Device FIG. 13 shows an outline of the configuration of an active matrix liquid crystal display device according to this embodiment. Here, an active matrix liquid crystal display device is described, but the present invention can also be applied to a simple matrix liquid crystal display device.

  The liquid crystal display device 10 includes an LCD panel (display panel in a broad sense, electro-optical device in a broader sense) 20. The LCD panel 20 is formed on a glass substrate, for example. On this glass substrate, a plurality of scanning lines (gate lines) GL1 to GLM (M is an integer of 2 or more) arranged in the Y direction and extending in the X direction, and a plurality of data lines arranged in the X direction and extending in the Y direction, respectively. (Source line) DL1 to DLN (N is an integer of 2 or more) are arranged. Also, the pixel region corresponds to the intersection position of the scanning line GLm (1 ≦ m ≦ M, m is an integer, the same applies hereinafter) and the data line DLn (1 ≦ n ≦ N, n is an integer, the same applies hereinafter). (Pixel) is provided, and a thin film transistor (hereinafter abbreviated as TFT) 22 mn is disposed in the pixel region.

  The gate of the TFT 22mn is connected to the scanning line GLn. The source of the TFT 22mn is connected to the data line DLn. The drain of the TFT 22mn is connected to the pixel electrode 26mn. Liquid crystal is sealed between the pixel electrode 26mn and the counter electrode 28mn facing the pixel electrode 26mn, thereby forming a liquid crystal capacitor (liquid crystal element in a broad sense) 24mn. The transmittance of the pixel changes according to the applied voltage between the pixel electrode 26mn and the counter electrode 28mn. The counter electrode voltage Vcom is supplied to the counter electrode 28mn.

  Such an LCD panel 20 includes, for example, a first substrate on which pixel electrodes and TFTs are formed and a second substrate on which counter electrodes are formed, and a liquid crystal as an electro-optical material is interposed between the two substrates. It is formed by enclosing.

  The liquid crystal display device 10 includes a data driver (display driver in a broad sense, drive circuit in a broader sense) 30. The data driver 30 drives the data lines DL1 to DLN of the LCD panel 20 on the basis of the gradation data by a so-called 1-bit FRC method.

  The liquid crystal display device 10 can include a gate driver (scan driver) 32. The gate driver 32 scans the scanning lines GL1 to GLM of the LCD panel 20 within one vertical scanning period.

  The liquid crystal display device 10 can include a power supply circuit 100. The power supply circuit 100 generates voltages necessary for driving the data lines and supplies them to the data driver 30. The power supply circuit 100 generates, for example, power supply voltages VDDH and VSSH necessary for driving the data lines of the data driver 30 and a voltage of a logic unit of the data driver 30.

  The power supply circuit 100 generates a voltage necessary for scanning the scanning line and supplies it to the gate driver 32.

  Further, the power supply circuit 100 generates a counter electrode voltage Vcom. In accordance with the timing of the polarity inversion signal POL generated by the data driver 30, the power supply circuit 100 generates the counter electrode voltage Vcom that periodically repeats the high potential side voltage VCOMH and the low potential side voltage VCOML on the LCD panel 20. Output to electrode.

  The liquid crystal display device 10 can include a display controller 38. The display controller 38 controls the data driver 30, the gate driver 32, and the power supply circuit 100 according to the contents set by a host such as a central processing unit (hereinafter abbreviated as CPU) (not shown). For example, the display controller 38 sets an operation mode and supplies an internally generated vertical synchronization signal and horizontal synchronization signal to the data driver 30 and the gate driver 32.

  In FIG. 13, the liquid crystal display device 10 is configured to include the power supply circuit 100 or the display controller 38, but at least one of these may be provided outside the liquid crystal display device 10. Good. Alternatively, the liquid crystal display device 10 may be configured to include a host.

  The data driver 30 may incorporate at least one of the gate driver 32 and the power supply circuit 100.

  Furthermore, some or all of the data driver 30, the gate driver 32, the display controller 38, and the power supply circuit 100 may be formed on the LCD panel 20. For example, in FIG. 14, a data driver 30 and a gate driver 32 are formed on the LCD panel 20. As described above, the LCD panel 20 includes a plurality of data lines, a plurality of scanning lines, a plurality of switching elements connected to the scanning lines of the plurality of scanning lines and the data lines of the plurality of data lines, and a plurality of switching elements. And a display driver for driving the data line. A plurality of pixels are formed in the pixel formation region 80 of the LCD panel 20.

4.2 Gate Driver FIG. 15 shows a configuration example of the gate driver 32 of FIG.

  The gate driver 32 includes a shift register 40, a level shifter 42, and an output buffer 44.

  The shift register 40 includes a plurality of flip-flops provided corresponding to each scanning line and sequentially connected. When the shift register 40 holds the start pulse signal STV in the flip-flop in synchronization with the clock signal CPV, the shift register 40 sequentially shifts the start pulse signal STV to the adjacent flip-flop in synchronization with the clock signal CPV. The clock signal CPV input here is a horizontal synchronizing signal, and the start pulse signal STV is a vertical synchronizing signal.

  The level shifter 42 shifts the voltage level from the shift register 40 to a voltage level corresponding to the liquid crystal element of the LCD panel 20 and the transistor capability of the TFT. As this voltage level, for example, a high voltage level of 20 V to 50 V is required.

  The output buffer 44 buffers the scanning voltage shifted by the level shifter 42 and outputs it to the scanning line to drive the scanning line.

4.3 Data driver (display driver)
FIG. 16 is a block diagram showing a configuration example of the data driver 30 shown in FIG.

  The data driver 30 includes a line latch 54, an FRC control circuit 56, an FRC circuit 58, a reference voltage generation circuit 60, a DAC (Digital / Analog Converter) (data voltage generation circuit in a broad sense) 62, and an output buffer 64.

  The data driver 30 is inputted with gradation data serially in pixel units (or in units of one dot). This gradation data is input in synchronization with the dot clock signal DCLK. The dot clock signal DCLK is supplied from the display controller 38.

  Shift register 50 includes a plurality of flip-flops in which each flip-flop is provided corresponding to each data line. Each flip-flop of the plurality of flip-flops is connected in series. That is, the data output terminal of the preceding flip-flop is connected to the data input terminal of each flip-flop of the plurality of flip-flops. A data take-in instruction signal EIO is input to the data input terminal of the first flip-flop. A dot clock signal DCLK is commonly supplied to the clock input terminals of the flip-flops. Therefore, the plurality of flip-flops shift the data take-in instruction signal EIO in synchronization with the change point of the dot clock signal DCLK.

  The data latch 52 includes a plurality of registers that are provided corresponding to the respective data lines and hold gradation data for one dot. Each register of the plurality of registers is commonly connected to a bus to which gradation data is supplied serially as described above. Each register receives a shift output from the data output terminal of each flip-flop of the plurality of flip-flops constituting the shift register 50. Each register takes in gradation data on the bus in synchronization with the shift output change point. When the plurality of registers of the data latch 52 fetch the gradation data on the bus based on the shift output from the flip-flop at the final stage of the plurality of flip-flops constituting the shift register 50, the data latch 52 The gradation data for scanning is taken in.

  The line latch 54 latches the grayscale data for one horizontal scan latched by the data latch 52 at the change timing of the horizontal synchronization signal LP. The line latch 54 also includes a plurality of registers in which each register holds gradation data for one dot. The gradation data held in the registers of the plurality of registers of the data latch 52 are taken into the registers of the plurality of registers of the line latch 54.

  The FRC control circuit 56 generates an FRC control signal for realizing the 1-bit FRC method, and supplies the FRC control signal to the FRC circuit 58. More specifically, the FRC control circuit 56 generates an FRC control signal based on the vertical synchronization signal FR horizontal synchronization signal LP and the dot clock signal DCLK. The FRC control circuit 56 is initialized by the reset signal XRES.

  Based on the FRC control signal from the FRC control circuit 56, the FRC circuit 58 uses, as output data, data after the FRC process including the increment process performed on the gradation data corresponding to each data line from the line latch 54. Or output the output data as it is without performing the FRC process including the increment process on the gradation data. Since the FRC circuit 58 employs a 1-bit FRC method for j-bit gradation data, the number of bits of output data is (j−1) bits.

The reference voltage generation circuit 60 generates a plurality of reference voltages in which each reference voltage corresponds to each gradation data. More specifically, the reference voltage generation circuit 60 generates a plurality of gradation voltages, each reference voltage corresponding to each gradation data, between the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH. When the number of bits of the gradation data is (j−1), the reference voltage generation circuit 60 generates 2 ^(j−1) +1 types of reference voltages. Such a reference voltage generation circuit 60 outputs, as reference voltages, voltages at a plurality of divided nodes of a resistor circuit to which the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH are supplied at both ends.

The DAC 62 generates a reference voltage corresponding to the output data from the FRC circuit 58 for each data line. More specifically, the DAC 62 selects a reference voltage corresponding to output data from the FRC circuit 58 from a plurality of 2 ^(j−1) +1 types of reference voltages generated by the reference voltage generation circuit 60. The reference voltage is output.

  The output buffer 64 drives a plurality of output lines in which each output line is connected to each data line of the LCD panel 20. More specifically, the output buffer 64 drives each output line based on the reference voltage output for each output line by the DAC 62.

  In FIG. 16, a data driver that does not incorporate a so-called frame memory will be described. However, the contents of the present embodiment are not limited to those that incorporate a frame memory.

In such a data driver 30, the FRC circuit 58 includes first to Nth FRC processing circuits 70 ₁ to 70 that each FRC processing circuit is provided corresponding to each output line and performs FRC processing on gradation data. _N is included. The first to Nth FRC processing circuits 70 ₁ to 70 _N have the same configuration.

In the data driver 30, the DAC 62 includes first to first data voltage selectors (voltage selection circuits in a broad sense) that are provided corresponding to the output lines and select a reference voltage corresponding to output data from the FRC processing circuit. N data voltage selectors (first to Nth voltage selection circuits in a broad sense) 72 _{1 to} 72 _N are included. The first to Nth data voltage selectors 72 _{1 to} 72 _N have the same configuration.

Further, in the data driver 30, the output buffer 64 includes _first to _Nth output circuits 74 ₁ to 74 _{N in} which each output circuit is provided corresponding to each output line. The first to Nth output circuits 74 ₁ to 74 _N have the same configuration. Each output circuit drives the data line based on the reference voltage selected by each data voltage selector. Each output circuit can be constituted by an operational amplifier connected by a voltage follower, a CMOS buffer circuit, or the like.

The data driver 30 includes a data line driving circuit _DD 1 Dd _N of the first to N for each output line. The r-th (1 ≦ r ≦ N, r is an integer) data line driving circuit DD _r includes an r-th FRC processing circuit 70 _r , an r-th data voltage selector 72 _r , and an r-th output circuit 74 _r .

FIG. 17 is an explanatory diagram of the FRC control circuit and the first to Nth data line driving circuits DD _{1 to} DD _N of FIG. However, FIG. 17 shows a case where the number of bits j of the gradation data is 6. Accordingly, the reference voltage generation circuit 60 generates 2 ^(6-1) +1 class reference voltages V0 to V32, and the reference voltages V0 to V32 are common to the _first to Nth data voltage selectors 72 _{1 to} 72 _N. Supplied.

The FRC control circuit 56 generates a first FRC control signal FRC_A and a second FRC control signal FRC_B. More specifically, the FRC control circuit 56 generates first and second FRC control signals FRC_A and FRC_B that change based on the vertical synchronization signal FR and the horizontal synchronization signal LP and have opposite phases to each other. The FRC control circuit 56 supplies the first FRC control signal FRC_A or the second FRC control signal FRC_B to each of the _first to _Nth FRC processing circuits 70 ₁ to 70 _N.

Here, attention is paid to the data line driving circuit _DD 1 Dd ₆ of first to sixth driving the data lines DL1～DL6. At this time, the data line DLi (1 ≦ i ≦ 5, i is an integer) (i-th data line) is adjacent to the data line DL (i + 1) ((i + 1) -th data line). The data lines DL1 and DL4 are connected to the pixel electrode of the R component that is the first color component of RGB, for example. The data lines DL2 and DL5 are connected to the pixel electrode of the G component that is the second color component of RGB, for example. The data lines DL3 and DL6 are connected to the pixel electrode of the B component which is the third color component of RGB, for example.

The FRC processing circuit of each data line driving circuit of the first to sixth data line driving circuits DD _{1 to} DD ₆ includes the first and second FRC control signals FRC_A and FRC_B and the lower two of the j-bit gradation data. The gradation data is incremented based on (= k + 1) -bit data. Further, the data voltage selector of each data line driving circuit has 5 (= (j−1)) of the gradation data after the increment processing from 2 ⁵ +1 types of reference voltages V0 to V32 (a plurality of reference voltages). A reference voltage corresponding to bit gradation data (for example, V31) or gradation data that is one gradation higher or lower than the gradation data (for example, V32) is selected. The output circuit of each data line driving circuit drives the data line using the reference voltage selected by the data voltage selector.

Then, the FRC processing circuit of each data line driving circuit of the adjacent first to third data line driving circuits DD _{1 to} DD ₃ performs the lower 2 bits of the first FRC control signal FRC_A and the j-bit gradation data. The gradation data is incremented based on the data. Further, the FRC processing circuit of each data line driving circuit of the adjacent fourth to sixth data line driving circuits DD _{4 to} DD ₆ performs the lower 2 bits of the second FRC control signal FRC_B and the j-bit gradation data. The gradation data is incremented based on the data.

Note that the FRC processing circuit of each of the data line drive circuits DD _{7 to} DD ₉ uses the first FRC control signal FRC_A and the lower 2 bits of the j-bit grayscale data. Based on this, the gradation data is incremented. Further, the FRC processing circuit of each data line driving circuit of the adjacent _{tenth to} twelfth data line driving circuits DD _{10 to} DD ₁₂ has the lower 2 bits of the second FRC control signal FRC_B and the j-bit gradation data. The gradation data is incremented based on the data. Thereafter, similarly, the first and second FRC control signals FRC_A and FRC_B are alternately supplied to the FRC processing circuit for every three adjacent data line driving circuits.

  With the configuration described above, the LCD panel 20 can be driven by the FRC method in units of one pixel composed of three dots in the horizontal direction.

  FIG. 18 shows a circuit diagram of a configuration example of the FRC control circuit 56 of FIG.

  The FRC control circuit 56 includes D flip-flops DFF1 and DFF2 that are initialized when the reset signal XRES is at the L level, and selectors SEL1 to SEL3 that are selectively controlled by the vertical synchronization signal FR or the horizontal synchronization signal LP. The dot clock signal DCLK is input to the clock input terminal C of the D flip-flops DFF1 and DFF2. Therefore, when the dot clock signal DCLK is at the H level, the D flip-flops DFF1 and DFF2 take in the input signal of the data input terminal D and output a signal having the same logic level as that of the input signal from the data output terminal Q. At the same time, a signal having a logic level different from the logic level of the input signal is output from the inverted data output terminal XQ. The D flip-flops DFF1 and DFF2 hold the input signal of the data input terminal D when the dot clock signal DCLK changes from the H level to the L level, and the held signals are sent from the data output terminal Q and the inverted data output terminal XQ. Output.

  When the vertical synchronization signal FR is at the H level, the selector SEL1 transmits the signal level of the data output terminal Q of the D flip-flop DFF1 to the data input terminal D of the D flip-flop DFF1. When the vertical synchronizing signal FR is at L level, the selector SEL1 transmits the signal level of the inverted data output terminal XQ of the D flip-flop DFF1 to the data input terminal D of the D flip-flop DFF1.

  When the horizontal synchronization signal LP is at the H level, the selector SEL2 transmits the signal level of the data output terminal Q of the D flip-flop DFF2 to the selector SEL3. When the horizontal synchronization signal LP is at L level, the selector SEL2 transmits the signal level of the inverted data output terminal XQ of the D flip-flop DFF2 to the selector SEL3.

  When the vertical synchronization signal FR is at the H level, the selector SEL3 transmits the signal level of the output of the selector SEL2 to the data input terminal D of the D flip-flop DFF2. When the vertical synchronization signal FR is at the L level, the selector SEL3 transmits the signal level of the inverted data output terminal XQ of the D flip-flop DFF1 to the data input terminal D of the D flip-flop DFF2.

  In such an FRC control circuit 56, the signal of the data output terminal Q of the D flip-flop DFF2 is output as the first FRC control signal FRC_A, and the signal of the inverted data output terminal XQ of the D flip-flop DFF2 is the second FRC control. Output as signal FRC_B.

  FIG. 19 shows a timing chart of an operation example of the FRC control circuit 56 of FIG.

  In FIG. 19, it is assumed that the reset signal XRES once changes to the L level, then changes to the H level, and then continues to the H level state.

  At this time, when the vertical synchronizing signal FR changes from the H level to the L level while the dot clock signal DCLK changes periodically, the selector SEL1 sends the H level signal to the data input terminal D of the D flip-flop DFF1. Even after the transmission and the vertical synchronization signal FR changes to the H level, the H level signal is output from the data output terminal Q of the D flip-flop DFF1. When the vertical synchronization signal FR changes from the H level to the L level again, the selector SEL1 transmits the L level signal to the data input terminal D of the D flip-flop DFF1, and after the vertical synchronization signal FR changes to the H level. Also, an L level signal is output from the data output terminal Q of the D flip-flop DFF1.

  As described above, in the FRC control circuit 56, the selector SEL1 and the D flip-flop DFF1 output a signal whose logic level is inverted every vertical scanning period from the data output terminal Q of the D flip-flop DFF1.

  Therefore, when the vertical synchronization signal FR and the horizontal synchronization signal LP change from the H level to the L level, the signal of the inverted data output terminal XQ of the D flip-flop DFF1 is transmitted to the data input terminal D of the D flip-flop DFF2. This signal is output as the first FRC control signal FRC_A. Therefore, when the vertical synchronization signal FR and the horizontal synchronization signal LP change from the H level to the L level and return to the H level again, the first FRC control is performed when the signal at the inverted data output terminal XQ of the D flip-flop DFF1 is at the L level. The signal FRC_A becomes L level, and the second FRC control signal FRC_B becomes H level (TG1).

  Next, when the horizontal synchronizing signal LP changes to the L level and returns to the H level while the vertical synchronizing signal FR remains at the H level, the data input terminal D of the D flip-flop DFF2 has the H level from the inverted data output terminal XQ. The signal is transmitted. Therefore, the first FRC control signal FRC_A becomes H level and the second FRC control signal FRC_B becomes L level (TG2). Thereafter, whenever the horizontal synchronization signal LP changes to L level and returns to H level while the vertical synchronization signal FR remains at H level, the logic level of the first FRC control signal FRC_A (second FRC control signal FRC_B) becomes Invert.

  When the vertical synchronizing signal FR and the horizontal synchronizing signal LP change from the H level to the L level, the logic level of the signal at the inverted data output terminal XQ of the D flip-flop DFF1 is inverted from the logic level in the immediately preceding vertical scanning period. It becomes. Therefore, in the next vertical scanning period, the signal of the inverted data output terminal XQ of the D flip-flop DFF1 becomes H level, the first FRC control signal FRC_A becomes H level, and the second FRC control signal FRC_B becomes L level ( TG3). Similarly, every time the horizontal synchronization signal LP changes to L level and returns to H level while the vertical synchronization signal FR remains at H level, the logic of the first FRC control signal FRC_A (second FRC control signal FRC_B) The level is reversed.

  By using such first and second FRC control signals FRC_A and FRC_B, it is possible to realize an FRC system that switches between a “bright pattern” and a “dark pattern” in the vertical direction.

20 shows a first configuration example of the data line driving circuit DD ₁ in Figure 17.

Shows an example of the configuration of FIG. 20 in the first data line driving circuit DD _1, the same configuration applies to the second to N data line driving circuit _DD 2 Dd _N. However, as shown in FIG. 17, the first to third data line drive circuits DD _{1 to} DD ₃ are supplied with the first FRC control signal FRC_A, while the fourth to sixth data line drive circuits. The second FRC control signal FRC_B is supplied to DD _{4 to} DD ₆ .

In Figure 20, the first FRC processing circuit 70 ₁ includes exclusive OR circuits EXOR1 _1, EXOR2 _1, the logical product circuits AND1 _1, increment circuit incC _1, the comparison circuit CMP _1. The first FRC processing circuit 70 _1, the first FRC control signal FRC_A, is 6-bit gradation data D5~D0 inputted. Exclusive OR circuit EXOR1 ₁ performs the data D0 of the least significant bit of the 6 bits of gray scale data D5 to D0, an exclusive OR operation between the first FRC control signal FRC_A. Exclusive OR circuit EXOR2 ₁ performs the low-order 2 bit of the data D1 of the 6-bit gray scale data D5 to D0, an exclusive OR operation on the output of the exclusive OR circuit EXOR1 _1. AND circuit AND1 ₁ is the least significant bit of the data D0 of the 6-bit gray scale data D5 to D0, ANDs the output of the exclusive OR circuit EXOR2 _1, as the increment control signal Inc results Output.

  FIG. 21 is an explanatory diagram of the increment control signal Inc of FIG.

  As shown in FIG. 21, when the least significant bit data D0 of the gradation data is 0, the increment control signal Inc becomes L level. When the least significant bit data D0 of the gradation data is 1, and when the lower second bit data D1 of the gradation data is 0, the increment control signal Inc is output according to the first FRC control signal FRC_A. . Then, when the least significant bit data D0 of the gradation data is 1, and when the data D1 of the least significant second bit of the gradation data is 1, the increment control signal Inc is inverted unlike when the data D1 is 0. To output.

  By doing so, the FRC pattern can be made different between when the lower second bit data of the gradation data is 0 and when the lower second bit data of the gradation data is 1.

The increment circuit INCC ₁ increments 6-bit gradation data D5 to D0 and outputs increment data SUM5 to SUM0 when the increment control signal Inc is at the H level. The increment circuit INCC ₁ outputs the 6-bit gradation data D5 to D0 as the increment data SUM5 to SUM0 as it is when the increment control signal Inc is at the L level. Of the increment data SUM5 to SUM0, the upper 5-bit increment data SUM5 to SUM1 is supplied to the _first data voltage selector 721.

The first data voltage selector 72 _1, of the reference voltage V0～V32, select the reference voltage corresponding to the grayscale value represented by the increment data SUM5～SUM1, and outputs the first output circuit 74 _1.

Incidentally, in the first FRC processing circuit 70 _1, the comparator circuit CMP ₁ compares the 6-bit gray scale data D5 to D0, and a given maximum gradation value or the minimum grayscale value. In Figure 20, 63 as a maximum tone value is supplied to the comparison circuit CMP _1. The comparison circuit CMP ₁ outputs a coincidence detection pulse to the _first data voltage selector 721 when the gradation value represented by the 6-bit gradation data D5 to D0 coincides with the maximum gradation value. 1 of the data voltage selector ₇₂₁ outputs the maximum gradation value and the corresponding reference voltage of the reference voltage V0～V32 (e.g. reference voltage V32). Accordingly, the first data voltage selector 72 _1, on condition that the gradation value represented by 6-bit grayscale data D5~D0 is mismatched with the maximum tone value, the upper five bits of the grayscale data It can be said that the reference voltage corresponding to the data D5 to D1 is selected.

Incidentally, the comparison circuit CMP ₁ may be configured to compare the gradation value and the minimum grayscale value represented by 6-bit gray scale data D5 to D0. In this case, the comparison circuit CMP _1, when the gradation value and the minimum grayscale value represented by 6-bit grayscale data D5~D0 match, the first data voltage selector 72 _1, reference voltage V0~ A reference voltage (for example, reference voltage V0) corresponding to the minimum gradation value of V32 is output.

The comparison circuit CMP ₁ as described above is provided, and so-called exceptional processing is performed in accordance with the gradation data, so that the LCD panel is based on an unnecessary processing result generated at the time of specific gradation data in the increment processing. The situation of driving 20 can be avoided, and deterioration of image quality can be prevented.

The first output circuit 74 ₁ is composed of an operational amplifier connected in a voltage follower, and drives the data line DL 1 based on the voltage from the _first data voltage selector 721.

  As described above, according to the present embodiment, it is possible to provide a display driver that realizes an FRC that does not deteriorate the image quality of a display pattern of an oblique gradation image with a simple configuration without adding an FRC pattern.

5. Application Example to Electronic Device FIG. 22 shows a block diagram of a configuration example of the electronic device in the present embodiment. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device. In FIG. 22, the same parts as those in FIG. 13 or FIG.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera and supplies image data captured by the CCD camera to the display controller 38 in the YUV format.

  Mobile phone 900 includes LCD panel 20. The LCD panel 20 is driven by a data driver 30 and a gate driver 32. The LCD panel 20 includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels.

  The display controller 38 is connected to the data driver 30 and the gate driver 32, and supplies RGB data gradation data to the data driver 30.

  The power supply circuit 100 is connected to the data driver 30 and the gate driver 32 and supplies a driving power supply voltage to each driver. Further, the counter electrode voltage Vcom is supplied to the counter electrode of the LCD panel 20.

  The host 940 is connected to the display controller 38. The host 940 controls the display controller 38. The host 940 can supply the gradation data received via the antenna 960 to the display controller 38 after demodulating the modulation / demodulation unit 950. The display controller 38 causes the data driver 30 and the gate driver 32 to display on the LCD panel 20 based on the gradation data.

  The host 940 can instruct transmission to another communication device via the antenna 960 after the modulation / demodulation unit 950 modulates the gradation data generated by the camera module 910.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the LCD panel 20 based on operation information from the operation input unit 970.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the above-described liquid crystal display panel, but can be applied to driving electroluminescence and plasma display devices. In this embodiment, 1-bit FRC in the case where k is 1 has been mainly described, but the present invention is not limited to this.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

The principle explanatory drawing of FRC. Explanatory drawing of the example of a FRC pattern. Explanatory drawing of an example of the process using a FRC pattern. The figure which shows an example of a FRC process. Explanatory drawing of the specific process example of FRC of FIG.3 and FIG.4. Explanatory drawing of the FRC process with respect to the display pattern of a horizontal gradation image. Explanatory drawing of the FRC process with respect to the display pattern of a vertical gradation image. Explanatory drawing of the FRC process with respect to the display pattern of a diagonal gradation image. The figure which shows an example of the FRC process of this embodiment. Explanatory drawing of the FRC process of this embodiment with respect to the display pattern of a horizontal gradation image. Explanatory drawing of the FRC process of this embodiment with respect to the display pattern of a vertical gradation image. Explanatory drawing of the FRC process of this embodiment with respect to the display pattern of a diagonal gradation image. 1 is a diagram illustrating an outline of a configuration of an active matrix liquid crystal display device according to an embodiment. The figure which shows the outline | summary of the other structure of the active matrix type liquid crystal display device in this embodiment. FIG. 14 is a diagram illustrating a configuration example of a scan driver in FIG. 13. FIG. 14 is a block diagram of a configuration example of the data driver in FIG. 13. FIG. 17 is an explanatory diagram of the FRC control circuit and the first to Nth data line driving circuits of FIG. 16. The circuit diagram of the structural example of the FRC control circuit of FIG. FIG. 19 is a timing diagram of an operation example of the FRC control circuit of FIG. 18. FIG. 18 is a diagram showing a configuration example of a first data line driving circuit in FIG. 17. FIG. 21 is an explanatory diagram of an increment control signal in FIG. 20. 1 is a block diagram of a configuration example of an electronic device according to an embodiment.

Explanation of symbols

10 liquid crystal display device, 20 LCD panel, 30 data driver,
32 gate drivers, 38 display controllers, 40, 50 shift registers,
42 level shifter, 44, 64 output buffer, 52 data latch,
54 line latch, 56 FRC control circuit, 58 FRC circuit,
60 reference voltage generation circuit, 62 DAC,
70 ₁ to 70 _{N first} to _Nth FRC processing circuits,
72 _{1 to} 72 _N first to Nth data voltage selectors,
74 ₁ to 74 _N first to Nth output circuits, 100 power supply circuit,
DCLK dot clock signal, DD _{1 to} DD _N first to Nth data line driving circuits,
FRC_A first FRC control signal, FRC_B second FRC control signal,
LP horizontal sync signal, FR vertical sync signal

Claims (10)

For gradation display by FRC (Frame Rate Control) method using lower-order k (j>k> 0, k is an integer) bit data of j (j ≧ 2, j is an integer) bit gradation data A method for driving an electro-optical device, comprising:
An FRC pattern for designating whether or not to perform gradation data increment processing for adjusting the brightness of the dot position based on the lower-order k-bit data of the gradation data of each dot constituting the pixel, Differently when the lower (k + 1) bit data of the data is 0 and when the lower (k + 1) bit data of the gradation data is 1.
The increment processing is performed according to different FRC patterns according to the lower (k + 1) -bit data, and the electro-optical device is driven based on the (j−k) -bit gradation data after the increment processing. A driving method of the electro-optical device. In claim 1,
First to Pth FRC patterns (P ≧ 2 ^k , P is an integer) are prepared,
Different FRC patterns are selected when the lower (k + 1) bit data of the gradation data is 0 and when the lower (k + 1) bit data of the gradation data is 1.
A driving method of an electro-optical device, wherein the increment processing is performed according to a selected FRC pattern, and the electro-optical device is driven based on (j−k) -bit gradation data after the increment processing. In claim 2,
Selected when the lower (k + 1) -bit data is 1 for the dot designated to perform the increment processing in the FRC pattern selected when the lower-order (k + 1) -bit data is 0 The FRC pattern is designated not to perform the increment process,
Select when the lower (k + 1) -bit data is 1 for the dot designated not to perform the increment processing in the FRC pattern selected when the lower (k + 1) -bit data is 0 A driving method for an electro-optical device, wherein the FRC pattern is designated to perform the increment processing. In any one of Claims 1 thru | or 3,
The FRC pattern is
A method for driving an electro-optical device, wherein whether or not to perform the increment processing is designated for each dot. In claim 4,
k is 1,
The driving method of an electro-optical device, wherein the FRC pattern is a checkered pattern in which dots designated to perform increment processing and dots designated not to perform increment processing are adjacent to each other. In any one of Claims 1 thru | or 3,
The FRC pattern is
A method for driving an electro-optical device, wherein whether to perform the increment processing is designated for each pixel. A display driver for driving at least the first to sixth data lines of the plurality of data lines of the electro-optical device,
First to sixth data line driving circuits for driving each data line of the first to sixth data lines based on gradation data,
An FRC control circuit that generates first and second FRC control signals that change based on the vertical synchronization signal and the horizontal synchronization signal and have opposite phases to each other;
When the i-th (1 ≦ i ≦ 5, i is an integer) data line is adjacent to the (i + 1) -th data line,
Each data line driving circuit of the first to sixth data line driving circuits includes:
An FRC processing circuit for performing gradation data increment processing based on the first or second FRC control signal and lower two bits of j (j ≧ 2, j is an integer) bit gradation data;
A voltage selection circuit that selects a reference voltage corresponding to (j−1) -bit gradation data among gradation data after the increment processing from a plurality of reference voltages;
An output circuit for driving a data line using a reference voltage selected by the voltage selection circuit,
An FRC processing circuit of each data line driving circuit of the adjacent first to third data line driving circuits is provided.
The gradation data is incremented based on the first FRC control signal and the lower 2 bits of the j-bit gradation data,
An FRC processing circuit of each data line driving circuit of the adjacent fourth to sixth data line driving circuits is provided.
A display driver, wherein gradation data increment processing is performed based on the second FRC control signal and lower two bits of j-bit gradation data. In claim 7,
Each data line driving circuit of the first to sixth data line driving circuits includes:
A comparison circuit for comparing a gradation value corresponding to the input gradation data with a given maximum gradation value or minimum gradation value;
On the condition that the gradation value does not match the maximum gradation value or the minimum gradation value, the voltage selection circuit generates a reference voltage corresponding to the upper (j−1) bits of the input gradation data. A display driver characterized by selection. A plurality of scan lines;
Multiple data lines,
A plurality of pixels specified by the scanning lines and the data lines;
A scan driver for scanning the scan line;
9. An electro-optical device comprising: the display driver according to claim 7 or 8, wherein the data line is driven based on the gradation data.   An electronic apparatus comprising the electro-optical device according to claim 9.

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